1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/types.h> 8 9 #include "../ipa_reg.h" 10 #include "../ipa_version.h" 11 12 static const u32 reg_comp_cfg_fmask[] = { 13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 /* Bit 4 reserved */ 18 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 19 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 30 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17), 31 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19), 32 [GENQMB_AOOOWR] = BIT(20), 33 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21), 34 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(24, 22), 35 /* Bits 25-29 reserved */ 36 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30), 37 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), 38 }; 39 40 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 41 42 static const u32 reg_clkon_cfg_fmask[] = { 43 [CLKON_RX] = BIT(0), 44 [CLKON_PROC] = BIT(1), 45 [TX_WRAPPER] = BIT(2), 46 [CLKON_MISC] = BIT(3), 47 [RAM_ARB] = BIT(4), 48 [FTCH_HPS] = BIT(5), 49 [FTCH_DPS] = BIT(6), 50 [CLKON_HPS] = BIT(7), 51 [CLKON_DPS] = BIT(8), 52 [RX_HPS_CMDQS] = BIT(9), 53 [HPS_DPS_CMDQS] = BIT(10), 54 [DPS_TX_CMDQS] = BIT(11), 55 [RSRC_MNGR] = BIT(12), 56 [CTX_HANDLER] = BIT(13), 57 [ACK_MNGR] = BIT(14), 58 [D_DCPH] = BIT(15), 59 [H_DCPH] = BIT(16), 60 [CLKON_DCMP] = BIT(17), 61 [NTF_TX_CMDQS] = BIT(18), 62 [CLKON_TX_0] = BIT(19), 63 [CLKON_TX_1] = BIT(20), 64 [CLKON_FNR] = BIT(21), 65 [QSB2AXI_CMDQ_L] = BIT(22), 66 [AGGR_WRAPPER] = BIT(23), 67 [RAM_SLAVEWAY] = BIT(24), 68 [CLKON_QMB] = BIT(25), 69 [WEIGHT_ARB] = BIT(26), 70 [GSI_IF] = BIT(27), 71 [CLKON_GLOBAL] = BIT(28), 72 [GLOBAL_2X_CLK] = BIT(29), 73 [DPL_FIFO] = BIT(30), 74 [DRBIP] = BIT(31), 75 }; 76 77 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 78 79 static const u32 reg_route_fmask[] = { 80 [ROUTE_DIS] = BIT(0), 81 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 82 [ROUTE_DEF_HDR_TABLE] = BIT(6), 83 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 84 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 85 /* Bits 22-23 reserved */ 86 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 87 /* Bits 25-31 reserved */ 88 }; 89 90 REG_FIELDS(ROUTE, route, 0x00000048); 91 92 static const u32 reg_shared_mem_size_fmask[] = { 93 [MEM_SIZE] = GENMASK(15, 0), 94 [MEM_BADDR] = GENMASK(31, 16), 95 }; 96 97 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 98 99 static const u32 reg_qsb_max_writes_fmask[] = { 100 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 101 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 102 /* Bits 8-31 reserved */ 103 }; 104 105 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 106 107 static const u32 reg_qsb_max_reads_fmask[] = { 108 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 109 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 110 /* Bits 8-15 reserved */ 111 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 112 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 113 }; 114 115 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 116 117 static const u32 reg_filt_rout_hash_en_fmask[] = { 118 [IPV6_ROUTER_HASH] = BIT(0), 119 /* Bits 1-3 reserved */ 120 [IPV6_FILTER_HASH] = BIT(4), 121 /* Bits 5-7 reserved */ 122 [IPV4_ROUTER_HASH] = BIT(8), 123 /* Bits 9-11 reserved */ 124 [IPV4_FILTER_HASH] = BIT(12), 125 /* Bits 13-31 reserved */ 126 }; 127 128 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 129 130 static const u32 reg_filt_rout_hash_flush_fmask[] = { 131 [IPV6_ROUTER_HASH] = BIT(0), 132 /* Bits 1-3 reserved */ 133 [IPV6_FILTER_HASH] = BIT(4), 134 /* Bits 5-7 reserved */ 135 [IPV4_ROUTER_HASH] = BIT(8), 136 /* Bits 9-11 reserved */ 137 [IPV4_FILTER_HASH] = BIT(12), 138 /* Bits 13-31 reserved */ 139 }; 140 141 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 142 143 /* Valid bits defined by ipa->available */ 144 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); 145 146 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 147 [IPA_BASE_ADDR] = GENMASK(17, 0), 148 /* Bits 18-31 reserved */ 149 }; 150 151 /* Offset must be a multiple of 8 */ 152 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 153 154 /* Valid bits defined by ipa->available */ 155 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 156 157 static const u32 reg_ipa_tx_cfg_fmask[] = { 158 /* Bits 0-1 reserved */ 159 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 160 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 161 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 162 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 163 [PA_MASK_EN] = BIT(12), 164 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 165 [DUAL_TX_ENABLE] = BIT(17), 166 [SSPND_PA_NO_START_STATE] = BIT(18), 167 /* Bits 19-31 reserved */ 168 }; 169 170 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 171 172 static const u32 reg_flavor_0_fmask[] = { 173 [MAX_PIPES] = GENMASK(3, 0), 174 /* Bits 4-7 reserved */ 175 [MAX_CONS_PIPES] = GENMASK(12, 8), 176 /* Bits 13-15 reserved */ 177 [MAX_PROD_PIPES] = GENMASK(20, 16), 178 /* Bits 21-23 reserved */ 179 [PROD_LOWEST] = GENMASK(27, 24), 180 /* Bits 28-31 reserved */ 181 }; 182 183 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 184 185 static const u32 reg_idle_indication_cfg_fmask[] = { 186 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 187 [CONST_NON_IDLE_ENABLE] = BIT(16), 188 /* Bits 17-31 reserved */ 189 }; 190 191 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 192 193 static const u32 reg_qtime_timestamp_cfg_fmask[] = { 194 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 195 /* Bits 5-6 reserved */ 196 [DPL_TIMESTAMP_SEL] = BIT(7), 197 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 198 /* Bits 13-15 reserved */ 199 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 200 /* Bits 21-31 reserved */ 201 }; 202 203 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 204 205 static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { 206 [DIV_VALUE] = GENMASK(8, 0), 207 /* Bits 9-30 reserved */ 208 [DIV_ENABLE] = BIT(31), 209 }; 210 211 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 212 213 static const u32 reg_timers_pulse_gran_cfg_fmask[] = { 214 [PULSE_GRAN_0] = GENMASK(2, 0), 215 [PULSE_GRAN_1] = GENMASK(5, 3), 216 [PULSE_GRAN_2] = GENMASK(8, 6), 217 }; 218 219 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 220 221 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 222 [X_MIN_LIM] = GENMASK(5, 0), 223 /* Bits 6-7 reserved */ 224 [X_MAX_LIM] = GENMASK(13, 8), 225 /* Bits 14-15 reserved */ 226 [Y_MIN_LIM] = GENMASK(21, 16), 227 /* Bits 22-23 reserved */ 228 [Y_MAX_LIM] = GENMASK(29, 24), 229 /* Bits 30-31 reserved */ 230 }; 231 232 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 233 0x00000400, 0x0020); 234 235 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 236 [X_MIN_LIM] = GENMASK(5, 0), 237 /* Bits 6-7 reserved */ 238 [X_MAX_LIM] = GENMASK(13, 8), 239 /* Bits 14-15 reserved */ 240 [Y_MIN_LIM] = GENMASK(21, 16), 241 /* Bits 22-23 reserved */ 242 [Y_MAX_LIM] = GENMASK(29, 24), 243 /* Bits 30-31 reserved */ 244 }; 245 246 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 247 0x00000404, 0x0020); 248 249 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 250 [X_MIN_LIM] = GENMASK(5, 0), 251 /* Bits 6-7 reserved */ 252 [X_MAX_LIM] = GENMASK(13, 8), 253 /* Bits 14-15 reserved */ 254 [Y_MIN_LIM] = GENMASK(21, 16), 255 /* Bits 22-23 reserved */ 256 [Y_MAX_LIM] = GENMASK(29, 24), 257 /* Bits 30-31 reserved */ 258 }; 259 260 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 261 0x00000500, 0x0020); 262 263 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 264 [X_MIN_LIM] = GENMASK(5, 0), 265 /* Bits 6-7 reserved */ 266 [X_MAX_LIM] = GENMASK(13, 8), 267 /* Bits 14-15 reserved */ 268 [Y_MIN_LIM] = GENMASK(21, 16), 269 /* Bits 22-23 reserved */ 270 [Y_MAX_LIM] = GENMASK(29, 24), 271 /* Bits 30-31 reserved */ 272 }; 273 274 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 275 0x00000504, 0x0020); 276 277 static const u32 reg_endp_init_cfg_fmask[] = { 278 [FRAG_OFFLOAD_EN] = BIT(0), 279 [CS_OFFLOAD_EN] = GENMASK(2, 1), 280 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 281 /* Bit 7 reserved */ 282 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 283 /* Bits 9-31 reserved */ 284 }; 285 286 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 287 288 static const u32 reg_endp_init_nat_fmask[] = { 289 [NAT_EN] = GENMASK(1, 0), 290 /* Bits 2-31 reserved */ 291 }; 292 293 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 294 295 static const u32 reg_endp_init_hdr_fmask[] = { 296 [HDR_LEN] = GENMASK(5, 0), 297 [HDR_OFST_METADATA_VALID] = BIT(6), 298 [HDR_OFST_METADATA] = GENMASK(12, 7), 299 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 300 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 301 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 302 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 303 [HDR_LEN_MSB] = GENMASK(29, 28), 304 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 305 }; 306 307 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 308 309 static const u32 reg_endp_init_hdr_ext_fmask[] = { 310 [HDR_ENDIANNESS] = BIT(0), 311 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 312 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 313 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 314 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 315 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 316 /* Bits 14-15 reserved */ 317 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 318 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 319 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 320 /* Bits 22-31 reserved */ 321 }; 322 323 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 324 325 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 326 0x00000818, 0x0070); 327 328 static const u32 reg_endp_init_mode_fmask[] = { 329 [ENDP_MODE] = GENMASK(2, 0), 330 [DCPH_ENABLE] = BIT(3), 331 [DEST_PIPE_INDEX] = GENMASK(8, 4), 332 /* Bits 9-11 reserved */ 333 [BYTE_THRESHOLD] = GENMASK(27, 12), 334 [PIPE_REPLICATION_EN] = BIT(28), 335 [PAD_EN] = BIT(29), 336 [DRBIP_ACL_ENABLE] = BIT(30), 337 /* Bit 31 reserved */ 338 }; 339 340 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 341 342 static const u32 reg_endp_init_aggr_fmask[] = { 343 [AGGR_EN] = GENMASK(1, 0), 344 [AGGR_TYPE] = GENMASK(4, 2), 345 [BYTE_LIMIT] = GENMASK(10, 5), 346 /* Bit 11 reserved */ 347 [TIME_LIMIT] = GENMASK(16, 12), 348 [PKT_LIMIT] = GENMASK(22, 17), 349 [SW_EOF_ACTIVE] = BIT(23), 350 [FORCE_CLOSE] = BIT(24), 351 /* Bit 25 reserved */ 352 [HARD_BYTE_LIMIT_EN] = BIT(26), 353 [AGGR_GRAN_SEL] = BIT(27), 354 /* Bits 28-31 reserved */ 355 }; 356 357 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 358 359 static const u32 reg_endp_init_hol_block_en_fmask[] = { 360 [HOL_BLOCK_EN] = BIT(0), 361 /* Bits 1-31 reserved */ 362 }; 363 364 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 365 0x0000082c, 0x0070); 366 367 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 368 [TIMER_LIMIT] = GENMASK(4, 0), 369 /* Bits 5-7 reserved */ 370 [TIMER_GRAN_SEL] = BIT(8), 371 /* Bits 9-31 reserved */ 372 }; 373 374 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 375 0x00000830, 0x0070); 376 377 static const u32 reg_endp_init_deaggr_fmask[] = { 378 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 379 [SYSPIPE_ERR_DETECTION] = BIT(6), 380 [PACKET_OFFSET_VALID] = BIT(7), 381 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 382 [IGNORE_MIN_PKT_ERR] = BIT(14), 383 /* Bit 15 reserved */ 384 [MAX_PACKET_LEN] = GENMASK(31, 16), 385 }; 386 387 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 388 389 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 390 [ENDP_RSRC_GRP] = GENMASK(1, 0), 391 /* Bits 2-31 reserved */ 392 }; 393 394 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 395 396 static const u32 reg_endp_init_seq_fmask[] = { 397 [SEQ_TYPE] = GENMASK(7, 0), 398 /* Bits 8-31 reserved */ 399 }; 400 401 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 402 403 static const u32 reg_endp_status_fmask[] = { 404 [STATUS_EN] = BIT(0), 405 [STATUS_ENDP] = GENMASK(5, 1), 406 /* Bits 6-8 reserved */ 407 [STATUS_PKT_SUPPRESS] = BIT(9), 408 /* Bits 10-31 reserved */ 409 }; 410 411 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 412 413 static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 414 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 415 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 416 [FILTER_HASH_MSK_DST_IP] = BIT(2), 417 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 418 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 419 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 420 [FILTER_HASH_MSK_METADATA] = BIT(6), 421 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 422 /* Bits 7-15 reserved */ 423 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 424 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 425 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 426 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 427 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 428 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 429 [ROUTER_HASH_MSK_METADATA] = BIT(22), 430 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 431 /* Bits 23-31 reserved */ 432 }; 433 434 REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 435 0x0000085c, 0x0070); 436 437 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 438 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); 439 440 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 441 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); 442 443 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 444 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); 445 446 static const u32 reg_ipa_irq_uc_fmask[] = { 447 [UC_INTR] = BIT(0), 448 /* Bits 1-31 reserved */ 449 }; 450 451 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); 452 453 /* Valid bits defined by ipa->available */ 454 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 455 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004); 456 457 /* Valid bits defined by ipa->available */ 458 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 459 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004); 460 461 /* Valid bits defined by ipa->available */ 462 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 463 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004); 464 465 static const struct reg *reg_array[] = { 466 [COMP_CFG] = ®_comp_cfg, 467 [CLKON_CFG] = ®_clkon_cfg, 468 [ROUTE] = ®_route, 469 [SHARED_MEM_SIZE] = ®_shared_mem_size, 470 [QSB_MAX_WRITES] = ®_qsb_max_writes, 471 [QSB_MAX_READS] = ®_qsb_max_reads, 472 [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, 473 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 474 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 475 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 476 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 477 [IPA_TX_CFG] = ®_ipa_tx_cfg, 478 [FLAVOR_0] = ®_flavor_0, 479 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 480 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, 481 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, 482 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, 483 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 484 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 485 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 486 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 487 [ENDP_INIT_CFG] = ®_endp_init_cfg, 488 [ENDP_INIT_NAT] = ®_endp_init_nat, 489 [ENDP_INIT_HDR] = ®_endp_init_hdr, 490 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 491 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 492 [ENDP_INIT_MODE] = ®_endp_init_mode, 493 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 494 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 495 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 496 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 497 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 498 [ENDP_INIT_SEQ] = ®_endp_init_seq, 499 [ENDP_STATUS] = ®_endp_status, 500 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 501 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 502 [IPA_IRQ_EN] = ®_ipa_irq_en, 503 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 504 [IPA_IRQ_UC] = ®_ipa_irq_uc, 505 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 506 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 507 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 508 }; 509 510 const struct regs ipa_regs_v4_9 = { 511 .reg_count = ARRAY_SIZE(reg_array), 512 .reg = reg_array, 513 }; 514