1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/types.h> 8 9 #include "../ipa_reg.h" 10 #include "../ipa_version.h" 11 12 static const u32 reg_comp_cfg_fmask[] = { 13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 /* Bit 4 reserved */ 18 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 19 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 30 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), 31 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21), 32 /* Bits 22-31 reserved */ 33 }; 34 35 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 36 37 static const u32 reg_clkon_cfg_fmask[] = { 38 [CLKON_RX] = BIT(0), 39 [CLKON_PROC] = BIT(1), 40 [TX_WRAPPER] = BIT(2), 41 [CLKON_MISC] = BIT(3), 42 [RAM_ARB] = BIT(4), 43 [FTCH_HPS] = BIT(5), 44 [FTCH_DPS] = BIT(6), 45 [CLKON_HPS] = BIT(7), 46 [CLKON_DPS] = BIT(8), 47 [RX_HPS_CMDQS] = BIT(9), 48 [HPS_DPS_CMDQS] = BIT(10), 49 [DPS_TX_CMDQS] = BIT(11), 50 [RSRC_MNGR] = BIT(12), 51 [CTX_HANDLER] = BIT(13), 52 [ACK_MNGR] = BIT(14), 53 [D_DCPH] = BIT(15), 54 [H_DCPH] = BIT(16), 55 [CLKON_DCMP] = BIT(17), 56 [NTF_TX_CMDQS] = BIT(18), 57 [CLKON_TX_0] = BIT(19), 58 [CLKON_TX_1] = BIT(20), 59 [CLKON_FNR] = BIT(21), 60 [QSB2AXI_CMDQ_L] = BIT(22), 61 [AGGR_WRAPPER] = BIT(23), 62 [RAM_SLAVEWAY] = BIT(24), 63 [CLKON_QMB] = BIT(25), 64 [WEIGHT_ARB] = BIT(26), 65 [GSI_IF] = BIT(27), 66 [CLKON_GLOBAL] = BIT(28), 67 [GLOBAL_2X_CLK] = BIT(29), 68 [DPL_FIFO] = BIT(30), 69 [DRBIP] = BIT(31), 70 }; 71 72 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 73 74 static const u32 reg_route_fmask[] = { 75 [ROUTE_DIS] = BIT(0), 76 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 77 [ROUTE_DEF_HDR_TABLE] = BIT(6), 78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 79 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 80 /* Bits 22-23 reserved */ 81 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 82 /* Bits 25-31 reserved */ 83 }; 84 85 REG_FIELDS(ROUTE, route, 0x00000048); 86 87 static const u32 reg_shared_mem_size_fmask[] = { 88 [MEM_SIZE] = GENMASK(15, 0), 89 [MEM_BADDR] = GENMASK(31, 16), 90 }; 91 92 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 93 94 static const u32 reg_qsb_max_writes_fmask[] = { 95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 96 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 97 /* Bits 8-31 reserved */ 98 }; 99 100 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 101 102 static const u32 reg_qsb_max_reads_fmask[] = { 103 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 104 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 105 /* Bits 8-15 reserved */ 106 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 107 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 108 }; 109 110 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 111 112 static const u32 reg_filt_rout_hash_en_fmask[] = { 113 [IPV6_ROUTER_HASH] = BIT(0), 114 /* Bits 1-3 reserved */ 115 [IPV6_FILTER_HASH] = BIT(4), 116 /* Bits 5-7 reserved */ 117 [IPV4_ROUTER_HASH] = BIT(8), 118 /* Bits 9-11 reserved */ 119 [IPV4_FILTER_HASH] = BIT(12), 120 /* Bits 13-31 reserved */ 121 }; 122 123 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 124 125 static const u32 reg_filt_rout_hash_flush_fmask[] = { 126 [IPV6_ROUTER_HASH] = BIT(0), 127 /* Bits 1-3 reserved */ 128 [IPV6_FILTER_HASH] = BIT(4), 129 /* Bits 5-7 reserved */ 130 [IPV4_ROUTER_HASH] = BIT(8), 131 /* Bits 9-11 reserved */ 132 [IPV4_FILTER_HASH] = BIT(12), 133 /* Bits 13-31 reserved */ 134 }; 135 136 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 137 138 /* Valid bits defined by ipa->available */ 139 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); 140 141 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 142 [IPA_BASE_ADDR] = GENMASK(17, 0), 143 /* Bits 18-31 reserved */ 144 }; 145 146 /* Offset must be a multiple of 8 */ 147 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 148 149 /* Valid bits defined by ipa->available */ 150 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 151 152 static const u32 reg_ipa_tx_cfg_fmask[] = { 153 /* Bits 0-1 reserved */ 154 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 155 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 156 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 157 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 158 [PA_MASK_EN] = BIT(12), 159 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 160 [DUAL_TX_ENABLE] = BIT(17), 161 [SSPND_PA_NO_START_STATE] = BIT(18), 162 /* Bits 19-31 reserved */ 163 }; 164 165 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 166 167 static const u32 reg_flavor_0_fmask[] = { 168 [MAX_PIPES] = GENMASK(3, 0), 169 /* Bits 4-7 reserved */ 170 [MAX_CONS_PIPES] = GENMASK(12, 8), 171 /* Bits 13-15 reserved */ 172 [MAX_PROD_PIPES] = GENMASK(20, 16), 173 /* Bits 21-23 reserved */ 174 [PROD_LOWEST] = GENMASK(27, 24), 175 /* Bits 28-31 reserved */ 176 }; 177 178 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 179 180 static const u32 reg_idle_indication_cfg_fmask[] = { 181 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 182 [CONST_NON_IDLE_ENABLE] = BIT(16), 183 /* Bits 17-31 reserved */ 184 }; 185 186 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 187 188 static const u32 reg_qtime_timestamp_cfg_fmask[] = { 189 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 190 /* Bits 5-6 reserved */ 191 [DPL_TIMESTAMP_SEL] = BIT(7), 192 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 193 /* Bits 13-15 reserved */ 194 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 195 /* Bits 21-31 reserved */ 196 }; 197 198 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 199 200 static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { 201 [DIV_VALUE] = GENMASK(8, 0), 202 /* Bits 9-30 reserved */ 203 [DIV_ENABLE] = BIT(31), 204 }; 205 206 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 207 208 static const u32 reg_timers_pulse_gran_cfg_fmask[] = { 209 [PULSE_GRAN_0] = GENMASK(2, 0), 210 [PULSE_GRAN_1] = GENMASK(5, 3), 211 [PULSE_GRAN_2] = GENMASK(8, 6), 212 }; 213 214 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 215 216 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 217 [X_MIN_LIM] = GENMASK(5, 0), 218 /* Bits 6-7 reserved */ 219 [X_MAX_LIM] = GENMASK(13, 8), 220 /* Bits 14-15 reserved */ 221 [Y_MIN_LIM] = GENMASK(21, 16), 222 /* Bits 22-23 reserved */ 223 [Y_MAX_LIM] = GENMASK(29, 24), 224 /* Bits 30-31 reserved */ 225 }; 226 227 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 228 0x00000400, 0x0020); 229 230 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 231 [X_MIN_LIM] = GENMASK(5, 0), 232 /* Bits 6-7 reserved */ 233 [X_MAX_LIM] = GENMASK(13, 8), 234 /* Bits 14-15 reserved */ 235 [Y_MIN_LIM] = GENMASK(21, 16), 236 /* Bits 22-23 reserved */ 237 [Y_MAX_LIM] = GENMASK(29, 24), 238 /* Bits 30-31 reserved */ 239 }; 240 241 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 242 0x00000404, 0x0020); 243 244 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 245 [X_MIN_LIM] = GENMASK(5, 0), 246 /* Bits 6-7 reserved */ 247 [X_MAX_LIM] = GENMASK(13, 8), 248 /* Bits 14-15 reserved */ 249 [Y_MIN_LIM] = GENMASK(21, 16), 250 /* Bits 22-23 reserved */ 251 [Y_MAX_LIM] = GENMASK(29, 24), 252 /* Bits 30-31 reserved */ 253 }; 254 255 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 256 0x00000500, 0x0020); 257 258 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 259 [X_MIN_LIM] = GENMASK(5, 0), 260 /* Bits 6-7 reserved */ 261 [X_MAX_LIM] = GENMASK(13, 8), 262 /* Bits 14-15 reserved */ 263 [Y_MIN_LIM] = GENMASK(21, 16), 264 /* Bits 22-23 reserved */ 265 [Y_MAX_LIM] = GENMASK(29, 24), 266 /* Bits 30-31 reserved */ 267 }; 268 269 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 270 0x00000504, 0x0020); 271 272 static const u32 reg_endp_init_cfg_fmask[] = { 273 [FRAG_OFFLOAD_EN] = BIT(0), 274 [CS_OFFLOAD_EN] = GENMASK(2, 1), 275 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 276 /* Bit 7 reserved */ 277 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 278 /* Bits 9-31 reserved */ 279 }; 280 281 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 282 283 static const u32 reg_endp_init_nat_fmask[] = { 284 [NAT_EN] = GENMASK(1, 0), 285 /* Bits 2-31 reserved */ 286 }; 287 288 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 289 290 static const u32 reg_endp_init_hdr_fmask[] = { 291 [HDR_LEN] = GENMASK(5, 0), 292 [HDR_OFST_METADATA_VALID] = BIT(6), 293 [HDR_OFST_METADATA] = GENMASK(12, 7), 294 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 295 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 296 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 297 [HDR_A5_MUX] = BIT(26), 298 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 299 [HDR_LEN_MSB] = GENMASK(29, 28), 300 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 301 }; 302 303 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 304 305 static const u32 reg_endp_init_hdr_ext_fmask[] = { 306 [HDR_ENDIANNESS] = BIT(0), 307 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 308 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 309 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 310 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 311 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 312 /* Bits 14-15 reserved */ 313 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 314 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 315 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 316 /* Bits 22-31 reserved */ 317 }; 318 319 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 320 321 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 322 0x00000818, 0x0070); 323 324 static const u32 reg_endp_init_mode_fmask[] = { 325 [ENDP_MODE] = GENMASK(2, 0), 326 [DCPH_ENABLE] = BIT(3), 327 [DEST_PIPE_INDEX] = GENMASK(8, 4), 328 /* Bits 9-11 reserved */ 329 [BYTE_THRESHOLD] = GENMASK(27, 12), 330 [PIPE_REPLICATION_EN] = BIT(28), 331 [PAD_EN] = BIT(29), 332 /* Bits 30-31 reserved */ 333 }; 334 335 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 336 337 static const u32 reg_endp_init_aggr_fmask[] = { 338 [AGGR_EN] = GENMASK(1, 0), 339 [AGGR_TYPE] = GENMASK(4, 2), 340 [BYTE_LIMIT] = GENMASK(10, 5), 341 /* Bit 11 reserved */ 342 [TIME_LIMIT] = GENMASK(16, 12), 343 [PKT_LIMIT] = GENMASK(22, 17), 344 [SW_EOF_ACTIVE] = BIT(23), 345 [FORCE_CLOSE] = BIT(24), 346 /* Bit 25 reserved */ 347 [HARD_BYTE_LIMIT_EN] = BIT(26), 348 [AGGR_GRAN_SEL] = BIT(27), 349 /* Bits 28-31 reserved */ 350 }; 351 352 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 353 354 static const u32 reg_endp_init_hol_block_en_fmask[] = { 355 [HOL_BLOCK_EN] = BIT(0), 356 /* Bits 1-31 reserved */ 357 }; 358 359 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 360 0x0000082c, 0x0070); 361 362 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 363 [TIMER_LIMIT] = GENMASK(4, 0), 364 /* Bits 5-7 reserved */ 365 [TIMER_GRAN_SEL] = BIT(8), 366 /* Bits 9-31 reserved */ 367 }; 368 369 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 370 0x00000830, 0x0070); 371 372 static const u32 reg_endp_init_deaggr_fmask[] = { 373 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 374 [SYSPIPE_ERR_DETECTION] = BIT(6), 375 [PACKET_OFFSET_VALID] = BIT(7), 376 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 377 [IGNORE_MIN_PKT_ERR] = BIT(14), 378 /* Bit 15 reserved */ 379 [MAX_PACKET_LEN] = GENMASK(31, 16), 380 }; 381 382 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 383 384 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 385 [ENDP_RSRC_GRP] = BIT(0), 386 /* Bits 1-31 reserved */ 387 }; 388 389 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 390 391 static const u32 reg_endp_init_seq_fmask[] = { 392 [SEQ_TYPE] = GENMASK(7, 0), 393 /* Bits 8-31 reserved */ 394 }; 395 396 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 397 398 static const u32 reg_endp_status_fmask[] = { 399 [STATUS_EN] = BIT(0), 400 [STATUS_ENDP] = GENMASK(5, 1), 401 /* Bits 6-8 reserved */ 402 [STATUS_PKT_SUPPRESS] = BIT(9), 403 /* Bits 10-31 reserved */ 404 }; 405 406 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 407 408 static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 409 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 410 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 411 [FILTER_HASH_MSK_DST_IP] = BIT(2), 412 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 413 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 414 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 415 [FILTER_HASH_MSK_METADATA] = BIT(6), 416 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 417 /* Bits 7-15 reserved */ 418 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 419 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 420 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 421 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 422 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 423 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 424 [ROUTER_HASH_MSK_METADATA] = BIT(22), 425 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 426 /* Bits 23-31 reserved */ 427 }; 428 429 REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 430 0x0000085c, 0x0070); 431 432 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 433 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 434 435 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 436 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 437 438 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 439 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 440 441 static const u32 reg_ipa_irq_uc_fmask[] = { 442 [UC_INTR] = BIT(0), 443 /* Bits 1-31 reserved */ 444 }; 445 446 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 447 448 /* Valid bits defined by ipa->available */ 449 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 450 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 451 452 /* Valid bits defined by ipa->available */ 453 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 454 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 455 456 /* Valid bits defined by ipa->available */ 457 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 458 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 459 460 static const struct reg *reg_array[] = { 461 [COMP_CFG] = ®_comp_cfg, 462 [CLKON_CFG] = ®_clkon_cfg, 463 [ROUTE] = ®_route, 464 [SHARED_MEM_SIZE] = ®_shared_mem_size, 465 [QSB_MAX_WRITES] = ®_qsb_max_writes, 466 [QSB_MAX_READS] = ®_qsb_max_reads, 467 [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, 468 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 469 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 470 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 471 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 472 [IPA_TX_CFG] = ®_ipa_tx_cfg, 473 [FLAVOR_0] = ®_flavor_0, 474 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 475 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, 476 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, 477 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, 478 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 479 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 480 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 481 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 482 [ENDP_INIT_CFG] = ®_endp_init_cfg, 483 [ENDP_INIT_NAT] = ®_endp_init_nat, 484 [ENDP_INIT_HDR] = ®_endp_init_hdr, 485 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 486 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 487 [ENDP_INIT_MODE] = ®_endp_init_mode, 488 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 489 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 490 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 491 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 492 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 493 [ENDP_INIT_SEQ] = ®_endp_init_seq, 494 [ENDP_STATUS] = ®_endp_status, 495 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 496 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 497 [IPA_IRQ_EN] = ®_ipa_irq_en, 498 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 499 [IPA_IRQ_UC] = ®_ipa_irq_uc, 500 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 501 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 502 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 503 }; 504 505 const struct regs ipa_regs_v4_7 = { 506 .reg_count = ARRAY_SIZE(reg_array), 507 .reg = reg_array, 508 }; 509