1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/types.h> 8 9 #include "../ipa_reg.h" 10 #include "../ipa_version.h" 11 12 static const u32 reg_comp_cfg_fmask[] = { 13 /* Bit 0 reserved */ 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 [IPA_DCMP_FAST_CLK_EN] = BIT(4), 18 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 19 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 30 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), 31 /* Bits 21-31 reserved */ 32 }; 33 34 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 35 36 static const u32 reg_clkon_cfg_fmask[] = { 37 [CLKON_RX] = BIT(0), 38 [CLKON_PROC] = BIT(1), 39 [TX_WRAPPER] = BIT(2), 40 [CLKON_MISC] = BIT(3), 41 [RAM_ARB] = BIT(4), 42 [FTCH_HPS] = BIT(5), 43 [FTCH_DPS] = BIT(6), 44 [CLKON_HPS] = BIT(7), 45 [CLKON_DPS] = BIT(8), 46 [RX_HPS_CMDQS] = BIT(9), 47 [HPS_DPS_CMDQS] = BIT(10), 48 [DPS_TX_CMDQS] = BIT(11), 49 [RSRC_MNGR] = BIT(12), 50 [CTX_HANDLER] = BIT(13), 51 [ACK_MNGR] = BIT(14), 52 [D_DCPH] = BIT(15), 53 [H_DCPH] = BIT(16), 54 /* Bit 17 reserved */ 55 [NTF_TX_CMDQS] = BIT(18), 56 [CLKON_TX_0] = BIT(19), 57 [CLKON_TX_1] = BIT(20), 58 [CLKON_FNR] = BIT(21), 59 [QSB2AXI_CMDQ_L] = BIT(22), 60 [AGGR_WRAPPER] = BIT(23), 61 [RAM_SLAVEWAY] = BIT(24), 62 [CLKON_QMB] = BIT(25), 63 [WEIGHT_ARB] = BIT(26), 64 [GSI_IF] = BIT(27), 65 [CLKON_GLOBAL] = BIT(28), 66 [GLOBAL_2X_CLK] = BIT(29), 67 /* Bits 30-31 reserved */ 68 }; 69 70 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 71 72 static const u32 reg_route_fmask[] = { 73 [ROUTE_DIS] = BIT(0), 74 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 75 [ROUTE_DEF_HDR_TABLE] = BIT(6), 76 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 77 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 78 /* Bits 22-23 reserved */ 79 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 80 /* Bits 25-31 reserved */ 81 }; 82 83 REG_FIELDS(ROUTE, route, 0x00000048); 84 85 static const u32 reg_shared_mem_size_fmask[] = { 86 [MEM_SIZE] = GENMASK(15, 0), 87 [MEM_BADDR] = GENMASK(31, 16), 88 }; 89 90 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 91 92 static const u32 reg_qsb_max_writes_fmask[] = { 93 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 94 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 95 /* Bits 8-31 reserved */ 96 }; 97 98 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 99 100 static const u32 reg_qsb_max_reads_fmask[] = { 101 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 102 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 103 /* Bits 8-15 reserved */ 104 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 105 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 106 }; 107 108 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 109 110 static const u32 reg_filt_rout_hash_en_fmask[] = { 111 [IPV6_ROUTER_HASH] = BIT(0), 112 /* Bits 1-3 reserved */ 113 [IPV6_FILTER_HASH] = BIT(4), 114 /* Bits 5-7 reserved */ 115 [IPV4_ROUTER_HASH] = BIT(8), 116 /* Bits 9-11 reserved */ 117 [IPV4_FILTER_HASH] = BIT(12), 118 /* Bits 13-31 reserved */ 119 }; 120 121 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 122 123 static const u32 reg_filt_rout_hash_flush_fmask[] = { 124 [IPV6_ROUTER_HASH] = BIT(0), 125 /* Bits 1-3 reserved */ 126 [IPV6_FILTER_HASH] = BIT(4), 127 /* Bits 5-7 reserved */ 128 [IPV4_ROUTER_HASH] = BIT(8), 129 /* Bits 9-11 reserved */ 130 [IPV4_FILTER_HASH] = BIT(12), 131 /* Bits 13-31 reserved */ 132 }; 133 134 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 135 136 /* Valid bits defined by ipa->available */ 137 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); 138 139 REG(IPA_BCR, ipa_bcr, 0x000001d0); 140 141 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 142 [IPA_BASE_ADDR] = GENMASK(16, 0), 143 /* Bits 17-31 reserved */ 144 }; 145 146 /* Offset must be a multiple of 8 */ 147 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 148 149 /* Valid bits defined by ipa->available */ 150 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 151 152 static const u32 reg_counter_cfg_fmask[] = { 153 /* Bits 0-3 reserved */ 154 [AGGR_GRANULARITY] = GENMASK(8, 4), 155 /* Bits 9-31 reserved */ 156 }; 157 158 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 159 160 static const u32 reg_ipa_tx_cfg_fmask[] = { 161 /* Bits 0-1 reserved */ 162 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 163 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 164 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 165 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 166 [PA_MASK_EN] = BIT(12), 167 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 168 /* Bit 17 reserved */ 169 [SSPND_PA_NO_START_STATE] = BIT(18), 170 [SSPND_PA_NO_BQ_STATE] = BIT(19), 171 /* Bits 20-31 reserved */ 172 }; 173 174 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 175 176 static const u32 reg_flavor_0_fmask[] = { 177 [MAX_PIPES] = GENMASK(3, 0), 178 /* Bits 4-7 reserved */ 179 [MAX_CONS_PIPES] = GENMASK(12, 8), 180 /* Bits 13-15 reserved */ 181 [MAX_PROD_PIPES] = GENMASK(20, 16), 182 /* Bits 21-23 reserved */ 183 [PROD_LOWEST] = GENMASK(27, 24), 184 /* Bits 28-31 reserved */ 185 }; 186 187 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 188 189 static const u32 reg_idle_indication_cfg_fmask[] = { 190 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 191 [CONST_NON_IDLE_ENABLE] = BIT(16), 192 /* Bits 17-31 reserved */ 193 }; 194 195 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 196 197 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 198 [X_MIN_LIM] = GENMASK(5, 0), 199 /* Bits 6-7 reserved */ 200 [X_MAX_LIM] = GENMASK(13, 8), 201 /* Bits 14-15 reserved */ 202 [Y_MIN_LIM] = GENMASK(21, 16), 203 /* Bits 22-23 reserved */ 204 [Y_MAX_LIM] = GENMASK(29, 24), 205 /* Bits 30-31 reserved */ 206 }; 207 208 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 209 0x00000400, 0x0020); 210 211 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 212 [X_MIN_LIM] = GENMASK(5, 0), 213 /* Bits 6-7 reserved */ 214 [X_MAX_LIM] = GENMASK(13, 8), 215 /* Bits 14-15 reserved */ 216 [Y_MIN_LIM] = GENMASK(21, 16), 217 /* Bits 22-23 reserved */ 218 [Y_MAX_LIM] = GENMASK(29, 24), 219 /* Bits 30-31 reserved */ 220 }; 221 222 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 223 0x00000404, 0x0020); 224 225 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 226 [X_MIN_LIM] = GENMASK(5, 0), 227 /* Bits 6-7 reserved */ 228 [X_MAX_LIM] = GENMASK(13, 8), 229 /* Bits 14-15 reserved */ 230 [Y_MIN_LIM] = GENMASK(21, 16), 231 /* Bits 22-23 reserved */ 232 [Y_MAX_LIM] = GENMASK(29, 24), 233 /* Bits 30-31 reserved */ 234 }; 235 236 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 237 0x00000500, 0x0020); 238 239 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 240 [X_MIN_LIM] = GENMASK(5, 0), 241 /* Bits 6-7 reserved */ 242 [X_MAX_LIM] = GENMASK(13, 8), 243 /* Bits 14-15 reserved */ 244 [Y_MIN_LIM] = GENMASK(21, 16), 245 /* Bits 22-23 reserved */ 246 [Y_MAX_LIM] = GENMASK(29, 24), 247 /* Bits 30-31 reserved */ 248 }; 249 250 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 251 0x00000504, 0x0020); 252 253 static const u32 reg_endp_init_cfg_fmask[] = { 254 [FRAG_OFFLOAD_EN] = BIT(0), 255 [CS_OFFLOAD_EN] = GENMASK(2, 1), 256 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 257 /* Bit 7 reserved */ 258 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 259 /* Bits 9-31 reserved */ 260 }; 261 262 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 263 264 static const u32 reg_endp_init_nat_fmask[] = { 265 [NAT_EN] = GENMASK(1, 0), 266 /* Bits 2-31 reserved */ 267 }; 268 269 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 270 271 static const u32 reg_endp_init_hdr_fmask[] = { 272 [HDR_LEN] = GENMASK(5, 0), 273 [HDR_OFST_METADATA_VALID] = BIT(6), 274 [HDR_OFST_METADATA] = GENMASK(12, 7), 275 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 276 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 277 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 278 [HDR_A5_MUX] = BIT(26), 279 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 280 [HDR_METADATA_REG_VALID] = BIT(28), 281 /* Bits 29-31 reserved */ 282 }; 283 284 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 285 286 static const u32 reg_endp_init_hdr_ext_fmask[] = { 287 [HDR_ENDIANNESS] = BIT(0), 288 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 289 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 290 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 291 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 292 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 293 /* Bits 14-31 reserved */ 294 }; 295 296 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 297 298 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 299 0x00000818, 0x0070); 300 301 static const u32 reg_endp_init_mode_fmask[] = { 302 [ENDP_MODE] = GENMASK(2, 0), 303 /* Bit 3 reserved */ 304 [DEST_PIPE_INDEX] = GENMASK(8, 4), 305 /* Bits 9-11 reserved */ 306 [BYTE_THRESHOLD] = GENMASK(27, 12), 307 [PIPE_REPLICATION_EN] = BIT(28), 308 [PAD_EN] = BIT(29), 309 [HDR_FTCH_DISABLE] = BIT(30), 310 /* Bit 31 reserved */ 311 }; 312 313 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 314 315 static const u32 reg_endp_init_aggr_fmask[] = { 316 [AGGR_EN] = GENMASK(1, 0), 317 [AGGR_TYPE] = GENMASK(4, 2), 318 [BYTE_LIMIT] = GENMASK(9, 5), 319 [TIME_LIMIT] = GENMASK(14, 10), 320 [PKT_LIMIT] = GENMASK(20, 15), 321 [SW_EOF_ACTIVE] = BIT(21), 322 [FORCE_CLOSE] = BIT(22), 323 /* Bit 23 reserved */ 324 [HARD_BYTE_LIMIT_EN] = BIT(24), 325 /* Bits 25-31 reserved */ 326 }; 327 328 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 329 330 static const u32 reg_endp_init_hol_block_en_fmask[] = { 331 [HOL_BLOCK_EN] = BIT(0), 332 /* Bits 1-31 reserved */ 333 }; 334 335 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 336 0x0000082c, 0x0070); 337 338 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 339 [TIMER_BASE_VALUE] = GENMASK(4, 0), 340 /* Bits 5-7 reserved */ 341 [TIMER_SCALE] = GENMASK(12, 8), 342 /* Bits 9-31 reserved */ 343 }; 344 345 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 346 0x00000830, 0x0070); 347 348 static const u32 reg_endp_init_deaggr_fmask[] = { 349 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 350 [SYSPIPE_ERR_DETECTION] = BIT(6), 351 [PACKET_OFFSET_VALID] = BIT(7), 352 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 353 [IGNORE_MIN_PKT_ERR] = BIT(14), 354 /* Bit 15 reserved */ 355 [MAX_PACKET_LEN] = GENMASK(31, 16), 356 }; 357 358 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 359 360 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 361 [ENDP_RSRC_GRP] = BIT(0), 362 /* Bits 1-31 reserved */ 363 }; 364 365 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 366 367 static const u32 reg_endp_init_seq_fmask[] = { 368 [SEQ_TYPE] = GENMASK(7, 0), 369 [SEQ_REP_TYPE] = GENMASK(15, 8), 370 /* Bits 16-31 reserved */ 371 }; 372 373 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 374 375 static const u32 reg_endp_status_fmask[] = { 376 [STATUS_EN] = BIT(0), 377 [STATUS_ENDP] = GENMASK(5, 1), 378 /* Bits 6-7 reserved */ 379 [STATUS_LOCATION] = BIT(8), 380 [STATUS_PKT_SUPPRESS] = BIT(9), 381 /* Bits 10-31 reserved */ 382 }; 383 384 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 385 386 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 387 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 388 389 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 390 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 391 392 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 393 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 394 395 static const u32 reg_ipa_irq_uc_fmask[] = { 396 [UC_INTR] = BIT(0), 397 /* Bits 1-31 reserved */ 398 }; 399 400 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 401 402 /* Valid bits defined by ipa->available */ 403 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 404 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 405 406 /* Valid bits defined by ipa->available */ 407 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 408 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 409 410 /* Valid bits defined by ipa->available */ 411 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 412 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 413 414 static const struct reg *reg_array[] = { 415 [COMP_CFG] = ®_comp_cfg, 416 [CLKON_CFG] = ®_clkon_cfg, 417 [ROUTE] = ®_route, 418 [SHARED_MEM_SIZE] = ®_shared_mem_size, 419 [QSB_MAX_WRITES] = ®_qsb_max_writes, 420 [QSB_MAX_READS] = ®_qsb_max_reads, 421 [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, 422 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 423 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 424 [IPA_BCR] = ®_ipa_bcr, 425 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 426 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 427 [COUNTER_CFG] = ®_counter_cfg, 428 [IPA_TX_CFG] = ®_ipa_tx_cfg, 429 [FLAVOR_0] = ®_flavor_0, 430 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 431 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 432 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 433 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 434 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 435 [ENDP_INIT_CFG] = ®_endp_init_cfg, 436 [ENDP_INIT_NAT] = ®_endp_init_nat, 437 [ENDP_INIT_HDR] = ®_endp_init_hdr, 438 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 439 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 440 [ENDP_INIT_MODE] = ®_endp_init_mode, 441 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 442 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 443 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 444 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 445 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 446 [ENDP_INIT_SEQ] = ®_endp_init_seq, 447 [ENDP_STATUS] = ®_endp_status, 448 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 449 [IPA_IRQ_EN] = ®_ipa_irq_en, 450 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 451 [IPA_IRQ_UC] = ®_ipa_irq_uc, 452 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 453 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 454 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 455 }; 456 457 const struct regs ipa_regs_v4_2 = { 458 .reg_count = ARRAY_SIZE(reg_array), 459 .reg = reg_array, 460 }; 461