1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/types.h> 8 9 #include "../ipa_reg.h" 10 #include "../ipa_version.h" 11 12 static const u32 reg_comp_cfg_fmask[] = { 13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 /* Bit 4 reserved */ 18 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 19 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 30 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17), 31 /* Bit 18 reserved */ 32 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19), 33 [GENQMB_AOOOWR] = BIT(20), 34 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21), 35 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(23, 22), 36 /* Bits 24-29 reserved */ 37 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30), 38 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31), 39 }; 40 41 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 42 43 static const u32 reg_clkon_cfg_fmask[] = { 44 [CLKON_RX] = BIT(0), 45 [CLKON_PROC] = BIT(1), 46 [TX_WRAPPER] = BIT(2), 47 [CLKON_MISC] = BIT(3), 48 [RAM_ARB] = BIT(4), 49 [FTCH_HPS] = BIT(5), 50 [FTCH_DPS] = BIT(6), 51 [CLKON_HPS] = BIT(7), 52 [CLKON_DPS] = BIT(8), 53 [RX_HPS_CMDQS] = BIT(9), 54 [HPS_DPS_CMDQS] = BIT(10), 55 [DPS_TX_CMDQS] = BIT(11), 56 [RSRC_MNGR] = BIT(12), 57 [CTX_HANDLER] = BIT(13), 58 [ACK_MNGR] = BIT(14), 59 [D_DCPH] = BIT(15), 60 [H_DCPH] = BIT(16), 61 /* Bit 17 reserved */ 62 [NTF_TX_CMDQS] = BIT(18), 63 [CLKON_TX_0] = BIT(19), 64 [CLKON_TX_1] = BIT(20), 65 [CLKON_FNR] = BIT(21), 66 [QSB2AXI_CMDQ_L] = BIT(22), 67 [AGGR_WRAPPER] = BIT(23), 68 [RAM_SLAVEWAY] = BIT(24), 69 [CLKON_QMB] = BIT(25), 70 [WEIGHT_ARB] = BIT(26), 71 [GSI_IF] = BIT(27), 72 [CLKON_GLOBAL] = BIT(28), 73 [GLOBAL_2X_CLK] = BIT(29), 74 [DPL_FIFO] = BIT(30), 75 [DRBIP] = BIT(31), 76 }; 77 78 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 79 80 static const u32 reg_route_fmask[] = { 81 [ROUTE_DIS] = BIT(0), 82 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 83 [ROUTE_DEF_HDR_TABLE] = BIT(6), 84 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 85 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 86 /* Bits 22-23 reserved */ 87 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 88 /* Bits 25-31 reserved */ 89 }; 90 91 REG_FIELDS(ROUTE, route, 0x00000048); 92 93 static const u32 reg_shared_mem_size_fmask[] = { 94 [MEM_SIZE] = GENMASK(15, 0), 95 [MEM_BADDR] = GENMASK(31, 16), 96 }; 97 98 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 99 100 static const u32 reg_qsb_max_writes_fmask[] = { 101 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 102 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 103 /* Bits 8-31 reserved */ 104 }; 105 106 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 107 108 static const u32 reg_qsb_max_reads_fmask[] = { 109 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 110 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 111 /* Bits 8-15 reserved */ 112 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 113 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 114 }; 115 116 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 117 118 static const u32 reg_filt_rout_hash_en_fmask[] = { 119 [IPV6_ROUTER_HASH] = BIT(0), 120 /* Bits 1-3 reserved */ 121 [IPV6_FILTER_HASH] = BIT(4), 122 /* Bits 5-7 reserved */ 123 [IPV4_ROUTER_HASH] = BIT(8), 124 /* Bits 9-11 reserved */ 125 [IPV4_FILTER_HASH] = BIT(12), 126 /* Bits 13-31 reserved */ 127 }; 128 129 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148); 130 131 static const u32 reg_filt_rout_hash_flush_fmask[] = { 132 [IPV6_ROUTER_HASH] = BIT(0), 133 /* Bits 1-3 reserved */ 134 [IPV6_FILTER_HASH] = BIT(4), 135 /* Bits 5-7 reserved */ 136 [IPV4_ROUTER_HASH] = BIT(8), 137 /* Bits 9-11 reserved */ 138 [IPV4_FILTER_HASH] = BIT(12), 139 /* Bits 13-31 reserved */ 140 }; 141 142 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 143 144 /* Valid bits defined by ipa->available */ 145 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); 146 147 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 148 [IPA_BASE_ADDR] = GENMASK(17, 0), 149 /* Bits 18-31 reserved */ 150 }; 151 152 /* Offset must be a multiple of 8 */ 153 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 154 155 /* Valid bits defined by ipa->available */ 156 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 157 158 static const u32 reg_ipa_tx_cfg_fmask[] = { 159 /* Bits 0-1 reserved */ 160 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 161 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 162 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 163 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 164 [PA_MASK_EN] = BIT(12), 165 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 166 [DUAL_TX_ENABLE] = BIT(17), 167 [SSPND_PA_NO_START_STATE] = BIT(18), 168 /* Bits 19-31 reserved */ 169 }; 170 171 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 172 173 static const u32 reg_flavor_0_fmask[] = { 174 [MAX_PIPES] = GENMASK(4, 0), 175 /* Bits 5-7 reserved */ 176 [MAX_CONS_PIPES] = GENMASK(12, 8), 177 /* Bits 13-15 reserved */ 178 [MAX_PROD_PIPES] = GENMASK(20, 16), 179 /* Bits 21-23 reserved */ 180 [PROD_LOWEST] = GENMASK(27, 24), 181 /* Bits 28-31 reserved */ 182 }; 183 184 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 185 186 static const u32 reg_idle_indication_cfg_fmask[] = { 187 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 188 [CONST_NON_IDLE_ENABLE] = BIT(16), 189 /* Bits 17-31 reserved */ 190 }; 191 192 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 193 194 static const u32 reg_qtime_timestamp_cfg_fmask[] = { 195 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 196 /* Bits 5-6 reserved */ 197 [DPL_TIMESTAMP_SEL] = BIT(7), 198 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 199 /* Bits 13-15 reserved */ 200 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 201 /* Bits 21-31 reserved */ 202 }; 203 204 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 205 206 static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { 207 [DIV_VALUE] = GENMASK(8, 0), 208 /* Bits 9-30 reserved */ 209 [DIV_ENABLE] = BIT(31), 210 }; 211 212 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 213 214 static const u32 reg_timers_pulse_gran_cfg_fmask[] = { 215 [PULSE_GRAN_0] = GENMASK(2, 0), 216 [PULSE_GRAN_1] = GENMASK(5, 3), 217 [PULSE_GRAN_2] = GENMASK(8, 6), 218 /* Bits 9-31 reserved */ 219 }; 220 221 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 222 223 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 224 [X_MIN_LIM] = GENMASK(5, 0), 225 /* Bits 6-7 reserved */ 226 [X_MAX_LIM] = GENMASK(13, 8), 227 /* Bits 14-15 reserved */ 228 [Y_MIN_LIM] = GENMASK(21, 16), 229 /* Bits 22-23 reserved */ 230 [Y_MAX_LIM] = GENMASK(29, 24), 231 /* Bits 30-31 reserved */ 232 }; 233 234 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 235 0x00000400, 0x0020); 236 237 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 238 [X_MIN_LIM] = GENMASK(5, 0), 239 /* Bits 6-7 reserved */ 240 [X_MAX_LIM] = GENMASK(13, 8), 241 /* Bits 14-15 reserved */ 242 [Y_MIN_LIM] = GENMASK(21, 16), 243 /* Bits 22-23 reserved */ 244 [Y_MAX_LIM] = GENMASK(29, 24), 245 /* Bits 30-31 reserved */ 246 }; 247 248 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 249 0x00000404, 0x0020); 250 251 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 252 [X_MIN_LIM] = GENMASK(5, 0), 253 /* Bits 6-7 reserved */ 254 [X_MAX_LIM] = GENMASK(13, 8), 255 /* Bits 14-15 reserved */ 256 [Y_MIN_LIM] = GENMASK(21, 16), 257 /* Bits 22-23 reserved */ 258 [Y_MAX_LIM] = GENMASK(29, 24), 259 /* Bits 30-31 reserved */ 260 }; 261 262 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 263 0x00000500, 0x0020); 264 265 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 266 [X_MIN_LIM] = GENMASK(5, 0), 267 /* Bits 6-7 reserved */ 268 [X_MAX_LIM] = GENMASK(13, 8), 269 /* Bits 14-15 reserved */ 270 [Y_MIN_LIM] = GENMASK(21, 16), 271 /* Bits 22-23 reserved */ 272 [Y_MAX_LIM] = GENMASK(29, 24), 273 /* Bits 30-31 reserved */ 274 }; 275 276 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 277 0x00000504, 0x0020); 278 279 static const u32 reg_endp_init_cfg_fmask[] = { 280 [FRAG_OFFLOAD_EN] = BIT(0), 281 [CS_OFFLOAD_EN] = GENMASK(2, 1), 282 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 283 /* Bit 7 reserved */ 284 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 285 /* Bits 9-31 reserved */ 286 }; 287 288 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 289 290 static const u32 reg_endp_init_nat_fmask[] = { 291 [NAT_EN] = GENMASK(1, 0), 292 /* Bits 2-31 reserved */ 293 }; 294 295 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 296 297 static const u32 reg_endp_init_hdr_fmask[] = { 298 [HDR_LEN] = GENMASK(5, 0), 299 [HDR_OFST_METADATA_VALID] = BIT(6), 300 [HDR_OFST_METADATA] = GENMASK(12, 7), 301 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 302 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 303 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 304 /* Bit 26 reserved */ 305 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 306 [HDR_LEN_MSB] = GENMASK(29, 28), 307 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 308 }; 309 310 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 311 312 static const u32 reg_endp_init_hdr_ext_fmask[] = { 313 [HDR_ENDIANNESS] = BIT(0), 314 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 315 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 316 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 317 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 318 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 319 /* Bits 14-15 reserved */ 320 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 321 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 322 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 323 /* Bits 22-31 reserved */ 324 }; 325 326 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 327 328 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 329 0x00000818, 0x0070); 330 331 static const u32 reg_endp_init_mode_fmask[] = { 332 [ENDP_MODE] = GENMASK(2, 0), 333 [DCPH_ENABLE] = BIT(3), 334 [DEST_PIPE_INDEX] = GENMASK(8, 4), 335 /* Bits 9-11 reserved */ 336 [BYTE_THRESHOLD] = GENMASK(27, 12), 337 [PIPE_REPLICATION_EN] = BIT(28), 338 [PAD_EN] = BIT(29), 339 [DRBIP_ACL_ENABLE] = BIT(30), 340 /* Bit 31 reserved */ 341 }; 342 343 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 344 345 static const u32 reg_endp_init_aggr_fmask[] = { 346 [AGGR_EN] = GENMASK(1, 0), 347 [AGGR_TYPE] = GENMASK(4, 2), 348 [BYTE_LIMIT] = GENMASK(10, 5), 349 /* Bit 11 reserved */ 350 [TIME_LIMIT] = GENMASK(16, 12), 351 [PKT_LIMIT] = GENMASK(22, 17), 352 [SW_EOF_ACTIVE] = BIT(23), 353 [FORCE_CLOSE] = BIT(24), 354 /* Bit 25 reserved */ 355 [HARD_BYTE_LIMIT_EN] = BIT(26), 356 [AGGR_GRAN_SEL] = BIT(27), 357 /* Bits 28-31 reserved */ 358 }; 359 360 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 361 362 static const u32 reg_endp_init_hol_block_en_fmask[] = { 363 [HOL_BLOCK_EN] = BIT(0), 364 /* Bits 1-31 reserved */ 365 }; 366 367 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 368 0x0000082c, 0x0070); 369 370 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 371 [TIMER_LIMIT] = GENMASK(4, 0), 372 /* Bits 5-7 reserved */ 373 [TIMER_GRAN_SEL] = BIT(8), 374 /* Bits 9-31 reserved */ 375 }; 376 377 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 378 0x00000830, 0x0070); 379 380 static const u32 reg_endp_init_deaggr_fmask[] = { 381 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 382 [SYSPIPE_ERR_DETECTION] = BIT(6), 383 [PACKET_OFFSET_VALID] = BIT(7), 384 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 385 [IGNORE_MIN_PKT_ERR] = BIT(14), 386 /* Bit 15 reserved */ 387 [MAX_PACKET_LEN] = GENMASK(31, 16), 388 }; 389 390 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 391 392 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 393 [ENDP_RSRC_GRP] = GENMASK(1, 0), 394 /* Bits 2-31 reserved */ 395 }; 396 397 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 398 399 static const u32 reg_endp_init_seq_fmask[] = { 400 [SEQ_TYPE] = GENMASK(7, 0), 401 /* Bits 8-31 reserved */ 402 }; 403 404 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 405 406 static const u32 reg_endp_status_fmask[] = { 407 [STATUS_EN] = BIT(0), 408 [STATUS_ENDP] = GENMASK(5, 1), 409 /* Bits 6-8 reserved */ 410 [STATUS_PKT_SUPPRESS] = BIT(9), 411 /* Bits 10-31 reserved */ 412 }; 413 414 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 415 416 static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 417 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 418 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 419 [FILTER_HASH_MSK_DST_IP] = BIT(2), 420 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 421 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 422 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 423 [FILTER_HASH_MSK_METADATA] = BIT(6), 424 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 425 /* Bits 7-15 reserved */ 426 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 427 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 428 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 429 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 430 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 431 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 432 [ROUTER_HASH_MSK_METADATA] = BIT(22), 433 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 434 /* Bits 23-31 reserved */ 435 }; 436 437 REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 438 0x0000085c, 0x0070); 439 440 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 441 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP); 442 443 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 444 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP); 445 446 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 447 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP); 448 449 static const u32 reg_ipa_irq_uc_fmask[] = { 450 [UC_INTR] = BIT(0), 451 /* Bits 1-31 reserved */ 452 }; 453 454 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP); 455 456 /* Valid bits defined by ipa->available */ 457 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 458 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004); 459 460 /* Valid bits defined by ipa->available */ 461 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 462 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004); 463 464 /* Valid bits defined by ipa->available */ 465 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 466 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004); 467 468 static const struct reg *reg_array[] = { 469 [COMP_CFG] = ®_comp_cfg, 470 [CLKON_CFG] = ®_clkon_cfg, 471 [ROUTE] = ®_route, 472 [SHARED_MEM_SIZE] = ®_shared_mem_size, 473 [QSB_MAX_WRITES] = ®_qsb_max_writes, 474 [QSB_MAX_READS] = ®_qsb_max_reads, 475 [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, 476 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 477 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 478 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 479 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 480 [IPA_TX_CFG] = ®_ipa_tx_cfg, 481 [FLAVOR_0] = ®_flavor_0, 482 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 483 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, 484 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, 485 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, 486 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 487 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 488 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 489 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 490 [ENDP_INIT_CFG] = ®_endp_init_cfg, 491 [ENDP_INIT_NAT] = ®_endp_init_nat, 492 [ENDP_INIT_HDR] = ®_endp_init_hdr, 493 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 494 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 495 [ENDP_INIT_MODE] = ®_endp_init_mode, 496 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 497 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 498 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 499 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 500 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 501 [ENDP_INIT_SEQ] = ®_endp_init_seq, 502 [ENDP_STATUS] = ®_endp_status, 503 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 504 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 505 [IPA_IRQ_EN] = ®_ipa_irq_en, 506 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 507 [IPA_IRQ_UC] = ®_ipa_irq_uc, 508 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 509 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 510 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 511 }; 512 513 const struct regs ipa_regs_v4_11 = { 514 .reg_count = ARRAY_SIZE(reg_array), 515 .reg = reg_array, 516 }; 517