1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/bits.h> 7 #include <linux/types.h> 8 9 #include "../ipa_reg.h" 10 #include "../ipa_version.h" 11 12 static const u32 reg_comp_cfg_fmask[] = { 13 [COMP_CFG_ENABLE] = BIT(0), 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 [IPA_DCMP_FAST_CLK_EN] = BIT(4), 18 /* Bits 5-31 reserved */ 19 }; 20 21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 22 23 static const u32 reg_clkon_cfg_fmask[] = { 24 [CLKON_RX] = BIT(0), 25 [CLKON_PROC] = BIT(1), 26 [TX_WRAPPER] = BIT(2), 27 [CLKON_MISC] = BIT(3), 28 [RAM_ARB] = BIT(4), 29 [FTCH_HPS] = BIT(5), 30 [FTCH_DPS] = BIT(6), 31 [CLKON_HPS] = BIT(7), 32 [CLKON_DPS] = BIT(8), 33 [RX_HPS_CMDQS] = BIT(9), 34 [HPS_DPS_CMDQS] = BIT(10), 35 [DPS_TX_CMDQS] = BIT(11), 36 [RSRC_MNGR] = BIT(12), 37 [CTX_HANDLER] = BIT(13), 38 [ACK_MNGR] = BIT(14), 39 [D_DCPH] = BIT(15), 40 [H_DCPH] = BIT(16), 41 /* Bit 17 reserved */ 42 [NTF_TX_CMDQS] = BIT(18), 43 [CLKON_TX_0] = BIT(19), 44 [CLKON_TX_1] = BIT(20), 45 [CLKON_FNR] = BIT(21), 46 /* Bits 22-31 reserved */ 47 }; 48 49 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 50 51 static const u32 reg_route_fmask[] = { 52 [ROUTE_DIS] = BIT(0), 53 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 54 [ROUTE_DEF_HDR_TABLE] = BIT(6), 55 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 56 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 57 /* Bits 22-23 reserved */ 58 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 59 /* Bits 25-31 reserved */ 60 }; 61 62 REG_FIELDS(ROUTE, route, 0x00000048); 63 64 static const u32 reg_shared_mem_size_fmask[] = { 65 [MEM_SIZE] = GENMASK(15, 0), 66 [MEM_BADDR] = GENMASK(31, 16), 67 }; 68 69 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 70 71 static const u32 reg_qsb_max_writes_fmask[] = { 72 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 73 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 74 /* Bits 8-31 reserved */ 75 }; 76 77 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 78 79 static const u32 reg_qsb_max_reads_fmask[] = { 80 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 81 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 82 }; 83 84 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 85 86 static const u32 reg_filt_rout_hash_en_fmask[] = { 87 [IPV6_ROUTER_HASH] = BIT(0), 88 /* Bits 1-3 reserved */ 89 [IPV6_FILTER_HASH] = BIT(4), 90 /* Bits 5-7 reserved */ 91 [IPV4_ROUTER_HASH] = BIT(8), 92 /* Bits 9-11 reserved */ 93 [IPV4_FILTER_HASH] = BIT(12), 94 /* Bits 13-31 reserved */ 95 }; 96 97 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); 98 99 static const u32 reg_filt_rout_hash_flush_fmask[] = { 100 [IPV6_ROUTER_HASH] = BIT(0), 101 /* Bits 1-3 reserved */ 102 [IPV6_FILTER_HASH] = BIT(4), 103 /* Bits 5-7 reserved */ 104 [IPV4_ROUTER_HASH] = BIT(8), 105 /* Bits 9-11 reserved */ 106 [IPV4_FILTER_HASH] = BIT(12), 107 /* Bits 13-31 reserved */ 108 }; 109 110 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); 111 112 /* Valid bits defined by ipa->available */ 113 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); 114 115 REG(IPA_BCR, ipa_bcr, 0x000001d0); 116 117 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 118 [IPA_BASE_ADDR] = GENMASK(16, 0), 119 /* Bits 17-31 reserved */ 120 }; 121 122 /* Offset must be a multiple of 8 */ 123 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 124 125 /* Valid bits defined by ipa->available */ 126 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 127 128 static const u32 reg_counter_cfg_fmask[] = { 129 /* Bits 0-3 reserved */ 130 [AGGR_GRANULARITY] = GENMASK(8, 4), 131 /* Bits 5-31 reserved */ 132 }; 133 134 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 135 136 static const u32 reg_ipa_tx_cfg_fmask[] = { 137 [TX0_PREFETCH_DISABLE] = BIT(0), 138 [TX1_PREFETCH_DISABLE] = BIT(1), 139 [PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2), 140 /* Bits 5-31 reserved */ 141 }; 142 143 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 144 145 static const u32 reg_flavor_0_fmask[] = { 146 [MAX_PIPES] = GENMASK(3, 0), 147 /* Bits 4-7 reserved */ 148 [MAX_CONS_PIPES] = GENMASK(12, 8), 149 /* Bits 13-15 reserved */ 150 [MAX_PROD_PIPES] = GENMASK(20, 16), 151 /* Bits 21-23 reserved */ 152 [PROD_LOWEST] = GENMASK(27, 24), 153 /* Bits 28-31 reserved */ 154 }; 155 156 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 157 158 static const u32 reg_idle_indication_cfg_fmask[] = { 159 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 160 [CONST_NON_IDLE_ENABLE] = BIT(16), 161 /* Bits 17-31 reserved */ 162 }; 163 164 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220); 165 166 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 167 [X_MIN_LIM] = GENMASK(5, 0), 168 /* Bits 6-7 reserved */ 169 [X_MAX_LIM] = GENMASK(13, 8), 170 /* Bits 14-15 reserved */ 171 [Y_MIN_LIM] = GENMASK(21, 16), 172 /* Bits 22-23 reserved */ 173 [Y_MAX_LIM] = GENMASK(29, 24), 174 /* Bits 30-31 reserved */ 175 }; 176 177 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 178 0x00000400, 0x0020); 179 180 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 181 [X_MIN_LIM] = GENMASK(5, 0), 182 /* Bits 6-7 reserved */ 183 [X_MAX_LIM] = GENMASK(13, 8), 184 /* Bits 14-15 reserved */ 185 [Y_MIN_LIM] = GENMASK(21, 16), 186 /* Bits 22-23 reserved */ 187 [Y_MAX_LIM] = GENMASK(29, 24), 188 /* Bits 30-31 reserved */ 189 }; 190 191 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 192 0x00000404, 0x0020); 193 194 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 195 [X_MIN_LIM] = GENMASK(5, 0), 196 /* Bits 6-7 reserved */ 197 [X_MAX_LIM] = GENMASK(13, 8), 198 /* Bits 14-15 reserved */ 199 [Y_MIN_LIM] = GENMASK(21, 16), 200 /* Bits 22-23 reserved */ 201 [Y_MAX_LIM] = GENMASK(29, 24), 202 /* Bits 30-31 reserved */ 203 }; 204 205 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 206 0x00000500, 0x0020); 207 208 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 209 [X_MIN_LIM] = GENMASK(5, 0), 210 /* Bits 6-7 reserved */ 211 [X_MAX_LIM] = GENMASK(13, 8), 212 /* Bits 14-15 reserved */ 213 [Y_MIN_LIM] = GENMASK(21, 16), 214 /* Bits 22-23 reserved */ 215 [Y_MAX_LIM] = GENMASK(29, 24), 216 /* Bits 30-31 reserved */ 217 }; 218 219 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 220 0x00000504, 0x0020); 221 222 static const u32 reg_endp_init_ctrl_fmask[] = { 223 [ENDP_SUSPEND] = BIT(0), 224 [ENDP_DELAY] = BIT(1), 225 /* Bits 2-31 reserved */ 226 }; 227 228 REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); 229 230 static const u32 reg_endp_init_cfg_fmask[] = { 231 [FRAG_OFFLOAD_EN] = BIT(0), 232 [CS_OFFLOAD_EN] = GENMASK(2, 1), 233 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 234 /* Bit 7 reserved */ 235 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 236 /* Bits 9-31 reserved */ 237 }; 238 239 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 240 241 static const u32 reg_endp_init_nat_fmask[] = { 242 [NAT_EN] = GENMASK(1, 0), 243 /* Bits 2-31 reserved */ 244 }; 245 246 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 247 248 static const u32 reg_endp_init_hdr_fmask[] = { 249 [HDR_LEN] = GENMASK(5, 0), 250 [HDR_OFST_METADATA_VALID] = BIT(6), 251 [HDR_OFST_METADATA] = GENMASK(12, 7), 252 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 253 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 254 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 255 [HDR_A5_MUX] = BIT(26), 256 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 257 [HDR_METADATA_REG_VALID] = BIT(28), 258 /* Bits 29-31 reserved */ 259 }; 260 261 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 262 263 static const u32 reg_endp_init_hdr_ext_fmask[] = { 264 [HDR_ENDIANNESS] = BIT(0), 265 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 266 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 267 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 268 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 269 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 270 /* Bits 14-31 reserved */ 271 }; 272 273 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 274 275 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 276 0x00000818, 0x0070); 277 278 static const u32 reg_endp_init_mode_fmask[] = { 279 [ENDP_MODE] = GENMASK(2, 0), 280 /* Bit 3 reserved */ 281 [DEST_PIPE_INDEX] = GENMASK(8, 4), 282 /* Bits 9-11 reserved */ 283 [BYTE_THRESHOLD] = GENMASK(27, 12), 284 [PIPE_REPLICATION_EN] = BIT(28), 285 [PAD_EN] = BIT(29), 286 [HDR_FTCH_DISABLE] = BIT(30), 287 /* Bit 31 reserved */ 288 }; 289 290 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 291 292 static const u32 reg_endp_init_aggr_fmask[] = { 293 [AGGR_EN] = GENMASK(1, 0), 294 [AGGR_TYPE] = GENMASK(4, 2), 295 [BYTE_LIMIT] = GENMASK(9, 5), 296 [TIME_LIMIT] = GENMASK(14, 10), 297 [PKT_LIMIT] = GENMASK(20, 15), 298 [SW_EOF_ACTIVE] = BIT(21), 299 [FORCE_CLOSE] = BIT(22), 300 /* Bit 23 reserved */ 301 [HARD_BYTE_LIMIT_EN] = BIT(24), 302 /* Bits 25-31 reserved */ 303 }; 304 305 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 306 307 static const u32 reg_endp_init_hol_block_en_fmask[] = { 308 [HOL_BLOCK_EN] = BIT(0), 309 /* Bits 1-31 reserved */ 310 }; 311 312 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 313 0x0000082c, 0x0070); 314 315 /* Entire register is a tick count */ 316 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 317 [TIMER_BASE_VALUE] = GENMASK(31, 0), 318 }; 319 320 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 321 0x00000830, 0x0070); 322 323 static const u32 reg_endp_init_deaggr_fmask[] = { 324 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 325 [SYSPIPE_ERR_DETECTION] = BIT(6), 326 [PACKET_OFFSET_VALID] = BIT(7), 327 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 328 [IGNORE_MIN_PKT_ERR] = BIT(14), 329 /* Bit 15 reserved */ 330 [MAX_PACKET_LEN] = GENMASK(31, 16), 331 }; 332 333 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 334 335 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 336 [ENDP_RSRC_GRP] = GENMASK(1, 0), 337 /* Bits 2-31 reserved */ 338 }; 339 340 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 341 342 static const u32 reg_endp_init_seq_fmask[] = { 343 [SEQ_TYPE] = GENMASK(7, 0), 344 [SEQ_REP_TYPE] = GENMASK(15, 8), 345 /* Bits 16-31 reserved */ 346 }; 347 348 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 349 350 static const u32 reg_endp_status_fmask[] = { 351 [STATUS_EN] = BIT(0), 352 [STATUS_ENDP] = GENMASK(5, 1), 353 /* Bits 6-7 reserved */ 354 [STATUS_LOCATION] = BIT(8), 355 /* Bits 9-31 reserved */ 356 }; 357 358 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 359 360 static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 361 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 362 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 363 [FILTER_HASH_MSK_DST_IP] = BIT(2), 364 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 365 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 366 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 367 [FILTER_HASH_MSK_METADATA] = BIT(6), 368 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 369 /* Bits 7-15 reserved */ 370 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 371 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 372 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 373 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 374 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 375 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 376 [ROUTER_HASH_MSK_METADATA] = BIT(22), 377 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 378 /* Bits 23-31 reserved */ 379 }; 380 381 REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 382 0x0000085c, 0x0070); 383 384 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 385 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 386 387 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 388 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 389 390 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 391 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 392 393 static const u32 reg_ipa_irq_uc_fmask[] = { 394 [UC_INTR] = BIT(0), 395 /* Bits 1-31 reserved */ 396 }; 397 398 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 399 400 /* Valid bits defined by ipa->available */ 401 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 402 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 403 404 /* Valid bits defined by ipa->available */ 405 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 406 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 407 408 /* Valid bits defined by ipa->available */ 409 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 410 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 411 412 static const struct reg *reg_array[] = { 413 [COMP_CFG] = ®_comp_cfg, 414 [CLKON_CFG] = ®_clkon_cfg, 415 [ROUTE] = ®_route, 416 [SHARED_MEM_SIZE] = ®_shared_mem_size, 417 [QSB_MAX_WRITES] = ®_qsb_max_writes, 418 [QSB_MAX_READS] = ®_qsb_max_reads, 419 [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, 420 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 421 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 422 [IPA_BCR] = ®_ipa_bcr, 423 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 424 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 425 [COUNTER_CFG] = ®_counter_cfg, 426 [IPA_TX_CFG] = ®_ipa_tx_cfg, 427 [FLAVOR_0] = ®_flavor_0, 428 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 429 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 430 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 431 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 432 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 433 [ENDP_INIT_CTRL] = ®_endp_init_ctrl, 434 [ENDP_INIT_CFG] = ®_endp_init_cfg, 435 [ENDP_INIT_NAT] = ®_endp_init_nat, 436 [ENDP_INIT_HDR] = ®_endp_init_hdr, 437 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 438 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 439 [ENDP_INIT_MODE] = ®_endp_init_mode, 440 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 441 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 442 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 443 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 444 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 445 [ENDP_INIT_SEQ] = ®_endp_init_seq, 446 [ENDP_STATUS] = ®_endp_status, 447 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 448 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 449 [IPA_IRQ_EN] = ®_ipa_irq_en, 450 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 451 [IPA_IRQ_UC] = ®_ipa_irq_uc, 452 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 453 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 454 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 455 }; 456 457 const struct regs ipa_regs_v3_5_1 = { 458 .reg_count = ARRAY_SIZE(reg_array), 459 .reg = reg_array, 460 }; 461