1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022 Linaro Ltd. */ 4 5 #include <linux/types.h> 6 7 #include "../ipa.h" 8 #include "../ipa_reg.h" 9 10 static const u32 reg_comp_cfg_fmask[] = { 11 [COMP_CFG_ENABLE] = BIT(0), 12 [GSI_SNOC_BYPASS_DIS] = BIT(1), 13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 15 [IPA_DCMP_FAST_CLK_EN] = BIT(4), 16 /* Bits 5-31 reserved */ 17 }; 18 19 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 20 21 static const u32 reg_clkon_cfg_fmask[] = { 22 [CLKON_RX] = BIT(0), 23 [CLKON_PROC] = BIT(1), 24 [TX_WRAPPER] = BIT(2), 25 [CLKON_MISC] = BIT(3), 26 [RAM_ARB] = BIT(4), 27 [FTCH_HPS] = BIT(5), 28 [FTCH_DPS] = BIT(6), 29 [CLKON_HPS] = BIT(7), 30 [CLKON_DPS] = BIT(8), 31 [RX_HPS_CMDQS] = BIT(9), 32 [HPS_DPS_CMDQS] = BIT(10), 33 [DPS_TX_CMDQS] = BIT(11), 34 [RSRC_MNGR] = BIT(12), 35 [CTX_HANDLER] = BIT(13), 36 [ACK_MNGR] = BIT(14), 37 [D_DCPH] = BIT(15), 38 [H_DCPH] = BIT(16), 39 /* Bit 17 reserved */ 40 [NTF_TX_CMDQS] = BIT(18), 41 [CLKON_TX_0] = BIT(19), 42 [CLKON_TX_1] = BIT(20), 43 [CLKON_FNR] = BIT(21), 44 /* Bits 22-31 reserved */ 45 }; 46 47 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 48 49 static const u32 reg_route_fmask[] = { 50 [ROUTE_DIS] = BIT(0), 51 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 52 [ROUTE_DEF_HDR_TABLE] = BIT(6), 53 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 54 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 55 /* Bits 22-23 reserved */ 56 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 57 /* Bits 25-31 reserved */ 58 }; 59 60 REG_FIELDS(ROUTE, route, 0x00000048); 61 62 static const u32 reg_shared_mem_size_fmask[] = { 63 [MEM_SIZE] = GENMASK(15, 0), 64 [MEM_BADDR] = GENMASK(31, 16), 65 }; 66 67 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 68 69 static const u32 reg_qsb_max_writes_fmask[] = { 70 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 71 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 72 /* Bits 8-31 reserved */ 73 }; 74 75 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 76 77 static const u32 reg_qsb_max_reads_fmask[] = { 78 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 79 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 80 }; 81 82 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 83 84 static const u32 reg_filt_rout_hash_en_fmask[] = { 85 [IPV6_ROUTER_HASH] = BIT(0), 86 /* Bits 1-3 reserved */ 87 [IPV6_FILTER_HASH] = BIT(4), 88 /* Bits 5-7 reserved */ 89 [IPV4_ROUTER_HASH] = BIT(8), 90 /* Bits 9-11 reserved */ 91 [IPV4_FILTER_HASH] = BIT(12), 92 /* Bits 13-31 reserved */ 93 }; 94 95 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c); 96 97 static const u32 reg_filt_rout_hash_flush_fmask[] = { 98 [IPV6_ROUTER_HASH] = BIT(0), 99 /* Bits 1-3 reserved */ 100 [IPV6_FILTER_HASH] = BIT(4), 101 /* Bits 5-7 reserved */ 102 [IPV4_ROUTER_HASH] = BIT(8), 103 /* Bits 9-11 reserved */ 104 [IPV4_FILTER_HASH] = BIT(12), 105 /* Bits 13-31 reserved */ 106 }; 107 108 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); 109 110 /* Valid bits defined by ipa->available */ 111 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); 112 113 REG(IPA_BCR, ipa_bcr, 0x000001d0); 114 115 static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 116 [IPA_BASE_ADDR] = GENMASK(16, 0), 117 /* Bits 17-31 reserved */ 118 }; 119 120 /* Offset must be a multiple of 8 */ 121 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 122 123 /* Valid bits defined by ipa->available */ 124 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 125 126 static const u32 reg_counter_cfg_fmask[] = { 127 /* Bits 0-3 reserved */ 128 [AGGR_GRANULARITY] = GENMASK(8, 4), 129 /* Bits 5-31 reserved */ 130 }; 131 132 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 133 134 static const u32 reg_ipa_tx_cfg_fmask[] = { 135 [TX0_PREFETCH_DISABLE] = BIT(0), 136 [TX1_PREFETCH_DISABLE] = BIT(1), 137 [PREFETCH_ALMOST_EMPTY_SIZE] = GENMASK(4, 2), 138 /* Bits 5-31 reserved */ 139 }; 140 141 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 142 143 static const u32 reg_flavor_0_fmask[] = { 144 [MAX_PIPES] = GENMASK(3, 0), 145 /* Bits 4-7 reserved */ 146 [MAX_CONS_PIPES] = GENMASK(12, 8), 147 /* Bits 13-15 reserved */ 148 [MAX_PROD_PIPES] = GENMASK(20, 16), 149 /* Bits 21-23 reserved */ 150 [PROD_LOWEST] = GENMASK(27, 24), 151 /* Bits 28-31 reserved */ 152 }; 153 154 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 155 156 static const u32 reg_idle_indication_cfg_fmask[] = { 157 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 158 [CONST_NON_IDLE_ENABLE] = BIT(16), 159 /* Bits 17-31 reserved */ 160 }; 161 162 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220); 163 164 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 165 [X_MIN_LIM] = GENMASK(5, 0), 166 /* Bits 6-7 reserved */ 167 [X_MAX_LIM] = GENMASK(13, 8), 168 /* Bits 14-15 reserved */ 169 [Y_MIN_LIM] = GENMASK(21, 16), 170 /* Bits 22-23 reserved */ 171 [Y_MAX_LIM] = GENMASK(29, 24), 172 /* Bits 30-31 reserved */ 173 }; 174 175 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 176 0x00000400, 0x0020); 177 178 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 179 [X_MIN_LIM] = GENMASK(5, 0), 180 /* Bits 6-7 reserved */ 181 [X_MAX_LIM] = GENMASK(13, 8), 182 /* Bits 14-15 reserved */ 183 [Y_MIN_LIM] = GENMASK(21, 16), 184 /* Bits 22-23 reserved */ 185 [Y_MAX_LIM] = GENMASK(29, 24), 186 /* Bits 30-31 reserved */ 187 }; 188 189 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 190 0x00000404, 0x0020); 191 192 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 193 [X_MIN_LIM] = GENMASK(5, 0), 194 /* Bits 6-7 reserved */ 195 [X_MAX_LIM] = GENMASK(13, 8), 196 /* Bits 14-15 reserved */ 197 [Y_MIN_LIM] = GENMASK(21, 16), 198 /* Bits 22-23 reserved */ 199 [Y_MAX_LIM] = GENMASK(29, 24), 200 /* Bits 30-31 reserved */ 201 }; 202 203 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 204 0x00000500, 0x0020); 205 206 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 207 [X_MIN_LIM] = GENMASK(5, 0), 208 /* Bits 6-7 reserved */ 209 [X_MAX_LIM] = GENMASK(13, 8), 210 /* Bits 14-15 reserved */ 211 [Y_MIN_LIM] = GENMASK(21, 16), 212 /* Bits 22-23 reserved */ 213 [Y_MAX_LIM] = GENMASK(29, 24), 214 /* Bits 30-31 reserved */ 215 }; 216 217 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 218 0x00000504, 0x0020); 219 220 static const u32 reg_endp_init_ctrl_fmask[] = { 221 [ENDP_SUSPEND] = BIT(0), 222 [ENDP_DELAY] = BIT(1), 223 /* Bits 2-31 reserved */ 224 }; 225 226 REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); 227 228 static const u32 reg_endp_init_cfg_fmask[] = { 229 [FRAG_OFFLOAD_EN] = BIT(0), 230 [CS_OFFLOAD_EN] = GENMASK(2, 1), 231 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 232 /* Bit 7 reserved */ 233 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 234 /* Bits 9-31 reserved */ 235 }; 236 237 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 238 239 static const u32 reg_endp_init_nat_fmask[] = { 240 [NAT_EN] = GENMASK(1, 0), 241 /* Bits 2-31 reserved */ 242 }; 243 244 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 245 246 static const u32 reg_endp_init_hdr_fmask[] = { 247 [HDR_LEN] = GENMASK(5, 0), 248 [HDR_OFST_METADATA_VALID] = BIT(6), 249 [HDR_OFST_METADATA] = GENMASK(12, 7), 250 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 251 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 252 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 253 [HDR_A5_MUX] = BIT(26), 254 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 255 [HDR_METADATA_REG_VALID] = BIT(28), 256 /* Bits 29-31 reserved */ 257 }; 258 259 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 260 261 static const u32 reg_endp_init_hdr_ext_fmask[] = { 262 [HDR_ENDIANNESS] = BIT(0), 263 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 264 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 265 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 266 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 267 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 268 /* Bits 14-31 reserved */ 269 }; 270 271 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 272 273 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 274 0x00000818, 0x0070); 275 276 static const u32 reg_endp_init_mode_fmask[] = { 277 [ENDP_MODE] = GENMASK(2, 0), 278 /* Bit 3 reserved */ 279 [DEST_PIPE_INDEX] = GENMASK(8, 4), 280 /* Bits 9-11 reserved */ 281 [BYTE_THRESHOLD] = GENMASK(27, 12), 282 [PIPE_REPLICATION_EN] = BIT(28), 283 [PAD_EN] = BIT(29), 284 [HDR_FTCH_DISABLE] = BIT(30), 285 /* Bit 31 reserved */ 286 }; 287 288 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 289 290 static const u32 reg_endp_init_aggr_fmask[] = { 291 [AGGR_EN] = GENMASK(1, 0), 292 [AGGR_TYPE] = GENMASK(4, 2), 293 [BYTE_LIMIT] = GENMASK(9, 5), 294 [TIME_LIMIT] = GENMASK(14, 10), 295 [PKT_LIMIT] = GENMASK(20, 15), 296 [SW_EOF_ACTIVE] = BIT(21), 297 [FORCE_CLOSE] = BIT(22), 298 /* Bit 23 reserved */ 299 [HARD_BYTE_LIMIT_EN] = BIT(24), 300 /* Bits 25-31 reserved */ 301 }; 302 303 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 304 305 static const u32 reg_endp_init_hol_block_en_fmask[] = { 306 [HOL_BLOCK_EN] = BIT(0), 307 /* Bits 1-31 reserved */ 308 }; 309 310 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 311 0x0000082c, 0x0070); 312 313 /* Entire register is a tick count */ 314 static const u32 reg_endp_init_hol_block_timer_fmask[] = { 315 [TIMER_BASE_VALUE] = GENMASK(31, 0), 316 }; 317 318 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 319 0x00000830, 0x0070); 320 321 static const u32 reg_endp_init_deaggr_fmask[] = { 322 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 323 [SYSPIPE_ERR_DETECTION] = BIT(6), 324 [PACKET_OFFSET_VALID] = BIT(7), 325 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 326 [IGNORE_MIN_PKT_ERR] = BIT(14), 327 /* Bit 15 reserved */ 328 [MAX_PACKET_LEN] = GENMASK(31, 16), 329 }; 330 331 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 332 333 static const u32 reg_endp_init_rsrc_grp_fmask[] = { 334 [ENDP_RSRC_GRP] = GENMASK(1, 0), 335 /* Bits 2-31 reserved */ 336 }; 337 338 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 339 340 static const u32 reg_endp_init_seq_fmask[] = { 341 [SEQ_TYPE] = GENMASK(7, 0), 342 [SEQ_REP_TYPE] = GENMASK(15, 8), 343 /* Bits 16-31 reserved */ 344 }; 345 346 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 347 348 static const u32 reg_endp_status_fmask[] = { 349 [STATUS_EN] = BIT(0), 350 [STATUS_ENDP] = GENMASK(5, 1), 351 /* Bits 6-7 reserved */ 352 [STATUS_LOCATION] = BIT(8), 353 /* Bits 9-31 reserved */ 354 }; 355 356 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 357 358 static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 359 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 360 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 361 [FILTER_HASH_MSK_DST_IP] = BIT(2), 362 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 363 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 364 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 365 [FILTER_HASH_MSK_METADATA] = BIT(6), 366 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 367 /* Bits 7-15 reserved */ 368 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 369 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 370 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 371 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 372 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 373 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 374 [ROUTER_HASH_MSK_METADATA] = BIT(22), 375 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 376 /* Bits 23-31 reserved */ 377 }; 378 379 REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 380 0x0000085c, 0x0070); 381 382 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 383 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 384 385 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 386 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 387 388 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 389 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 390 391 static const u32 reg_ipa_irq_uc_fmask[] = { 392 [UC_INTR] = BIT(0), 393 /* Bits 1-31 reserved */ 394 }; 395 396 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 397 398 /* Valid bits defined by ipa->available */ 399 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 400 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 401 402 /* Valid bits defined by ipa->available */ 403 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 404 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 405 406 /* Valid bits defined by ipa->available */ 407 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 408 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 409 410 static const struct reg *reg_array[] = { 411 [COMP_CFG] = ®_comp_cfg, 412 [CLKON_CFG] = ®_clkon_cfg, 413 [ROUTE] = ®_route, 414 [SHARED_MEM_SIZE] = ®_shared_mem_size, 415 [QSB_MAX_WRITES] = ®_qsb_max_writes, 416 [QSB_MAX_READS] = ®_qsb_max_reads, 417 [FILT_ROUT_HASH_EN] = ®_filt_rout_hash_en, 418 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 419 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 420 [IPA_BCR] = ®_ipa_bcr, 421 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 422 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 423 [COUNTER_CFG] = ®_counter_cfg, 424 [IPA_TX_CFG] = ®_ipa_tx_cfg, 425 [FLAVOR_0] = ®_flavor_0, 426 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 427 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 428 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 429 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 430 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 431 [ENDP_INIT_CTRL] = ®_endp_init_ctrl, 432 [ENDP_INIT_CFG] = ®_endp_init_cfg, 433 [ENDP_INIT_NAT] = ®_endp_init_nat, 434 [ENDP_INIT_HDR] = ®_endp_init_hdr, 435 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 436 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 437 [ENDP_INIT_MODE] = ®_endp_init_mode, 438 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 439 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 440 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 441 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 442 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 443 [ENDP_INIT_SEQ] = ®_endp_init_seq, 444 [ENDP_STATUS] = ®_endp_status, 445 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 446 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 447 [IPA_IRQ_EN] = ®_ipa_irq_en, 448 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 449 [IPA_IRQ_UC] = ®_ipa_irq_uc, 450 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 451 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 452 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 453 }; 454 455 const struct regs ipa_regs_v3_5_1 = { 456 .reg_count = ARRAY_SIZE(reg_array), 457 .reg = reg_array, 458 }; 459