xref: /linux/drivers/net/ipa/reg/ipa_reg-v3.1.c (revision 9fc31a9251de4acaab2d0704450d70ddc99f5ea2) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
4 
5 #include <linux/array_size.h>
6 #include <linux/bits.h>
7 #include <linux/types.h>
8 
9 #include "../ipa_reg.h"
10 #include "../ipa_version.h"
11 
12 static const u32 reg_comp_cfg_fmask[] = {
13 	[COMP_CFG_ENABLE]				= BIT(0),
14 	[GSI_SNOC_BYPASS_DIS]				= BIT(1),
15 	[GEN_QMB_0_SNOC_BYPASS_DIS]			= BIT(2),
16 	[GEN_QMB_1_SNOC_BYPASS_DIS]			= BIT(3),
17 	[IPA_DCMP_FAST_CLK_EN]				= BIT(4),
18 						/* Bits 5-31 reserved */
19 };
20 
21 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
22 
23 static const u32 reg_clkon_cfg_fmask[] = {
24 	[CLKON_RX]					= BIT(0),
25 	[CLKON_PROC]					= BIT(1),
26 	[TX_WRAPPER]					= BIT(2),
27 	[CLKON_MISC]					= BIT(3),
28 	[RAM_ARB]					= BIT(4),
29 	[FTCH_HPS]					= BIT(5),
30 	[FTCH_DPS]					= BIT(6),
31 	[CLKON_HPS]					= BIT(7),
32 	[CLKON_DPS]					= BIT(8),
33 	[RX_HPS_CMDQS]					= BIT(9),
34 	[HPS_DPS_CMDQS]					= BIT(10),
35 	[DPS_TX_CMDQS]					= BIT(11),
36 	[RSRC_MNGR]					= BIT(12),
37 	[CTX_HANDLER]					= BIT(13),
38 	[ACK_MNGR]					= BIT(14),
39 	[D_DCPH]					= BIT(15),
40 	[H_DCPH]					= BIT(16),
41 						/* Bits 17-31 reserved */
42 };
43 
44 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
45 
46 static const u32 reg_route_fmask[] = {
47 	[ROUTE_DIS]					= BIT(0),
48 	[ROUTE_DEF_PIPE]				= GENMASK(5, 1),
49 	[ROUTE_DEF_HDR_TABLE]				= BIT(6),
50 	[ROUTE_DEF_HDR_OFST]				= GENMASK(16, 7),
51 	[ROUTE_FRAG_DEF_PIPE]				= GENMASK(21, 17),
52 						/* Bits 22-23 reserved */
53 	[ROUTE_DEF_RETAIN_HDR]				= BIT(24),
54 						/* Bits 25-31 reserved */
55 };
56 
57 REG_FIELDS(ROUTE, route, 0x00000048);
58 
59 static const u32 reg_shared_mem_size_fmask[] = {
60 	[MEM_SIZE]					= GENMASK(15, 0),
61 	[MEM_BADDR]					= GENMASK(31, 16),
62 };
63 
64 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
65 
66 static const u32 reg_qsb_max_writes_fmask[] = {
67 	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),
68 	[GEN_QMB_1_MAX_WRITES]				= GENMASK(7, 4),
69 						/* Bits 8-31 reserved */
70 };
71 
72 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
73 
74 static const u32 reg_qsb_max_reads_fmask[] = {
75 	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),
76 	[GEN_QMB_1_MAX_READS]				= GENMASK(7, 4),
77 };
78 
79 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
80 
81 static const u32 reg_filt_rout_hash_en_fmask[] = {
82 	[IPV6_ROUTER_HASH]				= BIT(0),
83 						/* Bits 1-3 reserved */
84 	[IPV6_FILTER_HASH]				= BIT(4),
85 						/* Bits 5-7 reserved */
86 	[IPV4_ROUTER_HASH]				= BIT(8),
87 						/* Bits 9-11 reserved */
88 	[IPV4_FILTER_HASH]				= BIT(12),
89 						/* Bits 13-31 reserved */
90 };
91 
92 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x000008c);
93 
94 static const u32 reg_filt_rout_hash_flush_fmask[] = {
95 	[IPV6_ROUTER_HASH]				= BIT(0),
96 						/* Bits 1-3 reserved */
97 	[IPV6_FILTER_HASH]				= BIT(4),
98 						/* Bits 5-7 reserved */
99 	[IPV4_ROUTER_HASH]				= BIT(8),
100 						/* Bits 9-11 reserved */
101 	[IPV4_FILTER_HASH]				= BIT(12),
102 						/* Bits 13-31 reserved */
103 };
104 
105 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090);
106 
107 /* Valid bits defined by ipa->available */
108 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004);
109 
110 REG(IPA_BCR, ipa_bcr, 0x000001d0);
111 
112 static const u32 reg_local_pkt_proc_cntxt_fmask[] = {
113 	[IPA_BASE_ADDR]					= GENMASK(16, 0),
114 						/* Bits 17-31 reserved */
115 };
116 
117 /* Offset must be a multiple of 8 */
118 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
119 
120 /* Valid bits defined by ipa->available */
121 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
122 
123 static const u32 reg_counter_cfg_fmask[] = {
124 	[EOT_COAL_GRANULARITY]				= GENMASK(3, 0),
125 	[AGGR_GRANULARITY]				= GENMASK(8, 4),
126 						/* Bits 5-31 reserved */
127 };
128 
129 REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
130 
131 static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = {
132 	[X_MIN_LIM]					= GENMASK(7, 0),
133 	[X_MAX_LIM]					= GENMASK(15, 8),
134 	[Y_MIN_LIM]					= GENMASK(23, 16),
135 	[Y_MAX_LIM]					= GENMASK(31, 24),
136 };
137 
138 REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,
139 		  0x00000400, 0x0020);
140 
141 static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = {
142 	[X_MIN_LIM]					= GENMASK(7, 0),
143 	[X_MAX_LIM]					= GENMASK(15, 8),
144 	[Y_MIN_LIM]					= GENMASK(23, 16),
145 	[Y_MAX_LIM]					= GENMASK(31, 24),
146 };
147 
148 REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type,
149 		  0x00000404, 0x0020);
150 
151 static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = {
152 	[X_MIN_LIM]					= GENMASK(7, 0),
153 	[X_MAX_LIM]					= GENMASK(15, 8),
154 	[Y_MIN_LIM]					= GENMASK(23, 16),
155 	[Y_MAX_LIM]					= GENMASK(31, 24),
156 };
157 
158 REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type,
159 		  0x00000408, 0x0020);
160 
161 static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = {
162 	[X_MIN_LIM]					= GENMASK(7, 0),
163 	[X_MAX_LIM]					= GENMASK(15, 8),
164 	[Y_MIN_LIM]					= GENMASK(23, 16),
165 	[Y_MAX_LIM]					= GENMASK(31, 24),
166 };
167 
168 REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type,
169 		  0x0000040c, 0x0020);
170 
171 static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = {
172 	[X_MIN_LIM]					= GENMASK(7, 0),
173 	[X_MAX_LIM]					= GENMASK(15, 8),
174 	[Y_MIN_LIM]					= GENMASK(23, 16),
175 	[Y_MAX_LIM]					= GENMASK(31, 24),
176 };
177 
178 REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type,
179 		  0x00000500, 0x0020);
180 
181 static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = {
182 	[X_MIN_LIM]					= GENMASK(7, 0),
183 	[X_MAX_LIM]					= GENMASK(15, 8),
184 	[Y_MIN_LIM]					= GENMASK(23, 16),
185 	[Y_MAX_LIM]					= GENMASK(31, 24),
186 };
187 
188 REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type,
189 		  0x00000504, 0x0020);
190 
191 static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = {
192 	[X_MIN_LIM]					= GENMASK(7, 0),
193 	[X_MAX_LIM]					= GENMASK(15, 8),
194 	[Y_MIN_LIM]					= GENMASK(23, 16),
195 	[Y_MAX_LIM]					= GENMASK(31, 24),
196 };
197 
198 REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type,
199 		  0x00000508, 0x0020);
200 
201 static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = {
202 	[X_MIN_LIM]					= GENMASK(7, 0),
203 	[X_MAX_LIM]					= GENMASK(15, 8),
204 	[Y_MIN_LIM]					= GENMASK(23, 16),
205 	[Y_MAX_LIM]					= GENMASK(31, 24),
206 };
207 
208 REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type,
209 		  0x0000050c, 0x0020);
210 
211 static const u32 reg_endp_init_ctrl_fmask[] = {
212 	[ENDP_SUSPEND]					= BIT(0),
213 	[ENDP_DELAY]					= BIT(1),
214 						/* Bits 2-31 reserved */
215 };
216 
217 REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070);
218 
219 static const u32 reg_endp_init_cfg_fmask[] = {
220 	[FRAG_OFFLOAD_EN]				= BIT(0),
221 	[CS_OFFLOAD_EN]					= GENMASK(2, 1),
222 	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),
223 						/* Bit 7 reserved */
224 	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),
225 						/* Bits 9-31 reserved */
226 };
227 
228 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
229 
230 static const u32 reg_endp_init_nat_fmask[] = {
231 	[NAT_EN]					= GENMASK(1, 0),
232 						/* Bits 2-31 reserved */
233 };
234 
235 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
236 
237 static const u32 reg_endp_init_hdr_fmask[] = {
238 	[HDR_LEN]					= GENMASK(5, 0),
239 	[HDR_OFST_METADATA_VALID]			= BIT(6),
240 	[HDR_OFST_METADATA]				= GENMASK(12, 7),
241 	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),
242 	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),
243 	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),
244 	[HDR_A5_MUX]					= BIT(26),
245 	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),
246 	[HDR_METADATA_REG_VALID]			= BIT(28),
247 						/* Bits 29-31 reserved */
248 };
249 
250 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
251 
252 static const u32 reg_endp_init_hdr_ext_fmask[] = {
253 	[HDR_ENDIANNESS]				= BIT(0),
254 	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),
255 	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),
256 	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),
257 	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),
258 	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),
259 						/* Bits 14-31 reserved */
260 };
261 
262 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
263 
264 REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask,
265 	   0x00000818, 0x0070);
266 
267 static const u32 reg_endp_init_mode_fmask[] = {
268 	[ENDP_MODE]					= GENMASK(2, 0),
269 						/* Bit 3 reserved */
270 	[DEST_PIPE_INDEX]				= GENMASK(8, 4),
271 						/* Bits 9-11 reserved */
272 	[BYTE_THRESHOLD]				= GENMASK(27, 12),
273 	[PIPE_REPLICATION_EN]				= BIT(28),
274 	[PAD_EN]					= BIT(29),
275 	[HDR_FTCH_DISABLE]				= BIT(30),
276 						/* Bit 31 reserved */
277 };
278 
279 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
280 
281 static const u32 reg_endp_init_aggr_fmask[] = {
282 	[AGGR_EN]					= GENMASK(1, 0),
283 	[AGGR_TYPE]					= GENMASK(4, 2),
284 	[BYTE_LIMIT]					= GENMASK(9, 5),
285 	[TIME_LIMIT]					= GENMASK(14, 10),
286 	[PKT_LIMIT]					= GENMASK(20, 15),
287 	[SW_EOF_ACTIVE]					= BIT(21),
288 	[FORCE_CLOSE]					= BIT(22),
289 						/* Bit 23 reserved */
290 	[HARD_BYTE_LIMIT_EN]				= BIT(24),
291 						/* Bits 25-31 reserved */
292 };
293 
294 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
295 
296 static const u32 reg_endp_init_hol_block_en_fmask[] = {
297 	[HOL_BLOCK_EN]					= BIT(0),
298 						/* Bits 1-31 reserved */
299 };
300 
301 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en,
302 		  0x0000082c, 0x0070);
303 
304 /* Entire register is a tick count */
305 static const u32 reg_endp_init_hol_block_timer_fmask[] = {
306 	[TIMER_BASE_VALUE]				= GENMASK(31, 0),
307 };
308 
309 REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer,
310 		  0x00000830, 0x0070);
311 
312 static const u32 reg_endp_init_deaggr_fmask[] = {
313 	[DEAGGR_HDR_LEN]				= GENMASK(5, 0),
314 	[SYSPIPE_ERR_DETECTION]				= BIT(6),
315 	[PACKET_OFFSET_VALID]				= BIT(7),
316 	[PACKET_OFFSET_LOCATION]			= GENMASK(13, 8),
317 	[IGNORE_MIN_PKT_ERR]				= BIT(14),
318 						/* Bit 15 reserved */
319 	[MAX_PACKET_LEN]				= GENMASK(31, 16),
320 };
321 
322 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
323 
324 static const u32 reg_endp_init_rsrc_grp_fmask[] = {
325 	[ENDP_RSRC_GRP]					= GENMASK(2, 0),
326 						/* Bits 3-31 reserved */
327 };
328 
329 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
330 
331 static const u32 reg_endp_init_seq_fmask[] = {
332 	[SEQ_TYPE]					= GENMASK(7, 0),
333 	[SEQ_REP_TYPE]					= GENMASK(15, 8),
334 						/* Bits 16-31 reserved */
335 };
336 
337 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
338 
339 static const u32 reg_endp_status_fmask[] = {
340 	[STATUS_EN]					= BIT(0),
341 	[STATUS_ENDP]					= GENMASK(5, 1),
342 						/* Bits 6-7 reserved */
343 	[STATUS_LOCATION]				= BIT(8),
344 						/* Bits 9-31 reserved */
345 };
346 
347 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
348 
349 static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = {
350 	[FILTER_HASH_MSK_SRC_ID]			= BIT(0),
351 	[FILTER_HASH_MSK_SRC_IP]			= BIT(1),
352 	[FILTER_HASH_MSK_DST_IP]			= BIT(2),
353 	[FILTER_HASH_MSK_SRC_PORT]			= BIT(3),
354 	[FILTER_HASH_MSK_DST_PORT]			= BIT(4),
355 	[FILTER_HASH_MSK_PROTOCOL]			= BIT(5),
356 	[FILTER_HASH_MSK_METADATA]			= BIT(6),
357 	[FILTER_HASH_MSK_ALL]				= GENMASK(6, 0),
358 						/* Bits 7-15 reserved */
359 	[ROUTER_HASH_MSK_SRC_ID]			= BIT(16),
360 	[ROUTER_HASH_MSK_SRC_IP]			= BIT(17),
361 	[ROUTER_HASH_MSK_DST_IP]			= BIT(18),
362 	[ROUTER_HASH_MSK_SRC_PORT]			= BIT(19),
363 	[ROUTER_HASH_MSK_DST_PORT]			= BIT(20),
364 	[ROUTER_HASH_MSK_PROTOCOL]			= BIT(21),
365 	[ROUTER_HASH_MSK_METADATA]			= BIT(22),
366 	[ROUTER_HASH_MSK_ALL]				= GENMASK(22, 16),
367 						/* Bits 23-31 reserved */
368 };
369 
370 REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg,
371 		  0x0000085c, 0x0070);
372 
373 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
374 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP);
375 
376 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
377 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP);
378 
379 /* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */
380 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP);
381 
382 static const u32 reg_ipa_irq_uc_fmask[] = {
383 	[UC_INTR]					= BIT(0),
384 						/* Bits 1-31 reserved */
385 };
386 
387 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP);
388 
389 /* Valid bits defined by ipa->available */
390 REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info,
391 	   0x00003030 + 0x1000 * GSI_EE_AP, 0x0004);
392 
393 /* Valid bits defined by ipa->available */
394 REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en,
395 	   0x00003034 + 0x1000 * GSI_EE_AP, 0x0004);
396 
397 /* Valid bits defined by ipa->available */
398 REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr,
399 	   0x00003038 + 0x1000 * GSI_EE_AP, 0x0004);
400 
401 static const struct reg *reg_array[] = {
402 	[COMP_CFG]			= &reg_comp_cfg,
403 	[CLKON_CFG]			= &reg_clkon_cfg,
404 	[ROUTE]				= &reg_route,
405 	[SHARED_MEM_SIZE]		= &reg_shared_mem_size,
406 	[QSB_MAX_WRITES]		= &reg_qsb_max_writes,
407 	[QSB_MAX_READS]			= &reg_qsb_max_reads,
408 	[FILT_ROUT_HASH_EN]		= &reg_filt_rout_hash_en,
409 	[FILT_ROUT_HASH_FLUSH]		= &reg_filt_rout_hash_flush,
410 	[STATE_AGGR_ACTIVE]		= &reg_state_aggr_active,
411 	[IPA_BCR]			= &reg_ipa_bcr,
412 	[LOCAL_PKT_PROC_CNTXT]		= &reg_local_pkt_proc_cntxt,
413 	[AGGR_FORCE_CLOSE]		= &reg_aggr_force_close,
414 	[COUNTER_CFG]			= &reg_counter_cfg,
415 	[SRC_RSRC_GRP_01_RSRC_TYPE]	= &reg_src_rsrc_grp_01_rsrc_type,
416 	[SRC_RSRC_GRP_23_RSRC_TYPE]	= &reg_src_rsrc_grp_23_rsrc_type,
417 	[SRC_RSRC_GRP_45_RSRC_TYPE]	= &reg_src_rsrc_grp_45_rsrc_type,
418 	[SRC_RSRC_GRP_67_RSRC_TYPE]	= &reg_src_rsrc_grp_67_rsrc_type,
419 	[DST_RSRC_GRP_01_RSRC_TYPE]	= &reg_dst_rsrc_grp_01_rsrc_type,
420 	[DST_RSRC_GRP_23_RSRC_TYPE]	= &reg_dst_rsrc_grp_23_rsrc_type,
421 	[DST_RSRC_GRP_45_RSRC_TYPE]	= &reg_dst_rsrc_grp_45_rsrc_type,
422 	[DST_RSRC_GRP_67_RSRC_TYPE]	= &reg_dst_rsrc_grp_67_rsrc_type,
423 	[ENDP_INIT_CTRL]		= &reg_endp_init_ctrl,
424 	[ENDP_INIT_CFG]			= &reg_endp_init_cfg,
425 	[ENDP_INIT_NAT]			= &reg_endp_init_nat,
426 	[ENDP_INIT_HDR]			= &reg_endp_init_hdr,
427 	[ENDP_INIT_HDR_EXT]		= &reg_endp_init_hdr_ext,
428 	[ENDP_INIT_HDR_METADATA_MASK]	= &reg_endp_init_hdr_metadata_mask,
429 	[ENDP_INIT_MODE]		= &reg_endp_init_mode,
430 	[ENDP_INIT_AGGR]		= &reg_endp_init_aggr,
431 	[ENDP_INIT_HOL_BLOCK_EN]	= &reg_endp_init_hol_block_en,
432 	[ENDP_INIT_HOL_BLOCK_TIMER]	= &reg_endp_init_hol_block_timer,
433 	[ENDP_INIT_DEAGGR]		= &reg_endp_init_deaggr,
434 	[ENDP_INIT_RSRC_GRP]		= &reg_endp_init_rsrc_grp,
435 	[ENDP_INIT_SEQ]			= &reg_endp_init_seq,
436 	[ENDP_STATUS]			= &reg_endp_status,
437 	[ENDP_FILTER_ROUTER_HSH_CFG]	= &reg_endp_filter_router_hsh_cfg,
438 	[IPA_IRQ_STTS]			= &reg_ipa_irq_stts,
439 	[IPA_IRQ_EN]			= &reg_ipa_irq_en,
440 	[IPA_IRQ_CLR]			= &reg_ipa_irq_clr,
441 	[IPA_IRQ_UC]			= &reg_ipa_irq_uc,
442 	[IRQ_SUSPEND_INFO]		= &reg_irq_suspend_info,
443 	[IRQ_SUSPEND_EN]		= &reg_irq_suspend_en,
444 	[IRQ_SUSPEND_CLR]		= &reg_irq_suspend_clr,
445 };
446 
447 const struct regs ipa_regs_v3_1 = {
448 	.reg_count	= ARRAY_SIZE(reg_array),
449 	.reg		= reg_array,
450 };
451