xref: /linux/drivers/net/ipa/reg/gsi_reg-v4.9.c (revision 675f176b4dcc2b75adbcea7ba0e9a649527f53bd) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2023 Linaro Ltd. */
4 
5 #include <linux/types.h>
6 
7 #include "../gsi.h"
8 #include "../reg.h"
9 #include "../gsi_reg.h"
10 
11 /* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */
12 
13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
14     0x0000c020 + 0x1000 * GSI_EE_AP);
15 
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
17     0x0000c024 + 0x1000 * GSI_EE_AP);
18 
19 /* All other register offsets are relative to gsi->virt */
20 
21 static const u32 reg_ch_c_cntxt_0_fmask[] = {
22 	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
23 	[CHTYPE_DIR]					= BIT(3),
24 	[CH_EE]						= GENMASK(7, 4),
25 	[CHID]						= GENMASK(12, 8),
26 	[CHTYPE_PROTOCOL_MSB]				= BIT(13),
27 	[ERINDEX]					= GENMASK(18, 14),
28 						/* Bit 19 reserved */
29 	[CHSTATE]					= GENMASK(23, 20),
30 	[ELEMENT_SIZE]					= GENMASK(31, 24),
31 };
32 
33 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
34 		  0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
35 
36 static const u32 reg_ch_c_cntxt_1_fmask[] = {
37 	[CH_R_LENGTH]					= GENMASK(19, 0),
38 						/* Bits 20-31 reserved */
39 };
40 
41 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
42 		  0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
43 
44 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
45 
46 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
47 
48 static const u32 reg_ch_c_qos_fmask[] = {
49 	[WRR_WEIGHT]					= GENMASK(3, 0),
50 						/* Bits 4-7 reserved */
51 	[MAX_PREFETCH]					= BIT(8),
52 	[USE_DB_ENG]					= BIT(9),
53 	[PREFETCH_MODE]					= GENMASK(13, 10),
54 						/* Bits 14-15 reserved */
55 	[EMPTY_LVL_THRSHOLD]				= GENMASK(23, 16),
56 	[DB_IN_BYTES]					= BIT(24),
57 						/* Bits 25-31 reserved */
58 };
59 
60 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
61 
62 static const u32 reg_error_log_fmask[] = {
63 	[ERR_ARG3]					= GENMASK(3, 0),
64 	[ERR_ARG2]					= GENMASK(7, 4),
65 	[ERR_ARG1]					= GENMASK(11, 8),
66 	[ERR_CODE]					= GENMASK(15, 12),
67 						/* Bits 16-18 reserved */
68 	[ERR_VIRT_IDX]					= GENMASK(23, 19),
69 	[ERR_TYPE]					= GENMASK(27, 24),
70 	[ERR_EE]					= GENMASK(31, 28),
71 };
72 
73 REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
74 
75 REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
76 
77 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
78 	   0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
79 
80 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
81 	   0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
82 
83 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
84 	   0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
85 
86 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
87 	   0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
88 
89 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
90 	[EV_CHTYPE]					= GENMASK(3, 0),
91 	[EV_EE]						= GENMASK(7, 4),
92 	[EV_EVCHID]					= GENMASK(15, 8),
93 	[EV_INTYPE]					= BIT(16),
94 						/* Bits 17-19 reserved */
95 	[EV_CHSTATE]					= GENMASK(23, 20),
96 	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
97 };
98 
99 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
100 		  0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
101 
102 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
103 	   0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
104 
105 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
106 	   0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
107 
108 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
109 	   0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
110 
111 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
112 	   0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
113 
114 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
115 	[EV_MODT]					= GENMASK(15, 0),
116 	[EV_MODC]					= GENMASK(23, 16),
117 	[EV_MOD_CNT]					= GENMASK(31, 24),
118 };
119 
120 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
121 		  0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
122 
123 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
124 	   0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
125 
126 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
127 	   0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
128 
129 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
130 	   0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
131 
132 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
133 	   0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
134 
135 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
136 	   0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
137 
138 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
139 	   0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
140 
141 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
142 	   0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
143 
144 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
145 	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
146 
147 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
148 	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
149 
150 static const u32 reg_gsi_status_fmask[] = {
151 	[ENABLED]					= BIT(0),
152 						/* Bits 1-31 reserved */
153 };
154 
155 REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
156 
157 static const u32 reg_ch_cmd_fmask[] = {
158 	[CH_CHID]					= GENMASK(7, 0),
159 	[CH_OPCODE]					= GENMASK(31, 24),
160 };
161 
162 REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
163 
164 static const u32 reg_ev_ch_cmd_fmask[] = {
165 	[EV_CHID]					= GENMASK(7, 0),
166 	[EV_OPCODE]					= GENMASK(31, 24),
167 };
168 
169 REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
170 
171 static const u32 reg_generic_cmd_fmask[] = {
172 	[GENERIC_OPCODE]				= GENMASK(4, 0),
173 	[GENERIC_CHID]					= GENMASK(9, 5),
174 	[GENERIC_EE]					= GENMASK(13, 10),
175 						/* Bits 14-31 reserved */
176 };
177 
178 REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
179 
180 static const u32 reg_hw_param_2_fmask[] = {
181 	[IRAM_SIZE]					= GENMASK(2, 0),
182 	[NUM_CH_PER_EE]					= GENMASK(7, 3),
183 	[NUM_EV_PER_EE]					= GENMASK(12, 8),
184 	[GSI_CH_PEND_TRANSLATE]				= BIT(13),
185 	[GSI_CH_FULL_LOGIC]				= BIT(14),
186 	[GSI_USE_SDMA]					= BIT(15),
187 	[GSI_SDMA_N_INT]				= GENMASK(18, 16),
188 	[GSI_SDMA_MAX_BURST]				= GENMASK(26, 19),
189 	[GSI_SDMA_N_IOVEC]				= GENMASK(29, 27),
190 	[GSI_USE_RD_WR_ENG]				= BIT(30),
191 	[GSI_USE_INTER_EE]				= BIT(31),
192 };
193 
194 REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
195 
196 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
197 
198 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
199 
200 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
201 
202 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
203 
204 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
205     0x0001f098 + 0x4000 * GSI_EE_AP);
206 
207 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
208     0x0001f09c + 0x4000 * GSI_EE_AP);
209 
210 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
211     0x0001f0a0 + 0x4000 * GSI_EE_AP);
212 
213 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
214     0x0001f0a4 + 0x4000 * GSI_EE_AP);
215 
216 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
217 
218 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
219     0x0001f0b8 + 0x4000 * GSI_EE_AP);
220 
221 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
222     0x0001f0c0 + 0x4000 * GSI_EE_AP);
223 
224 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
225 
226 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
227 
228 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
229 
230 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
231 
232 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
233 
234 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
235 
236 static const u32 reg_cntxt_intset_fmask[] = {
237 	[INTYPE]					= BIT(0)
238 						/* Bits 1-31 reserved */
239 };
240 
241 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
242 
243 static const u32 reg_cntxt_scratch_0_fmask[] = {
244 	[INTER_EE_RESULT]				= GENMASK(2, 0),
245 						/* Bits 3-4 reserved */
246 	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
247 						/* Bits 8-31 reserved */
248 };
249 
250 REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
251 
252 static const struct reg *reg_array[] = {
253 	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
254 	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
255 	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
256 	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
257 	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
258 	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
259 	[CH_C_QOS]			= &reg_ch_c_qos,
260 	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
261 	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
262 	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
263 	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
264 	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
265 	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
266 	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
267 	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
268 	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
269 	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
270 	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
271 	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
272 	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
273 	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
274 	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
275 	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
276 	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
277 	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
278 	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
279 	[GSI_STATUS]			= &reg_gsi_status,
280 	[CH_CMD]			= &reg_ch_cmd,
281 	[EV_CH_CMD]			= &reg_ev_ch_cmd,
282 	[GENERIC_CMD]			= &reg_generic_cmd,
283 	[HW_PARAM_2]			= &reg_hw_param_2,
284 	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
285 	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
286 	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
287 	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
288 	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
289 	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
290 	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
291 	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
292 	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
293 	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
294 	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
295 	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
296 	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
297 	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
298 	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
299 	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
300 	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
301 	[CNTXT_INTSET]			= &reg_cntxt_intset,
302 	[ERROR_LOG]			= &reg_error_log,
303 	[ERROR_LOG_CLR]			= &reg_error_log_clr,
304 	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
305 };
306 
307 const struct regs gsi_regs_v4_9 = {
308 	.reg_count	= ARRAY_SIZE(reg_array),
309 	.reg		= reg_array,
310 };
311