1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2023 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 #include <linux/bug.h> 11 12 #include "ipa_version.h" 13 #include "reg.h" 14 15 struct ipa; 16 17 /** 18 * DOC: IPA Registers 19 * 20 * IPA registers are located within the "ipa-reg" address space defined by 21 * Device Tree. Each register has a specified offset within that space, 22 * which is mapped into virtual memory space in ipa_mem_init(). Each 23 * has a unique identifer, taken from the ipa_reg_id enumerated type. 24 * All IPA registers are 32 bits wide. 25 * 26 * Certain "parameterized" register types are duplicated for a number of 27 * instances of something. For example, each IPA endpoint has an set of 28 * registers defining its configuration. The offset to an endpoint's set 29 * of registers is computed based on an "base" offset, plus an endpoint's 30 * ID multiplied and a "stride" value for the register. Similarly, some 31 * registers have an offset that depends on execution environment. In 32 * this case, the stride is multiplied by a member of the gsi_ee_id 33 * enumerated type. 34 * 35 * Each version of IPA implements an array of ipa_reg structures indexed 36 * by register ID. Each entry in the array specifies the base offset and 37 * (for parameterized registers) a non-zero stride value. Not all versions 38 * of IPA define all registers. The offset for a register is returned by 39 * reg_offset() when the register's ipa_reg structure is supplied; 40 * zero is returned for an undefined register (this should never happen). 41 * 42 * Some registers encode multiple fields within them. Each field in 43 * such a register has a unique identifier (from an enumerated type). 44 * The position and width of the fields in a register are defined by 45 * an array of field masks, indexed by field ID. Two functions are 46 * used to access register fields; both take an ipa_reg structure as 47 * argument. To encode a value to be represented in a register field, 48 * the value and field ID are passed to reg_encode(). To extract 49 * a value encoded in a register field, the field ID is passed to 50 * reg_decode(). In addition, for single-bit fields, reg_bit() 51 * can be used to either encode the bit value, or to generate a mask 52 * used to extract the bit value. 53 */ 54 55 /* enum ipa_reg_id - IPA register IDs */ 56 enum ipa_reg_id { 57 COMP_CFG, 58 CLKON_CFG, 59 ROUTE, 60 SHARED_MEM_SIZE, 61 QSB_MAX_WRITES, 62 QSB_MAX_READS, 63 FILT_ROUT_HASH_EN, /* IPA v4.2 */ 64 FILT_ROUT_HASH_FLUSH, /* Not IPA v4.2 nor IPA v5.0+ */ 65 FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */ 66 STATE_AGGR_ACTIVE, 67 IPA_BCR, /* Not IPA v4.5+ */ 68 LOCAL_PKT_PROC_CNTXT, 69 AGGR_FORCE_CLOSE, 70 COUNTER_CFG, /* Not IPA v4.5+ */ 71 IPA_TX_CFG, /* IPA v3.5+ */ 72 FLAVOR_0, /* IPA v3.5+ */ 73 IDLE_INDICATION_CFG, /* IPA v3.5+ */ 74 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 75 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 76 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 77 SRC_RSRC_GRP_01_RSRC_TYPE, 78 SRC_RSRC_GRP_23_RSRC_TYPE, 79 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */ 80 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */ 81 DST_RSRC_GRP_01_RSRC_TYPE, 82 DST_RSRC_GRP_23_RSRC_TYPE, 83 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */ 84 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */ 85 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 86 ENDP_INIT_CFG, 87 ENDP_INIT_NAT, /* TX only */ 88 ENDP_INIT_HDR, 89 ENDP_INIT_HDR_EXT, 90 ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 91 ENDP_INIT_MODE, /* TX only */ 92 ENDP_INIT_AGGR, 93 ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 94 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 95 ENDP_INIT_DEAGGR, /* TX only */ 96 ENDP_INIT_RSRC_GRP, 97 ENDP_INIT_SEQ, /* TX only */ 98 ENDP_STATUS, 99 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 100 ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */ 101 ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */ 102 /* The IRQ registers that follow are only used for GSI_EE_AP */ 103 IPA_IRQ_STTS, 104 IPA_IRQ_EN, 105 IPA_IRQ_CLR, 106 IPA_IRQ_UC, 107 IRQ_SUSPEND_INFO, 108 IRQ_SUSPEND_EN, /* IPA v3.1+ */ 109 IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 110 IPA_REG_ID_COUNT, /* Last; not an ID */ 111 }; 112 113 /* COMP_CFG register */ 114 enum ipa_reg_comp_cfg_field_id { 115 COMP_CFG_ENABLE, /* Not IPA v4.0+ */ 116 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */ 117 GSI_SNOC_BYPASS_DIS, 118 GEN_QMB_0_SNOC_BYPASS_DIS, 119 GEN_QMB_1_SNOC_BYPASS_DIS, 120 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */ 121 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */ 122 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */ 123 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 124 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 125 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 126 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 127 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 128 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 129 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */ 130 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */ 131 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */ 132 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */ 133 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */ 134 GENQMB_AOOOWR, /* IPA v4.9+ */ 135 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */ 136 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */ 137 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */ 138 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */ 139 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */ 140 }; 141 142 /* CLKON_CFG register */ 143 enum ipa_reg_clkon_cfg_field_id { 144 CLKON_RX, 145 CLKON_PROC, 146 TX_WRAPPER, 147 CLKON_MISC, 148 RAM_ARB, 149 FTCH_HPS, 150 FTCH_DPS, 151 CLKON_HPS, 152 CLKON_DPS, 153 RX_HPS_CMDQS, 154 HPS_DPS_CMDQS, 155 DPS_TX_CMDQS, 156 RSRC_MNGR, 157 CTX_HANDLER, 158 ACK_MNGR, 159 D_DCPH, 160 H_DCPH, 161 CLKON_DCMP, /* IPA v4.5+ */ 162 NTF_TX_CMDQS, /* IPA v3.5+ */ 163 CLKON_TX_0, /* IPA v3.5+ */ 164 CLKON_TX_1, /* IPA v3.5+ */ 165 CLKON_FNR, /* IPA v3.5.1+ */ 166 QSB2AXI_CMDQ_L, /* IPA v4.0+ */ 167 AGGR_WRAPPER, /* IPA v4.0+ */ 168 RAM_SLAVEWAY, /* IPA v4.0+ */ 169 CLKON_QMB, /* IPA v4.0+ */ 170 WEIGHT_ARB, /* IPA v4.0+ */ 171 GSI_IF, /* IPA v4.0+ */ 172 CLKON_GLOBAL, /* IPA v4.0+ */ 173 GLOBAL_2X_CLK, /* IPA v4.0+ */ 174 DPL_FIFO, /* IPA v4.5+ */ 175 DRBIP, /* IPA v4.7+ */ 176 }; 177 178 /* ROUTE register */ 179 enum ipa_reg_route_field_id { 180 ROUTE_DIS, 181 ROUTE_DEF_PIPE, 182 ROUTE_DEF_HDR_TABLE, 183 ROUTE_DEF_HDR_OFST, 184 ROUTE_FRAG_DEF_PIPE, 185 ROUTE_DEF_RETAIN_HDR, 186 }; 187 188 /* SHARED_MEM_SIZE register */ 189 enum ipa_reg_shared_mem_size_field_id { 190 MEM_SIZE, 191 MEM_BADDR, 192 }; 193 194 /* QSB_MAX_WRITES register */ 195 enum ipa_reg_qsb_max_writes_field_id { 196 GEN_QMB_0_MAX_WRITES, 197 GEN_QMB_1_MAX_WRITES, 198 }; 199 200 /* QSB_MAX_READS register */ 201 enum ipa_reg_qsb_max_reads_field_id { 202 GEN_QMB_0_MAX_READS, 203 GEN_QMB_1_MAX_READS, 204 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */ 205 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ 206 }; 207 208 /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ 209 enum ipa_reg_filt_rout_hash_field_id { 210 IPV6_ROUTER_HASH, 211 IPV6_FILTER_HASH, 212 IPV4_ROUTER_HASH, 213 IPV4_FILTER_HASH, 214 }; 215 216 /* FILT_ROUT_CACHE_FLUSH register */ 217 enum ipa_reg_filt_rout_cache_field_id { 218 ROUTER_CACHE, 219 FILTER_CACHE, 220 }; 221 222 /* BCR register */ 223 enum ipa_bcr_compat { 224 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 225 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ 226 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ 227 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ 228 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ 229 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ 230 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ 231 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ 232 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ 233 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 234 }; 235 236 /* LOCAL_PKT_PROC_CNTXT register */ 237 enum ipa_reg_local_pkt_proc_cntxt_field_id { 238 IPA_BASE_ADDR, 239 }; 240 241 /* COUNTER_CFG register */ 242 enum ipa_reg_counter_cfg_field_id { 243 EOT_COAL_GRANULARITY, /* Not IPA v3.5+ */ 244 AGGR_GRANULARITY, 245 }; 246 247 /* IPA_TX_CFG register */ 248 enum ipa_reg_ipa_tx_cfg_field_id { 249 TX0_PREFETCH_DISABLE, /* Not IPA v4.0+ */ 250 TX1_PREFETCH_DISABLE, /* Not IPA v4.0+ */ 251 PREFETCH_ALMOST_EMPTY_SIZE, /* Not IPA v4.0+ */ 252 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* IPA v4.0+ */ 253 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* IPA v4.0+ */ 254 DMAW_SCND_OUTSD_PRED_EN, /* IPA v4.0+ */ 255 DMAW_MAX_BEATS_256_DIS, /* IPA v4.0+ */ 256 PA_MASK_EN, /* IPA v4.0+ */ 257 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* IPA v4.0+ */ 258 DUAL_TX_ENABLE, /* IPA v4.5+ */ 259 SSPND_PA_NO_START_STATE, /* IPA v4,2+, not IPA v4.5 */ 260 SSPND_PA_NO_BQ_STATE, /* IPA v4.2 only */ 261 HOLB_STICKY_DROP_EN, /* IPA v5.0+ */ 262 }; 263 264 /* FLAVOR_0 register */ 265 enum ipa_reg_flavor_0_field_id { 266 MAX_PIPES, 267 MAX_CONS_PIPES, 268 MAX_PROD_PIPES, 269 PROD_LOWEST, 270 }; 271 272 /* IDLE_INDICATION_CFG register */ 273 enum ipa_reg_idle_indication_cfg_field_id { 274 ENTER_IDLE_DEBOUNCE_THRESH, 275 CONST_NON_IDLE_ENABLE, 276 }; 277 278 /* QTIME_TIMESTAMP_CFG register */ 279 enum ipa_reg_qtime_timestamp_cfg_field_id { 280 DPL_TIMESTAMP_LSB, /* Not IPA v5.5+ */ 281 DPL_TIMESTAMP_SEL, /* Not IPA v5.5+ */ 282 TAG_TIMESTAMP_LSB, 283 NAT_TIMESTAMP_LSB, 284 }; 285 286 /* TIMERS_XO_CLK_DIV_CFG register */ 287 enum ipa_reg_timers_xo_clk_div_cfg_field_id { 288 DIV_VALUE, 289 DIV_ENABLE, 290 }; 291 292 /* TIMERS_PULSE_GRAN_CFG register */ 293 enum ipa_reg_timers_pulse_gran_cfg_field_id { 294 PULSE_GRAN_0, 295 PULSE_GRAN_1, 296 PULSE_GRAN_2, 297 PULSE_GRAN_3, 298 }; 299 300 /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 301 enum ipa_pulse_gran { 302 IPA_GRAN_10_US = 0x0, 303 IPA_GRAN_20_US = 0x1, 304 IPA_GRAN_50_US = 0x2, 305 IPA_GRAN_100_US = 0x3, 306 IPA_GRAN_1_MS = 0x4, 307 IPA_GRAN_10_MS = 0x5, 308 IPA_GRAN_100_MS = 0x6, 309 IPA_GRAN_655350_US = 0x7, 310 }; 311 312 /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ 313 enum ipa_reg_rsrc_grp_rsrc_type_field_id { 314 X_MIN_LIM, 315 X_MAX_LIM, 316 Y_MIN_LIM, 317 Y_MAX_LIM, 318 }; 319 320 /* ENDP_INIT_CTRL register */ 321 enum ipa_reg_endp_init_ctrl_field_id { 322 ENDP_SUSPEND, /* Not IPA v4.0+ */ 323 ENDP_DELAY, /* Not IPA v4.2+ */ 324 }; 325 326 /* ENDP_INIT_CFG register */ 327 enum ipa_reg_endp_init_cfg_field_id { 328 FRAG_OFFLOAD_EN, 329 CS_OFFLOAD_EN, 330 CS_METADATA_HDR_OFFSET, 331 CS_GEN_QMB_MASTER_SEL, 332 PIPE_REPLICATE_EN, /* IPA v5.5+ */ 333 }; 334 335 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 336 enum ipa_cs_offload_en { 337 IPA_CS_OFFLOAD_NONE = 0x0, 338 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ 339 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ 340 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 341 }; 342 343 /* ENDP_INIT_NAT register */ 344 enum ipa_reg_endp_init_nat_field_id { 345 NAT_EN, 346 }; 347 348 /** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */ 349 enum ipa_nat_type { 350 IPA_NAT_TYPE_BYPASS = 0, 351 IPA_NAT_TYPE_SRC = 1, 352 IPA_NAT_TYPE_DST = 2, 353 }; 354 355 /* ENDP_INIT_HDR register */ 356 enum ipa_reg_endp_init_hdr_field_id { 357 HDR_LEN, 358 HDR_OFST_METADATA_VALID, 359 HDR_OFST_METADATA, 360 HDR_ADDITIONAL_CONST_LEN, 361 HDR_OFST_PKT_SIZE_VALID, 362 HDR_OFST_PKT_SIZE, 363 HDR_A5_MUX, /* Not IPA v4.9+ */ 364 HDR_LEN_INC_DEAGG_HDR, 365 HDR_METADATA_REG_VALID, /* Not IPA v4.5+ */ 366 HDR_LEN_MSB, /* IPA v4.5+ */ 367 HDR_OFST_METADATA_MSB, /* IPA v4.5+ */ 368 }; 369 370 /* ENDP_INIT_HDR_EXT register */ 371 enum ipa_reg_endp_init_hdr_ext_field_id { 372 HDR_ENDIANNESS, 373 HDR_TOTAL_LEN_OR_PAD_VALID, 374 HDR_TOTAL_LEN_OR_PAD, 375 HDR_PAYLOAD_LEN_INC_PADDING, 376 HDR_TOTAL_LEN_OR_PAD_OFFSET, 377 HDR_PAD_TO_ALIGNMENT, 378 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* IPA v4.5+ */ 379 HDR_OFST_PKT_SIZE_MSB, /* IPA v4.5+ */ 380 HDR_ADDITIONAL_CONST_LEN_MSB, /* IPA v4.5+ */ 381 HDR_BYTES_TO_REMOVE_VALID, /* IPA v5.0+ */ 382 HDR_BYTES_TO_REMOVE, /* IPA v5.0+ */ 383 }; 384 385 /* ENDP_INIT_MODE register */ 386 enum ipa_reg_endp_init_mode_field_id { 387 ENDP_MODE, 388 DCPH_ENABLE, /* IPA v4.5+ */ 389 DEST_PIPE_INDEX, 390 BYTE_THRESHOLD, 391 PIPE_REPLICATION_EN, /* Not IPA v5.5+ */ 392 PAD_EN, 393 HDR_FTCH_DISABLE, /* IPA v4.5+ */ 394 DRBIP_ACL_ENABLE, /* IPA v4.9+ */ 395 }; 396 397 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 398 enum ipa_mode { 399 IPA_BASIC = 0x0, 400 IPA_ENABLE_FRAMING_HDLC = 0x1, 401 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 402 IPA_DMA = 0x3, 403 }; 404 405 /* ENDP_INIT_AGGR register */ 406 enum ipa_reg_endp_init_aggr_field_id { 407 AGGR_EN, 408 AGGR_TYPE, 409 BYTE_LIMIT, 410 TIME_LIMIT, 411 PKT_LIMIT, 412 SW_EOF_ACTIVE, 413 FORCE_CLOSE, 414 HARD_BYTE_LIMIT_EN, 415 AGGR_GRAN_SEL, 416 AGGR_COAL_L2, /* IPA v5.5+ */ 417 }; 418 419 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 420 enum ipa_aggr_en { 421 IPA_BYPASS_AGGR /* TX and RX */ = 0x0, 422 IPA_ENABLE_AGGR /* RX */ = 0x1, 423 IPA_ENABLE_DEAGGR /* TX */ = 0x2, 424 }; 425 426 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 427 enum ipa_aggr_type { 428 IPA_MBIM_16 = 0x0, 429 IPA_HDLC = 0x1, 430 IPA_TLP = 0x2, 431 IPA_RNDIS = 0x3, 432 IPA_GENERIC = 0x4, 433 IPA_COALESCE = 0x5, 434 IPA_QCMAP = 0x6, 435 }; 436 437 /* ENDP_INIT_HOL_BLOCK_EN register */ 438 enum ipa_reg_endp_init_hol_block_en_field_id { 439 HOL_BLOCK_EN, 440 }; 441 442 /* ENDP_INIT_HOL_BLOCK_TIMER register */ 443 enum ipa_reg_endp_init_hol_block_timer_field_id { 444 TIMER_BASE_VALUE, /* Not IPA v4.5+ */ 445 TIMER_SCALE, /* IPA v4.2 only */ 446 TIMER_LIMIT, /* IPA v4.5+ */ 447 TIMER_GRAN_SEL, /* IPA v4.5+ */ 448 }; 449 450 /* ENDP_INIT_DEAGGR register */ 451 enum ipa_reg_endp_deaggr_field_id { 452 DEAGGR_HDR_LEN, 453 SYSPIPE_ERR_DETECTION, 454 PACKET_OFFSET_VALID, 455 PACKET_OFFSET_LOCATION, 456 IGNORE_MIN_PKT_ERR, 457 MAX_PACKET_LEN, 458 }; 459 460 /* ENDP_INIT_RSRC_GRP register */ 461 enum ipa_reg_endp_init_rsrc_grp_field_id { 462 ENDP_RSRC_GRP, 463 }; 464 465 /* ENDP_INIT_SEQ register */ 466 enum ipa_reg_endp_init_seq_field_id { 467 SEQ_TYPE, 468 SEQ_REP_TYPE, /* Not IPA v4.5+ */ 469 }; 470 471 /** 472 * enum ipa_seq_type - HPS and DPS sequencer type 473 * @IPA_SEQ_DMA: Perform DMA only 474 * @IPA_SEQ_1_PASS: One pass through the pipeline 475 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 476 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 477 * @IPA_SEQ_2_PASS: Two passes through the pipeline 478 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 479 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 480 * 481 * The low-order byte of the sequencer type register defines the number of 482 * passes a packet takes through the IPA pipeline. The last pass through can 483 * optionally skip the microprocessor. Deciphering is optional for all types; 484 * if enabled, an additional mask (two bits) is added to the type value. 485 * 486 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 487 * supported (or meaningful). 488 */ 489 enum ipa_seq_type { 490 IPA_SEQ_DMA = 0x00, 491 IPA_SEQ_1_PASS = 0x02, 492 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 493 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 494 IPA_SEQ_2_PASS = 0x0a, 495 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 496 /* The next value can be ORed with the above */ 497 IPA_SEQ_DECIPHER = 0x11, 498 }; 499 500 /** 501 * enum ipa_seq_rep_type - replicated packet sequencer type 502 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 503 * 504 * This goes in the second byte of the endpoint sequencer type register. 505 * 506 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 507 * supported (or meaningful). 508 */ 509 enum ipa_seq_rep_type { 510 IPA_SEQ_REP_DMA_PARSER = 0x08, 511 }; 512 513 /* ENDP_STATUS register */ 514 enum ipa_reg_endp_status_field_id { 515 STATUS_EN, 516 STATUS_ENDP, 517 STATUS_LOCATION, /* Not IPA v4.5+ */ 518 STATUS_PKT_SUPPRESS, /* IPA v4.0+ */ 519 }; 520 521 /* ENDP_FILTER_ROUTER_HSH_CFG register */ 522 enum ipa_reg_endp_filter_router_hsh_cfg_field_id { 523 FILTER_HASH_MSK_SRC_ID, 524 FILTER_HASH_MSK_SRC_IP, 525 FILTER_HASH_MSK_DST_IP, 526 FILTER_HASH_MSK_SRC_PORT, 527 FILTER_HASH_MSK_DST_PORT, 528 FILTER_HASH_MSK_PROTOCOL, 529 FILTER_HASH_MSK_METADATA, 530 FILTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 531 532 ROUTER_HASH_MSK_SRC_ID, 533 ROUTER_HASH_MSK_SRC_IP, 534 ROUTER_HASH_MSK_DST_IP, 535 ROUTER_HASH_MSK_SRC_PORT, 536 ROUTER_HASH_MSK_DST_PORT, 537 ROUTER_HASH_MSK_PROTOCOL, 538 ROUTER_HASH_MSK_METADATA, 539 ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 540 }; 541 542 /* ENDP_FILTER_CACHE_CFG and ENDP_ROUTER_CACHE_CFG registers */ 543 enum ipa_reg_endp_cache_cfg_field_id { 544 CACHE_MSK_SRC_ID, 545 CACHE_MSK_SRC_IP, 546 CACHE_MSK_DST_IP, 547 CACHE_MSK_SRC_PORT, 548 CACHE_MSK_DST_PORT, 549 CACHE_MSK_PROTOCOL, 550 CACHE_MSK_METADATA, 551 }; 552 553 /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ 554 /** 555 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 556 * @IPA_IRQ_UC_0: Microcontroller event interrupt 557 * @IPA_IRQ_UC_1: Microcontroller response interrupt 558 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 559 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 560 * 561 * IRQ types not described above are not currently used. 562 * 563 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 564 * @IPA_IRQ_EOT_COAL: (Not currently used) 565 * @IPA_IRQ_UC_2: (Not currently used) 566 * @IPA_IRQ_UC_3: (Not currently used) 567 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 568 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 569 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 570 * @IPA_IRQ_RX_ERR: (Not currently used) 571 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 572 * @IPA_IRQ_TX_ERR: (Not currently used) 573 * @IPA_IRQ_STEP_MODE: (Not currently used) 574 * @IPA_IRQ_PROC_ERR: (Not currently used) 575 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 576 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 577 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 578 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 579 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 580 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 581 * @IPA_IRQ_UCP: (Not currently used) 582 * @IPA_IRQ_DCMP: (Not currently used) 583 * @IPA_IRQ_GSI_EE: (Not currently used) 584 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 585 * @IPA_IRQ_GSI_UC: (Not currently used) 586 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 587 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 588 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 589 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 590 * @IPA_IRQ_ERROR_NON_FATAL: (Not currently used) 591 * @IPA_IRQ_ERROR_FATAL: (Not currently used) 592 */ 593 enum ipa_irq_id { 594 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, /* Not IPA v5.5+ */ 595 IPA_IRQ_EOT_COAL = 0x1, /* Not IPA v3.5+ */ 596 IPA_IRQ_UC_0 = 0x2, 597 IPA_IRQ_UC_1 = 0x3, 598 IPA_IRQ_UC_2 = 0x4, 599 IPA_IRQ_UC_3 = 0x5, 600 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 601 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 602 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 603 IPA_IRQ_RX_ERR = 0x9, /* Not IPA v5.5+ */ 604 IPA_IRQ_DEAGGR_ERR = 0xa, /* Not IPA v5.5+ */ 605 IPA_IRQ_TX_ERR = 0xb, /* Not IPA v5.5+ */ 606 IPA_IRQ_STEP_MODE = 0xc, /* Not IPA v5.5+ */ 607 IPA_IRQ_PROC_ERR = 0xd, /* Not IPA v5.5+ */ 608 IPA_IRQ_TX_SUSPEND = 0xe, 609 IPA_IRQ_TX_HOLB_DROP = 0xf, 610 IPA_IRQ_BAM_GSI_IDLE = 0x10, 611 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 612 IPA_IRQ_PIPE_RED_BELOW = 0x12, 613 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 614 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 615 IPA_IRQ_UCP = 0x15, 616 IPA_IRQ_DCMP = 0x16, /* Not IPA v4.5+ */ 617 IPA_IRQ_GSI_EE = 0x17, 618 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 619 IPA_IRQ_GSI_UC = 0x19, 620 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, /* IPA v4.5-v5.2 */ 621 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, /* IPA v4.9-v5.2 */ 622 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, /* IPA v4.9-v5.2 */ 623 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, /* IPA v4.9-v5.2 */ 624 IPA_IRQ_ERROR_NON_FATAL = 0x1e, /* IPA v5.5+ */ 625 IPA_IRQ_ERROR_FATAL = 0x1f, /* IPA v5.5+ */ 626 IPA_IRQ_COUNT, /* Last; not an id */ 627 }; 628 629 /* IPA_IRQ_UC register */ 630 enum ipa_reg_ipa_irq_uc_field_id { 631 UC_INTR, 632 }; 633 634 extern const struct regs ipa_regs_v3_1; 635 extern const struct regs ipa_regs_v3_5_1; 636 extern const struct regs ipa_regs_v4_2; 637 extern const struct regs ipa_regs_v4_5; 638 extern const struct regs ipa_regs_v4_7; 639 extern const struct regs ipa_regs_v4_9; 640 extern const struct regs ipa_regs_v4_11; 641 extern const struct regs ipa_regs_v5_0; 642 extern const struct regs ipa_regs_v5_5; 643 644 const struct reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 645 646 int ipa_reg_init(struct ipa *ipa); 647 void ipa_reg_exit(struct ipa *ipa); 648 649 #endif /* _IPA_REG_H_ */ 650