1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint ID is computed by a macro 36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 37 * "ep" parameter is valid for any endpoint; a register with a "txep" or 38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 39 * "*ep" value is assumed to be less than the maximum valid endpoint ID 40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 41 * 42 * The offset of registers related to filter and route tables is computed 43 * by a macro that is supplied a parameter "er". The "er" represents an 44 * endpoint ID for filters, or a route ID for routes. For filters, the 45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 46 * because not all endpoints support filtering. For routes, the route ID 47 * must be less than IPA_ROUTE_MAX. 48 * 49 * The offset of registers related to resource types is computed by a macro 50 * that is supplied a parameter "rt". The "rt" represents a resource type, 51 * which is is a member of the ipa_resource_type_src enumerated type for 52 * source endpoint resources or the ipa_resource_type_dst enumerated type 53 * for destination endpoint resources. 54 * 55 * Some registers encode multiple fields within them. For these, each field 56 * has a symbol below defining a field mask that encodes both the position 57 * and width of the field within its register. 58 * 59 * In some cases, different versions of IPA hardware use different offset or 60 * field mask values. In such cases an inline_function(ipa) is used rather 61 * than a MACRO to define the offset or field mask to use. 62 * 63 * Finally, some registers hold bitmasks representing endpoints. In such 64 * cases the @available field in the @ipa structure defines the "full" set 65 * of valid bits for the register. 66 */ 67 68 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 69 /* The next field is not supported for IPA v4.1 */ 70 #define ENABLE_FMASK GENMASK(0, 0) 71 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 72 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 73 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 74 /* The next field is not present for IPA v4.5 */ 75 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 76 /* The remaining fields are not present for IPA v3.5.1 */ 77 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 78 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 79 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 80 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 81 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 82 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 83 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 84 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 85 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 86 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 87 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 88 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 89 #define IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_FMASK GENMASK(20, 17) 90 /* The next field is present for IPA v4.5 */ 91 #define IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN_FMASK GENMASK(21, 21) 92 93 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 94 #define RX_FMASK GENMASK(0, 0) 95 #define PROC_FMASK GENMASK(1, 1) 96 #define TX_WRAPPER_FMASK GENMASK(2, 2) 97 #define MISC_FMASK GENMASK(3, 3) 98 #define RAM_ARB_FMASK GENMASK(4, 4) 99 #define FTCH_HPS_FMASK GENMASK(5, 5) 100 #define FTCH_DPS_FMASK GENMASK(6, 6) 101 #define HPS_FMASK GENMASK(7, 7) 102 #define DPS_FMASK GENMASK(8, 8) 103 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 104 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 105 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 106 #define RSRC_MNGR_FMASK GENMASK(12, 12) 107 #define CTX_HANDLER_FMASK GENMASK(13, 13) 108 #define ACK_MNGR_FMASK GENMASK(14, 14) 109 #define D_DCPH_FMASK GENMASK(15, 15) 110 #define H_DCPH_FMASK GENMASK(16, 16) 111 /* The next field is not present for IPA v4.5 */ 112 #define DCMP_FMASK GENMASK(17, 17) 113 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 114 #define TX_0_FMASK GENMASK(19, 19) 115 #define TX_1_FMASK GENMASK(20, 20) 116 #define FNR_FMASK GENMASK(21, 21) 117 /* The remaining fields are not present for IPA v3.5.1 */ 118 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 119 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 120 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 121 #define QMB_FMASK GENMASK(25, 25) 122 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 123 #define GSI_IF_FMASK GENMASK(27, 27) 124 #define GLOBAL_FMASK GENMASK(28, 28) 125 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 126 /* The next field is present for IPA v4.5 */ 127 #define DPL_FIFO_FMASK GENMASK(30, 30) 128 129 #define IPA_REG_ROUTE_OFFSET 0x00000048 130 #define ROUTE_DIS_FMASK GENMASK(0, 0) 131 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 132 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 133 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 134 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 135 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 136 137 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 138 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 139 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 140 141 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 142 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 143 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 144 145 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 146 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 147 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 148 /* The next two fields are not present for IPA v3.5.1 */ 149 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 150 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 151 152 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 153 { 154 if (version == IPA_VERSION_3_5_1) 155 return 0x000008c; 156 157 return 0x0000148; 158 } 159 160 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 161 { 162 if (version == IPA_VERSION_3_5_1) 163 return 0x0000090; 164 165 return 0x000014c; 166 } 167 168 /* The next four fields are used for the hash enable and flush registers */ 169 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 170 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 171 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 172 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 173 174 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 175 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 176 { 177 if (version == IPA_VERSION_3_5_1) 178 return 0x0000010c; 179 180 return 0x000000b4; 181 } 182 183 /* The next register is not present for IPA v4.5 */ 184 #define IPA_REG_BCR_OFFSET 0x000001d0 185 /* The next two fields are not present for IPA v4.2 */ 186 #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) 187 #define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) 188 /* The next field is invalid for IPA v4.1 */ 189 #define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) 190 /* The next two fields are not present for IPA v4.2 */ 191 #define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) 192 #define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) 193 #define BCR_DUAL_TX_FMASK GENMASK(5, 5) 194 #define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) 195 #define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) 196 #define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) 197 #define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) 198 199 /* Backward compatibility register value to use for each version */ 200 static inline u32 ipa_reg_bcr_val(enum ipa_version version) 201 { 202 if (version == IPA_VERSION_3_5_1) 203 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 204 BCR_TX_NOT_USING_BRESP_FMASK | 205 BCR_SUSPEND_L2_IRQ_FMASK | 206 BCR_HOLB_DROP_L2_IRQ_FMASK | 207 BCR_DUAL_TX_FMASK; 208 209 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) 210 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 211 BCR_SUSPEND_L2_IRQ_FMASK | 212 BCR_HOLB_DROP_L2_IRQ_FMASK | 213 BCR_DUAL_TX_FMASK; 214 215 /* assert(version != IPA_VERSION_4_5); */ 216 217 return 0x00000000; 218 } 219 220 /* The value of the next register must be a multiple of 8 */ 221 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8 222 223 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 224 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 225 226 /* The next register is not present for IPA v4.5 */ 227 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 228 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 229 230 /* The internal inactivity timer clock is used for the aggregation timer */ 231 #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ 232 233 /* Compute the value to use in the AGGR_GRANULARITY field representing the 234 * given number of microseconds. The value is one less than the number of 235 * timer ticks in the requested period. 0 not a valid granularity value. 236 */ 237 static inline u32 ipa_aggr_granularity_val(u32 usec) 238 { 239 return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; 240 } 241 242 /* The next register is not present for IPA v4.5 */ 243 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 244 /* The first three fields are present for IPA v3.5.1 only */ 245 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 246 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 247 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 248 /* The next six fields are present for IPA v4.0 and above */ 249 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 250 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 251 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 252 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 253 #define PA_MASK_EN_FMASK GENMASK(12, 12) 254 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 255 /* The next field is present for IPA v4.5 */ 256 #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17) 257 /* The next two fields are present for IPA v4.2 only */ 258 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 259 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 260 261 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 262 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 263 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 264 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 265 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 266 267 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 268 { 269 if (version >= IPA_VERSION_4_2) 270 return 0x00000240; 271 272 return 0x00000220; 273 } 274 275 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 276 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 277 278 /* The next register is present for IPA v4.5 */ 279 #define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c 280 #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0) 281 #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7) 282 #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8) 283 #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16) 284 285 /* The next register is present for IPA v4.5 */ 286 #define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250 287 #define DIV_VALUE_FMASK GENMASK(8, 0) 288 #define DIV_ENABLE_FMASK GENMASK(31, 31) 289 290 /* The next register is present for IPA v4.5 */ 291 #define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254 292 #define GRAN_0_FMASK GENMASK(2, 0) 293 #define GRAN_1_FMASK GENMASK(5, 3) 294 #define GRAN_2_FMASK GENMASK(8, 6) 295 /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 296 enum ipa_pulse_gran { 297 IPA_GRAN_10_US = 0x0, 298 IPA_GRAN_20_US = 0x1, 299 IPA_GRAN_50_US = 0x2, 300 IPA_GRAN_100_US = 0x3, 301 IPA_GRAN_1_MS = 0x4, 302 IPA_GRAN_10_MS = 0x5, 303 IPA_GRAN_100_MS = 0x6, 304 IPA_GRAN_655350_US = 0x7, 305 }; 306 307 /* # IPA source resource groups available based on version */ 308 static inline u32 ipa_resource_group_src_count(enum ipa_version version) 309 { 310 switch (version) { 311 case IPA_VERSION_3_5_1: 312 case IPA_VERSION_4_0: 313 case IPA_VERSION_4_1: 314 return 4; 315 316 case IPA_VERSION_4_2: 317 return 1; 318 319 case IPA_VERSION_4_5: 320 return 5; 321 322 default: 323 return 0; 324 } 325 } 326 327 /* # IPA destination resource groups available based on version */ 328 static inline u32 ipa_resource_group_dst_count(enum ipa_version version) 329 { 330 switch (version) { 331 case IPA_VERSION_3_5_1: 332 return 3; 333 334 case IPA_VERSION_4_0: 335 case IPA_VERSION_4_1: 336 return 4; 337 338 case IPA_VERSION_4_2: 339 return 1; 340 341 case IPA_VERSION_4_5: 342 return 5; 343 344 default: 345 return 0; 346 } 347 } 348 349 /* Not all of the following are valid (depends on the count, above) */ 350 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 351 (0x00000400 + 0x0020 * (rt)) 352 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 353 (0x00000404 + 0x0020 * (rt)) 354 /* The next register is only present for IPA v4.5 */ 355 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 356 (0x00000408 + 0x0020 * (rt)) 357 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 358 (0x00000500 + 0x0020 * (rt)) 359 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 360 (0x00000504 + 0x0020 * (rt)) 361 /* The next register is only present for IPA v4.5 */ 362 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 363 (0x00000508 + 0x0020 * (rt)) 364 /* The next four fields are used for all resource group registers */ 365 #define X_MIN_LIM_FMASK GENMASK(5, 0) 366 #define X_MAX_LIM_FMASK GENMASK(13, 8) 367 /* The next two fields are not always present (if resource count is odd) */ 368 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 369 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 370 371 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 372 (0x00000800 + 0x0070 * (ep)) 373 /* The next field should only used for IPA v3.5.1 */ 374 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 375 #define ENDP_DELAY_FMASK GENMASK(1, 1) 376 377 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 378 (0x00000808 + 0x0070 * (ep)) 379 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 380 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 381 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 382 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 383 384 /** enum ipa_cs_offload_en - checksum offload field in ENDP_INIT_CFG_N */ 385 enum ipa_cs_offload_en { 386 IPA_CS_OFFLOAD_NONE = 0x0, 387 IPA_CS_OFFLOAD_UL = 0x1, 388 IPA_CS_OFFLOAD_DL = 0x2, 389 }; 390 391 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 392 (0x00000810 + 0x0070 * (ep)) 393 #define HDR_LEN_FMASK GENMASK(5, 0) 394 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 395 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 396 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 397 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 398 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 399 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 400 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 401 /* The next field is not present for IPA v4.5 */ 402 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 403 /* The next two fields are present for IPA v4.5 */ 404 #define HDR_LEN_MSB_FMASK GENMASK(29, 28) 405 #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30) 406 407 /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 408 static inline u32 ipa_header_size_encoded(enum ipa_version version, 409 u32 header_size) 410 { 411 u32 val; 412 413 val = u32_encode_bits(header_size, HDR_LEN_FMASK); 414 if (version < IPA_VERSION_4_5) 415 return val; 416 417 /* IPA v4.5 adds a few more most-significant bits */ 418 header_size >>= hweight32(HDR_LEN_FMASK); 419 val |= u32_encode_bits(header_size, HDR_LEN_MSB_FMASK); 420 421 return val; 422 } 423 424 /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 425 static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, 426 u32 offset) 427 { 428 u32 val; 429 430 val = u32_encode_bits(offset, HDR_OFST_METADATA_FMASK); 431 if (version < IPA_VERSION_4_5) 432 return val; 433 434 /* IPA v4.5 adds a few more most-significant bits */ 435 offset >>= hweight32(HDR_OFST_METADATA_FMASK); 436 val |= u32_encode_bits(offset, HDR_OFST_METADATA_MSB_FMASK); 437 438 return val; 439 } 440 441 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 442 (0x00000814 + 0x0070 * (ep)) 443 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 444 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 445 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 446 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 447 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 448 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 449 /* The next three fields are present for IPA v4.5 */ 450 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16) 451 #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18) 452 #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20) 453 454 /* Valid only for RX (IPA producer) endpoints */ 455 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 456 (0x00000818 + 0x0070 * (rxep)) 457 458 /* Valid only for TX (IPA consumer) endpoints */ 459 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 460 (0x00000820 + 0x0070 * (txep)) 461 #define MODE_FMASK GENMASK(2, 0) 462 /* The next field is present for IPA v4.5 */ 463 #define DCPH_ENABLE_FMASK GENMASK(3, 3) 464 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 465 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 466 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 467 #define PAD_EN_FMASK GENMASK(29, 29) 468 /* The next register is not present for IPA v4.5 */ 469 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 470 471 /** enum ipa_mode - mode field in ENDP_INIT_MODE_N */ 472 enum ipa_mode { 473 IPA_BASIC = 0x0, 474 IPA_ENABLE_FRAMING_HDLC = 0x1, 475 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 476 IPA_DMA = 0x3, 477 }; 478 479 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 480 (0x00000824 + 0x0070 * (ep)) 481 #define AGGR_EN_FMASK GENMASK(1, 0) 482 #define AGGR_TYPE_FMASK GENMASK(4, 2) 483 static inline u32 aggr_byte_limit_fmask(bool legacy) 484 { 485 return legacy ? GENMASK(9, 5) : GENMASK(10, 5); 486 } 487 488 static inline u32 aggr_time_limit_fmask(bool legacy) 489 { 490 return legacy ? GENMASK(14, 10) : GENMASK(16, 12); 491 } 492 493 static inline u32 aggr_pkt_limit_fmask(bool legacy) 494 { 495 return legacy ? GENMASK(20, 15) : GENMASK(22, 17); 496 } 497 498 static inline u32 aggr_sw_eof_active_fmask(bool legacy) 499 { 500 return legacy ? GENMASK(21, 21) : GENMASK(23, 23); 501 } 502 503 static inline u32 aggr_force_close_fmask(bool legacy) 504 { 505 return legacy ? GENMASK(22, 22) : GENMASK(24, 24); 506 } 507 508 static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy) 509 { 510 return legacy ? GENMASK(24, 24) : GENMASK(26, 26); 511 } 512 513 /* The next field is present for IPA v4.5 */ 514 #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27) 515 516 /** enum ipa_aggr_en - aggregation enable field in ENDP_INIT_AGGR_N */ 517 enum ipa_aggr_en { 518 IPA_BYPASS_AGGR = 0x0, 519 IPA_ENABLE_AGGR = 0x1, 520 IPA_ENABLE_DEAGGR = 0x2, 521 }; 522 523 /** enum ipa_aggr_type - aggregation type field in ENDP_INIT_AGGR_N */ 524 enum ipa_aggr_type { 525 IPA_MBIM_16 = 0x0, 526 IPA_HDLC = 0x1, 527 IPA_TLP = 0x2, 528 IPA_RNDIS = 0x3, 529 IPA_GENERIC = 0x4, 530 IPA_COALESCE = 0x5, 531 IPA_QCMAP = 0x6, 532 }; 533 534 /* Valid only for RX (IPA producer) endpoints */ 535 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 536 (0x0000082c + 0x0070 * (rxep)) 537 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 538 539 /* Valid only for RX (IPA producer) endpoints */ 540 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 541 (0x00000830 + 0x0070 * (rxep)) 542 /* The next two fields are present for IPA v4.2 only */ 543 #define BASE_VALUE_FMASK GENMASK(4, 0) 544 #define SCALE_FMASK GENMASK(12, 8) 545 /* The next two fields are present for IPA v4.5 */ 546 #define TIME_LIMIT_FMASK GENMASK(4, 0) 547 #define GRAN_SEL_FMASK GENMASK(8, 8) 548 549 /* Valid only for TX (IPA consumer) endpoints */ 550 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 551 (0x00000834 + 0x0070 * (txep)) 552 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 553 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 554 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 555 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 556 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 557 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 558 559 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 560 (0x00000838 + 0x0070 * (ep)) 561 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 562 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 563 { 564 switch (version) { 565 case IPA_VERSION_4_2: 566 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 567 case IPA_VERSION_4_5: 568 return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 569 default: 570 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 571 } 572 } 573 574 /* Valid only for TX (IPA consumer) endpoints */ 575 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 576 (0x0000083c + 0x0070 * (txep)) 577 #define HPS_SEQ_TYPE_FMASK GENMASK(3, 0) 578 #define DPS_SEQ_TYPE_FMASK GENMASK(7, 4) 579 #define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8) 580 #define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12) 581 582 /** 583 * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N 584 * @IPA_SEQ_DMA_ONLY: only DMA is performed 585 * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP: 586 * second packet processing pass + no decipher + microcontroller 587 * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP: 588 * packet processing + no decipher + no uCP + HPS REP DMA parser 589 * @IPA_SEQ_INVALID: invalid sequencer type 590 * 591 * The values defined here are broken into 4-bit nibbles that are written 592 * into fields of the ENDP_INIT_SEQ registers. 593 */ 594 enum ipa_seq_type { 595 IPA_SEQ_DMA_ONLY = 0x0000, 596 IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004, 597 IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806, 598 IPA_SEQ_INVALID = 0xffff, 599 }; 600 601 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 602 (0x00000840 + 0x0070 * (ep)) 603 #define STATUS_EN_FMASK GENMASK(0, 0) 604 #define STATUS_ENDP_FMASK GENMASK(5, 1) 605 /* The next field is not present for IPA v4.5 */ 606 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 607 /* The next field is not present for IPA v3.5.1 */ 608 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 609 610 /* The next register is only present for IPA versions that support hashing */ 611 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 612 (0x0000085c + 0x0070 * (er)) 613 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 614 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 615 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 616 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 617 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 618 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 619 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 620 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 621 622 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 623 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 624 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 625 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 626 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 627 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 628 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 629 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 630 631 #define IPA_REG_IRQ_STTS_OFFSET \ 632 IPA_REG_IRQ_STTS_EE_N_OFFSET(GSI_EE_AP) 633 #define IPA_REG_IRQ_STTS_EE_N_OFFSET(ee) \ 634 (0x00003008 + 0x1000 * (ee)) 635 636 #define IPA_REG_IRQ_EN_OFFSET \ 637 IPA_REG_IRQ_EN_EE_N_OFFSET(GSI_EE_AP) 638 #define IPA_REG_IRQ_EN_EE_N_OFFSET(ee) \ 639 (0x0000300c + 0x1000 * (ee)) 640 641 #define IPA_REG_IRQ_CLR_OFFSET \ 642 IPA_REG_IRQ_CLR_EE_N_OFFSET(GSI_EE_AP) 643 #define IPA_REG_IRQ_CLR_EE_N_OFFSET(ee) \ 644 (0x00003010 + 0x1000 * (ee)) 645 /** 646 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 647 * @IPA_IRQ_UC_0: Microcontroller event interrupt 648 * @IPA_IRQ_UC_1: Microcontroller response interrupt 649 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 650 * 651 * IRQ types not described above are not currently used. 652 */ 653 enum ipa_irq_id { 654 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 655 /* Type (bit) 0x1 is not defined */ 656 IPA_IRQ_UC_0 = 0x2, 657 IPA_IRQ_UC_1 = 0x3, 658 IPA_IRQ_UC_2 = 0x4, 659 IPA_IRQ_UC_3 = 0x5, 660 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 661 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 662 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 663 IPA_IRQ_RX_ERR = 0x9, 664 IPA_IRQ_DEAGGR_ERR = 0xa, 665 IPA_IRQ_TX_ERR = 0xb, 666 IPA_IRQ_STEP_MODE = 0xc, 667 IPA_IRQ_PROC_ERR = 0xd, 668 IPA_IRQ_TX_SUSPEND = 0xe, 669 IPA_IRQ_TX_HOLB_DROP = 0xf, 670 IPA_IRQ_BAM_GSI_IDLE = 0x10, 671 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 672 IPA_IRQ_PIPE_RED_BELOW = 0x12, 673 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 674 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 675 IPA_IRQ_UCP = 0x15, 676 IPA_IRQ_DCMP = 0x16, 677 IPA_IRQ_GSI_EE = 0x17, 678 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 679 IPA_IRQ_GSI_UC = 0x19, 680 /* The next bit is present for IPA v4.5 */ 681 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 682 IPA_IRQ_COUNT, /* Last; not an id */ 683 }; 684 685 #define IPA_REG_IRQ_UC_OFFSET \ 686 IPA_REG_IRQ_UC_EE_N_OFFSET(GSI_EE_AP) 687 #define IPA_REG_IRQ_UC_EE_N_OFFSET(ee) \ 688 (0x0000301c + 0x1000 * (ee)) 689 #define UC_INTR_FMASK GENMASK(0, 0) 690 691 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 692 #define IPA_REG_IRQ_SUSPEND_INFO_OFFSET \ 693 IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(GSI_EE_AP) 694 #define IPA_REG_IRQ_SUSPEND_INFO_EE_N_OFFSET(ee) \ 695 (0x00003030 + 0x1000 * (ee)) 696 697 /* ipa->available defines the valid bits in the IRQ_SUSPEND_EN register */ 698 #define IPA_REG_IRQ_SUSPEND_EN_OFFSET \ 699 IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(GSI_EE_AP) 700 #define IPA_REG_IRQ_SUSPEND_EN_EE_N_OFFSET(ee) \ 701 (0x00003034 + 0x1000 * (ee)) 702 703 /* ipa->available defines the valid bits in the IRQ_SUSPEND_CLR register */ 704 #define IPA_REG_IRQ_SUSPEND_CLR_OFFSET \ 705 IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(GSI_EE_AP) 706 #define IPA_REG_IRQ_SUSPEND_CLR_EE_N_OFFSET(ee) \ 707 (0x00003038 + 0x1000 * (ee)) 708 709 int ipa_reg_init(struct ipa *ipa); 710 void ipa_reg_exit(struct ipa *ipa); 711 712 #endif /* _IPA_REG_H_ */ 713