1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2023 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 #include <linux/bug.h> 11 12 #include "ipa_version.h" 13 14 struct ipa; 15 16 /** 17 * DOC: IPA Registers 18 * 19 * IPA registers are located within the "ipa-reg" address space defined by 20 * Device Tree. Each register has a specified offset within that space, 21 * which is mapped into virtual memory space in ipa_mem_init(). Each 22 * has a unique identifer, taken from the ipa_reg_id enumerated type. 23 * All IPA registers are 32 bits wide. 24 * 25 * Certain "parameterized" register types are duplicated for a number of 26 * instances of something. For example, each IPA endpoint has an set of 27 * registers defining its configuration. The offset to an endpoint's set 28 * of registers is computed based on an "base" offset, plus an endpoint's 29 * ID multiplied and a "stride" value for the register. Similarly, some 30 * registers have an offset that depends on execution environment. In 31 * this case, the stride is multiplied by a member of the gsi_ee_id 32 * enumerated type. 33 * 34 * Each version of IPA implements an array of ipa_reg structures indexed 35 * by register ID. Each entry in the array specifies the base offset and 36 * (for parameterized registers) a non-zero stride value. Not all versions 37 * of IPA define all registers. The offset for a register is returned by 38 * ipa_reg_offset() when the register's ipa_reg structure is supplied; 39 * zero is returned for an undefined register (this should never happen). 40 * 41 * Some registers encode multiple fields within them. Each field in 42 * such a register has a unique identifier (from an enumerated type). 43 * The position and width of the fields in a register are defined by 44 * an array of field masks, indexed by field ID. Two functions are 45 * used to access register fields; both take an ipa_reg structure as 46 * argument. To encode a value to be represented in a register field, 47 * the value and field ID are passed to ipa_reg_encode(). To extract 48 * a value encoded in a register field, the field ID is passed to 49 * ipa_reg_decode(). In addition, for single-bit fields, ipa_reg_bit() 50 * can be used to either encode the bit value, or to generate a mask 51 * used to extract the bit value. 52 */ 53 54 /* enum ipa_reg_id - IPA register IDs */ 55 enum ipa_reg_id { 56 COMP_CFG, 57 CLKON_CFG, 58 ROUTE, 59 SHARED_MEM_SIZE, 60 QSB_MAX_WRITES, 61 QSB_MAX_READS, 62 FILT_ROUT_HASH_EN, /* Not IPA v5.0+ */ 63 FILT_ROUT_CACHE_CFG, /* IPA v5.0+ */ 64 FILT_ROUT_HASH_FLUSH, /* Not IPA v5.0+ */ 65 FILT_ROUT_CACHE_FLUSH, /* IPA v5.0+ */ 66 STATE_AGGR_ACTIVE, 67 IPA_BCR, /* Not IPA v4.5+ */ 68 LOCAL_PKT_PROC_CNTXT, 69 AGGR_FORCE_CLOSE, 70 COUNTER_CFG, /* Not IPA v4.5+ */ 71 IPA_TX_CFG, /* IPA v3.5+ */ 72 FLAVOR_0, /* IPA v3.5+ */ 73 IDLE_INDICATION_CFG, /* IPA v3.5+ */ 74 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */ 75 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */ 76 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */ 77 SRC_RSRC_GRP_01_RSRC_TYPE, 78 SRC_RSRC_GRP_23_RSRC_TYPE, 79 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 80 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 81 DST_RSRC_GRP_01_RSRC_TYPE, 82 DST_RSRC_GRP_23_RSRC_TYPE, 83 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+, IPA v4.5 */ 84 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+ */ 85 ENDP_INIT_CTRL, /* Not IPA v4.2+ for TX, not IPA v4.0+ for RX */ 86 ENDP_INIT_CFG, 87 ENDP_INIT_NAT, /* TX only */ 88 ENDP_INIT_HDR, 89 ENDP_INIT_HDR_EXT, 90 ENDP_INIT_HDR_METADATA_MASK, /* RX only */ 91 ENDP_INIT_MODE, /* TX only */ 92 ENDP_INIT_AGGR, 93 ENDP_INIT_HOL_BLOCK_EN, /* RX only */ 94 ENDP_INIT_HOL_BLOCK_TIMER, /* RX only */ 95 ENDP_INIT_DEAGGR, /* TX only */ 96 ENDP_INIT_RSRC_GRP, 97 ENDP_INIT_SEQ, /* TX only */ 98 ENDP_STATUS, 99 ENDP_FILTER_ROUTER_HSH_CFG, /* Not IPA v4.2 */ 100 ENDP_FILTER_CACHE_CFG, /* IPA v5.0+ */ 101 ENDP_ROUTER_CACHE_CFG, /* IPA v5.0+ */ 102 /* The IRQ registers that follow are only used for GSI_EE_AP */ 103 IPA_IRQ_STTS, 104 IPA_IRQ_EN, 105 IPA_IRQ_CLR, 106 IPA_IRQ_UC, 107 IRQ_SUSPEND_INFO, 108 IRQ_SUSPEND_EN, /* IPA v3.1+ */ 109 IRQ_SUSPEND_CLR, /* IPA v3.1+ */ 110 IPA_REG_ID_COUNT, /* Last; not an ID */ 111 }; 112 113 /** 114 * struct ipa_reg - An IPA register descriptor 115 * @offset: Register offset relative to base of the "ipa-reg" memory 116 * @stride: Distance between two instances, if parameterized 117 * @fcount: Number of entries in the @fmask array 118 * @fmask: Array of mask values defining position and width of fields 119 * @name: Upper-case name of the IPA register 120 */ 121 struct ipa_reg { 122 u32 offset; 123 u32 stride; 124 u32 fcount; 125 const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */ 126 const char *name; 127 }; 128 129 /* Helper macro for defining "simple" (non-parameterized) registers */ 130 #define IPA_REG(__NAME, __reg_id, __offset) \ 131 IPA_REG_STRIDE(__NAME, __reg_id, __offset, 0) 132 133 /* Helper macro for defining parameterized registers, specifying stride */ 134 #define IPA_REG_STRIDE(__NAME, __reg_id, __offset, __stride) \ 135 static const struct ipa_reg ipa_reg_ ## __reg_id = { \ 136 .name = #__NAME, \ 137 .offset = __offset, \ 138 .stride = __stride, \ 139 } 140 141 #define IPA_REG_FIELDS(__NAME, __name, __offset) \ 142 IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, 0) 143 144 #define IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \ 145 static const struct ipa_reg ipa_reg_ ## __name = { \ 146 .name = #__NAME, \ 147 .offset = __offset, \ 148 .stride = __stride, \ 149 .fcount = ARRAY_SIZE(ipa_reg_ ## __name ## _fmask), \ 150 .fmask = ipa_reg_ ## __name ## _fmask, \ 151 } 152 153 /** 154 * struct ipa_regs - Description of registers supported by hardware 155 * @reg_count: Number of registers in the @reg[] array 156 * @reg: Array of register descriptors 157 */ 158 struct ipa_regs { 159 u32 reg_count; 160 const struct ipa_reg **reg; 161 }; 162 163 /* COMP_CFG register */ 164 enum ipa_reg_comp_cfg_field_id { 165 COMP_CFG_ENABLE, /* Not IPA v4.0+ */ 166 RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */ 167 GSI_SNOC_BYPASS_DIS, 168 GEN_QMB_0_SNOC_BYPASS_DIS, 169 GEN_QMB_1_SNOC_BYPASS_DIS, 170 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */ 171 IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */ 172 IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */ 173 GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 174 GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 175 GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 176 GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */ 177 GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 178 GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */ 179 GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */ 180 GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */ 181 GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */ 182 IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */ 183 QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */ 184 GENQMB_AOOOWR, /* IPA v4.9+ */ 185 IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */ 186 GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */ 187 GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */ 188 ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */ 189 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */ 190 }; 191 192 /* CLKON_CFG register */ 193 enum ipa_reg_clkon_cfg_field_id { 194 CLKON_RX, 195 CLKON_PROC, 196 TX_WRAPPER, 197 CLKON_MISC, 198 RAM_ARB, 199 FTCH_HPS, 200 FTCH_DPS, 201 CLKON_HPS, 202 CLKON_DPS, 203 RX_HPS_CMDQS, 204 HPS_DPS_CMDQS, 205 DPS_TX_CMDQS, 206 RSRC_MNGR, 207 CTX_HANDLER, 208 ACK_MNGR, 209 D_DCPH, 210 H_DCPH, 211 CLKON_DCMP, /* IPA v4.5+ */ 212 NTF_TX_CMDQS, /* IPA v3.5+ */ 213 CLKON_TX_0, /* IPA v3.5+ */ 214 CLKON_TX_1, /* IPA v3.5+ */ 215 CLKON_FNR, /* IPA v3.5.1+ */ 216 QSB2AXI_CMDQ_L, /* IPA v4.0+ */ 217 AGGR_WRAPPER, /* IPA v4.0+ */ 218 RAM_SLAVEWAY, /* IPA v4.0+ */ 219 CLKON_QMB, /* IPA v4.0+ */ 220 WEIGHT_ARB, /* IPA v4.0+ */ 221 GSI_IF, /* IPA v4.0+ */ 222 CLKON_GLOBAL, /* IPA v4.0+ */ 223 GLOBAL_2X_CLK, /* IPA v4.0+ */ 224 DPL_FIFO, /* IPA v4.5+ */ 225 DRBIP, /* IPA v4.7+ */ 226 }; 227 228 /* ROUTE register */ 229 enum ipa_reg_route_field_id { 230 ROUTE_DIS, 231 ROUTE_DEF_PIPE, 232 ROUTE_DEF_HDR_TABLE, 233 ROUTE_DEF_HDR_OFST, 234 ROUTE_FRAG_DEF_PIPE, 235 ROUTE_DEF_RETAIN_HDR, 236 }; 237 238 /* SHARED_MEM_SIZE register */ 239 enum ipa_reg_shared_mem_size_field_id { 240 MEM_SIZE, 241 MEM_BADDR, 242 }; 243 244 /* QSB_MAX_WRITES register */ 245 enum ipa_reg_qsb_max_writes_field_id { 246 GEN_QMB_0_MAX_WRITES, 247 GEN_QMB_1_MAX_WRITES, 248 }; 249 250 /* QSB_MAX_READS register */ 251 enum ipa_reg_qsb_max_reads_field_id { 252 GEN_QMB_0_MAX_READS, 253 GEN_QMB_1_MAX_READS, 254 GEN_QMB_0_MAX_READS_BEATS, /* IPA v4.0+ */ 255 GEN_QMB_1_MAX_READS_BEATS, /* IPA v4.0+ */ 256 }; 257 258 /* FILT_ROUT_CACHE_CFG register */ 259 enum ipa_reg_filt_rout_cache_cfg_field_id { 260 ROUTER_CACHE_EN, 261 FILTER_CACHE_EN, 262 LOW_PRI_HASH_HIT_DISABLE, 263 LRU_EVICTION_THRESHOLD, 264 }; 265 266 /* FILT_ROUT_HASH_EN and FILT_ROUT_HASH_FLUSH registers */ 267 enum ipa_reg_filt_rout_hash_field_id { 268 IPV6_ROUTER_HASH, 269 IPV6_FILTER_HASH, 270 IPV4_ROUTER_HASH, 271 IPV4_FILTER_HASH, 272 }; 273 274 /* FILT_ROUT_CACHE_FLUSH register */ 275 enum ipa_reg_filt_rout_cache_field_id { 276 ROUTER_CACHE, 277 FILTER_CACHE, 278 }; 279 280 /* BCR register */ 281 enum ipa_bcr_compat { 282 BCR_CMDQ_L_LACK_ONE_ENTRY = 0x0, /* Not IPA v4.2+ */ 283 BCR_TX_NOT_USING_BRESP = 0x1, /* Not IPA v4.2+ */ 284 BCR_TX_SUSPEND_IRQ_ASSERT_ONCE = 0x2, /* Not IPA v4.0+ */ 285 BCR_SUSPEND_L2_IRQ = 0x3, /* Not IPA v4.2+ */ 286 BCR_HOLB_DROP_L2_IRQ = 0x4, /* Not IPA v4.2+ */ 287 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */ 288 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */ 289 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */ 290 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */ 291 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */ 292 }; 293 294 /* LOCAL_PKT_PROC_CNTXT register */ 295 enum ipa_reg_local_pkt_proc_cntxt_field_id { 296 IPA_BASE_ADDR, 297 }; 298 299 /* COUNTER_CFG register */ 300 enum ipa_reg_counter_cfg_field_id { 301 EOT_COAL_GRANULARITY, /* Not v3.5+ */ 302 AGGR_GRANULARITY, 303 }; 304 305 /* IPA_TX_CFG register */ 306 enum ipa_reg_ipa_tx_cfg_field_id { 307 TX0_PREFETCH_DISABLE, /* Not v4.0+ */ 308 TX1_PREFETCH_DISABLE, /* Not v4.0+ */ 309 PREFETCH_ALMOST_EMPTY_SIZE, /* Not v4.0+ */ 310 PREFETCH_ALMOST_EMPTY_SIZE_TX0, /* v4.0+ */ 311 DMAW_SCND_OUTSD_PRED_THRESHOLD, /* v4.0+ */ 312 DMAW_SCND_OUTSD_PRED_EN, /* v4.0+ */ 313 DMAW_MAX_BEATS_256_DIS, /* v4.0+ */ 314 PA_MASK_EN, /* v4.0+ */ 315 PREFETCH_ALMOST_EMPTY_SIZE_TX1, /* v4.0+ */ 316 DUAL_TX_ENABLE, /* v4.5+ */ 317 SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */ 318 SSPND_PA_NO_BQ_STATE, /* v4.2 only */ 319 HOLB_STICKY_DROP_EN, /* v5.0+ */ 320 }; 321 322 /* FLAVOR_0 register */ 323 enum ipa_reg_flavor_0_field_id { 324 MAX_PIPES, 325 MAX_CONS_PIPES, 326 MAX_PROD_PIPES, 327 PROD_LOWEST, 328 }; 329 330 /* IDLE_INDICATION_CFG register */ 331 enum ipa_reg_idle_indication_cfg_field_id { 332 ENTER_IDLE_DEBOUNCE_THRESH, 333 CONST_NON_IDLE_ENABLE, 334 }; 335 336 /* QTIME_TIMESTAMP_CFG register */ 337 enum ipa_reg_qtime_timestamp_cfg_field_id { 338 DPL_TIMESTAMP_LSB, 339 DPL_TIMESTAMP_SEL, 340 TAG_TIMESTAMP_LSB, 341 NAT_TIMESTAMP_LSB, 342 }; 343 344 /* TIMERS_XO_CLK_DIV_CFG register */ 345 enum ipa_reg_timers_xo_clk_div_cfg_field_id { 346 DIV_VALUE, 347 DIV_ENABLE, 348 }; 349 350 /* TIMERS_PULSE_GRAN_CFG register */ 351 enum ipa_reg_timers_pulse_gran_cfg_field_id { 352 PULSE_GRAN_0, 353 PULSE_GRAN_1, 354 PULSE_GRAN_2, 355 PULSE_GRAN_3, 356 }; 357 358 /* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 359 enum ipa_pulse_gran { 360 IPA_GRAN_10_US = 0x0, 361 IPA_GRAN_20_US = 0x1, 362 IPA_GRAN_50_US = 0x2, 363 IPA_GRAN_100_US = 0x3, 364 IPA_GRAN_1_MS = 0x4, 365 IPA_GRAN_10_MS = 0x5, 366 IPA_GRAN_100_MS = 0x6, 367 IPA_GRAN_655350_US = 0x7, 368 }; 369 370 /* {SRC,DST}_RSRC_GRP_{01,23,45,67}_RSRC_TYPE registers */ 371 enum ipa_reg_rsrc_grp_rsrc_type_field_id { 372 X_MIN_LIM, 373 X_MAX_LIM, 374 Y_MIN_LIM, 375 Y_MAX_LIM, 376 }; 377 378 /* ENDP_INIT_CTRL register */ 379 enum ipa_reg_endp_init_ctrl_field_id { 380 ENDP_SUSPEND, /* Not v4.0+ */ 381 ENDP_DELAY, /* Not v4.2+ */ 382 }; 383 384 /* ENDP_INIT_CFG register */ 385 enum ipa_reg_endp_init_cfg_field_id { 386 FRAG_OFFLOAD_EN, 387 CS_OFFLOAD_EN, 388 CS_METADATA_HDR_OFFSET, 389 CS_GEN_QMB_MASTER_SEL, 390 }; 391 392 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 393 enum ipa_cs_offload_en { 394 IPA_CS_OFFLOAD_NONE = 0x0, 395 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */ 396 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */ 397 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */ 398 }; 399 400 /* ENDP_INIT_NAT register */ 401 enum ipa_reg_endp_init_nat_field_id { 402 NAT_EN, 403 }; 404 405 /** enum ipa_nat_type - ENDP_INIT_NAT register NAT_EN field value */ 406 enum ipa_nat_type { 407 IPA_NAT_TYPE_BYPASS = 0, 408 IPA_NAT_TYPE_SRC = 1, 409 IPA_NAT_TYPE_DST = 2, 410 }; 411 412 /* ENDP_INIT_HDR register */ 413 enum ipa_reg_endp_init_hdr_field_id { 414 HDR_LEN, 415 HDR_OFST_METADATA_VALID, 416 HDR_OFST_METADATA, 417 HDR_ADDITIONAL_CONST_LEN, 418 HDR_OFST_PKT_SIZE_VALID, 419 HDR_OFST_PKT_SIZE, 420 HDR_A5_MUX, /* Not v4.9+ */ 421 HDR_LEN_INC_DEAGG_HDR, 422 HDR_METADATA_REG_VALID, /* Not v4.5+ */ 423 HDR_LEN_MSB, /* v4.5+ */ 424 HDR_OFST_METADATA_MSB, /* v4.5+ */ 425 }; 426 427 /* ENDP_INIT_HDR_EXT register */ 428 enum ipa_reg_endp_init_hdr_ext_field_id { 429 HDR_ENDIANNESS, 430 HDR_TOTAL_LEN_OR_PAD_VALID, 431 HDR_TOTAL_LEN_OR_PAD, 432 HDR_PAYLOAD_LEN_INC_PADDING, 433 HDR_TOTAL_LEN_OR_PAD_OFFSET, 434 HDR_PAD_TO_ALIGNMENT, 435 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */ 436 HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */ 437 HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */ 438 HDR_BYTES_TO_REMOVE_VALID, /* v5.0+ */ 439 HDR_BYTES_TO_REMOVE, /* v5.0+ */ 440 }; 441 442 /* ENDP_INIT_MODE register */ 443 enum ipa_reg_endp_init_mode_field_id { 444 ENDP_MODE, 445 DCPH_ENABLE, /* v4.5+ */ 446 DEST_PIPE_INDEX, 447 BYTE_THRESHOLD, 448 PIPE_REPLICATION_EN, 449 PAD_EN, 450 HDR_FTCH_DISABLE, /* v4.5+ */ 451 DRBIP_ACL_ENABLE, /* v4.9+ */ 452 }; 453 454 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 455 enum ipa_mode { 456 IPA_BASIC = 0x0, 457 IPA_ENABLE_FRAMING_HDLC = 0x1, 458 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 459 IPA_DMA = 0x3, 460 }; 461 462 /* ENDP_INIT_AGGR register */ 463 enum ipa_reg_endp_init_aggr_field_id { 464 AGGR_EN, 465 AGGR_TYPE, 466 BYTE_LIMIT, 467 TIME_LIMIT, 468 PKT_LIMIT, 469 SW_EOF_ACTIVE, 470 FORCE_CLOSE, 471 HARD_BYTE_LIMIT_EN, 472 AGGR_GRAN_SEL, 473 }; 474 475 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 476 enum ipa_aggr_en { 477 IPA_BYPASS_AGGR /* TX and RX */ = 0x0, 478 IPA_ENABLE_AGGR /* RX */ = 0x1, 479 IPA_ENABLE_DEAGGR /* TX */ = 0x2, 480 }; 481 482 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 483 enum ipa_aggr_type { 484 IPA_MBIM_16 = 0x0, 485 IPA_HDLC = 0x1, 486 IPA_TLP = 0x2, 487 IPA_RNDIS = 0x3, 488 IPA_GENERIC = 0x4, 489 IPA_COALESCE = 0x5, 490 IPA_QCMAP = 0x6, 491 }; 492 493 /* ENDP_INIT_HOL_BLOCK_EN register */ 494 enum ipa_reg_endp_init_hol_block_en_field_id { 495 HOL_BLOCK_EN, 496 }; 497 498 /* ENDP_INIT_HOL_BLOCK_TIMER register */ 499 enum ipa_reg_endp_init_hol_block_timer_field_id { 500 TIMER_BASE_VALUE, /* Not v4.5+ */ 501 TIMER_SCALE, /* v4.2 only */ 502 TIMER_LIMIT, /* v4.5+ */ 503 TIMER_GRAN_SEL, /* v4.5+ */ 504 }; 505 506 /* ENDP_INIT_DEAGGR register */ 507 enum ipa_reg_endp_deaggr_field_id { 508 DEAGGR_HDR_LEN, 509 SYSPIPE_ERR_DETECTION, 510 PACKET_OFFSET_VALID, 511 PACKET_OFFSET_LOCATION, 512 IGNORE_MIN_PKT_ERR, 513 MAX_PACKET_LEN, 514 }; 515 516 /* ENDP_INIT_RSRC_GRP register */ 517 enum ipa_reg_endp_init_rsrc_grp_field_id { 518 ENDP_RSRC_GRP, 519 }; 520 521 /* ENDP_INIT_SEQ register */ 522 enum ipa_reg_endp_init_seq_field_id { 523 SEQ_TYPE, 524 SEQ_REP_TYPE, /* Not v4.5+ */ 525 }; 526 527 /** 528 * enum ipa_seq_type - HPS and DPS sequencer type 529 * @IPA_SEQ_DMA: Perform DMA only 530 * @IPA_SEQ_1_PASS: One pass through the pipeline 531 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 532 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 533 * @IPA_SEQ_2_PASS: Two passes through the pipeline 534 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 535 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 536 * 537 * The low-order byte of the sequencer type register defines the number of 538 * passes a packet takes through the IPA pipeline. The last pass through can 539 * optionally skip the microprocessor. Deciphering is optional for all types; 540 * if enabled, an additional mask (two bits) is added to the type value. 541 * 542 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 543 * supported (or meaningful). 544 */ 545 enum ipa_seq_type { 546 IPA_SEQ_DMA = 0x00, 547 IPA_SEQ_1_PASS = 0x02, 548 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 549 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 550 IPA_SEQ_2_PASS = 0x0a, 551 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 552 /* The next value can be ORed with the above */ 553 IPA_SEQ_DECIPHER = 0x11, 554 }; 555 556 /** 557 * enum ipa_seq_rep_type - replicated packet sequencer type 558 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 559 * 560 * This goes in the second byte of the endpoint sequencer type register. 561 * 562 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 563 * supported (or meaningful). 564 */ 565 enum ipa_seq_rep_type { 566 IPA_SEQ_REP_DMA_PARSER = 0x08, 567 }; 568 569 /* ENDP_STATUS register */ 570 enum ipa_reg_endp_status_field_id { 571 STATUS_EN, 572 STATUS_ENDP, 573 STATUS_LOCATION, /* Not v4.5+ */ 574 STATUS_PKT_SUPPRESS, /* v4.0+ */ 575 }; 576 577 /* ENDP_FILTER_ROUTER_HSH_CFG register */ 578 enum ipa_reg_endp_filter_router_hsh_cfg_field_id { 579 FILTER_HASH_MSK_SRC_ID, 580 FILTER_HASH_MSK_SRC_IP, 581 FILTER_HASH_MSK_DST_IP, 582 FILTER_HASH_MSK_SRC_PORT, 583 FILTER_HASH_MSK_DST_PORT, 584 FILTER_HASH_MSK_PROTOCOL, 585 FILTER_HASH_MSK_METADATA, 586 FILTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 587 588 ROUTER_HASH_MSK_SRC_ID, 589 ROUTER_HASH_MSK_SRC_IP, 590 ROUTER_HASH_MSK_DST_IP, 591 ROUTER_HASH_MSK_SRC_PORT, 592 ROUTER_HASH_MSK_DST_PORT, 593 ROUTER_HASH_MSK_PROTOCOL, 594 ROUTER_HASH_MSK_METADATA, 595 ROUTER_HASH_MSK_ALL, /* Bitwise OR of the above 6 fields */ 596 }; 597 598 /* ENDP_FILTER_CACHE_CFG and ENDP_ROUTER_CACHE_CFG registers */ 599 enum ipa_reg_endp_cache_cfg_field_id { 600 CACHE_MSK_SRC_ID, 601 CACHE_MSK_SRC_IP, 602 CACHE_MSK_DST_IP, 603 CACHE_MSK_SRC_PORT, 604 CACHE_MSK_DST_PORT, 605 CACHE_MSK_PROTOCOL, 606 CACHE_MSK_METADATA, 607 }; 608 609 /* IPA_IRQ_STTS, IPA_IRQ_EN, and IPA_IRQ_CLR registers */ 610 /** 611 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 612 * @IPA_IRQ_UC_0: Microcontroller event interrupt 613 * @IPA_IRQ_UC_1: Microcontroller response interrupt 614 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 615 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 616 * 617 * IRQ types not described above are not currently used. 618 * 619 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 620 * @IPA_IRQ_EOT_COAL: (Not currently used) 621 * @IPA_IRQ_UC_2: (Not currently used) 622 * @IPA_IRQ_UC_3: (Not currently used) 623 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 624 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 625 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 626 * @IPA_IRQ_RX_ERR: (Not currently used) 627 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 628 * @IPA_IRQ_TX_ERR: (Not currently used) 629 * @IPA_IRQ_STEP_MODE: (Not currently used) 630 * @IPA_IRQ_PROC_ERR: (Not currently used) 631 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 632 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 633 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 634 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 635 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 636 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 637 * @IPA_IRQ_UCP: (Not currently used) 638 * @IPA_IRQ_DCMP: (Not currently used) 639 * @IPA_IRQ_GSI_EE: (Not currently used) 640 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 641 * @IPA_IRQ_GSI_UC: (Not currently used) 642 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 643 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 644 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 645 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 646 */ 647 enum ipa_irq_id { 648 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 649 /* The next bit is not present for IPA v3.5+ */ 650 IPA_IRQ_EOT_COAL = 0x1, 651 IPA_IRQ_UC_0 = 0x2, 652 IPA_IRQ_UC_1 = 0x3, 653 IPA_IRQ_UC_2 = 0x4, 654 IPA_IRQ_UC_3 = 0x5, 655 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 656 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 657 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 658 IPA_IRQ_RX_ERR = 0x9, 659 IPA_IRQ_DEAGGR_ERR = 0xa, 660 IPA_IRQ_TX_ERR = 0xb, 661 IPA_IRQ_STEP_MODE = 0xc, 662 IPA_IRQ_PROC_ERR = 0xd, 663 IPA_IRQ_TX_SUSPEND = 0xe, 664 IPA_IRQ_TX_HOLB_DROP = 0xf, 665 IPA_IRQ_BAM_GSI_IDLE = 0x10, 666 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 667 IPA_IRQ_PIPE_RED_BELOW = 0x12, 668 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 669 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 670 IPA_IRQ_UCP = 0x15, 671 /* The next bit is not present for IPA v4.5+ */ 672 IPA_IRQ_DCMP = 0x16, 673 IPA_IRQ_GSI_EE = 0x17, 674 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 675 IPA_IRQ_GSI_UC = 0x19, 676 /* The next bit is present for IPA v4.5+ */ 677 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 678 /* The next three bits are present for IPA v4.9+ */ 679 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 680 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 681 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 682 IPA_IRQ_COUNT, /* Last; not an id */ 683 }; 684 685 /* IPA_IRQ_UC register */ 686 enum ipa_reg_ipa_irq_uc_field_id { 687 UC_INTR, 688 }; 689 690 extern const struct ipa_regs ipa_regs_v3_1; 691 extern const struct ipa_regs ipa_regs_v3_5_1; 692 extern const struct ipa_regs ipa_regs_v4_2; 693 extern const struct ipa_regs ipa_regs_v4_5; 694 extern const struct ipa_regs ipa_regs_v4_7; 695 extern const struct ipa_regs ipa_regs_v4_9; 696 extern const struct ipa_regs ipa_regs_v4_11; 697 698 /* Return the field mask for a field in a register */ 699 static inline u32 ipa_reg_fmask(const struct ipa_reg *reg, u32 field_id) 700 { 701 if (!reg || WARN_ON(field_id >= reg->fcount)) 702 return 0; 703 704 return reg->fmask[field_id]; 705 } 706 707 /* Return the mask for a single-bit field in a register */ 708 static inline u32 ipa_reg_bit(const struct ipa_reg *reg, u32 field_id) 709 { 710 u32 fmask = ipa_reg_fmask(reg, field_id); 711 712 WARN_ON(!is_power_of_2(fmask)); 713 714 return fmask; 715 } 716 717 /* Encode a value into the given field of a register */ 718 static inline u32 719 ipa_reg_encode(const struct ipa_reg *reg, u32 field_id, u32 val) 720 { 721 u32 fmask = ipa_reg_fmask(reg, field_id); 722 723 if (!fmask) 724 return 0; 725 726 val <<= __ffs(fmask); 727 if (WARN_ON(val & ~fmask)) 728 return 0; 729 730 return val; 731 } 732 733 /* Given a register value, decode (extract) the value in the given field */ 734 static inline u32 735 ipa_reg_decode(const struct ipa_reg *reg, u32 field_id, u32 val) 736 { 737 u32 fmask = ipa_reg_fmask(reg, field_id); 738 739 return fmask ? (val & fmask) >> __ffs(fmask) : 0; 740 } 741 742 /* Return the maximum value representable by the given field; always 2^n - 1 */ 743 static inline u32 ipa_reg_field_max(const struct ipa_reg *reg, u32 field_id) 744 { 745 u32 fmask = ipa_reg_fmask(reg, field_id); 746 747 return fmask ? fmask >> __ffs(fmask) : 0; 748 } 749 750 const struct ipa_reg *ipa_reg(struct ipa *ipa, enum ipa_reg_id reg_id); 751 752 /* Returns 0 for NULL reg; warning will have already been issued */ 753 static inline u32 ipa_reg_offset(const struct ipa_reg *reg) 754 { 755 return reg ? reg->offset : 0; 756 } 757 758 /* Returns 0 for NULL reg; warning will have already been issued */ 759 static inline u32 ipa_reg_n_offset(const struct ipa_reg *reg, u32 n) 760 { 761 return reg ? reg->offset + n * reg->stride : 0; 762 } 763 764 int ipa_reg_init(struct ipa *ipa); 765 void ipa_reg_exit(struct ipa *ipa); 766 767 #endif /* _IPA_REG_H_ */ 768