1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 #ifndef _IPA_REG_H_ 7 #define _IPA_REG_H_ 8 9 #include <linux/bitfield.h> 10 11 #include "ipa_version.h" 12 13 struct ipa; 14 15 /** 16 * DOC: IPA Registers 17 * 18 * IPA registers are located within the "ipa-reg" address space defined by 19 * Device Tree. The offset of each register within that space is specified 20 * by symbols defined below. The address space is mapped to virtual memory 21 * space in ipa_mem_init(). All IPA registers are 32 bits wide. 22 * 23 * Certain register types are duplicated for a number of instances of 24 * something. For example, each IPA endpoint has an set of registers 25 * defining its configuration. The offset to an endpoint's set of registers 26 * is computed based on an "base" offset, plus an endpoint's ID multiplied 27 * and a "stride" value for the register. For such registers, the offset is 28 * computed by a function-like macro that takes a parameter used in the 29 * computation. 30 * 31 * Some register offsets depend on execution environment. For these an "ee" 32 * parameter is supplied to the offset macro. The "ee" value is a member of 33 * the gsi_ee enumerated type. 34 * 35 * The offset of a register dependent on endpoint ID is computed by a macro 36 * that is supplied a parameter "ep", "txep", or "rxep". A register with an 37 * "ep" parameter is valid for any endpoint; a register with a "txep" or 38 * "rxep" parameter is valid only for TX or RX endpoints, respectively. The 39 * "*ep" value is assumed to be less than the maximum valid endpoint ID 40 * for the current hardware, and that will not exceed IPA_ENDPOINT_MAX. 41 * 42 * The offset of registers related to filter and route tables is computed 43 * by a macro that is supplied a parameter "er". The "er" represents an 44 * endpoint ID for filters, or a route ID for routes. For filters, the 45 * endpoint ID must be less than IPA_ENDPOINT_MAX, but is further restricted 46 * because not all endpoints support filtering. For routes, the route ID 47 * must be less than IPA_ROUTE_MAX. 48 * 49 * The offset of registers related to resource types is computed by a macro 50 * that is supplied a parameter "rt". The "rt" represents a resource type, 51 * which is is a member of the ipa_resource_type_src enumerated type for 52 * source endpoint resources or the ipa_resource_type_dst enumerated type 53 * for destination endpoint resources. 54 * 55 * Some registers encode multiple fields within them. For these, each field 56 * has a symbol below defining a field mask that encodes both the position 57 * and width of the field within its register. 58 * 59 * In some cases, different versions of IPA hardware use different offset or 60 * field mask values. In such cases an inline_function(ipa) is used rather 61 * than a MACRO to define the offset or field mask to use. 62 * 63 * Finally, some registers hold bitmasks representing endpoints. In such 64 * cases the @available field in the @ipa structure defines the "full" set 65 * of valid bits for the register. 66 */ 67 68 #define IPA_REG_COMP_CFG_OFFSET 0x0000003c 69 /* The next field is not supported for IPA v4.0+, not present for IPA v4.5+ */ 70 #define ENABLE_FMASK GENMASK(0, 0) 71 /* The next field is present for IPA v4.7+ */ 72 #define RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS_FMASK GENMASK(0, 0) 73 #define GSI_SNOC_BYPASS_DIS_FMASK GENMASK(1, 1) 74 #define GEN_QMB_0_SNOC_BYPASS_DIS_FMASK GENMASK(2, 2) 75 #define GEN_QMB_1_SNOC_BYPASS_DIS_FMASK GENMASK(3, 3) 76 /* The next field is not present for IPA v4.5+ */ 77 #define IPA_DCMP_FAST_CLK_EN_FMASK GENMASK(4, 4) 78 /* The next twelve fields are present for IPA v4.0+ */ 79 #define IPA_QMB_SELECT_CONS_EN_FMASK GENMASK(5, 5) 80 #define IPA_QMB_SELECT_PROD_EN_FMASK GENMASK(6, 6) 81 #define GSI_MULTI_INORDER_RD_DIS_FMASK GENMASK(7, 7) 82 #define GSI_MULTI_INORDER_WR_DIS_FMASK GENMASK(8, 8) 83 #define GEN_QMB_0_MULTI_INORDER_RD_DIS_FMASK GENMASK(9, 9) 84 #define GEN_QMB_1_MULTI_INORDER_RD_DIS_FMASK GENMASK(10, 10) 85 #define GEN_QMB_0_MULTI_INORDER_WR_DIS_FMASK GENMASK(11, 11) 86 #define GEN_QMB_1_MULTI_INORDER_WR_DIS_FMASK GENMASK(12, 12) 87 #define GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS_FMASK GENMASK(13, 13) 88 #define GSI_SNOC_CNOC_LOOP_PROT_DISABLE_FMASK GENMASK(14, 14) 89 #define GSI_MULTI_AXI_MASTERS_DIS_FMASK GENMASK(15, 15) 90 #define IPA_QMB_SELECT_GLOBAL_EN_FMASK GENMASK(16, 16) 91 /* The next five fields are present for IPA v4.9+ */ 92 #define QMB_RAM_RD_CACHE_DISABLE_FMASK GENMASK(19, 19) 93 #define GENQMB_AOOOWR_FMASK GENMASK(20, 20) 94 #define IF_OUT_OF_BUF_STOP_RESET_MASK_EN_FMASK GENMASK(21, 21) 95 #define GEN_QMB_1_DYNAMIC_ASIZE_FMASK GENMASK(30, 30) 96 #define GEN_QMB_0_DYNAMIC_ASIZE_FMASK GENMASK(31, 31) 97 98 /* Encoded value for COMP_CFG register ATOMIC_FETCHER_ARB_LOCK_DIS field */ 99 static inline u32 arbitration_lock_disable_encoded(enum ipa_version version, 100 u32 mask) 101 { 102 /* assert(version >= IPA_VERSION_4_0); */ 103 104 if (version < IPA_VERSION_4_9) 105 return u32_encode_bits(mask, GENMASK(20, 17)); 106 107 if (version == IPA_VERSION_4_9) 108 return u32_encode_bits(mask, GENMASK(24, 22)); 109 110 return u32_encode_bits(mask, GENMASK(23, 22)); 111 } 112 113 /* Encoded value for COMP_CFG register FULL_FLUSH_WAIT_RS_CLOSURE_EN field */ 114 static inline u32 full_flush_rsc_closure_en_encoded(enum ipa_version version, 115 bool enable) 116 { 117 u32 val = enable ? 1 : 0; 118 119 /* assert(version >= IPA_VERSION_4_5); */ 120 121 if (version == IPA_VERSION_4_5 || version == IPA_VERSION_4_7) 122 return u32_encode_bits(val, GENMASK(21, 21)); 123 124 return u32_encode_bits(val, GENMASK(17, 17)); 125 } 126 127 #define IPA_REG_CLKON_CFG_OFFSET 0x00000044 128 #define RX_FMASK GENMASK(0, 0) 129 #define PROC_FMASK GENMASK(1, 1) 130 #define TX_WRAPPER_FMASK GENMASK(2, 2) 131 #define MISC_FMASK GENMASK(3, 3) 132 #define RAM_ARB_FMASK GENMASK(4, 4) 133 #define FTCH_HPS_FMASK GENMASK(5, 5) 134 #define FTCH_DPS_FMASK GENMASK(6, 6) 135 #define HPS_FMASK GENMASK(7, 7) 136 #define DPS_FMASK GENMASK(8, 8) 137 #define RX_HPS_CMDQS_FMASK GENMASK(9, 9) 138 #define HPS_DPS_CMDQS_FMASK GENMASK(10, 10) 139 #define DPS_TX_CMDQS_FMASK GENMASK(11, 11) 140 #define RSRC_MNGR_FMASK GENMASK(12, 12) 141 #define CTX_HANDLER_FMASK GENMASK(13, 13) 142 #define ACK_MNGR_FMASK GENMASK(14, 14) 143 #define D_DCPH_FMASK GENMASK(15, 15) 144 #define H_DCPH_FMASK GENMASK(16, 16) 145 /* The next field is not present for IPA v4.5+ */ 146 #define DCMP_FMASK GENMASK(17, 17) 147 /* The next three fields are present for IPA v3.5+ */ 148 #define NTF_TX_CMDQS_FMASK GENMASK(18, 18) 149 #define TX_0_FMASK GENMASK(19, 19) 150 #define TX_1_FMASK GENMASK(20, 20) 151 /* The next field is present for IPA v3.5.1+ */ 152 #define FNR_FMASK GENMASK(21, 21) 153 /* The next eight fields are present for IPA v4.0+ */ 154 #define QSB2AXI_CMDQ_L_FMASK GENMASK(22, 22) 155 #define AGGR_WRAPPER_FMASK GENMASK(23, 23) 156 #define RAM_SLAVEWAY_FMASK GENMASK(24, 24) 157 #define QMB_FMASK GENMASK(25, 25) 158 #define WEIGHT_ARB_FMASK GENMASK(26, 26) 159 #define GSI_IF_FMASK GENMASK(27, 27) 160 #define GLOBAL_FMASK GENMASK(28, 28) 161 #define GLOBAL_2X_CLK_FMASK GENMASK(29, 29) 162 /* The next field is present for IPA v4.5+ */ 163 #define DPL_FIFO_FMASK GENMASK(30, 30) 164 /* The next field is present for IPA v4.7+ */ 165 #define DRBIP_FMASK GENMASK(31, 31) 166 167 #define IPA_REG_ROUTE_OFFSET 0x00000048 168 #define ROUTE_DIS_FMASK GENMASK(0, 0) 169 #define ROUTE_DEF_PIPE_FMASK GENMASK(5, 1) 170 #define ROUTE_DEF_HDR_TABLE_FMASK GENMASK(6, 6) 171 #define ROUTE_DEF_HDR_OFST_FMASK GENMASK(16, 7) 172 #define ROUTE_FRAG_DEF_PIPE_FMASK GENMASK(21, 17) 173 #define ROUTE_DEF_RETAIN_HDR_FMASK GENMASK(24, 24) 174 175 #define IPA_REG_SHARED_MEM_SIZE_OFFSET 0x00000054 176 #define SHARED_MEM_SIZE_FMASK GENMASK(15, 0) 177 #define SHARED_MEM_BADDR_FMASK GENMASK(31, 16) 178 179 #define IPA_REG_QSB_MAX_WRITES_OFFSET 0x00000074 180 #define GEN_QMB_0_MAX_WRITES_FMASK GENMASK(3, 0) 181 #define GEN_QMB_1_MAX_WRITES_FMASK GENMASK(7, 4) 182 183 #define IPA_REG_QSB_MAX_READS_OFFSET 0x00000078 184 #define GEN_QMB_0_MAX_READS_FMASK GENMASK(3, 0) 185 #define GEN_QMB_1_MAX_READS_FMASK GENMASK(7, 4) 186 /* The next two fields are present for IPA v4.0+ */ 187 #define GEN_QMB_0_MAX_READS_BEATS_FMASK GENMASK(23, 16) 188 #define GEN_QMB_1_MAX_READS_BEATS_FMASK GENMASK(31, 24) 189 190 static inline u32 ipa_reg_filt_rout_hash_en_offset(enum ipa_version version) 191 { 192 if (version < IPA_VERSION_4_0) 193 return 0x000008c; 194 195 return 0x0000148; 196 } 197 198 static inline u32 ipa_reg_filt_rout_hash_flush_offset(enum ipa_version version) 199 { 200 if (version < IPA_VERSION_4_0) 201 return 0x0000090; 202 203 return 0x000014c; 204 } 205 206 /* The next four fields are used for the hash enable and flush registers */ 207 #define IPV6_ROUTER_HASH_FMASK GENMASK(0, 0) 208 #define IPV6_FILTER_HASH_FMASK GENMASK(4, 4) 209 #define IPV4_ROUTER_HASH_FMASK GENMASK(8, 8) 210 #define IPV4_FILTER_HASH_FMASK GENMASK(12, 12) 211 212 /* ipa->available defines the valid bits in the STATE_AGGR_ACTIVE register */ 213 static inline u32 ipa_reg_state_aggr_active_offset(enum ipa_version version) 214 { 215 if (version < IPA_VERSION_4_0) 216 return 0x0000010c; 217 218 return 0x000000b4; 219 } 220 221 /* The next register is not present for IPA v4.5+ */ 222 #define IPA_REG_BCR_OFFSET 0x000001d0 223 /* The next two fields are not present for IPA v4.2+ */ 224 #define BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK GENMASK(0, 0) 225 #define BCR_TX_NOT_USING_BRESP_FMASK GENMASK(1, 1) 226 /* The next field is invalid for IPA v4.0+ */ 227 #define BCR_TX_SUSPEND_IRQ_ASSERT_ONCE_FMASK GENMASK(2, 2) 228 /* The next two fields are not present for IPA v4.2+ */ 229 #define BCR_SUSPEND_L2_IRQ_FMASK GENMASK(3, 3) 230 #define BCR_HOLB_DROP_L2_IRQ_FMASK GENMASK(4, 4) 231 /* The next five fields are present for IPA v3.5+ */ 232 #define BCR_DUAL_TX_FMASK GENMASK(5, 5) 233 #define BCR_ENABLE_FILTER_DATA_CACHE_FMASK GENMASK(6, 6) 234 #define BCR_NOTIF_PRIORITY_OVER_ZLT_FMASK GENMASK(7, 7) 235 #define BCR_FILTER_PREFETCH_EN_FMASK GENMASK(8, 8) 236 #define BCR_ROUTER_PREFETCH_EN_FMASK GENMASK(9, 9) 237 238 /* Backward compatibility register value to use for each version */ 239 static inline u32 ipa_reg_bcr_val(enum ipa_version version) 240 { 241 if (version == IPA_VERSION_3_5_1) 242 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 243 BCR_TX_NOT_USING_BRESP_FMASK | 244 BCR_SUSPEND_L2_IRQ_FMASK | 245 BCR_HOLB_DROP_L2_IRQ_FMASK | 246 BCR_DUAL_TX_FMASK; 247 248 if (version == IPA_VERSION_4_0 || version == IPA_VERSION_4_1) 249 return BCR_CMDQ_L_LACK_ONE_ENTRY_FMASK | 250 BCR_SUSPEND_L2_IRQ_FMASK | 251 BCR_HOLB_DROP_L2_IRQ_FMASK | 252 BCR_DUAL_TX_FMASK; 253 254 /* assert(version != IPA_VERSION_4_5); */ 255 256 return 0x00000000; 257 } 258 259 /* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */ 260 #define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8 261 262 /* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */ 263 static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version, 264 u32 addr) 265 { 266 if (version < IPA_VERSION_4_5) 267 return u32_encode_bits(addr, GENMASK(16, 0)); 268 269 return u32_encode_bits(addr, GENMASK(17, 0)); 270 } 271 272 /* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */ 273 #define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec 274 275 /* The next register is not present for IPA v4.5+ */ 276 #define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0 277 /* The next field is not present for IPA v3.5+ */ 278 #define EOT_COAL_GRANULARITY GENMASK(3, 0) 279 #define AGGR_GRANULARITY_FMASK GENMASK(8, 4) 280 281 /* The next register is present for IPA v3.5+ */ 282 #define IPA_REG_TX_CFG_OFFSET 0x000001fc 283 /* The next three fields are not present for IPA v4.0+ */ 284 #define TX0_PREFETCH_DISABLE_FMASK GENMASK(0, 0) 285 #define TX1_PREFETCH_DISABLE_FMASK GENMASK(1, 1) 286 #define PREFETCH_ALMOST_EMPTY_SIZE_FMASK GENMASK(4, 2) 287 /* The next six fields are present for IPA v4.0+ */ 288 #define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK GENMASK(5, 2) 289 #define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK GENMASK(9, 6) 290 #define DMAW_SCND_OUTSD_PRED_EN_FMASK GENMASK(10, 10) 291 #define DMAW_MAX_BEATS_256_DIS_FMASK GENMASK(11, 11) 292 #define PA_MASK_EN_FMASK GENMASK(12, 12) 293 #define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK GENMASK(16, 13) 294 /* The next field is present for IPA v4.5+ */ 295 #define DUAL_TX_ENABLE_FMASK GENMASK(17, 17) 296 /* The next field is present for IPA v4.2+, but not IPA v4.5 */ 297 #define SSPND_PA_NO_START_STATE_FMASK GENMASK(18, 18) 298 /* The next field is present for IPA v4.2 only */ 299 #define SSPND_PA_NO_BQ_STATE_FMASK GENMASK(19, 19) 300 301 /* The next register is present for IPA v3.5+ */ 302 #define IPA_REG_FLAVOR_0_OFFSET 0x00000210 303 #define IPA_MAX_PIPES_FMASK GENMASK(3, 0) 304 #define IPA_MAX_CONS_PIPES_FMASK GENMASK(12, 8) 305 #define IPA_MAX_PROD_PIPES_FMASK GENMASK(20, 16) 306 #define IPA_PROD_LOWEST_FMASK GENMASK(27, 24) 307 308 /* The next register is present for IPA v3.5+ */ 309 static inline u32 ipa_reg_idle_indication_cfg_offset(enum ipa_version version) 310 { 311 if (version >= IPA_VERSION_4_2) 312 return 0x00000240; 313 314 return 0x00000220; 315 } 316 317 #define ENTER_IDLE_DEBOUNCE_THRESH_FMASK GENMASK(15, 0) 318 #define CONST_NON_IDLE_ENABLE_FMASK GENMASK(16, 16) 319 320 /* The next register is present for IPA v4.5+ */ 321 #define IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET 0x0000024c 322 #define DPL_TIMESTAMP_LSB_FMASK GENMASK(4, 0) 323 #define DPL_TIMESTAMP_SEL_FMASK GENMASK(7, 7) 324 #define TAG_TIMESTAMP_LSB_FMASK GENMASK(12, 8) 325 #define NAT_TIMESTAMP_LSB_FMASK GENMASK(20, 16) 326 327 /* The next register is present for IPA v4.5+ */ 328 #define IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET 0x00000250 329 #define DIV_VALUE_FMASK GENMASK(8, 0) 330 #define DIV_ENABLE_FMASK GENMASK(31, 31) 331 332 /* The next register is present for IPA v4.5+ */ 333 #define IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET 0x00000254 334 #define GRAN_0_FMASK GENMASK(2, 0) 335 #define GRAN_1_FMASK GENMASK(5, 3) 336 #define GRAN_2_FMASK GENMASK(8, 6) 337 /* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */ 338 enum ipa_pulse_gran { 339 IPA_GRAN_10_US = 0x0, 340 IPA_GRAN_20_US = 0x1, 341 IPA_GRAN_50_US = 0x2, 342 IPA_GRAN_100_US = 0x3, 343 IPA_GRAN_1_MS = 0x4, 344 IPA_GRAN_10_MS = 0x5, 345 IPA_GRAN_100_MS = 0x6, 346 IPA_GRAN_655350_US = 0x7, 347 }; 348 349 /* Not all of the following are present (depends on IPA version) */ 350 #define IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 351 (0x00000400 + 0x0020 * (rt)) 352 #define IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 353 (0x00000404 + 0x0020 * (rt)) 354 #define IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 355 (0x00000408 + 0x0020 * (rt)) 356 #define IPA_REG_SRC_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(rt) \ 357 (0x0000040c + 0x0020 * (rt)) 358 #define IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N_OFFSET(rt) \ 359 (0x00000500 + 0x0020 * (rt)) 360 #define IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N_OFFSET(rt) \ 361 (0x00000504 + 0x0020 * (rt)) 362 #define IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N_OFFSET(rt) \ 363 (0x00000508 + 0x0020 * (rt)) 364 #define IPA_REG_DST_RSRC_GRP_67_RSRC_TYPE_N_OFFSET(rt) \ 365 (0x0000050c + 0x0020 * (rt)) 366 /* The next four fields are used for all resource group registers */ 367 #define X_MIN_LIM_FMASK GENMASK(5, 0) 368 #define X_MAX_LIM_FMASK GENMASK(13, 8) 369 /* The next two fields are not always present (if resource count is odd) */ 370 #define Y_MIN_LIM_FMASK GENMASK(21, 16) 371 #define Y_MAX_LIM_FMASK GENMASK(29, 24) 372 373 #define IPA_REG_ENDP_INIT_CTRL_N_OFFSET(ep) \ 374 (0x00000800 + 0x0070 * (ep)) 375 /* Valid only for RX (IPA producer) endpoints (do not use for IPA v4.0+) */ 376 #define ENDP_SUSPEND_FMASK GENMASK(0, 0) 377 /* Valid only for TX (IPA consumer) endpoints */ 378 #define ENDP_DELAY_FMASK GENMASK(1, 1) 379 380 #define IPA_REG_ENDP_INIT_CFG_N_OFFSET(ep) \ 381 (0x00000808 + 0x0070 * (ep)) 382 #define FRAG_OFFLOAD_EN_FMASK GENMASK(0, 0) 383 #define CS_OFFLOAD_EN_FMASK GENMASK(2, 1) 384 #define CS_METADATA_HDR_OFFSET_FMASK GENMASK(6, 3) 385 #define CS_GEN_QMB_MASTER_SEL_FMASK GENMASK(8, 8) 386 387 /** enum ipa_cs_offload_en - ENDP_INIT_CFG register CS_OFFLOAD_EN field value */ 388 enum ipa_cs_offload_en { 389 IPA_CS_OFFLOAD_NONE = 0x0, 390 IPA_CS_OFFLOAD_UL = 0x1, /* Before IPA v4.5 (TX) */ 391 IPA_CS_OFFLOAD_DL = 0x2, /* Before IPA v4.5 (RX) */ 392 }; 393 394 /* Valid only for TX (IPA consumer) endpoints */ 395 #define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \ 396 (0x0000080c + 0x0070 * (ep)) 397 #define NAT_EN_FMASK GENMASK(1, 0) 398 399 /** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */ 400 enum ipa_nat_en { 401 IPA_NAT_BYPASS = 0x0, 402 IPA_NAT_SRC = 0x1, 403 IPA_NAT_DST = 0x2, 404 }; 405 406 #define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \ 407 (0x00000810 + 0x0070 * (ep)) 408 #define HDR_LEN_FMASK GENMASK(5, 0) 409 #define HDR_OFST_METADATA_VALID_FMASK GENMASK(6, 6) 410 #define HDR_OFST_METADATA_FMASK GENMASK(12, 7) 411 #define HDR_ADDITIONAL_CONST_LEN_FMASK GENMASK(18, 13) 412 #define HDR_OFST_PKT_SIZE_VALID_FMASK GENMASK(19, 19) 413 #define HDR_OFST_PKT_SIZE_FMASK GENMASK(25, 20) 414 /* The next field is not present for IPA v4.9+ */ 415 #define HDR_A5_MUX_FMASK GENMASK(26, 26) 416 #define HDR_LEN_INC_DEAGG_HDR_FMASK GENMASK(27, 27) 417 /* The next field is not present for IPA v4.5+ */ 418 #define HDR_METADATA_REG_VALID_FMASK GENMASK(28, 28) 419 /* The next two fields are present for IPA v4.5+ */ 420 #define HDR_LEN_MSB_FMASK GENMASK(29, 28) 421 #define HDR_OFST_METADATA_MSB_FMASK GENMASK(31, 30) 422 423 /* Encoded value for ENDP_INIT_HDR register HDR_LEN* field(s) */ 424 static inline u32 ipa_header_size_encoded(enum ipa_version version, 425 u32 header_size) 426 { 427 u32 size = header_size & field_mask(HDR_LEN_FMASK); 428 u32 val; 429 430 val = u32_encode_bits(size, HDR_LEN_FMASK); 431 if (version < IPA_VERSION_4_5) { 432 /* ipa_assert(header_size == size); */ 433 return val; 434 } 435 436 /* IPA v4.5 adds a few more most-significant bits */ 437 size = header_size >> hweight32(HDR_LEN_FMASK); 438 val |= u32_encode_bits(size, HDR_LEN_MSB_FMASK); 439 440 return val; 441 } 442 443 /* Encoded value for ENDP_INIT_HDR register OFST_METADATA* field(s) */ 444 static inline u32 ipa_metadata_offset_encoded(enum ipa_version version, 445 u32 offset) 446 { 447 u32 off = offset & field_mask(HDR_OFST_METADATA_FMASK); 448 u32 val; 449 450 val = u32_encode_bits(off, HDR_OFST_METADATA_FMASK); 451 if (version < IPA_VERSION_4_5) { 452 /* ipa_assert(offset == off); */ 453 return val; 454 } 455 456 /* IPA v4.5 adds a few more most-significant bits */ 457 off = offset >> hweight32(HDR_OFST_METADATA_FMASK); 458 val |= u32_encode_bits(off, HDR_OFST_METADATA_MSB_FMASK); 459 460 return val; 461 } 462 463 #define IPA_REG_ENDP_INIT_HDR_EXT_N_OFFSET(ep) \ 464 (0x00000814 + 0x0070 * (ep)) 465 #define HDR_ENDIANNESS_FMASK GENMASK(0, 0) 466 #define HDR_TOTAL_LEN_OR_PAD_VALID_FMASK GENMASK(1, 1) 467 #define HDR_TOTAL_LEN_OR_PAD_FMASK GENMASK(2, 2) 468 #define HDR_PAYLOAD_LEN_INC_PADDING_FMASK GENMASK(3, 3) 469 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_FMASK GENMASK(9, 4) 470 #define HDR_PAD_TO_ALIGNMENT_FMASK GENMASK(13, 10) 471 /* The next three fields are present for IPA v4.5+ */ 472 #define HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB_FMASK GENMASK(17, 16) 473 #define HDR_OFST_PKT_SIZE_MSB_FMASK GENMASK(19, 18) 474 #define HDR_ADDITIONAL_CONST_LEN_MSB_FMASK GENMASK(21, 20) 475 476 /* Valid only for RX (IPA producer) endpoints */ 477 #define IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N_OFFSET(rxep) \ 478 (0x00000818 + 0x0070 * (rxep)) 479 480 /* Valid only for TX (IPA consumer) endpoints */ 481 #define IPA_REG_ENDP_INIT_MODE_N_OFFSET(txep) \ 482 (0x00000820 + 0x0070 * (txep)) 483 #define MODE_FMASK GENMASK(2, 0) 484 /* The next field is present for IPA v4.5+ */ 485 #define DCPH_ENABLE_FMASK GENMASK(3, 3) 486 #define DEST_PIPE_INDEX_FMASK GENMASK(8, 4) 487 #define BYTE_THRESHOLD_FMASK GENMASK(27, 12) 488 #define PIPE_REPLICATION_EN_FMASK GENMASK(28, 28) 489 #define PAD_EN_FMASK GENMASK(29, 29) 490 /* The next field is not present for IPA v4.5+ */ 491 #define HDR_FTCH_DISABLE_FMASK GENMASK(30, 30) 492 /* The next field is present for IPA v4.9+ */ 493 #define DRBIP_ACL_ENABLE GENMASK(30, 30) 494 495 /** enum ipa_mode - ENDP_INIT_MODE register MODE field value */ 496 enum ipa_mode { 497 IPA_BASIC = 0x0, 498 IPA_ENABLE_FRAMING_HDLC = 0x1, 499 IPA_ENABLE_DEFRAMING_HDLC = 0x2, 500 IPA_DMA = 0x3, 501 }; 502 503 #define IPA_REG_ENDP_INIT_AGGR_N_OFFSET(ep) \ 504 (0x00000824 + 0x0070 * (ep)) 505 #define AGGR_EN_FMASK GENMASK(1, 0) 506 #define AGGR_TYPE_FMASK GENMASK(4, 2) 507 508 /* The legacy value is used for IPA hardware before IPA v4.5 */ 509 static inline u32 aggr_byte_limit_fmask(bool legacy) 510 { 511 return legacy ? GENMASK(9, 5) : GENMASK(10, 5); 512 } 513 514 /* The legacy value is used for IPA hardware before IPA v4.5 */ 515 static inline u32 aggr_time_limit_fmask(bool legacy) 516 { 517 return legacy ? GENMASK(14, 10) : GENMASK(16, 12); 518 } 519 520 /* The legacy value is used for IPA hardware before IPA v4.5 */ 521 static inline u32 aggr_pkt_limit_fmask(bool legacy) 522 { 523 return legacy ? GENMASK(20, 15) : GENMASK(22, 17); 524 } 525 526 /* The legacy value is used for IPA hardware before IPA v4.5 */ 527 static inline u32 aggr_sw_eof_active_fmask(bool legacy) 528 { 529 return legacy ? GENMASK(21, 21) : GENMASK(23, 23); 530 } 531 532 /* The legacy value is used for IPA hardware before IPA v4.5 */ 533 static inline u32 aggr_force_close_fmask(bool legacy) 534 { 535 return legacy ? GENMASK(22, 22) : GENMASK(24, 24); 536 } 537 538 /* The legacy value is used for IPA hardware before IPA v4.5 */ 539 static inline u32 aggr_hard_byte_limit_enable_fmask(bool legacy) 540 { 541 return legacy ? GENMASK(24, 24) : GENMASK(26, 26); 542 } 543 544 /* The next field is present for IPA v4.5+ */ 545 #define AGGR_GRAN_SEL_FMASK GENMASK(27, 27) 546 547 /** enum ipa_aggr_en - ENDP_INIT_AGGR register AGGR_EN field value */ 548 enum ipa_aggr_en { 549 IPA_BYPASS_AGGR = 0x0, /* (TX, RX) */ 550 IPA_ENABLE_AGGR = 0x1, /* (RX) */ 551 IPA_ENABLE_DEAGGR = 0x2, /* (TX) */ 552 }; 553 554 /** enum ipa_aggr_type - ENDP_INIT_AGGR register AGGR_TYPE field value */ 555 enum ipa_aggr_type { 556 IPA_MBIM_16 = 0x0, 557 IPA_HDLC = 0x1, 558 IPA_TLP = 0x2, 559 IPA_RNDIS = 0x3, 560 IPA_GENERIC = 0x4, 561 IPA_COALESCE = 0x5, 562 IPA_QCMAP = 0x6, 563 }; 564 565 /* Valid only for RX (IPA producer) endpoints */ 566 #define IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N_OFFSET(rxep) \ 567 (0x0000082c + 0x0070 * (rxep)) 568 #define HOL_BLOCK_EN_FMASK GENMASK(0, 0) 569 570 /* Valid only for RX (IPA producer) endpoints */ 571 #define IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N_OFFSET(rxep) \ 572 (0x00000830 + 0x0070 * (rxep)) 573 /* The next two fields are present for IPA v4.2 only */ 574 #define BASE_VALUE_FMASK GENMASK(4, 0) 575 #define SCALE_FMASK GENMASK(12, 8) 576 /* The next two fields are present for IPA v4.5 */ 577 #define TIME_LIMIT_FMASK GENMASK(4, 0) 578 #define GRAN_SEL_FMASK GENMASK(8, 8) 579 580 /* Valid only for TX (IPA consumer) endpoints */ 581 #define IPA_REG_ENDP_INIT_DEAGGR_N_OFFSET(txep) \ 582 (0x00000834 + 0x0070 * (txep)) 583 #define DEAGGR_HDR_LEN_FMASK GENMASK(5, 0) 584 #define SYSPIPE_ERR_DETECTION_FMASK GENMASK(6, 6) 585 #define PACKET_OFFSET_VALID_FMASK GENMASK(7, 7) 586 #define PACKET_OFFSET_LOCATION_FMASK GENMASK(13, 8) 587 #define IGNORE_MIN_PKT_ERR_FMASK GENMASK(14, 14) 588 #define MAX_PACKET_LEN_FMASK GENMASK(31, 16) 589 590 #define IPA_REG_ENDP_INIT_RSRC_GRP_N_OFFSET(ep) \ 591 (0x00000838 + 0x0070 * (ep)) 592 /* Encoded value for ENDP_INIT_RSRC_GRP register RSRC_GRP field */ 593 static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp) 594 { 595 if (version < IPA_VERSION_3_5 || version == IPA_VERSION_4_5) 596 return u32_encode_bits(rsrc_grp, GENMASK(2, 0)); 597 598 if (version == IPA_VERSION_4_2 || version == IPA_VERSION_4_7) 599 return u32_encode_bits(rsrc_grp, GENMASK(0, 0)); 600 601 return u32_encode_bits(rsrc_grp, GENMASK(1, 0)); 602 } 603 604 /* Valid only for TX (IPA consumer) endpoints */ 605 #define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \ 606 (0x0000083c + 0x0070 * (txep)) 607 #define SEQ_TYPE_FMASK GENMASK(7, 0) 608 #define SEQ_REP_TYPE_FMASK GENMASK(15, 8) 609 610 /** 611 * enum ipa_seq_type - HPS and DPS sequencer type 612 * @IPA_SEQ_DMA: Perform DMA only 613 * @IPA_SEQ_1_PASS: One pass through the pipeline 614 * @IPA_SEQ_2_PASS_SKIP_LAST_UC: Two passes, skip the microcprocessor 615 * @IPA_SEQ_1_PASS_SKIP_LAST_UC: One pass, skip the microcprocessor 616 * @IPA_SEQ_2_PASS: Two passes through the pipeline 617 * @IPA_SEQ_3_PASS_SKIP_LAST_UC: Three passes, skip the microcprocessor 618 * @IPA_SEQ_DECIPHER: Optional deciphering step (combined) 619 * 620 * The low-order byte of the sequencer type register defines the number of 621 * passes a packet takes through the IPA pipeline. The last pass through can 622 * optionally skip the microprocessor. Deciphering is optional for all types; 623 * if enabled, an additional mask (two bits) is added to the type value. 624 * 625 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 626 * supported (or meaningful). 627 */ 628 enum ipa_seq_type { 629 IPA_SEQ_DMA = 0x00, 630 IPA_SEQ_1_PASS = 0x02, 631 IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04, 632 IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06, 633 IPA_SEQ_2_PASS = 0x0a, 634 IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c, 635 /* The next value can be ORed with the above */ 636 IPA_SEQ_DECIPHER = 0x11, 637 }; 638 639 /** 640 * enum ipa_seq_rep_type - replicated packet sequencer type 641 * @IPA_SEQ_REP_DMA_PARSER: DMA parser for replicated packets 642 * 643 * This goes in the second byte of the endpoint sequencer type register. 644 * 645 * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are 646 * supported (or meaningful). 647 */ 648 enum ipa_seq_rep_type { 649 IPA_SEQ_REP_DMA_PARSER = 0x08, 650 }; 651 652 #define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \ 653 (0x00000840 + 0x0070 * (ep)) 654 #define STATUS_EN_FMASK GENMASK(0, 0) 655 #define STATUS_ENDP_FMASK GENMASK(5, 1) 656 /* The next field is not present for IPA v4.5+ */ 657 #define STATUS_LOCATION_FMASK GENMASK(8, 8) 658 /* The next field is present for IPA v4.0+ */ 659 #define STATUS_PKT_SUPPRESS_FMASK GENMASK(9, 9) 660 661 /* The next register is not present for IPA v4.2 (which no hashing support) */ 662 #define IPA_REG_ENDP_FILTER_ROUTER_HSH_CFG_N_OFFSET(er) \ 663 (0x0000085c + 0x0070 * (er)) 664 #define FILTER_HASH_MSK_SRC_ID_FMASK GENMASK(0, 0) 665 #define FILTER_HASH_MSK_SRC_IP_FMASK GENMASK(1, 1) 666 #define FILTER_HASH_MSK_DST_IP_FMASK GENMASK(2, 2) 667 #define FILTER_HASH_MSK_SRC_PORT_FMASK GENMASK(3, 3) 668 #define FILTER_HASH_MSK_DST_PORT_FMASK GENMASK(4, 4) 669 #define FILTER_HASH_MSK_PROTOCOL_FMASK GENMASK(5, 5) 670 #define FILTER_HASH_MSK_METADATA_FMASK GENMASK(6, 6) 671 #define IPA_REG_ENDP_FILTER_HASH_MSK_ALL GENMASK(6, 0) 672 673 #define ROUTER_HASH_MSK_SRC_ID_FMASK GENMASK(16, 16) 674 #define ROUTER_HASH_MSK_SRC_IP_FMASK GENMASK(17, 17) 675 #define ROUTER_HASH_MSK_DST_IP_FMASK GENMASK(18, 18) 676 #define ROUTER_HASH_MSK_SRC_PORT_FMASK GENMASK(19, 19) 677 #define ROUTER_HASH_MSK_DST_PORT_FMASK GENMASK(20, 20) 678 #define ROUTER_HASH_MSK_PROTOCOL_FMASK GENMASK(21, 21) 679 #define ROUTER_HASH_MSK_METADATA_FMASK GENMASK(22, 22) 680 #define IPA_REG_ENDP_ROUTER_HASH_MSK_ALL GENMASK(22, 16) 681 682 static inline u32 ipa_reg_irq_stts_ee_n_offset(enum ipa_version version, 683 u32 ee) 684 { 685 if (version < IPA_VERSION_4_9) 686 return 0x00003008 + 0x1000 * ee; 687 688 return 0x00004008 + 0x1000 * ee; 689 } 690 691 static inline u32 ipa_reg_irq_stts_offset(enum ipa_version version) 692 { 693 return ipa_reg_irq_stts_ee_n_offset(version, GSI_EE_AP); 694 } 695 696 static inline u32 ipa_reg_irq_en_ee_n_offset(enum ipa_version version, u32 ee) 697 { 698 if (version < IPA_VERSION_4_9) 699 return 0x0000300c + 0x1000 * ee; 700 701 return 0x0000400c + 0x1000 * ee; 702 } 703 704 static inline u32 ipa_reg_irq_en_offset(enum ipa_version version) 705 { 706 return ipa_reg_irq_en_ee_n_offset(version, GSI_EE_AP); 707 } 708 709 static inline u32 ipa_reg_irq_clr_ee_n_offset(enum ipa_version version, u32 ee) 710 { 711 if (version < IPA_VERSION_4_9) 712 return 0x00003010 + 0x1000 * ee; 713 714 return 0x00004010 + 0x1000 * ee; 715 } 716 717 static inline u32 ipa_reg_irq_clr_offset(enum ipa_version version) 718 { 719 return ipa_reg_irq_clr_ee_n_offset(version, GSI_EE_AP); 720 } 721 722 /** 723 * enum ipa_irq_id - Bit positions representing type of IPA IRQ 724 * @IPA_IRQ_UC_0: Microcontroller event interrupt 725 * @IPA_IRQ_UC_1: Microcontroller response interrupt 726 * @IPA_IRQ_TX_SUSPEND: Data ready interrupt 727 * @IPA_IRQ_COUNT: Number of IRQ ids (must be last) 728 * 729 * IRQ types not described above are not currently used. 730 * 731 * @IPA_IRQ_BAD_SNOC_ACCESS: (Not currently used) 732 * @IPA_IRQ_EOT_COAL: (Not currently used) 733 * @IPA_IRQ_UC_2: (Not currently used) 734 * @IPA_IRQ_UC_3: (Not currently used) 735 * @IPA_IRQ_UC_IN_Q_NOT_EMPTY: (Not currently used) 736 * @IPA_IRQ_UC_RX_CMD_Q_NOT_FULL: (Not currently used) 737 * @IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY: (Not currently used) 738 * @IPA_IRQ_RX_ERR: (Not currently used) 739 * @IPA_IRQ_DEAGGR_ERR: (Not currently used) 740 * @IPA_IRQ_TX_ERR: (Not currently used) 741 * @IPA_IRQ_STEP_MODE: (Not currently used) 742 * @IPA_IRQ_PROC_ERR: (Not currently used) 743 * @IPA_IRQ_TX_HOLB_DROP: (Not currently used) 744 * @IPA_IRQ_BAM_GSI_IDLE: (Not currently used) 745 * @IPA_IRQ_PIPE_YELLOW_BELOW: (Not currently used) 746 * @IPA_IRQ_PIPE_RED_BELOW: (Not currently used) 747 * @IPA_IRQ_PIPE_YELLOW_ABOVE: (Not currently used) 748 * @IPA_IRQ_PIPE_RED_ABOVE: (Not currently used) 749 * @IPA_IRQ_UCP: (Not currently used) 750 * @IPA_IRQ_DCMP: (Not currently used) 751 * @IPA_IRQ_GSI_EE: (Not currently used) 752 * @IPA_IRQ_GSI_IPA_IF_TLV_RCVD: (Not currently used) 753 * @IPA_IRQ_GSI_UC: (Not currently used) 754 * @IPA_IRQ_TLV_LEN_MIN_DSM: (Not currently used) 755 * @IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN: (Not currently used) 756 * @IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN: (Not currently used) 757 * @IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN: (Not currently used) 758 */ 759 enum ipa_irq_id { 760 IPA_IRQ_BAD_SNOC_ACCESS = 0x0, 761 /* The next bit is not present for IPA v3.5+ */ 762 IPA_IRQ_EOT_COAL = 0x1, 763 IPA_IRQ_UC_0 = 0x2, 764 IPA_IRQ_UC_1 = 0x3, 765 IPA_IRQ_UC_2 = 0x4, 766 IPA_IRQ_UC_3 = 0x5, 767 IPA_IRQ_UC_IN_Q_NOT_EMPTY = 0x6, 768 IPA_IRQ_UC_RX_CMD_Q_NOT_FULL = 0x7, 769 IPA_IRQ_PROC_UC_ACK_Q_NOT_EMPTY = 0x8, 770 IPA_IRQ_RX_ERR = 0x9, 771 IPA_IRQ_DEAGGR_ERR = 0xa, 772 IPA_IRQ_TX_ERR = 0xb, 773 IPA_IRQ_STEP_MODE = 0xc, 774 IPA_IRQ_PROC_ERR = 0xd, 775 IPA_IRQ_TX_SUSPEND = 0xe, 776 IPA_IRQ_TX_HOLB_DROP = 0xf, 777 IPA_IRQ_BAM_GSI_IDLE = 0x10, 778 IPA_IRQ_PIPE_YELLOW_BELOW = 0x11, 779 IPA_IRQ_PIPE_RED_BELOW = 0x12, 780 IPA_IRQ_PIPE_YELLOW_ABOVE = 0x13, 781 IPA_IRQ_PIPE_RED_ABOVE = 0x14, 782 IPA_IRQ_UCP = 0x15, 783 /* The next bit is not present for IPA v4.5+ */ 784 IPA_IRQ_DCMP = 0x16, 785 IPA_IRQ_GSI_EE = 0x17, 786 IPA_IRQ_GSI_IPA_IF_TLV_RCVD = 0x18, 787 IPA_IRQ_GSI_UC = 0x19, 788 /* The next bit is present for IPA v4.5+ */ 789 IPA_IRQ_TLV_LEN_MIN_DSM = 0x1a, 790 /* The next three bits are present for IPA v4.9+ */ 791 IPA_IRQ_DRBIP_PKT_EXCEED_MAX_SIZE_EN = 0x1b, 792 IPA_IRQ_DRBIP_DATA_SCTR_CFG_ERROR_EN = 0x1c, 793 IPA_IRQ_DRBIP_IMM_CMD_NO_FLSH_HZRD_EN = 0x1d, 794 IPA_IRQ_COUNT, /* Last; not an id */ 795 }; 796 797 static inline u32 ipa_reg_irq_uc_ee_n_offset(enum ipa_version version, u32 ee) 798 { 799 if (version < IPA_VERSION_4_9) 800 return 0x0000301c + 0x1000 * ee; 801 802 return 0x0000401c + 0x1000 * ee; 803 } 804 805 static inline u32 ipa_reg_irq_uc_offset(enum ipa_version version) 806 { 807 return ipa_reg_irq_uc_ee_n_offset(version, GSI_EE_AP); 808 } 809 810 #define UC_INTR_FMASK GENMASK(0, 0) 811 812 /* ipa->available defines the valid bits in the SUSPEND_INFO register */ 813 static inline u32 814 ipa_reg_irq_suspend_info_ee_n_offset(enum ipa_version version, u32 ee) 815 { 816 if (version == IPA_VERSION_3_0) 817 return 0x00003098 + 0x1000 * ee; 818 819 if (version < IPA_VERSION_4_9) 820 return 0x00003030 + 0x1000 * ee; 821 822 return 0x00004030 + 0x1000 * ee; 823 } 824 825 static inline u32 826 ipa_reg_irq_suspend_info_offset(enum ipa_version version) 827 { 828 return ipa_reg_irq_suspend_info_ee_n_offset(version, GSI_EE_AP); 829 } 830 831 /* ipa->available defines the valid bits in the SUSPEND_EN register */ 832 static inline u32 833 ipa_reg_irq_suspend_en_ee_n_offset(enum ipa_version version, u32 ee) 834 { 835 /* assert(version != IPA_VERSION_3_0); */ 836 837 if (version < IPA_VERSION_4_9) 838 return 0x00003034 + 0x1000 * ee; 839 840 return 0x00004034 + 0x1000 * ee; 841 } 842 843 static inline u32 844 ipa_reg_irq_suspend_en_offset(enum ipa_version version) 845 { 846 return ipa_reg_irq_suspend_en_ee_n_offset(version, GSI_EE_AP); 847 } 848 849 /* ipa->available defines the valid bits in the SUSPEND_CLR register */ 850 static inline u32 851 ipa_reg_irq_suspend_clr_ee_n_offset(enum ipa_version version, u32 ee) 852 { 853 /* assert(version != IPA_VERSION_3_0); */ 854 855 if (version < IPA_VERSION_4_9) 856 return 0x00003038 + 0x1000 * ee; 857 858 return 0x00004038 + 0x1000 * ee; 859 } 860 861 static inline u32 862 ipa_reg_irq_suspend_clr_offset(enum ipa_version version) 863 { 864 return ipa_reg_irq_suspend_clr_ee_n_offset(version, GSI_EE_AP); 865 } 866 867 int ipa_reg_init(struct ipa *ipa); 868 void ipa_reg_exit(struct ipa *ipa); 869 870 #endif /* _IPA_REG_H_ */ 871