1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/atomic.h> 9 #include <linux/bitfield.h> 10 #include <linux/device.h> 11 #include <linux/bug.h> 12 #include <linux/io.h> 13 #include <linux/firmware.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_address.h> 18 #include <linux/qcom_scm.h> 19 #include <linux/soc/qcom/mdt_loader.h> 20 21 #include "ipa.h" 22 #include "ipa_clock.h" 23 #include "ipa_data.h" 24 #include "ipa_endpoint.h" 25 #include "ipa_resource.h" 26 #include "ipa_cmd.h" 27 #include "ipa_reg.h" 28 #include "ipa_mem.h" 29 #include "ipa_table.h" 30 #include "ipa_modem.h" 31 #include "ipa_uc.h" 32 #include "ipa_interrupt.h" 33 #include "gsi_trans.h" 34 #include "ipa_sysfs.h" 35 36 /** 37 * DOC: The IP Accelerator 38 * 39 * This driver supports the Qualcomm IP Accelerator (IPA), which is a 40 * networking component found in many Qualcomm SoCs. The IPA is connected 41 * to the application processor (AP), but is also connected (and partially 42 * controlled by) other "execution environments" (EEs), such as a modem. 43 * 44 * The IPA is the conduit between the AP and the modem that carries network 45 * traffic. This driver presents a network interface representing the 46 * connection of the modem to external (e.g. LTE) networks. 47 * 48 * The IPA provides protocol checksum calculation, offloading this work 49 * from the AP. The IPA offers additional functionality, including routing, 50 * filtering, and NAT support, but that more advanced functionality is not 51 * currently supported. Despite that, some resources--including routing 52 * tables and filter tables--are defined in this driver because they must 53 * be initialized even when the advanced hardware features are not used. 54 * 55 * There are two distinct layers that implement the IPA hardware, and this 56 * is reflected in the organization of the driver. The generic software 57 * interface (GSI) is an integral component of the IPA, providing a 58 * well-defined communication layer between the AP subsystem and the IPA 59 * core. The GSI implements a set of "channels" used for communication 60 * between the AP and the IPA. 61 * 62 * The IPA layer uses GSI channels to implement its "endpoints". And while 63 * a GSI channel carries data between the AP and the IPA, a pair of IPA 64 * endpoints is used to carry traffic between two EEs. Specifically, the main 65 * modem network interface is implemented by two pairs of endpoints: a TX 66 * endpoint on the AP coupled with an RX endpoint on the modem; and another 67 * RX endpoint on the AP receiving data from a TX endpoint on the modem. 68 */ 69 70 /* The name of the GSI firmware file relative to /lib/firmware */ 71 #define IPA_FW_PATH_DEFAULT "ipa_fws.mdt" 72 #define IPA_PAS_ID 15 73 74 /* Shift of 19.2 MHz timestamp to achieve lower resolution timestamps */ 75 #define DPL_TIMESTAMP_SHIFT 14 /* ~1.172 kHz, ~853 usec per tick */ 76 #define TAG_TIMESTAMP_SHIFT 14 77 #define NAT_TIMESTAMP_SHIFT 24 /* ~1.144 Hz, ~874 msec per tick */ 78 79 /* Divider for 19.2 MHz crystal oscillator clock to get common timer clock */ 80 #define IPA_XO_CLOCK_DIVIDER 192 /* 1 is subtracted where used */ 81 82 /** 83 * ipa_suspend_handler() - Handle the suspend IPA interrupt 84 * @ipa: IPA pointer 85 * @irq_id: IPA interrupt type (unused) 86 * 87 * If an RX endpoint is in suspend state, and the IPA has a packet 88 * destined for that endpoint, the IPA generates a SUSPEND interrupt 89 * to inform the AP that it should resume the endpoint. If we get 90 * one of these interrupts we just resume everything. 91 */ 92 static void ipa_suspend_handler(struct ipa *ipa, enum ipa_irq_id irq_id) 93 { 94 /* Just report the event, and let system resume handle the rest. 95 * More than one endpoint could signal this; if so, ignore 96 * all but the first. 97 */ 98 if (!test_and_set_bit(IPA_FLAG_RESUMED, ipa->flags)) 99 pm_wakeup_dev_event(&ipa->pdev->dev, 0, true); 100 101 /* Acknowledge/clear the suspend interrupt on all endpoints */ 102 ipa_interrupt_suspend_clear_all(ipa->interrupt); 103 } 104 105 /** 106 * ipa_setup() - Set up IPA hardware 107 * @ipa: IPA pointer 108 * 109 * Perform initialization that requires issuing immediate commands on 110 * the command TX endpoint. If the modem is doing GSI firmware load 111 * and initialization, this function will be called when an SMP2P 112 * interrupt has been signaled by the modem. Otherwise it will be 113 * called from ipa_probe() after GSI firmware has been successfully 114 * loaded, authenticated, and started by Trust Zone. 115 */ 116 int ipa_setup(struct ipa *ipa) 117 { 118 struct ipa_endpoint *exception_endpoint; 119 struct ipa_endpoint *command_endpoint; 120 struct device *dev = &ipa->pdev->dev; 121 int ret; 122 123 ret = gsi_setup(&ipa->gsi); 124 if (ret) 125 return ret; 126 127 ipa->interrupt = ipa_interrupt_setup(ipa); 128 if (IS_ERR(ipa->interrupt)) { 129 ret = PTR_ERR(ipa->interrupt); 130 goto err_gsi_teardown; 131 } 132 ipa_interrupt_add(ipa->interrupt, IPA_IRQ_TX_SUSPEND, 133 ipa_suspend_handler); 134 135 ipa_uc_setup(ipa); 136 137 ret = device_init_wakeup(dev, true); 138 if (ret) 139 goto err_uc_teardown; 140 141 ipa_endpoint_setup(ipa); 142 143 /* We need to use the AP command TX endpoint to perform other 144 * initialization, so we enable first. 145 */ 146 command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; 147 ret = ipa_endpoint_enable_one(command_endpoint); 148 if (ret) 149 goto err_endpoint_teardown; 150 151 ret = ipa_mem_setup(ipa); /* No matching teardown required */ 152 if (ret) 153 goto err_command_disable; 154 155 ret = ipa_table_setup(ipa); /* No matching teardown required */ 156 if (ret) 157 goto err_command_disable; 158 159 /* Enable the exception handling endpoint, and tell the hardware 160 * to use it by default. 161 */ 162 exception_endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]; 163 ret = ipa_endpoint_enable_one(exception_endpoint); 164 if (ret) 165 goto err_command_disable; 166 167 ipa_endpoint_default_route_set(ipa, exception_endpoint->endpoint_id); 168 169 /* We're all set. Now prepare for communication with the modem */ 170 ret = ipa_modem_setup(ipa); 171 if (ret) 172 goto err_default_route_clear; 173 174 ipa->setup_complete = true; 175 176 dev_info(dev, "IPA driver setup completed successfully\n"); 177 178 return 0; 179 180 err_default_route_clear: 181 ipa_endpoint_default_route_clear(ipa); 182 ipa_endpoint_disable_one(exception_endpoint); 183 err_command_disable: 184 ipa_endpoint_disable_one(command_endpoint); 185 err_endpoint_teardown: 186 ipa_endpoint_teardown(ipa); 187 (void)device_init_wakeup(dev, false); 188 err_uc_teardown: 189 ipa_uc_teardown(ipa); 190 ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_TX_SUSPEND); 191 ipa_interrupt_teardown(ipa->interrupt); 192 err_gsi_teardown: 193 gsi_teardown(&ipa->gsi); 194 195 return ret; 196 } 197 198 /** 199 * ipa_teardown() - Inverse of ipa_setup() 200 * @ipa: IPA pointer 201 */ 202 static void ipa_teardown(struct ipa *ipa) 203 { 204 struct ipa_endpoint *exception_endpoint; 205 struct ipa_endpoint *command_endpoint; 206 207 ipa_modem_teardown(ipa); 208 ipa_endpoint_default_route_clear(ipa); 209 exception_endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]; 210 ipa_endpoint_disable_one(exception_endpoint); 211 command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; 212 ipa_endpoint_disable_one(command_endpoint); 213 ipa_endpoint_teardown(ipa); 214 (void)device_init_wakeup(&ipa->pdev->dev, false); 215 ipa_uc_teardown(ipa); 216 ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_TX_SUSPEND); 217 ipa_interrupt_teardown(ipa->interrupt); 218 gsi_teardown(&ipa->gsi); 219 } 220 221 /* Configure bus access behavior for IPA components */ 222 static void ipa_hardware_config_comp(struct ipa *ipa) 223 { 224 u32 val; 225 226 /* Nothing to configure prior to IPA v4.0 */ 227 if (ipa->version < IPA_VERSION_4_0) 228 return; 229 230 val = ioread32(ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET); 231 232 if (ipa->version == IPA_VERSION_4_0) { 233 val &= ~IPA_QMB_SELECT_CONS_EN_FMASK; 234 val &= ~IPA_QMB_SELECT_PROD_EN_FMASK; 235 val &= ~IPA_QMB_SELECT_GLOBAL_EN_FMASK; 236 } else if (ipa->version < IPA_VERSION_4_5) { 237 val |= GSI_MULTI_AXI_MASTERS_DIS_FMASK; 238 } else { 239 /* For IPA v4.5 IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN is 0 */ 240 } 241 242 val |= GSI_MULTI_INORDER_RD_DIS_FMASK; 243 val |= GSI_MULTI_INORDER_WR_DIS_FMASK; 244 245 iowrite32(val, ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET); 246 } 247 248 /* Configure DDR and (possibly) PCIe max read/write QSB values */ 249 static void 250 ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data) 251 { 252 const struct ipa_qsb_data *data0; 253 const struct ipa_qsb_data *data1; 254 u32 val; 255 256 /* assert(data->qsb_count > 0); */ 257 /* assert(data->qsb_count < 3); */ 258 259 /* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */ 260 data0 = &data->qsb_data[IPA_QSB_MASTER_DDR]; 261 if (data->qsb_count > 1) 262 data1 = &data->qsb_data[IPA_QSB_MASTER_PCIE]; 263 264 /* Max outstanding write accesses for QSB masters */ 265 val = u32_encode_bits(data0->max_writes, GEN_QMB_0_MAX_WRITES_FMASK); 266 if (data->qsb_count > 1) 267 val |= u32_encode_bits(data1->max_writes, 268 GEN_QMB_1_MAX_WRITES_FMASK); 269 iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_WRITES_OFFSET); 270 271 /* Max outstanding read accesses for QSB masters */ 272 val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK); 273 if (ipa->version >= IPA_VERSION_4_0) 274 val |= u32_encode_bits(data0->max_reads_beats, 275 GEN_QMB_0_MAX_READS_BEATS_FMASK); 276 if (data->qsb_count > 1) { 277 val |= u32_encode_bits(data1->max_reads, 278 GEN_QMB_1_MAX_READS_FMASK); 279 if (ipa->version >= IPA_VERSION_4_0) 280 val |= u32_encode_bits(data1->max_reads_beats, 281 GEN_QMB_1_MAX_READS_BEATS_FMASK); 282 } 283 iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET); 284 } 285 286 /* The internal inactivity timer clock is used for the aggregation timer */ 287 #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ 288 289 /* Compute the value to use in the COUNTER_CFG register AGGR_GRANULARITY 290 * field to represent the given number of microseconds. The value is one 291 * less than the number of timer ticks in the requested period. 0 is not 292 * a valid granularity value. 293 */ 294 static u32 ipa_aggr_granularity_val(u32 usec) 295 { 296 /* assert(usec != 0); */ 297 298 return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; 299 } 300 301 /* IPA uses unified Qtime starting at IPA v4.5, implementing various 302 * timestamps and timers independent of the IPA core clock rate. The 303 * Qtimer is based on a 56-bit timestamp incremented at each tick of 304 * a 19.2 MHz SoC crystal oscillator (XO clock). 305 * 306 * For IPA timestamps (tag, NAT, data path logging) a lower resolution 307 * timestamp is achieved by shifting the Qtimer timestamp value right 308 * some number of bits to produce the low-order bits of the coarser 309 * granularity timestamp. 310 * 311 * For timers, a common timer clock is derived from the XO clock using 312 * a divider (we use 192, to produce a 100kHz timer clock). From 313 * this common clock, three "pulse generators" are used to produce 314 * timer ticks at a configurable frequency. IPA timers (such as 315 * those used for aggregation or head-of-line block handling) now 316 * define their period based on one of these pulse generators. 317 */ 318 static void ipa_qtime_config(struct ipa *ipa) 319 { 320 u32 val; 321 322 /* Timer clock divider must be disabled when we change the rate */ 323 iowrite32(0, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 324 325 /* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */ 326 val = u32_encode_bits(DPL_TIMESTAMP_SHIFT, DPL_TIMESTAMP_LSB_FMASK); 327 val |= u32_encode_bits(1, DPL_TIMESTAMP_SEL_FMASK); 328 /* Configure tag and NAT Qtime timestamp resolution as well */ 329 val |= u32_encode_bits(TAG_TIMESTAMP_SHIFT, TAG_TIMESTAMP_LSB_FMASK); 330 val |= u32_encode_bits(NAT_TIMESTAMP_SHIFT, NAT_TIMESTAMP_LSB_FMASK); 331 iowrite32(val, ipa->reg_virt + IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET); 332 333 /* Set granularity of pulse generators used for other timers */ 334 val = u32_encode_bits(IPA_GRAN_100_US, GRAN_0_FMASK); 335 val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_1_FMASK); 336 val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_2_FMASK); 337 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET); 338 339 /* Actual divider is 1 more than value supplied here */ 340 val = u32_encode_bits(IPA_XO_CLOCK_DIVIDER - 1, DIV_VALUE_FMASK); 341 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 342 343 /* Divider value is set; re-enable the common timer clock divider */ 344 val |= u32_encode_bits(1, DIV_ENABLE_FMASK); 345 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 346 } 347 348 static void ipa_idle_indication_cfg(struct ipa *ipa, 349 u32 enter_idle_debounce_thresh, 350 bool const_non_idle_enable) 351 { 352 u32 offset; 353 u32 val; 354 355 val = u32_encode_bits(enter_idle_debounce_thresh, 356 ENTER_IDLE_DEBOUNCE_THRESH_FMASK); 357 if (const_non_idle_enable) 358 val |= CONST_NON_IDLE_ENABLE_FMASK; 359 360 offset = ipa_reg_idle_indication_cfg_offset(ipa->version); 361 iowrite32(val, ipa->reg_virt + offset); 362 } 363 364 /** 365 * ipa_hardware_dcd_config() - Enable dynamic clock division on IPA 366 * @ipa: IPA pointer 367 * 368 * Configures when the IPA signals it is idle to the global clock 369 * controller, which can respond by scalling down the clock to 370 * save power. 371 */ 372 static void ipa_hardware_dcd_config(struct ipa *ipa) 373 { 374 /* Recommended values for IPA 3.5 and later according to IPA HPG */ 375 ipa_idle_indication_cfg(ipa, 256, false); 376 } 377 378 static void ipa_hardware_dcd_deconfig(struct ipa *ipa) 379 { 380 /* Power-on reset values */ 381 ipa_idle_indication_cfg(ipa, 0, true); 382 } 383 384 /** 385 * ipa_hardware_config() - Primitive hardware initialization 386 * @ipa: IPA pointer 387 * @data: IPA configuration data 388 */ 389 static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) 390 { 391 enum ipa_version version = ipa->version; 392 u32 granularity; 393 u32 val; 394 395 /* IPA v4.5+ has no backward compatibility register */ 396 if (version < IPA_VERSION_4_5) { 397 val = data->backward_compat; 398 iowrite32(val, ipa->reg_virt + IPA_REG_BCR_OFFSET); 399 } 400 401 /* Implement some hardware workarounds */ 402 if (version >= IPA_VERSION_4_0 && version < IPA_VERSION_4_5) { 403 /* Disable PA mask to allow HOLB drop */ 404 val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); 405 val &= ~PA_MASK_EN_FMASK; 406 iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); 407 408 /* Enable open global clocks in the CLKON configuration */ 409 val = GLOBAL_FMASK | GLOBAL_2X_CLK_FMASK; 410 } else if (version == IPA_VERSION_3_1) { 411 val = MISC_FMASK; /* Disable MISC clock gating */ 412 } else { 413 val = 0; /* No CLKON configuration needed */ 414 } 415 if (val) 416 iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); 417 418 ipa_hardware_config_comp(ipa); 419 420 /* Configure system bus limits */ 421 ipa_hardware_config_qsb(ipa, data); 422 423 if (version < IPA_VERSION_4_5) { 424 /* Configure aggregation timer granularity */ 425 granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY); 426 val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK); 427 iowrite32(val, ipa->reg_virt + IPA_REG_COUNTER_CFG_OFFSET); 428 } else { 429 ipa_qtime_config(ipa); 430 } 431 432 /* IPA v4.2 does not support hashed tables, so disable them */ 433 if (version == IPA_VERSION_4_2) { 434 u32 offset = ipa_reg_filt_rout_hash_en_offset(version); 435 436 iowrite32(0, ipa->reg_virt + offset); 437 } 438 439 /* Enable dynamic clock division */ 440 ipa_hardware_dcd_config(ipa); 441 } 442 443 /** 444 * ipa_hardware_deconfig() - Inverse of ipa_hardware_config() 445 * @ipa: IPA pointer 446 * 447 * This restores the power-on reset values (even if they aren't different) 448 */ 449 static void ipa_hardware_deconfig(struct ipa *ipa) 450 { 451 /* Mostly we just leave things as we set them. */ 452 ipa_hardware_dcd_deconfig(ipa); 453 } 454 455 /** 456 * ipa_config() - Configure IPA hardware 457 * @ipa: IPA pointer 458 * @data: IPA configuration data 459 * 460 * Perform initialization requiring IPA clock to be enabled. 461 */ 462 static int ipa_config(struct ipa *ipa, const struct ipa_data *data) 463 { 464 int ret; 465 466 /* Get a clock reference to allow initialization. This reference 467 * is held after initialization completes, and won't get dropped 468 * unless/until a system suspend request arrives. 469 */ 470 ipa_clock_get(ipa); 471 472 ipa_hardware_config(ipa, data); 473 474 ret = ipa_endpoint_config(ipa); 475 if (ret) 476 goto err_hardware_deconfig; 477 478 ret = ipa_mem_config(ipa); 479 if (ret) 480 goto err_endpoint_deconfig; 481 482 ipa_table_config(ipa); /* No deconfig required */ 483 484 /* Assign resource limitation to each group; no deconfig required */ 485 ret = ipa_resource_config(ipa, data->resource_data); 486 if (ret) 487 goto err_mem_deconfig; 488 489 ret = ipa_modem_config(ipa); 490 if (ret) 491 goto err_mem_deconfig; 492 493 return 0; 494 495 err_mem_deconfig: 496 ipa_mem_deconfig(ipa); 497 err_endpoint_deconfig: 498 ipa_endpoint_deconfig(ipa); 499 err_hardware_deconfig: 500 ipa_hardware_deconfig(ipa); 501 ipa_clock_put(ipa); 502 503 return ret; 504 } 505 506 /** 507 * ipa_deconfig() - Inverse of ipa_config() 508 * @ipa: IPA pointer 509 */ 510 static void ipa_deconfig(struct ipa *ipa) 511 { 512 ipa_modem_deconfig(ipa); 513 ipa_mem_deconfig(ipa); 514 ipa_endpoint_deconfig(ipa); 515 ipa_hardware_deconfig(ipa); 516 ipa_clock_put(ipa); 517 } 518 519 static int ipa_firmware_load(struct device *dev) 520 { 521 const struct firmware *fw; 522 struct device_node *node; 523 struct resource res; 524 phys_addr_t phys; 525 const char *path; 526 ssize_t size; 527 void *virt; 528 int ret; 529 530 node = of_parse_phandle(dev->of_node, "memory-region", 0); 531 if (!node) { 532 dev_err(dev, "DT error getting \"memory-region\" property\n"); 533 return -EINVAL; 534 } 535 536 ret = of_address_to_resource(node, 0, &res); 537 of_node_put(node); 538 if (ret) { 539 dev_err(dev, "error %d getting \"memory-region\" resource\n", 540 ret); 541 return ret; 542 } 543 544 /* Use name from DTB if specified; use default for *any* error */ 545 ret = of_property_read_string(dev->of_node, "firmware-name", &path); 546 if (ret) { 547 dev_dbg(dev, "error %d getting \"firmware-name\" resource\n", 548 ret); 549 path = IPA_FW_PATH_DEFAULT; 550 } 551 552 ret = request_firmware(&fw, path, dev); 553 if (ret) { 554 dev_err(dev, "error %d requesting \"%s\"\n", ret, path); 555 return ret; 556 } 557 558 phys = res.start; 559 size = (size_t)resource_size(&res); 560 virt = memremap(phys, size, MEMREMAP_WC); 561 if (!virt) { 562 dev_err(dev, "unable to remap firmware memory\n"); 563 ret = -ENOMEM; 564 goto out_release_firmware; 565 } 566 567 ret = qcom_mdt_load(dev, fw, path, IPA_PAS_ID, virt, phys, size, NULL); 568 if (ret) 569 dev_err(dev, "error %d loading \"%s\"\n", ret, path); 570 else if ((ret = qcom_scm_pas_auth_and_reset(IPA_PAS_ID))) 571 dev_err(dev, "error %d authenticating \"%s\"\n", ret, path); 572 573 memunmap(virt); 574 out_release_firmware: 575 release_firmware(fw); 576 577 return ret; 578 } 579 580 static const struct of_device_id ipa_match[] = { 581 { 582 .compatible = "qcom,msm8998-ipa", 583 .data = &ipa_data_v3_1, 584 }, 585 { 586 .compatible = "qcom,sdm845-ipa", 587 .data = &ipa_data_v3_5_1, 588 }, 589 { 590 .compatible = "qcom,sc7180-ipa", 591 .data = &ipa_data_v4_2, 592 }, 593 { 594 .compatible = "qcom,sdx55-ipa", 595 .data = &ipa_data_v4_5, 596 }, 597 { 598 .compatible = "qcom,sm8350-ipa", 599 .data = &ipa_data_v4_9, 600 }, 601 { 602 .compatible = "qcom,sc7280-ipa", 603 .data = &ipa_data_v4_11, 604 }, 605 { }, 606 }; 607 MODULE_DEVICE_TABLE(of, ipa_match); 608 609 /* Check things that can be validated at build time. This just 610 * groups these things BUILD_BUG_ON() calls don't clutter the rest 611 * of the code. 612 * */ 613 static void ipa_validate_build(void) 614 { 615 #ifdef IPA_VALIDATE 616 /* At one time we assumed a 64-bit build, allowing some do_div() 617 * calls to be replaced by simple division or modulo operations. 618 * We currently only perform divide and modulo operations on u32, 619 * u16, or size_t objects, and of those only size_t has any chance 620 * of being a 64-bit value. (It should be guaranteed 32 bits wide 621 * on a 32-bit build, but there is no harm in verifying that.) 622 */ 623 BUILD_BUG_ON(!IS_ENABLED(CONFIG_64BIT) && sizeof(size_t) != 4); 624 625 /* Code assumes the EE ID for the AP is 0 (zeroed structure field) */ 626 BUILD_BUG_ON(GSI_EE_AP != 0); 627 628 /* There's no point if we have no channels or event rings */ 629 BUILD_BUG_ON(!GSI_CHANNEL_COUNT_MAX); 630 BUILD_BUG_ON(!GSI_EVT_RING_COUNT_MAX); 631 632 /* GSI hardware design limits */ 633 BUILD_BUG_ON(GSI_CHANNEL_COUNT_MAX > 32); 634 BUILD_BUG_ON(GSI_EVT_RING_COUNT_MAX > 31); 635 636 /* The number of TREs in a transaction is limited by the channel's 637 * TLV FIFO size. A transaction structure uses 8-bit fields 638 * to represents the number of TREs it has allocated and used. 639 */ 640 BUILD_BUG_ON(GSI_TLV_MAX > U8_MAX); 641 642 /* This is used as a divisor */ 643 BUILD_BUG_ON(!IPA_AGGR_GRANULARITY); 644 645 /* Aggregation granularity value can't be 0, and must fit */ 646 BUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY)); 647 BUILD_BUG_ON(ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY) > 648 field_max(AGGR_GRANULARITY_FMASK)); 649 #endif /* IPA_VALIDATE */ 650 } 651 652 static bool ipa_version_valid(enum ipa_version version) 653 { 654 switch (version) { 655 case IPA_VERSION_3_0: 656 case IPA_VERSION_3_1: 657 case IPA_VERSION_3_5: 658 case IPA_VERSION_3_5_1: 659 case IPA_VERSION_4_0: 660 case IPA_VERSION_4_1: 661 case IPA_VERSION_4_2: 662 case IPA_VERSION_4_5: 663 case IPA_VERSION_4_7: 664 case IPA_VERSION_4_9: 665 case IPA_VERSION_4_11: 666 return true; 667 668 default: 669 return false; 670 } 671 } 672 673 /** 674 * ipa_probe() - IPA platform driver probe function 675 * @pdev: Platform device pointer 676 * 677 * Return: 0 if successful, or a negative error code (possibly 678 * EPROBE_DEFER) 679 * 680 * This is the main entry point for the IPA driver. Initialization proceeds 681 * in several stages: 682 * - The "init" stage involves activities that can be initialized without 683 * access to the IPA hardware. 684 * - The "config" stage requires the IPA clock to be active so IPA registers 685 * can be accessed, but does not require the use of IPA immediate commands. 686 * - The "setup" stage uses IPA immediate commands, and so requires the GSI 687 * layer to be initialized. 688 * 689 * A Boolean Device Tree "modem-init" property determines whether GSI 690 * initialization will be performed by the AP (Trust Zone) or the modem. 691 * If the AP does GSI initialization, the setup phase is entered after 692 * this has completed successfully. Otherwise the modem initializes 693 * the GSI layer and signals it has finished by sending an SMP2P interrupt 694 * to the AP; this triggers the start if IPA setup. 695 */ 696 static int ipa_probe(struct platform_device *pdev) 697 { 698 struct device *dev = &pdev->dev; 699 const struct ipa_data *data; 700 struct ipa_clock *clock; 701 bool modem_init; 702 struct ipa *ipa; 703 int ret; 704 705 ipa_validate_build(); 706 707 /* Get configuration data early; needed for clock initialization */ 708 data = of_device_get_match_data(dev); 709 if (!data) { 710 dev_err(dev, "matched hardware not supported\n"); 711 return -ENODEV; 712 } 713 714 if (!ipa_version_valid(data->version)) { 715 dev_err(dev, "invalid IPA version\n"); 716 return -EINVAL; 717 } 718 719 /* If we need Trust Zone, make sure it's available */ 720 modem_init = of_property_read_bool(dev->of_node, "modem-init"); 721 if (!modem_init) 722 if (!qcom_scm_is_available()) 723 return -EPROBE_DEFER; 724 725 /* The clock and interconnects might not be ready when we're 726 * probed, so might return -EPROBE_DEFER. 727 */ 728 clock = ipa_clock_init(dev, data->clock_data); 729 if (IS_ERR(clock)) 730 return PTR_ERR(clock); 731 732 /* No more EPROBE_DEFER. Allocate and initialize the IPA structure */ 733 ipa = kzalloc(sizeof(*ipa), GFP_KERNEL); 734 if (!ipa) { 735 ret = -ENOMEM; 736 goto err_clock_exit; 737 } 738 739 ipa->pdev = pdev; 740 dev_set_drvdata(dev, ipa); 741 ipa->clock = clock; 742 ipa->version = data->version; 743 init_completion(&ipa->completion); 744 745 ret = ipa_reg_init(ipa); 746 if (ret) 747 goto err_kfree_ipa; 748 749 ret = ipa_mem_init(ipa, data->mem_data); 750 if (ret) 751 goto err_reg_exit; 752 753 ret = gsi_init(&ipa->gsi, pdev, ipa->version, data->endpoint_count, 754 data->endpoint_data); 755 if (ret) 756 goto err_mem_exit; 757 758 /* Result is a non-zero mask of endpoints that support filtering */ 759 ipa->filter_map = ipa_endpoint_init(ipa, data->endpoint_count, 760 data->endpoint_data); 761 if (!ipa->filter_map) { 762 ret = -EINVAL; 763 goto err_gsi_exit; 764 } 765 766 ret = ipa_table_init(ipa); 767 if (ret) 768 goto err_endpoint_exit; 769 770 ret = ipa_modem_init(ipa, modem_init); 771 if (ret) 772 goto err_table_exit; 773 774 ret = ipa_config(ipa, data); 775 if (ret) 776 goto err_modem_exit; 777 778 dev_info(dev, "IPA driver initialized"); 779 780 /* If the modem is doing early initialization, it will trigger a 781 * call to ipa_setup() call when it has finished. In that case 782 * we're done here. 783 */ 784 if (modem_init) 785 return 0; 786 787 /* Otherwise we need to load the firmware and have Trust Zone validate 788 * and install it. If that succeeds we can proceed with setup. 789 */ 790 ret = ipa_firmware_load(dev); 791 if (ret) 792 goto err_deconfig; 793 794 ret = ipa_setup(ipa); 795 if (ret) 796 goto err_deconfig; 797 798 return 0; 799 800 err_deconfig: 801 ipa_deconfig(ipa); 802 err_modem_exit: 803 ipa_modem_exit(ipa); 804 err_table_exit: 805 ipa_table_exit(ipa); 806 err_endpoint_exit: 807 ipa_endpoint_exit(ipa); 808 err_gsi_exit: 809 gsi_exit(&ipa->gsi); 810 err_mem_exit: 811 ipa_mem_exit(ipa); 812 err_reg_exit: 813 ipa_reg_exit(ipa); 814 err_kfree_ipa: 815 kfree(ipa); 816 err_clock_exit: 817 ipa_clock_exit(clock); 818 819 return ret; 820 } 821 822 static int ipa_remove(struct platform_device *pdev) 823 { 824 struct ipa *ipa = dev_get_drvdata(&pdev->dev); 825 struct ipa_clock *clock = ipa->clock; 826 int ret; 827 828 if (ipa->setup_complete) { 829 ret = ipa_modem_stop(ipa); 830 /* If starting or stopping is in progress, try once more */ 831 if (ret == -EBUSY) { 832 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 833 ret = ipa_modem_stop(ipa); 834 } 835 if (ret) 836 return ret; 837 838 ipa_teardown(ipa); 839 } 840 841 ipa_deconfig(ipa); 842 ipa_modem_exit(ipa); 843 ipa_table_exit(ipa); 844 ipa_endpoint_exit(ipa); 845 gsi_exit(&ipa->gsi); 846 ipa_mem_exit(ipa); 847 ipa_reg_exit(ipa); 848 kfree(ipa); 849 ipa_clock_exit(clock); 850 851 return 0; 852 } 853 854 static void ipa_shutdown(struct platform_device *pdev) 855 { 856 int ret; 857 858 ret = ipa_remove(pdev); 859 if (ret) 860 dev_err(&pdev->dev, "shutdown: remove returned %d\n", ret); 861 } 862 863 /** 864 * ipa_suspend() - Power management system suspend callback 865 * @dev: IPA device structure 866 * 867 * Return: Always returns zero 868 * 869 * Called by the PM framework when a system suspend operation is invoked. 870 * Suspends endpoints and releases the clock reference held to keep 871 * the IPA clock running until this point. 872 */ 873 static int ipa_suspend(struct device *dev) 874 { 875 struct ipa *ipa = dev_get_drvdata(dev); 876 877 /* When a suspended RX endpoint has a packet ready to receive, we 878 * get an IPA SUSPEND interrupt. We trigger a system resume in 879 * that case, but only on the first such interrupt since suspend. 880 */ 881 __clear_bit(IPA_FLAG_RESUMED, ipa->flags); 882 883 ipa_endpoint_suspend(ipa); 884 885 ipa_clock_put(ipa); 886 887 return 0; 888 } 889 890 /** 891 * ipa_resume() - Power management system resume callback 892 * @dev: IPA device structure 893 * 894 * Return: Always returns 0 895 * 896 * Called by the PM framework when a system resume operation is invoked. 897 * Takes an IPA clock reference to keep the clock running until suspend, 898 * and resumes endpoints. 899 */ 900 static int ipa_resume(struct device *dev) 901 { 902 struct ipa *ipa = dev_get_drvdata(dev); 903 904 /* This clock reference will keep the IPA out of suspend 905 * until we get a power management suspend request. 906 */ 907 ipa_clock_get(ipa); 908 909 ipa_endpoint_resume(ipa); 910 911 return 0; 912 } 913 914 static const struct dev_pm_ops ipa_pm_ops = { 915 .suspend = ipa_suspend, 916 .resume = ipa_resume, 917 }; 918 919 static const struct attribute_group *ipa_attribute_groups[] = { 920 &ipa_attribute_group, 921 &ipa_feature_attribute_group, 922 &ipa_modem_attribute_group, 923 NULL, 924 }; 925 926 static struct platform_driver ipa_driver = { 927 .probe = ipa_probe, 928 .remove = ipa_remove, 929 .shutdown = ipa_shutdown, 930 .driver = { 931 .name = "ipa", 932 .pm = &ipa_pm_ops, 933 .of_match_table = ipa_match, 934 .dev_groups = ipa_attribute_groups, 935 }, 936 }; 937 938 module_platform_driver(ipa_driver); 939 940 MODULE_LICENSE("GPL v2"); 941 MODULE_DESCRIPTION("Qualcomm IP Accelerator device driver"); 942