1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/atomic.h> 9 #include <linux/bitfield.h> 10 #include <linux/device.h> 11 #include <linux/bug.h> 12 #include <linux/io.h> 13 #include <linux/firmware.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_address.h> 18 #include <linux/qcom_scm.h> 19 #include <linux/soc/qcom/mdt_loader.h> 20 21 #include "ipa.h" 22 #include "ipa_clock.h" 23 #include "ipa_data.h" 24 #include "ipa_endpoint.h" 25 #include "ipa_resource.h" 26 #include "ipa_cmd.h" 27 #include "ipa_reg.h" 28 #include "ipa_mem.h" 29 #include "ipa_table.h" 30 #include "ipa_modem.h" 31 #include "ipa_uc.h" 32 #include "ipa_interrupt.h" 33 #include "gsi_trans.h" 34 35 /** 36 * DOC: The IP Accelerator 37 * 38 * This driver supports the Qualcomm IP Accelerator (IPA), which is a 39 * networking component found in many Qualcomm SoCs. The IPA is connected 40 * to the application processor (AP), but is also connected (and partially 41 * controlled by) other "execution environments" (EEs), such as a modem. 42 * 43 * The IPA is the conduit between the AP and the modem that carries network 44 * traffic. This driver presents a network interface representing the 45 * connection of the modem to external (e.g. LTE) networks. 46 * 47 * The IPA provides protocol checksum calculation, offloading this work 48 * from the AP. The IPA offers additional functionality, including routing, 49 * filtering, and NAT support, but that more advanced functionality is not 50 * currently supported. Despite that, some resources--including routing 51 * tables and filter tables--are defined in this driver because they must 52 * be initialized even when the advanced hardware features are not used. 53 * 54 * There are two distinct layers that implement the IPA hardware, and this 55 * is reflected in the organization of the driver. The generic software 56 * interface (GSI) is an integral component of the IPA, providing a 57 * well-defined communication layer between the AP subsystem and the IPA 58 * core. The GSI implements a set of "channels" used for communication 59 * between the AP and the IPA. 60 * 61 * The IPA layer uses GSI channels to implement its "endpoints". And while 62 * a GSI channel carries data between the AP and the IPA, a pair of IPA 63 * endpoints is used to carry traffic between two EEs. Specifically, the main 64 * modem network interface is implemented by two pairs of endpoints: a TX 65 * endpoint on the AP coupled with an RX endpoint on the modem; and another 66 * RX endpoint on the AP receiving data from a TX endpoint on the modem. 67 */ 68 69 /* The name of the GSI firmware file relative to /lib/firmware */ 70 #define IPA_FWS_PATH "ipa_fws.mdt" 71 #define IPA_PAS_ID 15 72 73 /* Shift of 19.2 MHz timestamp to achieve lower resolution timestamps */ 74 #define DPL_TIMESTAMP_SHIFT 14 /* ~1.172 kHz, ~853 usec per tick */ 75 #define TAG_TIMESTAMP_SHIFT 14 76 #define NAT_TIMESTAMP_SHIFT 24 /* ~1.144 Hz, ~874 msec per tick */ 77 78 /* Divider for 19.2 MHz crystal oscillator clock to get common timer clock */ 79 #define IPA_XO_CLOCK_DIVIDER 192 /* 1 is subtracted where used */ 80 81 /** 82 * ipa_suspend_handler() - Handle the suspend IPA interrupt 83 * @ipa: IPA pointer 84 * @irq_id: IPA interrupt type (unused) 85 * 86 * If an RX endpoint is in suspend state, and the IPA has a packet 87 * destined for that endpoint, the IPA generates a SUSPEND interrupt 88 * to inform the AP that it should resume the endpoint. If we get 89 * one of these interrupts we just resume everything. 90 */ 91 static void ipa_suspend_handler(struct ipa *ipa, enum ipa_irq_id irq_id) 92 { 93 /* Just report the event, and let system resume handle the rest. 94 * More than one endpoint could signal this; if so, ignore 95 * all but the first. 96 */ 97 if (!test_and_set_bit(IPA_FLAG_RESUMED, ipa->flags)) 98 pm_wakeup_dev_event(&ipa->pdev->dev, 0, true); 99 100 /* Acknowledge/clear the suspend interrupt on all endpoints */ 101 ipa_interrupt_suspend_clear_all(ipa->interrupt); 102 } 103 104 /** 105 * ipa_setup() - Set up IPA hardware 106 * @ipa: IPA pointer 107 * 108 * Perform initialization that requires issuing immediate commands on 109 * the command TX endpoint. If the modem is doing GSI firmware load 110 * and initialization, this function will be called when an SMP2P 111 * interrupt has been signaled by the modem. Otherwise it will be 112 * called from ipa_probe() after GSI firmware has been successfully 113 * loaded, authenticated, and started by Trust Zone. 114 */ 115 int ipa_setup(struct ipa *ipa) 116 { 117 struct ipa_endpoint *exception_endpoint; 118 struct ipa_endpoint *command_endpoint; 119 struct device *dev = &ipa->pdev->dev; 120 int ret; 121 122 ret = gsi_setup(&ipa->gsi); 123 if (ret) 124 return ret; 125 126 ipa->interrupt = ipa_interrupt_setup(ipa); 127 if (IS_ERR(ipa->interrupt)) { 128 ret = PTR_ERR(ipa->interrupt); 129 goto err_gsi_teardown; 130 } 131 ipa_interrupt_add(ipa->interrupt, IPA_IRQ_TX_SUSPEND, 132 ipa_suspend_handler); 133 134 ipa_uc_setup(ipa); 135 136 ret = device_init_wakeup(dev, true); 137 if (ret) 138 goto err_uc_teardown; 139 140 ipa_endpoint_setup(ipa); 141 142 /* We need to use the AP command TX endpoint to perform other 143 * initialization, so we enable first. 144 */ 145 command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; 146 ret = ipa_endpoint_enable_one(command_endpoint); 147 if (ret) 148 goto err_endpoint_teardown; 149 150 ret = ipa_mem_setup(ipa); 151 if (ret) 152 goto err_command_disable; 153 154 ret = ipa_table_setup(ipa); 155 if (ret) 156 goto err_mem_teardown; 157 158 /* Enable the exception handling endpoint, and tell the hardware 159 * to use it by default. 160 */ 161 exception_endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]; 162 ret = ipa_endpoint_enable_one(exception_endpoint); 163 if (ret) 164 goto err_table_teardown; 165 166 ipa_endpoint_default_route_set(ipa, exception_endpoint->endpoint_id); 167 168 /* We're all set. Now prepare for communication with the modem */ 169 ret = ipa_modem_setup(ipa); 170 if (ret) 171 goto err_default_route_clear; 172 173 ipa->setup_complete = true; 174 175 dev_info(dev, "IPA driver setup completed successfully\n"); 176 177 return 0; 178 179 err_default_route_clear: 180 ipa_endpoint_default_route_clear(ipa); 181 ipa_endpoint_disable_one(exception_endpoint); 182 err_table_teardown: 183 ipa_table_teardown(ipa); 184 err_mem_teardown: 185 ipa_mem_teardown(ipa); 186 err_command_disable: 187 ipa_endpoint_disable_one(command_endpoint); 188 err_endpoint_teardown: 189 ipa_endpoint_teardown(ipa); 190 (void)device_init_wakeup(dev, false); 191 err_uc_teardown: 192 ipa_uc_teardown(ipa); 193 ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_TX_SUSPEND); 194 ipa_interrupt_teardown(ipa->interrupt); 195 err_gsi_teardown: 196 gsi_teardown(&ipa->gsi); 197 198 return ret; 199 } 200 201 /** 202 * ipa_teardown() - Inverse of ipa_setup() 203 * @ipa: IPA pointer 204 */ 205 static void ipa_teardown(struct ipa *ipa) 206 { 207 struct ipa_endpoint *exception_endpoint; 208 struct ipa_endpoint *command_endpoint; 209 210 ipa_modem_teardown(ipa); 211 ipa_endpoint_default_route_clear(ipa); 212 exception_endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX]; 213 ipa_endpoint_disable_one(exception_endpoint); 214 ipa_table_teardown(ipa); 215 ipa_mem_teardown(ipa); 216 command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX]; 217 ipa_endpoint_disable_one(command_endpoint); 218 ipa_endpoint_teardown(ipa); 219 (void)device_init_wakeup(&ipa->pdev->dev, false); 220 ipa_uc_teardown(ipa); 221 ipa_interrupt_remove(ipa->interrupt, IPA_IRQ_TX_SUSPEND); 222 ipa_interrupt_teardown(ipa->interrupt); 223 gsi_teardown(&ipa->gsi); 224 } 225 226 /* Configure bus access behavior for IPA components */ 227 static void ipa_hardware_config_comp(struct ipa *ipa) 228 { 229 u32 val; 230 231 /* Nothing to configure prior to IPA v4.0 */ 232 if (ipa->version < IPA_VERSION_4_0) 233 return; 234 235 val = ioread32(ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET); 236 237 if (ipa->version == IPA_VERSION_4_0) { 238 val &= ~IPA_QMB_SELECT_CONS_EN_FMASK; 239 val &= ~IPA_QMB_SELECT_PROD_EN_FMASK; 240 val &= ~IPA_QMB_SELECT_GLOBAL_EN_FMASK; 241 } else if (ipa->version < IPA_VERSION_4_5) { 242 val |= GSI_MULTI_AXI_MASTERS_DIS_FMASK; 243 } else { 244 /* For IPA v4.5 IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN is 0 */ 245 } 246 247 val |= GSI_MULTI_INORDER_RD_DIS_FMASK; 248 val |= GSI_MULTI_INORDER_WR_DIS_FMASK; 249 250 iowrite32(val, ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET); 251 } 252 253 /* Configure DDR and (possibly) PCIe max read/write QSB values */ 254 static void 255 ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data) 256 { 257 const struct ipa_qsb_data *data0; 258 const struct ipa_qsb_data *data1; 259 u32 val; 260 261 /* assert(data->qsb_count > 0); */ 262 /* assert(data->qsb_count < 3); */ 263 264 /* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */ 265 data0 = &data->qsb_data[IPA_QSB_MASTER_DDR]; 266 if (data->qsb_count > 1) 267 data1 = &data->qsb_data[IPA_QSB_MASTER_PCIE]; 268 269 /* Max outstanding write accesses for QSB masters */ 270 val = u32_encode_bits(data0->max_writes, GEN_QMB_0_MAX_WRITES_FMASK); 271 if (data->qsb_count > 1) 272 val |= u32_encode_bits(data1->max_writes, 273 GEN_QMB_1_MAX_WRITES_FMASK); 274 iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_WRITES_OFFSET); 275 276 /* Max outstanding read accesses for QSB masters */ 277 val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK); 278 if (ipa->version >= IPA_VERSION_4_0) 279 val |= u32_encode_bits(data0->max_reads_beats, 280 GEN_QMB_0_MAX_READS_BEATS_FMASK); 281 if (data->qsb_count > 1) { 282 val |= u32_encode_bits(data1->max_reads, 283 GEN_QMB_1_MAX_READS_FMASK); 284 if (ipa->version >= IPA_VERSION_4_0) 285 val |= u32_encode_bits(data1->max_reads_beats, 286 GEN_QMB_1_MAX_READS_BEATS_FMASK); 287 } 288 iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET); 289 } 290 291 /* The internal inactivity timer clock is used for the aggregation timer */ 292 #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */ 293 294 /* Compute the value to use in the COUNTER_CFG register AGGR_GRANULARITY 295 * field to represent the given number of microseconds. The value is one 296 * less than the number of timer ticks in the requested period. 0 is not 297 * a valid granularity value. 298 */ 299 static u32 ipa_aggr_granularity_val(u32 usec) 300 { 301 /* assert(usec != 0); */ 302 303 return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1; 304 } 305 306 /* IPA uses unified Qtime starting at IPA v4.5, implementing various 307 * timestamps and timers independent of the IPA core clock rate. The 308 * Qtimer is based on a 56-bit timestamp incremented at each tick of 309 * a 19.2 MHz SoC crystal oscillator (XO clock). 310 * 311 * For IPA timestamps (tag, NAT, data path logging) a lower resolution 312 * timestamp is achieved by shifting the Qtimer timestamp value right 313 * some number of bits to produce the low-order bits of the coarser 314 * granularity timestamp. 315 * 316 * For timers, a common timer clock is derived from the XO clock using 317 * a divider (we use 192, to produce a 100kHz timer clock). From 318 * this common clock, three "pulse generators" are used to produce 319 * timer ticks at a configurable frequency. IPA timers (such as 320 * those used for aggregation or head-of-line block handling) now 321 * define their period based on one of these pulse generators. 322 */ 323 static void ipa_qtime_config(struct ipa *ipa) 324 { 325 u32 val; 326 327 /* Timer clock divider must be disabled when we change the rate */ 328 iowrite32(0, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 329 330 /* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */ 331 val = u32_encode_bits(DPL_TIMESTAMP_SHIFT, DPL_TIMESTAMP_LSB_FMASK); 332 val |= u32_encode_bits(1, DPL_TIMESTAMP_SEL_FMASK); 333 /* Configure tag and NAT Qtime timestamp resolution as well */ 334 val |= u32_encode_bits(TAG_TIMESTAMP_SHIFT, TAG_TIMESTAMP_LSB_FMASK); 335 val |= u32_encode_bits(NAT_TIMESTAMP_SHIFT, NAT_TIMESTAMP_LSB_FMASK); 336 iowrite32(val, ipa->reg_virt + IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET); 337 338 /* Set granularity of pulse generators used for other timers */ 339 val = u32_encode_bits(IPA_GRAN_100_US, GRAN_0_FMASK); 340 val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_1_FMASK); 341 val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_2_FMASK); 342 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET); 343 344 /* Actual divider is 1 more than value supplied here */ 345 val = u32_encode_bits(IPA_XO_CLOCK_DIVIDER - 1, DIV_VALUE_FMASK); 346 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 347 348 /* Divider value is set; re-enable the common timer clock divider */ 349 val |= u32_encode_bits(1, DIV_ENABLE_FMASK); 350 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET); 351 } 352 353 static void ipa_idle_indication_cfg(struct ipa *ipa, 354 u32 enter_idle_debounce_thresh, 355 bool const_non_idle_enable) 356 { 357 u32 offset; 358 u32 val; 359 360 val = u32_encode_bits(enter_idle_debounce_thresh, 361 ENTER_IDLE_DEBOUNCE_THRESH_FMASK); 362 if (const_non_idle_enable) 363 val |= CONST_NON_IDLE_ENABLE_FMASK; 364 365 offset = ipa_reg_idle_indication_cfg_offset(ipa->version); 366 iowrite32(val, ipa->reg_virt + offset); 367 } 368 369 /** 370 * ipa_hardware_dcd_config() - Enable dynamic clock division on IPA 371 * @ipa: IPA pointer 372 * 373 * Configures when the IPA signals it is idle to the global clock 374 * controller, which can respond by scalling down the clock to 375 * save power. 376 */ 377 static void ipa_hardware_dcd_config(struct ipa *ipa) 378 { 379 /* Recommended values for IPA 3.5 and later according to IPA HPG */ 380 ipa_idle_indication_cfg(ipa, 256, false); 381 } 382 383 static void ipa_hardware_dcd_deconfig(struct ipa *ipa) 384 { 385 /* Power-on reset values */ 386 ipa_idle_indication_cfg(ipa, 0, true); 387 } 388 389 /** 390 * ipa_hardware_config() - Primitive hardware initialization 391 * @ipa: IPA pointer 392 * @data: IPA configuration data 393 */ 394 static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data) 395 { 396 enum ipa_version version = ipa->version; 397 u32 granularity; 398 u32 val; 399 400 /* IPA v4.5 has no backward compatibility register */ 401 if (version < IPA_VERSION_4_5) { 402 val = ipa_reg_bcr_val(version); 403 iowrite32(val, ipa->reg_virt + IPA_REG_BCR_OFFSET); 404 } 405 406 /* Implement some hardware workarounds */ 407 if (version >= IPA_VERSION_4_0 && version < IPA_VERSION_4_5) { 408 /* Enable open global clocks (not needed for IPA v4.5) */ 409 val = GLOBAL_FMASK; 410 val |= GLOBAL_2X_CLK_FMASK; 411 iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET); 412 413 /* Disable PA mask to allow HOLB drop */ 414 val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); 415 val &= ~PA_MASK_EN_FMASK; 416 iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET); 417 } 418 419 ipa_hardware_config_comp(ipa); 420 421 /* Configure system bus limits */ 422 ipa_hardware_config_qsb(ipa, data); 423 424 if (version < IPA_VERSION_4_5) { 425 /* Configure aggregation timer granularity */ 426 granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY); 427 val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK); 428 iowrite32(val, ipa->reg_virt + IPA_REG_COUNTER_CFG_OFFSET); 429 } else { 430 ipa_qtime_config(ipa); 431 } 432 433 /* IPA v4.2 does not support hashed tables, so disable them */ 434 if (version == IPA_VERSION_4_2) { 435 u32 offset = ipa_reg_filt_rout_hash_en_offset(version); 436 437 iowrite32(0, ipa->reg_virt + offset); 438 } 439 440 /* Enable dynamic clock division */ 441 ipa_hardware_dcd_config(ipa); 442 } 443 444 /** 445 * ipa_hardware_deconfig() - Inverse of ipa_hardware_config() 446 * @ipa: IPA pointer 447 * 448 * This restores the power-on reset values (even if they aren't different) 449 */ 450 static void ipa_hardware_deconfig(struct ipa *ipa) 451 { 452 /* Mostly we just leave things as we set them. */ 453 ipa_hardware_dcd_deconfig(ipa); 454 } 455 456 /** 457 * ipa_config() - Configure IPA hardware 458 * @ipa: IPA pointer 459 * @data: IPA configuration data 460 * 461 * Perform initialization requiring IPA clock to be enabled. 462 */ 463 static int ipa_config(struct ipa *ipa, const struct ipa_data *data) 464 { 465 int ret; 466 467 /* Get a clock reference to allow initialization. This reference 468 * is held after initialization completes, and won't get dropped 469 * unless/until a system suspend request arrives. 470 */ 471 ipa_clock_get(ipa); 472 473 ipa_hardware_config(ipa, data); 474 475 ret = ipa_endpoint_config(ipa); 476 if (ret) 477 goto err_hardware_deconfig; 478 479 ret = ipa_mem_config(ipa); 480 if (ret) 481 goto err_endpoint_deconfig; 482 483 ipa_table_config(ipa); 484 485 /* Assign resource limitation to each group */ 486 ret = ipa_resource_config(ipa, data->resource_data); 487 if (ret) 488 goto err_table_deconfig; 489 490 ret = ipa_modem_config(ipa); 491 if (ret) 492 goto err_resource_deconfig; 493 494 return 0; 495 496 err_resource_deconfig: 497 ipa_resource_deconfig(ipa); 498 err_table_deconfig: 499 ipa_table_deconfig(ipa); 500 ipa_mem_deconfig(ipa); 501 err_endpoint_deconfig: 502 ipa_endpoint_deconfig(ipa); 503 err_hardware_deconfig: 504 ipa_hardware_deconfig(ipa); 505 ipa_clock_put(ipa); 506 507 return ret; 508 } 509 510 /** 511 * ipa_deconfig() - Inverse of ipa_config() 512 * @ipa: IPA pointer 513 */ 514 static void ipa_deconfig(struct ipa *ipa) 515 { 516 ipa_modem_deconfig(ipa); 517 ipa_resource_deconfig(ipa); 518 ipa_table_deconfig(ipa); 519 ipa_mem_deconfig(ipa); 520 ipa_endpoint_deconfig(ipa); 521 ipa_hardware_deconfig(ipa); 522 ipa_clock_put(ipa); 523 } 524 525 static int ipa_firmware_load(struct device *dev) 526 { 527 const struct firmware *fw; 528 struct device_node *node; 529 struct resource res; 530 phys_addr_t phys; 531 ssize_t size; 532 void *virt; 533 int ret; 534 535 node = of_parse_phandle(dev->of_node, "memory-region", 0); 536 if (!node) { 537 dev_err(dev, "DT error getting \"memory-region\" property\n"); 538 return -EINVAL; 539 } 540 541 ret = of_address_to_resource(node, 0, &res); 542 if (ret) { 543 dev_err(dev, "error %d getting \"memory-region\" resource\n", 544 ret); 545 return ret; 546 } 547 548 ret = request_firmware(&fw, IPA_FWS_PATH, dev); 549 if (ret) { 550 dev_err(dev, "error %d requesting \"%s\"\n", ret, IPA_FWS_PATH); 551 return ret; 552 } 553 554 phys = res.start; 555 size = (size_t)resource_size(&res); 556 virt = memremap(phys, size, MEMREMAP_WC); 557 if (!virt) { 558 dev_err(dev, "unable to remap firmware memory\n"); 559 ret = -ENOMEM; 560 goto out_release_firmware; 561 } 562 563 ret = qcom_mdt_load(dev, fw, IPA_FWS_PATH, IPA_PAS_ID, 564 virt, phys, size, NULL); 565 if (ret) 566 dev_err(dev, "error %d loading \"%s\"\n", ret, IPA_FWS_PATH); 567 else if ((ret = qcom_scm_pas_auth_and_reset(IPA_PAS_ID))) 568 dev_err(dev, "error %d authenticating \"%s\"\n", ret, 569 IPA_FWS_PATH); 570 571 memunmap(virt); 572 out_release_firmware: 573 release_firmware(fw); 574 575 return ret; 576 } 577 578 static const struct of_device_id ipa_match[] = { 579 { 580 .compatible = "qcom,sdm845-ipa", 581 .data = &ipa_data_sdm845, 582 }, 583 { 584 .compatible = "qcom,sc7180-ipa", 585 .data = &ipa_data_sc7180, 586 }, 587 { }, 588 }; 589 MODULE_DEVICE_TABLE(of, ipa_match); 590 591 /* Check things that can be validated at build time. This just 592 * groups these things BUILD_BUG_ON() calls don't clutter the rest 593 * of the code. 594 * */ 595 static void ipa_validate_build(void) 596 { 597 #ifdef IPA_VALIDATE 598 /* At one time we assumed a 64-bit build, allowing some do_div() 599 * calls to be replaced by simple division or modulo operations. 600 * We currently only perform divide and modulo operations on u32, 601 * u16, or size_t objects, and of those only size_t has any chance 602 * of being a 64-bit value. (It should be guaranteed 32 bits wide 603 * on a 32-bit build, but there is no harm in verifying that.) 604 */ 605 BUILD_BUG_ON(!IS_ENABLED(CONFIG_64BIT) && sizeof(size_t) != 4); 606 607 /* Code assumes the EE ID for the AP is 0 (zeroed structure field) */ 608 BUILD_BUG_ON(GSI_EE_AP != 0); 609 610 /* There's no point if we have no channels or event rings */ 611 BUILD_BUG_ON(!GSI_CHANNEL_COUNT_MAX); 612 BUILD_BUG_ON(!GSI_EVT_RING_COUNT_MAX); 613 614 /* GSI hardware design limits */ 615 BUILD_BUG_ON(GSI_CHANNEL_COUNT_MAX > 32); 616 BUILD_BUG_ON(GSI_EVT_RING_COUNT_MAX > 31); 617 618 /* The number of TREs in a transaction is limited by the channel's 619 * TLV FIFO size. A transaction structure uses 8-bit fields 620 * to represents the number of TREs it has allocated and used. 621 */ 622 BUILD_BUG_ON(GSI_TLV_MAX > U8_MAX); 623 624 /* This is used as a divisor */ 625 BUILD_BUG_ON(!IPA_AGGR_GRANULARITY); 626 627 /* Aggregation granularity value can't be 0, and must fit */ 628 BUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY)); 629 BUILD_BUG_ON(ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY) > 630 field_max(AGGR_GRANULARITY_FMASK)); 631 #endif /* IPA_VALIDATE */ 632 } 633 634 /** 635 * ipa_probe() - IPA platform driver probe function 636 * @pdev: Platform device pointer 637 * 638 * Return: 0 if successful, or a negative error code (possibly 639 * EPROBE_DEFER) 640 * 641 * This is the main entry point for the IPA driver. Initialization proceeds 642 * in several stages: 643 * - The "init" stage involves activities that can be initialized without 644 * access to the IPA hardware. 645 * - The "config" stage requires the IPA clock to be active so IPA registers 646 * can be accessed, but does not require the use of IPA immediate commands. 647 * - The "setup" stage uses IPA immediate commands, and so requires the GSI 648 * layer to be initialized. 649 * 650 * A Boolean Device Tree "modem-init" property determines whether GSI 651 * initialization will be performed by the AP (Trust Zone) or the modem. 652 * If the AP does GSI initialization, the setup phase is entered after 653 * this has completed successfully. Otherwise the modem initializes 654 * the GSI layer and signals it has finished by sending an SMP2P interrupt 655 * to the AP; this triggers the start if IPA setup. 656 */ 657 static int ipa_probe(struct platform_device *pdev) 658 { 659 struct device *dev = &pdev->dev; 660 const struct ipa_data *data; 661 struct ipa_clock *clock; 662 bool modem_init; 663 struct ipa *ipa; 664 int ret; 665 666 ipa_validate_build(); 667 668 /* Get configuration data early; needed for clock initialization */ 669 data = of_device_get_match_data(dev); 670 if (!data) { 671 /* This is really IPA_VALIDATE (should never happen) */ 672 dev_err(dev, "matched hardware not supported\n"); 673 return -ENODEV; 674 } 675 676 /* If we need Trust Zone, make sure it's available */ 677 modem_init = of_property_read_bool(dev->of_node, "modem-init"); 678 if (!modem_init) 679 if (!qcom_scm_is_available()) 680 return -EPROBE_DEFER; 681 682 /* The clock and interconnects might not be ready when we're 683 * probed, so might return -EPROBE_DEFER. 684 */ 685 clock = ipa_clock_init(dev, data->clock_data); 686 if (IS_ERR(clock)) 687 return PTR_ERR(clock); 688 689 /* No more EPROBE_DEFER. Allocate and initialize the IPA structure */ 690 ipa = kzalloc(sizeof(*ipa), GFP_KERNEL); 691 if (!ipa) { 692 ret = -ENOMEM; 693 goto err_clock_exit; 694 } 695 696 ipa->pdev = pdev; 697 dev_set_drvdata(dev, ipa); 698 ipa->clock = clock; 699 ipa->version = data->version; 700 init_completion(&ipa->completion); 701 702 ret = ipa_reg_init(ipa); 703 if (ret) 704 goto err_kfree_ipa; 705 706 ret = ipa_mem_init(ipa, data->mem_data); 707 if (ret) 708 goto err_reg_exit; 709 710 ret = gsi_init(&ipa->gsi, pdev, ipa->version, data->endpoint_count, 711 data->endpoint_data); 712 if (ret) 713 goto err_mem_exit; 714 715 /* Result is a non-zero mask of endpoints that support filtering */ 716 ipa->filter_map = ipa_endpoint_init(ipa, data->endpoint_count, 717 data->endpoint_data); 718 if (!ipa->filter_map) { 719 ret = -EINVAL; 720 goto err_gsi_exit; 721 } 722 723 ret = ipa_table_init(ipa); 724 if (ret) 725 goto err_endpoint_exit; 726 727 ret = ipa_modem_init(ipa, modem_init); 728 if (ret) 729 goto err_table_exit; 730 731 ret = ipa_config(ipa, data); 732 if (ret) 733 goto err_modem_exit; 734 735 dev_info(dev, "IPA driver initialized"); 736 737 /* If the modem is doing early initialization, it will trigger a 738 * call to ipa_setup() call when it has finished. In that case 739 * we're done here. 740 */ 741 if (modem_init) 742 return 0; 743 744 /* Otherwise we need to load the firmware and have Trust Zone validate 745 * and install it. If that succeeds we can proceed with setup. 746 */ 747 ret = ipa_firmware_load(dev); 748 if (ret) 749 goto err_deconfig; 750 751 ret = ipa_setup(ipa); 752 if (ret) 753 goto err_deconfig; 754 755 return 0; 756 757 err_deconfig: 758 ipa_deconfig(ipa); 759 err_modem_exit: 760 ipa_modem_exit(ipa); 761 err_table_exit: 762 ipa_table_exit(ipa); 763 err_endpoint_exit: 764 ipa_endpoint_exit(ipa); 765 err_gsi_exit: 766 gsi_exit(&ipa->gsi); 767 err_mem_exit: 768 ipa_mem_exit(ipa); 769 err_reg_exit: 770 ipa_reg_exit(ipa); 771 err_kfree_ipa: 772 kfree(ipa); 773 err_clock_exit: 774 ipa_clock_exit(clock); 775 776 return ret; 777 } 778 779 static int ipa_remove(struct platform_device *pdev) 780 { 781 struct ipa *ipa = dev_get_drvdata(&pdev->dev); 782 struct ipa_clock *clock = ipa->clock; 783 int ret; 784 785 if (ipa->setup_complete) { 786 ret = ipa_modem_stop(ipa); 787 /* If starting or stopping is in progress, try once more */ 788 if (ret == -EBUSY) { 789 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 790 ret = ipa_modem_stop(ipa); 791 } 792 if (ret) 793 return ret; 794 795 ipa_teardown(ipa); 796 } 797 798 ipa_deconfig(ipa); 799 ipa_modem_exit(ipa); 800 ipa_table_exit(ipa); 801 ipa_endpoint_exit(ipa); 802 gsi_exit(&ipa->gsi); 803 ipa_mem_exit(ipa); 804 ipa_reg_exit(ipa); 805 kfree(ipa); 806 ipa_clock_exit(clock); 807 808 return 0; 809 } 810 811 static void ipa_shutdown(struct platform_device *pdev) 812 { 813 int ret; 814 815 ret = ipa_remove(pdev); 816 if (ret) 817 dev_err(&pdev->dev, "shutdown: remove returned %d\n", ret); 818 } 819 820 /** 821 * ipa_suspend() - Power management system suspend callback 822 * @dev: IPA device structure 823 * 824 * Return: Always returns zero 825 * 826 * Called by the PM framework when a system suspend operation is invoked. 827 * Suspends endpoints and releases the clock reference held to keep 828 * the IPA clock running until this point. 829 */ 830 static int ipa_suspend(struct device *dev) 831 { 832 struct ipa *ipa = dev_get_drvdata(dev); 833 834 /* When a suspended RX endpoint has a packet ready to receive, we 835 * get an IPA SUSPEND interrupt. We trigger a system resume in 836 * that case, but only on the first such interrupt since suspend. 837 */ 838 __clear_bit(IPA_FLAG_RESUMED, ipa->flags); 839 840 ipa_endpoint_suspend(ipa); 841 842 ipa_clock_put(ipa); 843 844 return 0; 845 } 846 847 /** 848 * ipa_resume() - Power management system resume callback 849 * @dev: IPA device structure 850 * 851 * Return: Always returns 0 852 * 853 * Called by the PM framework when a system resume operation is invoked. 854 * Takes an IPA clock reference to keep the clock running until suspend, 855 * and resumes endpoints. 856 */ 857 static int ipa_resume(struct device *dev) 858 { 859 struct ipa *ipa = dev_get_drvdata(dev); 860 861 /* This clock reference will keep the IPA out of suspend 862 * until we get a power management suspend request. 863 */ 864 ipa_clock_get(ipa); 865 866 ipa_endpoint_resume(ipa); 867 868 return 0; 869 } 870 871 static const struct dev_pm_ops ipa_pm_ops = { 872 .suspend = ipa_suspend, 873 .resume = ipa_resume, 874 }; 875 876 static struct platform_driver ipa_driver = { 877 .probe = ipa_probe, 878 .remove = ipa_remove, 879 .shutdown = ipa_shutdown, 880 .driver = { 881 .name = "ipa", 882 .pm = &ipa_pm_ops, 883 .of_match_table = ipa_match, 884 }, 885 }; 886 887 module_platform_driver(ipa_driver); 888 889 MODULE_LICENSE("GPL v2"); 890 MODULE_DESCRIPTION("Qualcomm IP Accelerator device driver"); 891