1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2020 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 #define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \ 42 GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 43 #define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \ 44 (0x0000c018 + 0x1000 * (ee)) 45 46 #define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \ 47 GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 48 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \ 49 (0x0000c01c + 0x1000 * (ee)) 50 51 #define GSI_INTER_EE_SRC_CH_IRQ_CLR_OFFSET \ 52 GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 53 #define GSI_INTER_EE_N_SRC_CH_IRQ_CLR_OFFSET(ee) \ 54 (0x0000c028 + 0x1000 * (ee)) 55 56 #define GSI_INTER_EE_SRC_EV_CH_IRQ_CLR_OFFSET \ 57 GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 58 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 59 (0x0000c02c + 0x1000 * (ee)) 60 61 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ 62 GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP) 63 #define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \ 64 (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch)) 65 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) 66 #define CHTYPE_DIR_FMASK GENMASK(3, 3) 67 #define EE_FMASK GENMASK(7, 4) 68 #define CHID_FMASK GENMASK(12, 8) 69 /* The next field is present for IPA v4.5 and above */ 70 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) 71 #define ERINDEX_FMASK GENMASK(18, 14) 72 #define CHSTATE_FMASK GENMASK(23, 20) 73 #define ELEMENT_SIZE_FMASK GENMASK(31, 24) 74 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ 75 enum gsi_channel_type { 76 GSI_CHANNEL_TYPE_MHI = 0x0, 77 GSI_CHANNEL_TYPE_XHCI = 0x1, 78 GSI_CHANNEL_TYPE_GPI = 0x2, 79 GSI_CHANNEL_TYPE_XDCI = 0x3, 80 }; 81 82 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ 83 GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP) 84 #define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \ 85 (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch)) 86 #define R_LENGTH_FMASK GENMASK(15, 0) 87 88 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ 89 GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP) 90 #define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \ 91 (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch)) 92 93 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ 94 GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP) 95 #define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \ 96 (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch)) 97 98 #define GSI_CH_C_QOS_OFFSET(ch) \ 99 GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP) 100 #define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \ 101 (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch)) 102 #define WRR_WEIGHT_FMASK GENMASK(3, 0) 103 #define MAX_PREFETCH_FMASK GENMASK(8, 8) 104 #define USE_DB_ENG_FMASK GENMASK(9, 9) 105 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */ 106 #define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) 107 108 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ 109 GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP) 110 #define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \ 111 (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch)) 112 113 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ 114 GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP) 115 #define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \ 116 (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch)) 117 118 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ 119 GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP) 120 #define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \ 121 (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch)) 122 123 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ 124 GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP) 125 #define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \ 126 (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch)) 127 128 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ 129 GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP) 130 #define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \ 131 (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev)) 132 #define EV_CHTYPE_FMASK GENMASK(3, 0) 133 #define EV_EE_FMASK GENMASK(7, 4) 134 #define EV_EVCHID_FMASK GENMASK(15, 8) 135 #define EV_INTYPE_FMASK GENMASK(16, 16) 136 #define EV_CHSTATE_FMASK GENMASK(23, 20) 137 #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) 138 /* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ 139 140 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ 141 GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP) 142 #define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \ 143 (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev)) 144 #define EV_R_LENGTH_FMASK GENMASK(15, 0) 145 146 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ 147 GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP) 148 #define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \ 149 (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev)) 150 151 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ 152 GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP) 153 #define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \ 154 (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev)) 155 156 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ 157 GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP) 158 #define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \ 159 (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev)) 160 161 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ 162 GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP) 163 #define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \ 164 (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev)) 165 #define MODT_FMASK GENMASK(15, 0) 166 #define MODC_FMASK GENMASK(23, 16) 167 #define MOD_CNT_FMASK GENMASK(31, 24) 168 169 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ 170 GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP) 171 #define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \ 172 (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev)) 173 174 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ 175 GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP) 176 #define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \ 177 (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev)) 178 179 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ 180 GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP) 181 #define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \ 182 (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev)) 183 184 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ 185 GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP) 186 #define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \ 187 (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev)) 188 189 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ 190 GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP) 191 #define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \ 192 (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev)) 193 194 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ 195 GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP) 196 #define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \ 197 (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev)) 198 199 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ 200 GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP) 201 #define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \ 202 (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev)) 203 204 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ 205 GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP) 206 #define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \ 207 (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch)) 208 209 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ 210 GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP) 211 #define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \ 212 (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev)) 213 214 #define GSI_GSI_STATUS_OFFSET \ 215 GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP) 216 #define GSI_EE_N_GSI_STATUS_OFFSET(ee) \ 217 (0x0001f000 + 0x4000 * (ee)) 218 #define ENABLED_FMASK GENMASK(0, 0) 219 220 #define GSI_CH_CMD_OFFSET \ 221 GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP) 222 #define GSI_EE_N_CH_CMD_OFFSET(ee) \ 223 (0x0001f008 + 0x4000 * (ee)) 224 #define CH_CHID_FMASK GENMASK(7, 0) 225 #define CH_OPCODE_FMASK GENMASK(31, 24) 226 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ 227 enum gsi_ch_cmd_opcode { 228 GSI_CH_ALLOCATE = 0x0, 229 GSI_CH_START = 0x1, 230 GSI_CH_STOP = 0x2, 231 GSI_CH_RESET = 0x9, 232 GSI_CH_DE_ALLOC = 0xa, 233 }; 234 235 #define GSI_EV_CH_CMD_OFFSET \ 236 GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP) 237 #define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \ 238 (0x0001f010 + 0x4000 * (ee)) 239 #define EV_CHID_FMASK GENMASK(7, 0) 240 #define EV_OPCODE_FMASK GENMASK(31, 24) 241 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ 242 enum gsi_evt_cmd_opcode { 243 GSI_EVT_ALLOCATE = 0x0, 244 GSI_EVT_RESET = 0x9, 245 GSI_EVT_DE_ALLOC = 0xa, 246 }; 247 248 #define GSI_GENERIC_CMD_OFFSET \ 249 GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP) 250 #define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \ 251 (0x0001f018 + 0x4000 * (ee)) 252 #define GENERIC_OPCODE_FMASK GENMASK(4, 0) 253 #define GENERIC_CHID_FMASK GENMASK(9, 5) 254 #define GENERIC_EE_FMASK GENMASK(13, 10) 255 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ 256 enum gsi_generic_cmd_opcode { 257 GSI_GENERIC_HALT_CHANNEL = 0x1, 258 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 259 }; 260 261 #define GSI_GSI_HW_PARAM_2_OFFSET \ 262 GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP) 263 #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \ 264 (0x0001f040 + 0x4000 * (ee)) 265 #define IRAM_SIZE_FMASK GENMASK(2, 0) 266 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) 267 #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) 268 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) 269 #define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) 270 /* Fields below are present for IPA v4.0 and above */ 271 #define GSI_USE_SDMA_FMASK GENMASK(15, 15) 272 #define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) 273 #define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) 274 #define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) 275 /* Fields below are present for IPA v4.2 and above */ 276 #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) 277 #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) 278 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ 279 enum gsi_iram_size { 280 IRAM_SIZE_ONE_KB = 0x0, 281 IRAM_SIZE_TWO_KB = 0x1, 282 /* The next two values are available for IPA v4.0 and above */ 283 IRAM_SIZE_TWO_N_HALF_KB = 0x2, 284 IRAM_SIZE_THREE_KB = 0x3, 285 }; 286 287 /* IRQ condition for each type is cleared by writing type-specific register */ 288 #define GSI_CNTXT_TYPE_IRQ_OFFSET \ 289 GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) 290 #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ 291 (0x0001f080 + 0x4000 * (ee)) 292 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ 293 GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) 294 #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ 295 (0x0001f088 + 0x4000 * (ee)) 296 /* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */ 297 enum gsi_irq_type_id { 298 GSI_CH_CTRL = 0, /* channel allocation, etc. */ 299 GSI_EV_CTRL = 1, /* event ring allocation, etc. */ 300 GSI_GLOB_EE = 2, /* global/general event */ 301 GSI_IEOB = 3, /* TRE completion */ 302 GSI_INTER_EE_CH_CTRL = 4, /* remote-issued stop/reset (unused) */ 303 GSI_INTER_EE_EV_CTRL = 5, /* remote-issued event reset (unused) */ 304 GSI_GENERAL = 6, /* general-purpose event */ 305 }; 306 307 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ 308 GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 309 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \ 310 (0x0001f090 + 0x4000 * (ee)) 311 312 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ 313 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 314 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \ 315 (0x0001f094 + 0x4000 * (ee)) 316 317 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ 318 GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 319 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \ 320 (0x0001f098 + 0x4000 * (ee)) 321 322 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ 323 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 324 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ 325 (0x0001f09c + 0x4000 * (ee)) 326 327 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ 328 GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 329 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \ 330 (0x0001f0a0 + 0x4000 * (ee)) 331 332 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ 333 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 334 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 335 (0x0001f0a4 + 0x4000 * (ee)) 336 337 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ 338 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP) 339 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \ 340 (0x0001f0b0 + 0x4000 * (ee)) 341 342 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ 343 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP) 344 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \ 345 (0x0001f0b8 + 0x4000 * (ee)) 346 347 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ 348 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP) 349 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \ 350 (0x0001f0c0 + 0x4000 * (ee)) 351 352 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ 353 GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP) 354 #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \ 355 (0x0001f100 + 0x4000 * (ee)) 356 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ 357 GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP) 358 #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \ 359 (0x0001f108 + 0x4000 * (ee)) 360 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ 361 GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) 362 #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ 363 (0x0001f110 + 0x4000 * (ee)) 364 /* Values here are bit positions in the GLOB_IRQ_* registers */ 365 enum gsi_global_irq_id { 366 ERROR_INT = 0x0, 367 GP_INT1 = 0x1, 368 GP_INT2 = 0x2, 369 GP_INT3 = 0x3, 370 }; 371 372 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ 373 GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) 374 #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ 375 (0x0001f118 + 0x4000 * (ee)) 376 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ 377 GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) 378 #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ 379 (0x0001f120 + 0x4000 * (ee)) 380 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ 381 GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) 382 #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ 383 (0x0001f128 + 0x4000 * (ee)) 384 /* Values here are bit positions in the (general) GSI_IRQ_* registers */ 385 enum gsi_general_id { 386 BREAK_POINT = 0x0, 387 BUS_ERROR = 0x1, 388 CMD_FIFO_OVRFLOW = 0x2, 389 MCS_STACK_OVRFLOW = 0x3, 390 }; 391 392 #define GSI_CNTXT_INTSET_OFFSET \ 393 GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) 394 #define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \ 395 (0x0001f180 + 0x4000 * (ee)) 396 #define INTYPE_FMASK GENMASK(0, 0) 397 398 #define GSI_ERROR_LOG_OFFSET \ 399 GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP) 400 #define GSI_EE_N_ERROR_LOG_OFFSET(ee) \ 401 (0x0001f200 + 0x4000 * (ee)) 402 #define ERR_ARG3_FMASK GENMASK(3, 0) 403 #define ERR_ARG2_FMASK GENMASK(7, 4) 404 #define ERR_ARG1_FMASK GENMASK(11, 8) 405 #define ERR_CODE_FMASK GENMASK(15, 12) 406 #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) 407 #define ERR_TYPE_FMASK GENMASK(27, 24) 408 #define ERR_EE_FMASK GENMASK(31, 28) 409 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ 410 enum gsi_err_code { 411 GSI_INVALID_TRE = 0x1, 412 GSI_OUT_OF_BUFFERS = 0x2, 413 GSI_OUT_OF_RESOURCES = 0x3, 414 GSI_UNSUPPORTED_INTER_EE_OP = 0x4, 415 GSI_EVT_RING_EMPTY = 0x5, 416 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, 417 /* 7 is not assigned */ 418 GSI_HWO_1 = 0x8, 419 }; 420 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ 421 enum gsi_err_type { 422 GSI_ERR_TYPE_GLOB = 0x1, 423 GSI_ERR_TYPE_CHAN = 0x2, 424 GSI_ERR_TYPE_EVT = 0x3, 425 }; 426 427 #define GSI_ERROR_LOG_CLR_OFFSET \ 428 GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP) 429 #define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \ 430 (0x0001f210 + 0x4000 * (ee)) 431 432 #define GSI_CNTXT_SCRATCH_0_OFFSET \ 433 GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP) 434 #define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \ 435 (0x0001f400 + 0x4000 * (ee)) 436 #define INTER_EE_RESULT_FMASK GENMASK(2, 0) 437 #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) 438 enum gsi_generic_ee_result { 439 GENERIC_EE_SUCCESS = 0x1, 440 GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2, 441 GENERIC_EE_INCORRECT_DIRECTION = 0x3, 442 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, 443 GENERIC_EE_INCORRECT_CHANNEL = 0x5, 444 GENERIC_EE_RETRY = 0x6, 445 GENERIC_EE_NO_RESOURCES = 0x7, 446 }; 447 #define USB_MAX_PACKET_FMASK GENMASK(15, 15) /* 0: HS; 1: SS */ 448 #define MHI_BASE_CHANNEL_FMASK GENMASK(31, 24) 449 450 #endif /* _GSI_REG_H_ */ 451