1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2021 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 /* GSI EE registers as a group are shifted downward by a fixed constant amount 42 * for IPA versions 4.5 and beyond. This applies to all GSI registers we use 43 * *except* the ones that disable inter-EE interrupts for channels and event 44 * channels. 45 * 46 * The "raw" (not adjusted) GSI register range is mapped, and a pointer to 47 * the mapped range is held in gsi->virt_raw. The inter-EE interrupt 48 * registers are accessed using that pointer. 49 * 50 * Most registers are accessed using gsi->virt, which is a copy of the "raw" 51 * pointer, adjusted downward by the fixed amount. 52 */ 53 #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */ 54 55 /* The two inter-EE IRQ register offsets are relative to gsi->virt_raw */ 56 #define GSI_INTER_EE_SRC_CH_IRQ_OFFSET \ 57 GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 58 #define GSI_INTER_EE_N_SRC_CH_IRQ_OFFSET(ee) \ 59 (0x0000c018 + 0x1000 * (ee)) 60 61 #define GSI_INTER_EE_SRC_EV_CH_IRQ_OFFSET \ 62 GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 63 #define GSI_INTER_EE_N_SRC_EV_CH_IRQ_OFFSET(ee) \ 64 (0x0000c01c + 0x1000 * (ee)) 65 66 /* All other register offsets are relative to gsi->virt */ 67 68 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ 69 enum gsi_channel_type { 70 GSI_CHANNEL_TYPE_MHI = 0x0, 71 GSI_CHANNEL_TYPE_XHCI = 0x1, 72 GSI_CHANNEL_TYPE_GPI = 0x2, 73 GSI_CHANNEL_TYPE_XDCI = 0x3, 74 GSI_CHANNEL_TYPE_WDI2 = 0x4, 75 GSI_CHANNEL_TYPE_GCI = 0x5, 76 GSI_CHANNEL_TYPE_WDI3 = 0x6, 77 GSI_CHANNEL_TYPE_MHIP = 0x7, 78 GSI_CHANNEL_TYPE_AQC = 0x8, 79 GSI_CHANNEL_TYPE_11AD = 0x9, 80 }; 81 82 #define GSI_CH_C_CNTXT_0_OFFSET(ch) \ 83 GSI_EE_N_CH_C_CNTXT_0_OFFSET((ch), GSI_EE_AP) 84 #define GSI_EE_N_CH_C_CNTXT_0_OFFSET(ch, ee) \ 85 (0x0001c000 + 0x4000 * (ee) + 0x80 * (ch)) 86 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0) 87 #define CHTYPE_DIR_FMASK GENMASK(3, 3) 88 #define EE_FMASK GENMASK(7, 4) 89 #define CHID_FMASK GENMASK(12, 8) 90 /* The next field is present for IPA v4.5 and above */ 91 #define CHTYPE_PROTOCOL_MSB_FMASK GENMASK(13, 13) 92 #define ERINDEX_FMASK GENMASK(18, 14) 93 #define CHSTATE_FMASK GENMASK(23, 20) 94 #define ELEMENT_SIZE_FMASK GENMASK(31, 24) 95 96 /* Encoded value for CH_C_CNTXT_0 register channel protocol fields */ 97 static inline u32 98 chtype_protocol_encoded(enum ipa_version version, enum gsi_channel_type type) 99 { 100 u32 val; 101 102 val = u32_encode_bits(type, CHTYPE_PROTOCOL_FMASK); 103 if (version < IPA_VERSION_4_5) 104 return val; 105 106 /* Encode upper bit(s) as well */ 107 type >>= hweight32(CHTYPE_PROTOCOL_FMASK); 108 val |= u32_encode_bits(type, CHTYPE_PROTOCOL_MSB_FMASK); 109 110 return val; 111 } 112 113 #define GSI_CH_C_CNTXT_1_OFFSET(ch) \ 114 GSI_EE_N_CH_C_CNTXT_1_OFFSET((ch), GSI_EE_AP) 115 #define GSI_EE_N_CH_C_CNTXT_1_OFFSET(ch, ee) \ 116 (0x0001c004 + 0x4000 * (ee) + 0x80 * (ch)) 117 118 /* Encoded value for CH_C_CNTXT_1 register R_LENGTH field */ 119 static inline u32 r_length_encoded(enum ipa_version version, u32 length) 120 { 121 if (version < IPA_VERSION_4_9) 122 return u32_encode_bits(length, GENMASK(15, 0)); 123 return u32_encode_bits(length, GENMASK(19, 0)); 124 } 125 126 #define GSI_CH_C_CNTXT_2_OFFSET(ch) \ 127 GSI_EE_N_CH_C_CNTXT_2_OFFSET((ch), GSI_EE_AP) 128 #define GSI_EE_N_CH_C_CNTXT_2_OFFSET(ch, ee) \ 129 (0x0001c008 + 0x4000 * (ee) + 0x80 * (ch)) 130 131 #define GSI_CH_C_CNTXT_3_OFFSET(ch) \ 132 GSI_EE_N_CH_C_CNTXT_3_OFFSET((ch), GSI_EE_AP) 133 #define GSI_EE_N_CH_C_CNTXT_3_OFFSET(ch, ee) \ 134 (0x0001c00c + 0x4000 * (ee) + 0x80 * (ch)) 135 136 #define GSI_CH_C_QOS_OFFSET(ch) \ 137 GSI_EE_N_CH_C_QOS_OFFSET((ch), GSI_EE_AP) 138 #define GSI_EE_N_CH_C_QOS_OFFSET(ch, ee) \ 139 (0x0001c05c + 0x4000 * (ee) + 0x80 * (ch)) 140 #define WRR_WEIGHT_FMASK GENMASK(3, 0) 141 #define MAX_PREFETCH_FMASK GENMASK(8, 8) 142 #define USE_DB_ENG_FMASK GENMASK(9, 9) 143 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */ 144 #define USE_ESCAPE_BUF_ONLY_FMASK GENMASK(10, 10) 145 /* The next two fields are present for IPA v4.5 and above */ 146 #define PREFETCH_MODE_FMASK GENMASK(13, 10) 147 #define EMPTY_LVL_THRSHOLD_FMASK GENMASK(23, 16) 148 /* The next field is present for IPA v4.9 and above */ 149 #define DB_IN_BYTES GENMASK(24, 24) 150 151 /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */ 152 enum gsi_prefetch_mode { 153 GSI_USE_PREFETCH_BUFS = 0x0, 154 GSI_ESCAPE_BUF_ONLY = 0x1, 155 GSI_SMART_PREFETCH = 0x2, 156 GSI_FREE_PREFETCH = 0x3, 157 }; 158 159 #define GSI_CH_C_SCRATCH_0_OFFSET(ch) \ 160 GSI_EE_N_CH_C_SCRATCH_0_OFFSET((ch), GSI_EE_AP) 161 #define GSI_EE_N_CH_C_SCRATCH_0_OFFSET(ch, ee) \ 162 (0x0001c060 + 0x4000 * (ee) + 0x80 * (ch)) 163 164 #define GSI_CH_C_SCRATCH_1_OFFSET(ch) \ 165 GSI_EE_N_CH_C_SCRATCH_1_OFFSET((ch), GSI_EE_AP) 166 #define GSI_EE_N_CH_C_SCRATCH_1_OFFSET(ch, ee) \ 167 (0x0001c064 + 0x4000 * (ee) + 0x80 * (ch)) 168 169 #define GSI_CH_C_SCRATCH_2_OFFSET(ch) \ 170 GSI_EE_N_CH_C_SCRATCH_2_OFFSET((ch), GSI_EE_AP) 171 #define GSI_EE_N_CH_C_SCRATCH_2_OFFSET(ch, ee) \ 172 (0x0001c068 + 0x4000 * (ee) + 0x80 * (ch)) 173 174 #define GSI_CH_C_SCRATCH_3_OFFSET(ch) \ 175 GSI_EE_N_CH_C_SCRATCH_3_OFFSET((ch), GSI_EE_AP) 176 #define GSI_EE_N_CH_C_SCRATCH_3_OFFSET(ch, ee) \ 177 (0x0001c06c + 0x4000 * (ee) + 0x80 * (ch)) 178 179 #define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \ 180 GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET((ev), GSI_EE_AP) 181 #define GSI_EE_N_EV_CH_E_CNTXT_0_OFFSET(ev, ee) \ 182 (0x0001d000 + 0x4000 * (ee) + 0x80 * (ev)) 183 /* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */ 184 #define EV_CHTYPE_FMASK GENMASK(3, 0) 185 #define EV_EE_FMASK GENMASK(7, 4) 186 #define EV_EVCHID_FMASK GENMASK(15, 8) 187 #define EV_INTYPE_FMASK GENMASK(16, 16) 188 #define EV_CHSTATE_FMASK GENMASK(23, 20) 189 #define EV_ELEMENT_SIZE_FMASK GENMASK(31, 24) 190 191 #define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \ 192 GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET((ev), GSI_EE_AP) 193 #define GSI_EE_N_EV_CH_E_CNTXT_1_OFFSET(ev, ee) \ 194 (0x0001d004 + 0x4000 * (ee) + 0x80 * (ev)) 195 /* Encoded value for EV_CH_C_CNTXT_1 register EV_R_LENGTH field */ 196 static inline u32 ev_r_length_encoded(enum ipa_version version, u32 length) 197 { 198 if (version < IPA_VERSION_4_9) 199 return u32_encode_bits(length, GENMASK(15, 0)); 200 return u32_encode_bits(length, GENMASK(19, 0)); 201 } 202 203 #define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \ 204 GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET((ev), GSI_EE_AP) 205 #define GSI_EE_N_EV_CH_E_CNTXT_2_OFFSET(ev, ee) \ 206 (0x0001d008 + 0x4000 * (ee) + 0x80 * (ev)) 207 208 #define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \ 209 GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET((ev), GSI_EE_AP) 210 #define GSI_EE_N_EV_CH_E_CNTXT_3_OFFSET(ev, ee) \ 211 (0x0001d00c + 0x4000 * (ee) + 0x80 * (ev)) 212 213 #define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \ 214 GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET((ev), GSI_EE_AP) 215 #define GSI_EE_N_EV_CH_E_CNTXT_4_OFFSET(ev, ee) \ 216 (0x0001d010 + 0x4000 * (ee) + 0x80 * (ev)) 217 218 #define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \ 219 GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET((ev), GSI_EE_AP) 220 #define GSI_EE_N_EV_CH_E_CNTXT_8_OFFSET(ev, ee) \ 221 (0x0001d020 + 0x4000 * (ee) + 0x80 * (ev)) 222 #define MODT_FMASK GENMASK(15, 0) 223 #define MODC_FMASK GENMASK(23, 16) 224 #define MOD_CNT_FMASK GENMASK(31, 24) 225 226 #define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \ 227 GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET((ev), GSI_EE_AP) 228 #define GSI_EE_N_EV_CH_E_CNTXT_9_OFFSET(ev, ee) \ 229 (0x0001d024 + 0x4000 * (ee) + 0x80 * (ev)) 230 231 #define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \ 232 GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET((ev), GSI_EE_AP) 233 #define GSI_EE_N_EV_CH_E_CNTXT_10_OFFSET(ev, ee) \ 234 (0x0001d028 + 0x4000 * (ee) + 0x80 * (ev)) 235 236 #define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \ 237 GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET((ev), GSI_EE_AP) 238 #define GSI_EE_N_EV_CH_E_CNTXT_11_OFFSET(ev, ee) \ 239 (0x0001d02c + 0x4000 * (ee) + 0x80 * (ev)) 240 241 #define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \ 242 GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET((ev), GSI_EE_AP) 243 #define GSI_EE_N_EV_CH_E_CNTXT_12_OFFSET(ev, ee) \ 244 (0x0001d030 + 0x4000 * (ee) + 0x80 * (ev)) 245 246 #define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \ 247 GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET((ev), GSI_EE_AP) 248 #define GSI_EE_N_EV_CH_E_CNTXT_13_OFFSET(ev, ee) \ 249 (0x0001d034 + 0x4000 * (ee) + 0x80 * (ev)) 250 251 #define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \ 252 GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET((ev), GSI_EE_AP) 253 #define GSI_EE_N_EV_CH_E_SCRATCH_0_OFFSET(ev, ee) \ 254 (0x0001d048 + 0x4000 * (ee) + 0x80 * (ev)) 255 256 #define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \ 257 GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET((ev), GSI_EE_AP) 258 #define GSI_EE_N_EV_CH_E_SCRATCH_1_OFFSET(ev, ee) \ 259 (0x0001d04c + 0x4000 * (ee) + 0x80 * (ev)) 260 261 #define GSI_CH_C_DOORBELL_0_OFFSET(ch) \ 262 GSI_EE_N_CH_C_DOORBELL_0_OFFSET((ch), GSI_EE_AP) 263 #define GSI_EE_N_CH_C_DOORBELL_0_OFFSET(ch, ee) \ 264 (0x0001e000 + 0x4000 * (ee) + 0x08 * (ch)) 265 266 #define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \ 267 GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET((ev), GSI_EE_AP) 268 #define GSI_EE_N_EV_CH_E_DOORBELL_0_OFFSET(ev, ee) \ 269 (0x0001e100 + 0x4000 * (ee) + 0x08 * (ev)) 270 271 #define GSI_GSI_STATUS_OFFSET \ 272 GSI_EE_N_GSI_STATUS_OFFSET(GSI_EE_AP) 273 #define GSI_EE_N_GSI_STATUS_OFFSET(ee) \ 274 (0x0001f000 + 0x4000 * (ee)) 275 #define ENABLED_FMASK GENMASK(0, 0) 276 277 #define GSI_CH_CMD_OFFSET \ 278 GSI_EE_N_CH_CMD_OFFSET(GSI_EE_AP) 279 #define GSI_EE_N_CH_CMD_OFFSET(ee) \ 280 (0x0001f008 + 0x4000 * (ee)) 281 #define CH_CHID_FMASK GENMASK(7, 0) 282 #define CH_OPCODE_FMASK GENMASK(31, 24) 283 284 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ 285 enum gsi_ch_cmd_opcode { 286 GSI_CH_ALLOCATE = 0x0, 287 GSI_CH_START = 0x1, 288 GSI_CH_STOP = 0x2, 289 GSI_CH_RESET = 0x9, 290 GSI_CH_DE_ALLOC = 0xa, 291 GSI_CH_DB_STOP = 0xb, 292 }; 293 294 #define GSI_EV_CH_CMD_OFFSET \ 295 GSI_EE_N_EV_CH_CMD_OFFSET(GSI_EE_AP) 296 #define GSI_EE_N_EV_CH_CMD_OFFSET(ee) \ 297 (0x0001f010 + 0x4000 * (ee)) 298 #define EV_CHID_FMASK GENMASK(7, 0) 299 #define EV_OPCODE_FMASK GENMASK(31, 24) 300 301 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ 302 enum gsi_evt_cmd_opcode { 303 GSI_EVT_ALLOCATE = 0x0, 304 GSI_EVT_RESET = 0x9, 305 GSI_EVT_DE_ALLOC = 0xa, 306 }; 307 308 #define GSI_GENERIC_CMD_OFFSET \ 309 GSI_EE_N_GENERIC_CMD_OFFSET(GSI_EE_AP) 310 #define GSI_EE_N_GENERIC_CMD_OFFSET(ee) \ 311 (0x0001f018 + 0x4000 * (ee)) 312 #define GENERIC_OPCODE_FMASK GENMASK(4, 0) 313 #define GENERIC_CHID_FMASK GENMASK(9, 5) 314 #define GENERIC_EE_FMASK GENMASK(13, 10) 315 316 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ 317 enum gsi_generic_cmd_opcode { 318 GSI_GENERIC_HALT_CHANNEL = 0x1, 319 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 320 }; 321 322 /* The next register is present for IPA v3.5.1 and above */ 323 #define GSI_GSI_HW_PARAM_2_OFFSET \ 324 GSI_EE_N_GSI_HW_PARAM_2_OFFSET(GSI_EE_AP) 325 #define GSI_EE_N_GSI_HW_PARAM_2_OFFSET(ee) \ 326 (0x0001f040 + 0x4000 * (ee)) 327 #define IRAM_SIZE_FMASK GENMASK(2, 0) 328 #define NUM_CH_PER_EE_FMASK GENMASK(7, 3) 329 #define NUM_EV_PER_EE_FMASK GENMASK(12, 8) 330 #define GSI_CH_PEND_TRANSLATE_FMASK GENMASK(13, 13) 331 #define GSI_CH_FULL_LOGIC_FMASK GENMASK(14, 14) 332 /* Fields below are present for IPA v4.0 and above */ 333 #define GSI_USE_SDMA_FMASK GENMASK(15, 15) 334 #define GSI_SDMA_N_INT_FMASK GENMASK(18, 16) 335 #define GSI_SDMA_MAX_BURST_FMASK GENMASK(26, 19) 336 #define GSI_SDMA_N_IOVEC_FMASK GENMASK(29, 27) 337 /* Fields below are present for IPA v4.2 and above */ 338 #define GSI_USE_RD_WR_ENG_FMASK GENMASK(30, 30) 339 #define GSI_USE_INTER_EE_FMASK GENMASK(31, 31) 340 341 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ 342 enum gsi_iram_size { 343 IRAM_SIZE_ONE_KB = 0x0, 344 IRAM_SIZE_TWO_KB = 0x1, 345 /* The next two values are available for IPA v4.0 and above */ 346 IRAM_SIZE_TWO_N_HALF_KB = 0x2, 347 IRAM_SIZE_THREE_KB = 0x3, 348 /* The next two values are available for IPA v4.5 and above */ 349 IRAM_SIZE_THREE_N_HALF_KB = 0x4, 350 IRAM_SIZE_FOUR_KB = 0x5, 351 }; 352 353 /* IRQ condition for each type is cleared by writing type-specific register */ 354 #define GSI_CNTXT_TYPE_IRQ_OFFSET \ 355 GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP) 356 #define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \ 357 (0x0001f080 + 0x4000 * (ee)) 358 #define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \ 359 GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP) 360 #define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \ 361 (0x0001f088 + 0x4000 * (ee)) 362 363 /* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */ 364 enum gsi_irq_type_id { 365 GSI_CH_CTRL = 0x0, /* channel allocation, etc. */ 366 GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */ 367 GSI_GLOB_EE = 0x2, /* global/general event */ 368 GSI_IEOB = 0x3, /* TRE completion */ 369 GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */ 370 GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */ 371 GSI_GENERAL = 0x6, /* general-purpose event */ 372 }; 373 374 #define GSI_CNTXT_SRC_CH_IRQ_OFFSET \ 375 GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP) 376 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(ee) \ 377 (0x0001f090 + 0x4000 * (ee)) 378 379 #define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \ 380 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(GSI_EE_AP) 381 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_OFFSET(ee) \ 382 (0x0001f094 + 0x4000 * (ee)) 383 384 #define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \ 385 GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 386 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_MSK_OFFSET(ee) \ 387 (0x0001f098 + 0x4000 * (ee)) 388 389 #define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \ 390 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(GSI_EE_AP) 391 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET(ee) \ 392 (0x0001f09c + 0x4000 * (ee)) 393 394 #define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \ 395 GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 396 #define GSI_EE_N_CNTXT_SRC_CH_IRQ_CLR_OFFSET(ee) \ 397 (0x0001f0a0 + 0x4000 * (ee)) 398 399 #define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \ 400 GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(GSI_EE_AP) 401 #define GSI_EE_N_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET(ee) \ 402 (0x0001f0a4 + 0x4000 * (ee)) 403 404 #define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \ 405 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(GSI_EE_AP) 406 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_OFFSET(ee) \ 407 (0x0001f0b0 + 0x4000 * (ee)) 408 409 #define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \ 410 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(GSI_EE_AP) 411 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET(ee) \ 412 (0x0001f0b8 + 0x4000 * (ee)) 413 414 #define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \ 415 GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(GSI_EE_AP) 416 #define GSI_EE_N_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET(ee) \ 417 (0x0001f0c0 + 0x4000 * (ee)) 418 419 #define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \ 420 GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(GSI_EE_AP) 421 #define GSI_EE_N_CNTXT_GLOB_IRQ_STTS_OFFSET(ee) \ 422 (0x0001f100 + 0x4000 * (ee)) 423 #define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \ 424 GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(GSI_EE_AP) 425 #define GSI_EE_N_CNTXT_GLOB_IRQ_EN_OFFSET(ee) \ 426 (0x0001f108 + 0x4000 * (ee)) 427 #define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \ 428 GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(GSI_EE_AP) 429 #define GSI_EE_N_CNTXT_GLOB_IRQ_CLR_OFFSET(ee) \ 430 (0x0001f110 + 0x4000 * (ee)) 431 /* Values here are bit positions in the GLOB_IRQ_* registers */ 432 enum gsi_global_irq_id { 433 ERROR_INT = 0x0, 434 GP_INT1 = 0x1, 435 GP_INT2 = 0x2, 436 GP_INT3 = 0x3, 437 }; 438 439 #define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \ 440 GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(GSI_EE_AP) 441 #define GSI_EE_N_CNTXT_GSI_IRQ_STTS_OFFSET(ee) \ 442 (0x0001f118 + 0x4000 * (ee)) 443 #define GSI_CNTXT_GSI_IRQ_EN_OFFSET \ 444 GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(GSI_EE_AP) 445 #define GSI_EE_N_CNTXT_GSI_IRQ_EN_OFFSET(ee) \ 446 (0x0001f120 + 0x4000 * (ee)) 447 #define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \ 448 GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(GSI_EE_AP) 449 #define GSI_EE_N_CNTXT_GSI_IRQ_CLR_OFFSET(ee) \ 450 (0x0001f128 + 0x4000 * (ee)) 451 /* Values here are bit positions in the (general) GSI_IRQ_* registers */ 452 enum gsi_general_id { 453 BREAK_POINT = 0x0, 454 BUS_ERROR = 0x1, 455 CMD_FIFO_OVRFLOW = 0x2, 456 MCS_STACK_OVRFLOW = 0x3, 457 }; 458 459 #define GSI_CNTXT_INTSET_OFFSET \ 460 GSI_EE_N_CNTXT_INTSET_OFFSET(GSI_EE_AP) 461 #define GSI_EE_N_CNTXT_INTSET_OFFSET(ee) \ 462 (0x0001f180 + 0x4000 * (ee)) 463 #define INTYPE_FMASK GENMASK(0, 0) 464 465 #define GSI_ERROR_LOG_OFFSET \ 466 GSI_EE_N_ERROR_LOG_OFFSET(GSI_EE_AP) 467 #define GSI_EE_N_ERROR_LOG_OFFSET(ee) \ 468 (0x0001f200 + 0x4000 * (ee)) 469 470 /* Fields below are present for IPA v3.5.1 and above */ 471 #define ERR_ARG3_FMASK GENMASK(3, 0) 472 #define ERR_ARG2_FMASK GENMASK(7, 4) 473 #define ERR_ARG1_FMASK GENMASK(11, 8) 474 #define ERR_CODE_FMASK GENMASK(15, 12) 475 #define ERR_VIRT_IDX_FMASK GENMASK(23, 19) 476 #define ERR_TYPE_FMASK GENMASK(27, 24) 477 #define ERR_EE_FMASK GENMASK(31, 28) 478 479 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ 480 enum gsi_err_code { 481 GSI_INVALID_TRE = 0x1, 482 GSI_OUT_OF_BUFFERS = 0x2, 483 GSI_OUT_OF_RESOURCES = 0x3, 484 GSI_UNSUPPORTED_INTER_EE_OP = 0x4, 485 GSI_EVT_RING_EMPTY = 0x5, 486 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, 487 /* 7 is not assigned */ 488 GSI_HWO_1 = 0x8, 489 }; 490 491 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ 492 enum gsi_err_type { 493 GSI_ERR_TYPE_GLOB = 0x1, 494 GSI_ERR_TYPE_CHAN = 0x2, 495 GSI_ERR_TYPE_EVT = 0x3, 496 }; 497 498 #define GSI_ERROR_LOG_CLR_OFFSET \ 499 GSI_EE_N_ERROR_LOG_CLR_OFFSET(GSI_EE_AP) 500 #define GSI_EE_N_ERROR_LOG_CLR_OFFSET(ee) \ 501 (0x0001f210 + 0x4000 * (ee)) 502 503 #define GSI_CNTXT_SCRATCH_0_OFFSET \ 504 GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(GSI_EE_AP) 505 #define GSI_EE_N_CNTXT_SCRATCH_0_OFFSET(ee) \ 506 (0x0001f400 + 0x4000 * (ee)) 507 #define INTER_EE_RESULT_FMASK GENMASK(2, 0) 508 #define GENERIC_EE_RESULT_FMASK GENMASK(7, 5) 509 510 /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ 511 enum gsi_generic_ee_result { 512 GENERIC_EE_SUCCESS = 0x1, 513 GENERIC_EE_CHANNEL_NOT_RUNNING = 0x2, 514 GENERIC_EE_INCORRECT_DIRECTION = 0x3, 515 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, 516 GENERIC_EE_INCORRECT_CHANNEL = 0x5, 517 GENERIC_EE_RETRY = 0x6, 518 GENERIC_EE_NO_RESOURCES = 0x7, 519 }; 520 521 #endif /* _GSI_REG_H_ */ 522