1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2018-2023 Linaro Ltd. 5 */ 6 #ifndef _GSI_REG_H_ 7 #define _GSI_REG_H_ 8 9 /* === Only "gsi.c" and "gsi_reg.c" should include this file === */ 10 11 #include <linux/bits.h> 12 13 /** 14 * DOC: GSI Registers 15 * 16 * GSI registers are located within the "gsi" address space defined by Device 17 * Tree. The offset of each register within that space is specified by 18 * symbols defined below. The GSI address space is mapped to virtual memory 19 * space in gsi_init(). All GSI registers are 32 bits wide. 20 * 21 * Each register type is duplicated for a number of instances of something. 22 * For example, each GSI channel has its own set of registers defining its 23 * configuration. The offset to a channel's set of registers is computed 24 * based on a "base" offset plus an additional "stride" amount computed 25 * from the channel's ID. For such registers, the offset is computed by a 26 * function-like macro that takes a parameter used in the computation. 27 * 28 * The offset of a register dependent on execution environment is computed 29 * by a macro that is supplied a parameter "ee". The "ee" value is a member 30 * of the gsi_ee_id enumerated type. 31 * 32 * The offset of a channel register is computed by a macro that is supplied a 33 * parameter "ch". The "ch" value is a channel id whose maximum value is 30 34 * (though the actual limit is hardware-dependent). 35 * 36 * The offset of an event register is computed by a macro that is supplied a 37 * parameter "ev". The "ev" value is an event id whose maximum value is 15 38 * (though the actual limit is hardware-dependent). 39 */ 40 41 /* enum gsi_reg_id - GSI register IDs */ 42 enum gsi_reg_id { 43 INTER_EE_SRC_CH_IRQ_MSK, /* IPA v3.5+ */ 44 INTER_EE_SRC_EV_CH_IRQ_MSK, /* IPA v3.5+ */ 45 CH_C_CNTXT_0, 46 CH_C_CNTXT_1, 47 CH_C_CNTXT_2, 48 CH_C_CNTXT_3, 49 CH_C_QOS, 50 CH_C_SCRATCH_0, 51 CH_C_SCRATCH_1, 52 CH_C_SCRATCH_2, 53 CH_C_SCRATCH_3, 54 EV_CH_E_CNTXT_0, 55 EV_CH_E_CNTXT_1, 56 EV_CH_E_CNTXT_2, 57 EV_CH_E_CNTXT_3, 58 EV_CH_E_CNTXT_4, 59 EV_CH_E_CNTXT_8, 60 EV_CH_E_CNTXT_9, 61 EV_CH_E_CNTXT_10, 62 EV_CH_E_CNTXT_11, 63 EV_CH_E_CNTXT_12, 64 EV_CH_E_CNTXT_13, 65 EV_CH_E_SCRATCH_0, 66 EV_CH_E_SCRATCH_1, 67 CH_C_DOORBELL_0, 68 EV_CH_E_DOORBELL_0, 69 GSI_STATUS, 70 CH_CMD, 71 EV_CH_CMD, 72 GENERIC_CMD, 73 HW_PARAM_2, /* IPA v3.5.1+ */ 74 CNTXT_TYPE_IRQ, 75 CNTXT_TYPE_IRQ_MSK, 76 CNTXT_SRC_CH_IRQ, 77 CNTXT_SRC_CH_IRQ_MSK, 78 CNTXT_SRC_CH_IRQ_CLR, 79 CNTXT_SRC_EV_CH_IRQ, 80 CNTXT_SRC_EV_CH_IRQ_MSK, 81 CNTXT_SRC_EV_CH_IRQ_CLR, 82 CNTXT_SRC_IEOB_IRQ, 83 CNTXT_SRC_IEOB_IRQ_MSK, 84 CNTXT_SRC_IEOB_IRQ_CLR, 85 CNTXT_GLOB_IRQ_STTS, 86 CNTXT_GLOB_IRQ_EN, 87 CNTXT_GLOB_IRQ_CLR, 88 CNTXT_GSI_IRQ_STTS, 89 CNTXT_GSI_IRQ_EN, 90 CNTXT_GSI_IRQ_CLR, 91 CNTXT_INTSET, 92 ERROR_LOG, 93 ERROR_LOG_CLR, 94 CNTXT_SCRATCH_0, 95 GSI_REG_ID_COUNT, /* Last; not an ID */ 96 }; 97 98 /* CH_C_CNTXT_0 register */ 99 enum gsi_reg_ch_c_cntxt_0_field_id { 100 CHTYPE_PROTOCOL, 101 CHTYPE_DIR, 102 CH_EE, 103 CHID, 104 CHTYPE_PROTOCOL_MSB, /* IPA v4.9+ */ 105 ERINDEX, 106 CHSTATE, 107 ELEMENT_SIZE, 108 }; 109 110 /** enum gsi_channel_type - CHTYPE_PROTOCOL field values in CH_C_CNTXT_0 */ 111 enum gsi_channel_type { 112 GSI_CHANNEL_TYPE_MHI = 0x0, 113 GSI_CHANNEL_TYPE_XHCI = 0x1, 114 GSI_CHANNEL_TYPE_GPI = 0x2, 115 GSI_CHANNEL_TYPE_XDCI = 0x3, 116 GSI_CHANNEL_TYPE_WDI2 = 0x4, 117 GSI_CHANNEL_TYPE_GCI = 0x5, 118 GSI_CHANNEL_TYPE_WDI3 = 0x6, 119 GSI_CHANNEL_TYPE_MHIP = 0x7, 120 GSI_CHANNEL_TYPE_AQC = 0x8, 121 GSI_CHANNEL_TYPE_11AD = 0x9, 122 }; 123 124 /* CH_C_CNTXT_1 register */ 125 enum gsi_reg_ch_c_cntxt_1_field_id { 126 CH_R_LENGTH, 127 }; 128 129 /* CH_C_QOS register */ 130 enum gsi_reg_ch_c_qos_field_id { 131 WRR_WEIGHT, 132 MAX_PREFETCH, 133 USE_DB_ENG, 134 USE_ESCAPE_BUF_ONLY, /* IPA v4.0-4.2 */ 135 PREFETCH_MODE, /* IPA v4.5+ */ 136 EMPTY_LVL_THRSHOLD, /* IPA v4.5+ */ 137 DB_IN_BYTES, /* IPA v4.9+ */ 138 }; 139 140 /** enum gsi_prefetch_mode - PREFETCH_MODE field in CH_C_QOS */ 141 enum gsi_prefetch_mode { 142 USE_PREFETCH_BUFS = 0, 143 ESCAPE_BUF_ONLY = 1, 144 SMART_PREFETCH = 2, 145 FREE_PREFETCH = 3, 146 }; 147 148 /* EV_CH_E_CNTXT_0 register */ 149 enum gsi_reg_ch_c_ev_ch_e_cntxt_0_field_id { 150 EV_CHTYPE, /* enum gsi_channel_type */ 151 EV_EE, /* enum gsi_ee_id; always GSI_EE_AP for us */ 152 EV_EVCHID, 153 EV_INTYPE, 154 EV_CHSTATE, 155 EV_ELEMENT_SIZE, 156 }; 157 158 /* EV_CH_E_CNTXT_8 register */ 159 enum gsi_reg_ch_c_ev_ch_e_cntxt_8_field_id { 160 EV_MODT, 161 EV_MODC, 162 EV_MOD_CNT, 163 }; 164 165 /* GSI_STATUS register */ 166 enum gsi_reg_gsi_status_field_id { 167 ENABLED, 168 }; 169 170 /* CH_CMD register */ 171 enum gsi_reg_gsi_ch_cmd_field_id { 172 CH_CHID, 173 CH_OPCODE, 174 }; 175 176 /** enum gsi_ch_cmd_opcode - CH_OPCODE field values in CH_CMD */ 177 enum gsi_ch_cmd_opcode { 178 GSI_CH_ALLOCATE = 0x0, 179 GSI_CH_START = 0x1, 180 GSI_CH_STOP = 0x2, 181 GSI_CH_RESET = 0x9, 182 GSI_CH_DE_ALLOC = 0xa, 183 GSI_CH_DB_STOP = 0xb, 184 }; 185 186 /* EV_CH_CMD register */ 187 enum gsi_ev_ch_cmd_field_id { 188 EV_CHID, 189 EV_OPCODE, 190 }; 191 192 /** enum gsi_evt_cmd_opcode - EV_OPCODE field values in EV_CH_CMD */ 193 enum gsi_evt_cmd_opcode { 194 GSI_EVT_ALLOCATE = 0x0, 195 GSI_EVT_RESET = 0x9, 196 GSI_EVT_DE_ALLOC = 0xa, 197 }; 198 199 /* GENERIC_CMD register */ 200 enum gsi_generic_cmd_field_id { 201 GENERIC_OPCODE, 202 GENERIC_CHID, 203 GENERIC_EE, 204 GENERIC_PARAMS, /* IPA v4.11+ */ 205 }; 206 207 /** enum gsi_generic_cmd_opcode - GENERIC_OPCODE field values in GENERIC_CMD */ 208 enum gsi_generic_cmd_opcode { 209 GSI_GENERIC_HALT_CHANNEL = 0x1, 210 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2, 211 GSI_GENERIC_ENABLE_FLOW_CONTROL = 0x3, /* IPA v4.2+ */ 212 GSI_GENERIC_DISABLE_FLOW_CONTROL = 0x4, /* IPA v4.2+ */ 213 GSI_GENERIC_QUERY_FLOW_CONTROL = 0x5, /* IPA v4.11+ */ 214 }; 215 216 /* HW_PARAM_2 register */ /* IPA v3.5.1+ */ 217 enum gsi_hw_param_2_field_id { 218 IRAM_SIZE, 219 NUM_CH_PER_EE, 220 NUM_EV_PER_EE, 221 GSI_CH_PEND_TRANSLATE, 222 GSI_CH_FULL_LOGIC, 223 GSI_USE_SDMA, /* IPA v4.0+ */ 224 GSI_SDMA_N_INT, /* IPA v4.0+ */ 225 GSI_SDMA_MAX_BURST, /* IPA v4.0+ */ 226 GSI_SDMA_N_IOVEC, /* IPA v4.0+ */ 227 GSI_USE_RD_WR_ENG, /* IPA v4.2+ */ 228 GSI_USE_INTER_EE, /* IPA v4.2+ */ 229 }; 230 231 /** enum gsi_iram_size - IRAM_SIZE field values in HW_PARAM_2 */ 232 enum gsi_iram_size { 233 IRAM_SIZE_ONE_KB = 0x0, 234 IRAM_SIZE_TWO_KB = 0x1, 235 /* The next two values are available for IPA v4.0 and above */ 236 IRAM_SIZE_TWO_N_HALF_KB = 0x2, 237 IRAM_SIZE_THREE_KB = 0x3, 238 /* The next two values are available for IPA v4.5 and above */ 239 IRAM_SIZE_THREE_N_HALF_KB = 0x4, 240 IRAM_SIZE_FOUR_KB = 0x5, 241 }; 242 243 /** 244 * enum gsi_irq_type_id: GSI IRQ types 245 * @GSI_CH_CTRL: Channel allocation, deallocation, etc. 246 * @GSI_EV_CTRL: Event ring allocation, deallocation, etc. 247 * @GSI_GLOB_EE: Global/general event 248 * @GSI_IEOB: Transfer (TRE) completion 249 * @GSI_INTER_EE_CH_CTRL: Remote-issued stop/reset (unused) 250 * @GSI_INTER_EE_EV_CTRL: Remote-issued event reset (unused) 251 * @GSI_GENERAL: General hardware event (bus error, etc.) 252 */ 253 enum gsi_irq_type_id { 254 GSI_CH_CTRL = BIT(0), 255 GSI_EV_CTRL = BIT(1), 256 GSI_GLOB_EE = BIT(2), 257 GSI_IEOB = BIT(3), 258 GSI_INTER_EE_CH_CTRL = BIT(4), 259 GSI_INTER_EE_EV_CTRL = BIT(5), 260 GSI_GENERAL = BIT(6), 261 /* IRQ types 7-31 (and their bit values) are reserved */ 262 }; 263 264 /** enum gsi_global_irq_id: Global GSI interrupt events */ 265 enum gsi_global_irq_id { 266 ERROR_INT = BIT(0), 267 GP_INT1 = BIT(1), 268 GP_INT2 = BIT(2), 269 GP_INT3 = BIT(3), 270 /* Global IRQ types 4-31 (and their bit values) are reserved */ 271 }; 272 273 /** enum gsi_general_irq_id: GSI general IRQ conditions */ 274 enum gsi_general_irq_id { 275 BREAK_POINT = BIT(0), 276 BUS_ERROR = BIT(1), 277 CMD_FIFO_OVRFLOW = BIT(2), 278 MCS_STACK_OVRFLOW = BIT(3), 279 /* General IRQ types 4-31 (and their bit values) are reserved */ 280 }; 281 282 /* CNTXT_INTSET register */ 283 enum gsi_cntxt_intset_field_id { 284 INTYPE, 285 }; 286 287 /* ERROR_LOG register */ 288 enum gsi_error_log_field_id { 289 ERR_ARG3, 290 ERR_ARG2, 291 ERR_ARG1, 292 ERR_CODE, 293 ERR_VIRT_IDX, 294 ERR_TYPE, 295 ERR_EE, 296 }; 297 298 /** enum gsi_err_code - ERR_CODE field values in EE_ERR_LOG */ 299 enum gsi_err_code { 300 GSI_INVALID_TRE = 0x1, 301 GSI_OUT_OF_BUFFERS = 0x2, 302 GSI_OUT_OF_RESOURCES = 0x3, 303 GSI_UNSUPPORTED_INTER_EE_OP = 0x4, 304 GSI_EVT_RING_EMPTY = 0x5, 305 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6, 306 /* 7 is not assigned */ 307 GSI_HWO_1 = 0x8, 308 }; 309 310 /** enum gsi_err_type - ERR_TYPE field values in EE_ERR_LOG */ 311 enum gsi_err_type { 312 GSI_ERR_TYPE_GLOB = 0x1, 313 GSI_ERR_TYPE_CHAN = 0x2, 314 GSI_ERR_TYPE_EVT = 0x3, 315 }; 316 317 /* CNTXT_SCRATCH_0 register */ 318 enum gsi_cntxt_scratch_0_field_id { 319 INTER_EE_RESULT, 320 GENERIC_EE_RESULT, 321 }; 322 323 /** enum gsi_generic_ee_result - GENERIC_EE_RESULT field values in SCRATCH_0 */ 324 enum gsi_generic_ee_result { 325 GENERIC_EE_SUCCESS = 0x1, 326 GENERIC_EE_INCORRECT_CHANNEL_STATE = 0x2, 327 GENERIC_EE_INCORRECT_DIRECTION = 0x3, 328 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4, 329 GENERIC_EE_INCORRECT_CHANNEL = 0x5, 330 GENERIC_EE_RETRY = 0x6, 331 GENERIC_EE_NO_RESOURCES = 0x7, 332 }; 333 334 extern const struct regs gsi_regs_v3_1; 335 extern const struct regs gsi_regs_v3_5_1; 336 extern const struct regs gsi_regs_v4_0; 337 extern const struct regs gsi_regs_v4_5; 338 extern const struct regs gsi_regs_v4_9; 339 extern const struct regs gsi_regs_v4_11; 340 341 /** 342 * gsi_reg() - Return the structure describing a GSI register 343 * @gsi: GSI pointer 344 * @reg_id: GSI register ID 345 */ 346 const struct reg *gsi_reg(struct gsi *gsi, enum gsi_reg_id reg_id); 347 348 /** 349 * gsi_reg_init() - Perform GSI register initialization 350 * @gsi: GSI pointer 351 * @pdev: GSI (IPA) platform device 352 * 353 * Initialize GSI registers, including looking up and I/O mapping 354 * the "gsi" memory space. This function sets gsi->virt_raw and 355 * gsi->virt. 356 */ 357 int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev); 358 359 /** 360 * gsi_reg_exit() - Inverse of gsi_reg_init() 361 * @gsi: GSI pointer 362 */ 363 void gsi_reg_exit(struct gsi *gsi); 364 365 #endif /* _GSI_REG_H_ */ 366