xref: /linux/drivers/net/ipa/data/ipa_data-v5.2.c (revision 05e352444b2430de4b183b4a988085381e5fd6ad) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2023-2024 Linaro Ltd.
4  * Copyright (c) 2026, Luca Weiss <luca.weiss@fairphone.com>
5  */
6 
7 #include <linux/array_size.h>
8 #include <linux/log2.h>
9 
10 #include "../ipa_data.h"
11 #include "../ipa_endpoint.h"
12 #include "../ipa_mem.h"
13 #include "../ipa_version.h"
14 
15 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.2 */
16 enum ipa_resource_type {
17 	/* Source resource types; first must have value 0 */
18 	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,
19 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
20 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
21 	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
22 	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
23 
24 	/* Destination resource types; first must have value 0 */
25 	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,
26 	IPA_RESOURCE_TYPE_DST_DPS_DMARS,
27 	IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,
28 };
29 
30 /* Resource groups used for an SoC having IPA v5.2 */
31 enum ipa_rsrc_group_id {
32 	/* Source resource group identifiers */
33 	IPA_RSRC_GROUP_SRC_UL				= 0,
34 	IPA_RSRC_GROUP_SRC_DL,
35 	IPA_RSRC_GROUP_SRC_URLLC,
36 	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */
37 
38 	/* Destination resource group identifiers */
39 	IPA_RSRC_GROUP_DST_UL				= 0,
40 	IPA_RSRC_GROUP_DST_DL,
41 	IPA_RSRC_GROUP_DST_UNUSED_1,
42 	IPA_RSRC_GROUP_DST_DRB_IP,
43 	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */
44 };
45 
46 /* QSB configuration data for an SoC having IPA v5.2 */
47 static const struct ipa_qsb_data ipa_qsb_data[] = {
48 	[IPA_QSB_MASTER_DDR] = {
49 		.max_writes		= 13,
50 		.max_reads		= 13,
51 		.max_reads_beats	= 0,
52 	},
53 };
54 
55 /* Endpoint configuration data for an SoC having IPA v5.2 */
56 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
57 	[IPA_ENDPOINT_AP_COMMAND_TX] = {
58 		.ee_id		= GSI_EE_AP,
59 		.channel_id	= 6,
60 		.endpoint_id	= 9,
61 		.toward_ipa	= true,
62 		.channel = {
63 			.tre_count	= 256,
64 			.event_count	= 256,
65 			.tlv_count	= 20,
66 		},
67 		.endpoint = {
68 			.config = {
69 				.resource_group	= IPA_RSRC_GROUP_SRC_UL,
70 				.dma_mode	= true,
71 				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,
72 				.tx = {
73 					.seq_type = IPA_SEQ_DMA,
74 				},
75 			},
76 		},
77 	},
78 	[IPA_ENDPOINT_AP_LAN_RX] = {
79 		.ee_id		= GSI_EE_AP,
80 		.channel_id	= 7,
81 		.endpoint_id	= 11,
82 		.toward_ipa	= false,
83 		.channel = {
84 			.tre_count	= 256,
85 			.event_count	= 256,
86 			.tlv_count	= 9,
87 		},
88 		.endpoint = {
89 			.config = {
90 				.resource_group	= IPA_RSRC_GROUP_DST_UL,
91 				.aggregation	= true,
92 				.status_enable	= true,
93 				.rx = {
94 					.buffer_size	= 8192,
95 					.pad_align	= ilog2(sizeof(u32)),
96 					.aggr_time_limit = 500,
97 				},
98 			},
99 		},
100 	},
101 	[IPA_ENDPOINT_AP_MODEM_TX] = {
102 		.ee_id		= GSI_EE_AP,
103 		.channel_id	= 5,
104 		.endpoint_id	= 2,
105 		.toward_ipa	= true,
106 		.channel = {
107 			.tre_count	= 512,
108 			.event_count	= 512,
109 			.tlv_count	= 25,
110 		},
111 		.endpoint = {
112 			.filter_support	= true,
113 			.config = {
114 				.resource_group	= IPA_RSRC_GROUP_SRC_UL,
115 				.checksum       = true,
116 				.qmap		= true,
117 				.status_enable	= true,
118 				.tx = {
119 					.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
120 					.status_endpoint =
121 						IPA_ENDPOINT_MODEM_AP_RX,
122 				},
123 			},
124 		},
125 	},
126 	[IPA_ENDPOINT_AP_MODEM_RX] = {
127 		.ee_id		= GSI_EE_AP,
128 		.channel_id	= 9,
129 		.endpoint_id	= 18,
130 		.toward_ipa	= false,
131 		.channel = {
132 			.tre_count	= 256,
133 			.event_count	= 256,
134 			.tlv_count	= 9,
135 		},
136 		.endpoint = {
137 			.config = {
138 				.resource_group	= IPA_RSRC_GROUP_DST_DL,
139 				.checksum       = true,
140 				.qmap		= true,
141 				.aggregation	= true,
142 				.rx = {
143 					.buffer_size	= 8192,
144 					.aggr_time_limit = 500,
145 					.aggr_close_eof	= true,
146 				},
147 			},
148 		},
149 	},
150 	[IPA_ENDPOINT_MODEM_AP_TX] = {
151 		.ee_id		= GSI_EE_MODEM,
152 		.channel_id	= 0,
153 		.endpoint_id	= 7,
154 		.toward_ipa	= true,
155 		.endpoint = {
156 			.filter_support	= true,
157 		},
158 	},
159 	[IPA_ENDPOINT_MODEM_AP_RX] = {
160 		.ee_id		= GSI_EE_MODEM,
161 		.channel_id	= 7,
162 		.endpoint_id	= 16,
163 		.toward_ipa	= false,
164 	},
165 	[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
166 		.ee_id		= GSI_EE_MODEM,
167 		.channel_id	= 2,
168 		.endpoint_id	= 10,
169 		.toward_ipa	= true,
170 		.endpoint = {
171 			.filter_support	= true,
172 		},
173 	},
174 };
175 
176 /* Source resource configuration data for an SoC having IPA v5.2 */
177 static const struct ipa_resource ipa_resource_src[] = {
178 	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
179 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
180 			.min = 1,	.max = 7,
181 		},
182 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
183 			.min = 1,	.max = 7,
184 		},
185 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
186 			.min = 0,	.max = 5,
187 		},
188 	},
189 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
190 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
191 			.min = 8,	.max = 8,
192 		},
193 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
194 			.min = 8,	.max = 8,
195 		},
196 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
197 			.min = 8,	.max = 8,
198 		},
199 	},
200 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
201 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
202 			.min = 10,	.max = 10,
203 		},
204 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
205 			.min = 12,	.max = 12,
206 		},
207 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
208 			.min = 12,	.max = 12,
209 		},
210 	},
211 	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
212 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
213 			.min = 0,	.max = 63,
214 		},
215 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
216 			.min = 0,	.max = 63,
217 		},
218 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
219 			.min = 0,	.max = 63,
220 		},
221 	},
222 	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
223 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
224 			.min = 15,	.max = 15,
225 		},
226 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
227 			.min = 15,	.max = 15,
228 		},
229 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
230 			.min = 12,	.max = 12,
231 		},
232 	},
233 };
234 
235 /* Destination resource configuration data for an SoC having IPA v5.2 */
236 static const struct ipa_resource ipa_resource_dst[] = {
237 	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
238 		.limits[IPA_RSRC_GROUP_DST_UL] = {
239 			.min = 3,	.max = 3,
240 		},
241 		.limits[IPA_RSRC_GROUP_DST_DL] = {
242 			.min = 3,	.max = 3,
243 		},
244 		.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
245 			.min = 23,	.max = 23,
246 		},
247 	},
248 	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
249 		.limits[IPA_RSRC_GROUP_DST_UL] = {
250 			.min = 1,	.max = 2,
251 		},
252 		.limits[IPA_RSRC_GROUP_DST_DL] = {
253 			.min = 1,	.max = 2,
254 		},
255 	},
256 	[IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {
257 		.limits[IPA_RSRC_GROUP_DST_UL] = {
258 			.min = 1,	.max = 63,
259 		},
260 		.limits[IPA_RSRC_GROUP_DST_DL] = {
261 			.min = 1,	.max = 63,
262 		},
263 	},
264 };
265 
266 /* Resource configuration data for an SoC having IPA v5.2 */
267 static const struct ipa_resource_data ipa_resource_data = {
268 	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,
269 	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,
270 	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),
271 	.resource_src		= ipa_resource_src,
272 	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),
273 	.resource_dst		= ipa_resource_dst,
274 };
275 
276 /* IPA-resident memory region data for an SoC having IPA v5.2 */
277 static const struct ipa_mem ipa_mem_local_data[] = {
278 	{
279 		.id		= IPA_MEM_UC_SHARED,
280 		.offset		= 0x0000,
281 		.size		= 0x0080,
282 		.canary_count	= 0,
283 	},
284 	{
285 		.id		= IPA_MEM_UC_INFO,
286 		.offset		= 0x0080,
287 		.size		= 0x0200,
288 		.canary_count	= 0,
289 	},
290 	{
291 		.id		= IPA_MEM_V4_FILTER_HASHED,
292 		.offset		= 0x0288,
293 		.size		= 0x0078,
294 		.canary_count	= 2,
295 	},
296 	{
297 		.id		= IPA_MEM_V4_FILTER,
298 		.offset		= 0x0308,
299 		.size		= 0x0078,
300 		.canary_count	= 2,
301 	},
302 	{
303 		.id		= IPA_MEM_V6_FILTER_HASHED,
304 		.offset		= 0x0388,
305 		.size		= 0x0078,
306 		.canary_count	= 2,
307 	},
308 	{
309 		.id		= IPA_MEM_V6_FILTER,
310 		.offset		= 0x0408,
311 		.size		= 0x0078,
312 		.canary_count	= 2,
313 	},
314 	{
315 		.id		= IPA_MEM_V4_ROUTE_HASHED,
316 		.offset		= 0x0488,
317 		.size		= 0x0098,
318 		.canary_count	= 2,
319 	},
320 	{
321 		.id		= IPA_MEM_V4_ROUTE,
322 		.offset		= 0x0528,
323 		.size		= 0x0098,
324 		.canary_count	= 2,
325 	},
326 	{
327 		.id		= IPA_MEM_V6_ROUTE_HASHED,
328 		.offset		= 0x05c8,
329 		.size		= 0x0098,
330 		.canary_count	= 2,
331 	},
332 	{
333 		.id		= IPA_MEM_V6_ROUTE,
334 		.offset		= 0x0668,
335 		.size		= 0x0098,
336 		.canary_count	= 2,
337 	},
338 	{
339 		.id		= IPA_MEM_MODEM_HEADER,
340 		.offset		= 0x0708,
341 		.size		= 0x0240,
342 		.canary_count	= 2,
343 	},
344 	{
345 		.id		= IPA_MEM_AP_HEADER,
346 		.offset		= 0x0948,
347 		.size		= 0x01e0,
348 		.canary_count	= 0,
349 	},
350 	{
351 		.id		= IPA_MEM_MODEM_PROC_CTX,
352 		.offset		= 0x0b40,
353 		.size		= 0x0b20,
354 		.canary_count	= 2,
355 	},
356 	{
357 		.id		= IPA_MEM_AP_PROC_CTX,
358 		.offset		= 0x1660,
359 		.size		= 0x0200,
360 		.canary_count	= 0,
361 	},
362 	{
363 		.id		= IPA_MEM_STATS_QUOTA_MODEM,
364 		.offset		= 0x1868,
365 		.size		= 0x0060,
366 		.canary_count	= 2,
367 	},
368 	{
369 		.id		= IPA_MEM_STATS_QUOTA_AP,
370 		.offset		= 0x18c8,
371 		.size		= 0x0048,
372 		.canary_count	= 0,
373 	},
374 	{
375 		.id		= IPA_MEM_STATS_TETHERING,
376 		.offset		= 0x1910,
377 		.size		= 0x03c0,
378 		.canary_count	= 0,
379 	},
380 	{
381 		.id		= IPA_MEM_STATS_FILTER_ROUTE,
382 		.offset		= 0x1cd0,
383 		.size		= 0x0ba0,
384 		.canary_count	= 0,
385 	},
386 	{
387 		.id		= IPA_MEM_STATS_DROP,
388 		.offset		= 0x2870,
389 		.size		= 0x0020,
390 		.canary_count	= 0,
391 	},
392 	{
393 		.id		= IPA_MEM_MODEM,
394 		.offset		= 0x2898,
395 		.size		= 0x0d48,
396 		.canary_count	= 2,
397 	},
398 	{
399 		.id		= IPA_MEM_NAT_TABLE,
400 		.offset		= 0x35e0,
401 		.size		= 0x0900,
402 		.canary_count	= 0,
403 	},
404 	{
405 		.id		= IPA_MEM_PDN_CONFIG,
406 		.offset		= 0x3ee8,
407 		.size		= 0x0100,
408 		.canary_count	= 2,
409 	},
410 };
411 
412 /* Memory configuration data for an SoC having IPA v5.2 */
413 static const struct ipa_mem_data ipa_mem_data = {
414 	.local_count	= ARRAY_SIZE(ipa_mem_local_data),
415 	.local		= ipa_mem_local_data,
416 	.smem_size	= 0x0000b000,
417 };
418 
419 /* Interconnect rates are in 1000 byte/second units */
420 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
421 	{
422 		.name			= "memory",
423 		.peak_bandwidth		= 1300000,	/* 1.3 GBps */
424 		.average_bandwidth	= 600000,	/* 600 MBps */
425 	},
426 	/* Average rate is unused for the next interconnect */
427 	{
428 		.name			= "config",
429 		.peak_bandwidth		= 76800,	/* 76.8 MBps */
430 		.average_bandwidth	= 0,		/* unused */
431 	},
432 };
433 
434 /* Clock and interconnect configuration data for an SoC having IPA v5.2 */
435 static const struct ipa_power_data ipa_power_data = {
436 	.core_clock_rate	= 120 * 1000 * 1000,	/* Hz */
437 	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),
438 	.interconnect_data	= ipa_interconnect_data,
439 };
440 
441 /* Configuration data for an SoC having IPA v5.2. */
442 const struct ipa_data ipa_data_v5_2 = {
443 	.version		= IPA_VERSION_5_2,
444 	.qsb_count		= ARRAY_SIZE(ipa_qsb_data),
445 	.qsb_data		= ipa_qsb_data,
446 	.modem_route_count	= 11,
447 	.endpoint_count		= ARRAY_SIZE(ipa_gsi_endpoint_data),
448 	.endpoint_data		= ipa_gsi_endpoint_data,
449 	.resource_data		= &ipa_resource_data,
450 	.mem_data		= &ipa_mem_data,
451 	.power_data		= &ipa_power_data,
452 };
453