xref: /linux/drivers/net/ipa/data/ipa_data-v5.2.c (revision 4bf38bac1b2e2586a14529053cf56346db8a0032)
1*4bf38bacSLuca Weiss // SPDX-License-Identifier: GPL-2.0
2*4bf38bacSLuca Weiss /*
3*4bf38bacSLuca Weiss  * Copyright (C) 2023-2024 Linaro Ltd.
4*4bf38bacSLuca Weiss  * Copyright (c) 2026, Luca Weiss <luca.weiss@fairphone.com>
5*4bf38bacSLuca Weiss  */
6*4bf38bacSLuca Weiss 
7*4bf38bacSLuca Weiss #include <linux/array_size.h>
8*4bf38bacSLuca Weiss #include <linux/log2.h>
9*4bf38bacSLuca Weiss 
10*4bf38bacSLuca Weiss #include "../ipa_data.h"
11*4bf38bacSLuca Weiss #include "../ipa_endpoint.h"
12*4bf38bacSLuca Weiss #include "../ipa_mem.h"
13*4bf38bacSLuca Weiss #include "../ipa_version.h"
14*4bf38bacSLuca Weiss 
15*4bf38bacSLuca Weiss /** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.2 */
16*4bf38bacSLuca Weiss enum ipa_resource_type {
17*4bf38bacSLuca Weiss 	/* Source resource types; first must have value 0 */
18*4bf38bacSLuca Weiss 	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,
19*4bf38bacSLuca Weiss 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
20*4bf38bacSLuca Weiss 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
21*4bf38bacSLuca Weiss 	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
22*4bf38bacSLuca Weiss 	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
23*4bf38bacSLuca Weiss 
24*4bf38bacSLuca Weiss 	/* Destination resource types; first must have value 0 */
25*4bf38bacSLuca Weiss 	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,
26*4bf38bacSLuca Weiss 	IPA_RESOURCE_TYPE_DST_DPS_DMARS,
27*4bf38bacSLuca Weiss 	IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS,
28*4bf38bacSLuca Weiss };
29*4bf38bacSLuca Weiss 
30*4bf38bacSLuca Weiss /* Resource groups used for an SoC having IPA v5.2 */
31*4bf38bacSLuca Weiss enum ipa_rsrc_group_id {
32*4bf38bacSLuca Weiss 	/* Source resource group identifiers */
33*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_SRC_UL				= 0,
34*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_SRC_DL,
35*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_SRC_URLLC,
36*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */
37*4bf38bacSLuca Weiss 
38*4bf38bacSLuca Weiss 	/* Destination resource group identifiers */
39*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_DST_UL				= 0,
40*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_DST_DL,
41*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_DST_UNUSED_1,
42*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_DST_DRB_IP,
43*4bf38bacSLuca Weiss 	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */
44*4bf38bacSLuca Weiss };
45*4bf38bacSLuca Weiss 
46*4bf38bacSLuca Weiss /* QSB configuration data for an SoC having IPA v5.2 */
47*4bf38bacSLuca Weiss static const struct ipa_qsb_data ipa_qsb_data[] = {
48*4bf38bacSLuca Weiss 	[IPA_QSB_MASTER_DDR] = {
49*4bf38bacSLuca Weiss 		.max_writes		= 13,
50*4bf38bacSLuca Weiss 		.max_reads		= 13,
51*4bf38bacSLuca Weiss 		.max_reads_beats	= 0,
52*4bf38bacSLuca Weiss 	},
53*4bf38bacSLuca Weiss };
54*4bf38bacSLuca Weiss 
55*4bf38bacSLuca Weiss /* Endpoint configuration data for an SoC having IPA v5.2 */
56*4bf38bacSLuca Weiss static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
57*4bf38bacSLuca Weiss 	[IPA_ENDPOINT_AP_COMMAND_TX] = {
58*4bf38bacSLuca Weiss 		.ee_id		= GSI_EE_AP,
59*4bf38bacSLuca Weiss 		.channel_id	= 6,
60*4bf38bacSLuca Weiss 		.endpoint_id	= 9,
61*4bf38bacSLuca Weiss 		.toward_ipa	= true,
62*4bf38bacSLuca Weiss 		.channel = {
63*4bf38bacSLuca Weiss 			.tre_count	= 256,
64*4bf38bacSLuca Weiss 			.event_count	= 256,
65*4bf38bacSLuca Weiss 			.tlv_count	= 20,
66*4bf38bacSLuca Weiss 		},
67*4bf38bacSLuca Weiss 		.endpoint = {
68*4bf38bacSLuca Weiss 			.config = {
69*4bf38bacSLuca Weiss 				.resource_group	= IPA_RSRC_GROUP_SRC_UL,
70*4bf38bacSLuca Weiss 				.dma_mode	= true,
71*4bf38bacSLuca Weiss 				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,
72*4bf38bacSLuca Weiss 				.tx = {
73*4bf38bacSLuca Weiss 					.seq_type = IPA_SEQ_DMA,
74*4bf38bacSLuca Weiss 				},
75*4bf38bacSLuca Weiss 			},
76*4bf38bacSLuca Weiss 		},
77*4bf38bacSLuca Weiss 	},
78*4bf38bacSLuca Weiss 	[IPA_ENDPOINT_AP_LAN_RX] = {
79*4bf38bacSLuca Weiss 		.ee_id		= GSI_EE_AP,
80*4bf38bacSLuca Weiss 		.channel_id	= 7,
81*4bf38bacSLuca Weiss 		.endpoint_id	= 11,
82*4bf38bacSLuca Weiss 		.toward_ipa	= false,
83*4bf38bacSLuca Weiss 		.channel = {
84*4bf38bacSLuca Weiss 			.tre_count	= 256,
85*4bf38bacSLuca Weiss 			.event_count	= 256,
86*4bf38bacSLuca Weiss 			.tlv_count	= 9,
87*4bf38bacSLuca Weiss 		},
88*4bf38bacSLuca Weiss 		.endpoint = {
89*4bf38bacSLuca Weiss 			.config = {
90*4bf38bacSLuca Weiss 				.resource_group	= IPA_RSRC_GROUP_DST_UL,
91*4bf38bacSLuca Weiss 				.aggregation	= true,
92*4bf38bacSLuca Weiss 				.status_enable	= true,
93*4bf38bacSLuca Weiss 				.rx = {
94*4bf38bacSLuca Weiss 					.buffer_size	= 8192,
95*4bf38bacSLuca Weiss 					.pad_align	= ilog2(sizeof(u32)),
96*4bf38bacSLuca Weiss 					.aggr_time_limit = 500,
97*4bf38bacSLuca Weiss 				},
98*4bf38bacSLuca Weiss 			},
99*4bf38bacSLuca Weiss 		},
100*4bf38bacSLuca Weiss 	},
101*4bf38bacSLuca Weiss 	[IPA_ENDPOINT_AP_MODEM_TX] = {
102*4bf38bacSLuca Weiss 		.ee_id		= GSI_EE_AP,
103*4bf38bacSLuca Weiss 		.channel_id	= 5,
104*4bf38bacSLuca Weiss 		.endpoint_id	= 2,
105*4bf38bacSLuca Weiss 		.toward_ipa	= true,
106*4bf38bacSLuca Weiss 		.channel = {
107*4bf38bacSLuca Weiss 			.tre_count	= 512,
108*4bf38bacSLuca Weiss 			.event_count	= 512,
109*4bf38bacSLuca Weiss 			.tlv_count	= 25,
110*4bf38bacSLuca Weiss 		},
111*4bf38bacSLuca Weiss 		.endpoint = {
112*4bf38bacSLuca Weiss 			.filter_support	= true,
113*4bf38bacSLuca Weiss 			.config = {
114*4bf38bacSLuca Weiss 				.resource_group	= IPA_RSRC_GROUP_SRC_UL,
115*4bf38bacSLuca Weiss 				.checksum       = true,
116*4bf38bacSLuca Weiss 				.qmap		= true,
117*4bf38bacSLuca Weiss 				.status_enable	= true,
118*4bf38bacSLuca Weiss 				.tx = {
119*4bf38bacSLuca Weiss 					.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
120*4bf38bacSLuca Weiss 					.status_endpoint =
121*4bf38bacSLuca Weiss 						IPA_ENDPOINT_MODEM_AP_RX,
122*4bf38bacSLuca Weiss 				},
123*4bf38bacSLuca Weiss 			},
124*4bf38bacSLuca Weiss 		},
125*4bf38bacSLuca Weiss 	},
126*4bf38bacSLuca Weiss 	[IPA_ENDPOINT_AP_MODEM_RX] = {
127*4bf38bacSLuca Weiss 		.ee_id		= GSI_EE_AP,
128*4bf38bacSLuca Weiss 		.channel_id	= 9,
129*4bf38bacSLuca Weiss 		.endpoint_id	= 18,
130*4bf38bacSLuca Weiss 		.toward_ipa	= false,
131*4bf38bacSLuca Weiss 		.channel = {
132*4bf38bacSLuca Weiss 			.tre_count	= 256,
133*4bf38bacSLuca Weiss 			.event_count	= 256,
134*4bf38bacSLuca Weiss 			.tlv_count	= 9,
135*4bf38bacSLuca Weiss 		},
136*4bf38bacSLuca Weiss 		.endpoint = {
137*4bf38bacSLuca Weiss 			.config = {
138*4bf38bacSLuca Weiss 				.resource_group	= IPA_RSRC_GROUP_DST_DL,
139*4bf38bacSLuca Weiss 				.checksum       = true,
140*4bf38bacSLuca Weiss 				.qmap		= true,
141*4bf38bacSLuca Weiss 				.aggregation	= true,
142*4bf38bacSLuca Weiss 				.rx = {
143*4bf38bacSLuca Weiss 					.buffer_size	= 8192,
144*4bf38bacSLuca Weiss 					.aggr_time_limit = 500,
145*4bf38bacSLuca Weiss 					.aggr_close_eof	= true,
146*4bf38bacSLuca Weiss 				},
147*4bf38bacSLuca Weiss 			},
148*4bf38bacSLuca Weiss 		},
149*4bf38bacSLuca Weiss 	},
150*4bf38bacSLuca Weiss 	[IPA_ENDPOINT_MODEM_AP_TX] = {
151*4bf38bacSLuca Weiss 		.ee_id		= GSI_EE_MODEM,
152*4bf38bacSLuca Weiss 		.channel_id	= 0,
153*4bf38bacSLuca Weiss 		.endpoint_id	= 7,
154*4bf38bacSLuca Weiss 		.toward_ipa	= true,
155*4bf38bacSLuca Weiss 		.endpoint = {
156*4bf38bacSLuca Weiss 			.filter_support	= true,
157*4bf38bacSLuca Weiss 		},
158*4bf38bacSLuca Weiss 	},
159*4bf38bacSLuca Weiss 	[IPA_ENDPOINT_MODEM_AP_RX] = {
160*4bf38bacSLuca Weiss 		.ee_id		= GSI_EE_MODEM,
161*4bf38bacSLuca Weiss 		.channel_id	= 7,
162*4bf38bacSLuca Weiss 		.endpoint_id	= 16,
163*4bf38bacSLuca Weiss 		.toward_ipa	= false,
164*4bf38bacSLuca Weiss 	},
165*4bf38bacSLuca Weiss 	[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
166*4bf38bacSLuca Weiss 		.ee_id		= GSI_EE_MODEM,
167*4bf38bacSLuca Weiss 		.channel_id	= 2,
168*4bf38bacSLuca Weiss 		.endpoint_id	= 10,
169*4bf38bacSLuca Weiss 		.toward_ipa	= true,
170*4bf38bacSLuca Weiss 		.endpoint = {
171*4bf38bacSLuca Weiss 			.filter_support	= true,
172*4bf38bacSLuca Weiss 		},
173*4bf38bacSLuca Weiss 	},
174*4bf38bacSLuca Weiss };
175*4bf38bacSLuca Weiss 
176*4bf38bacSLuca Weiss /* Source resource configuration data for an SoC having IPA v5.2 */
177*4bf38bacSLuca Weiss static const struct ipa_resource ipa_resource_src[] = {
178*4bf38bacSLuca Weiss 	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
179*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
180*4bf38bacSLuca Weiss 			.min = 1,	.max = 7,
181*4bf38bacSLuca Weiss 		},
182*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
183*4bf38bacSLuca Weiss 			.min = 1,	.max = 7,
184*4bf38bacSLuca Weiss 		},
185*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
186*4bf38bacSLuca Weiss 			.min = 0,	.max = 5,
187*4bf38bacSLuca Weiss 		},
188*4bf38bacSLuca Weiss 	},
189*4bf38bacSLuca Weiss 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
190*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
191*4bf38bacSLuca Weiss 			.min = 8,	.max = 8,
192*4bf38bacSLuca Weiss 		},
193*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
194*4bf38bacSLuca Weiss 			.min = 8,	.max = 8,
195*4bf38bacSLuca Weiss 		},
196*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
197*4bf38bacSLuca Weiss 			.min = 8,	.max = 8,
198*4bf38bacSLuca Weiss 		},
199*4bf38bacSLuca Weiss 	},
200*4bf38bacSLuca Weiss 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
201*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
202*4bf38bacSLuca Weiss 			.min = 10,	.max = 10,
203*4bf38bacSLuca Weiss 		},
204*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
205*4bf38bacSLuca Weiss 			.min = 12,	.max = 12,
206*4bf38bacSLuca Weiss 		},
207*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
208*4bf38bacSLuca Weiss 			.min = 12,	.max = 12,
209*4bf38bacSLuca Weiss 		},
210*4bf38bacSLuca Weiss 	},
211*4bf38bacSLuca Weiss 	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
212*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
213*4bf38bacSLuca Weiss 			.min = 0,	.max = 63,
214*4bf38bacSLuca Weiss 		},
215*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
216*4bf38bacSLuca Weiss 			.min = 0,	.max = 63,
217*4bf38bacSLuca Weiss 		},
218*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
219*4bf38bacSLuca Weiss 			.min = 0,	.max = 63,
220*4bf38bacSLuca Weiss 		},
221*4bf38bacSLuca Weiss 	},
222*4bf38bacSLuca Weiss 	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
223*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_UL] = {
224*4bf38bacSLuca Weiss 			.min = 15,	.max = 15,
225*4bf38bacSLuca Weiss 		},
226*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_DL] = {
227*4bf38bacSLuca Weiss 			.min = 15,	.max = 15,
228*4bf38bacSLuca Weiss 		},
229*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_SRC_URLLC] = {
230*4bf38bacSLuca Weiss 			.min = 12,	.max = 12,
231*4bf38bacSLuca Weiss 		},
232*4bf38bacSLuca Weiss 	},
233*4bf38bacSLuca Weiss };
234*4bf38bacSLuca Weiss 
235*4bf38bacSLuca Weiss /* Destination resource configuration data for an SoC having IPA v5.2 */
236*4bf38bacSLuca Weiss static const struct ipa_resource ipa_resource_dst[] = {
237*4bf38bacSLuca Weiss 	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
238*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_DST_UL] = {
239*4bf38bacSLuca Weiss 			.min = 3,	.max = 3,
240*4bf38bacSLuca Weiss 		},
241*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_DST_DL] = {
242*4bf38bacSLuca Weiss 			.min = 3,	.max = 3,
243*4bf38bacSLuca Weiss 		},
244*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
245*4bf38bacSLuca Weiss 			.min = 23,	.max = 23,
246*4bf38bacSLuca Weiss 		},
247*4bf38bacSLuca Weiss 	},
248*4bf38bacSLuca Weiss 	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
249*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_DST_UL] = {
250*4bf38bacSLuca Weiss 			.min = 1,	.max = 2,
251*4bf38bacSLuca Weiss 		},
252*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_DST_DL] = {
253*4bf38bacSLuca Weiss 			.min = 1,	.max = 2,
254*4bf38bacSLuca Weiss 		},
255*4bf38bacSLuca Weiss 	},
256*4bf38bacSLuca Weiss 	[IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = {
257*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_DST_UL] = {
258*4bf38bacSLuca Weiss 			.min = 1,	.max = 63,
259*4bf38bacSLuca Weiss 		},
260*4bf38bacSLuca Weiss 		.limits[IPA_RSRC_GROUP_DST_DL] = {
261*4bf38bacSLuca Weiss 			.min = 1,	.max = 63,
262*4bf38bacSLuca Weiss 		},
263*4bf38bacSLuca Weiss 	},
264*4bf38bacSLuca Weiss };
265*4bf38bacSLuca Weiss 
266*4bf38bacSLuca Weiss /* Resource configuration data for an SoC having IPA v5.2 */
267*4bf38bacSLuca Weiss static const struct ipa_resource_data ipa_resource_data = {
268*4bf38bacSLuca Weiss 	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,
269*4bf38bacSLuca Weiss 	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,
270*4bf38bacSLuca Weiss 	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),
271*4bf38bacSLuca Weiss 	.resource_src		= ipa_resource_src,
272*4bf38bacSLuca Weiss 	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),
273*4bf38bacSLuca Weiss 	.resource_dst		= ipa_resource_dst,
274*4bf38bacSLuca Weiss };
275*4bf38bacSLuca Weiss 
276*4bf38bacSLuca Weiss /* IPA-resident memory region data for an SoC having IPA v5.2 */
277*4bf38bacSLuca Weiss static const struct ipa_mem ipa_mem_local_data[] = {
278*4bf38bacSLuca Weiss 	{
279*4bf38bacSLuca Weiss 		.id		= IPA_MEM_UC_SHARED,
280*4bf38bacSLuca Weiss 		.offset		= 0x0000,
281*4bf38bacSLuca Weiss 		.size		= 0x0080,
282*4bf38bacSLuca Weiss 		.canary_count	= 0,
283*4bf38bacSLuca Weiss 	},
284*4bf38bacSLuca Weiss 	{
285*4bf38bacSLuca Weiss 		.id		= IPA_MEM_UC_INFO,
286*4bf38bacSLuca Weiss 		.offset		= 0x0080,
287*4bf38bacSLuca Weiss 		.size		= 0x0200,
288*4bf38bacSLuca Weiss 		.canary_count	= 0,
289*4bf38bacSLuca Weiss 	},
290*4bf38bacSLuca Weiss 	{
291*4bf38bacSLuca Weiss 		.id		= IPA_MEM_V4_FILTER_HASHED,
292*4bf38bacSLuca Weiss 		.offset		= 0x0288,
293*4bf38bacSLuca Weiss 		.size		= 0x0078,
294*4bf38bacSLuca Weiss 		.canary_count	= 2,
295*4bf38bacSLuca Weiss 	},
296*4bf38bacSLuca Weiss 	{
297*4bf38bacSLuca Weiss 		.id		= IPA_MEM_V4_FILTER,
298*4bf38bacSLuca Weiss 		.offset		= 0x0308,
299*4bf38bacSLuca Weiss 		.size		= 0x0078,
300*4bf38bacSLuca Weiss 		.canary_count	= 2,
301*4bf38bacSLuca Weiss 	},
302*4bf38bacSLuca Weiss 	{
303*4bf38bacSLuca Weiss 		.id		= IPA_MEM_V6_FILTER_HASHED,
304*4bf38bacSLuca Weiss 		.offset		= 0x0388,
305*4bf38bacSLuca Weiss 		.size		= 0x0078,
306*4bf38bacSLuca Weiss 		.canary_count	= 2,
307*4bf38bacSLuca Weiss 	},
308*4bf38bacSLuca Weiss 	{
309*4bf38bacSLuca Weiss 		.id		= IPA_MEM_V6_FILTER,
310*4bf38bacSLuca Weiss 		.offset		= 0x0408,
311*4bf38bacSLuca Weiss 		.size		= 0x0078,
312*4bf38bacSLuca Weiss 		.canary_count	= 2,
313*4bf38bacSLuca Weiss 	},
314*4bf38bacSLuca Weiss 	{
315*4bf38bacSLuca Weiss 		.id		= IPA_MEM_V4_ROUTE_HASHED,
316*4bf38bacSLuca Weiss 		.offset		= 0x0488,
317*4bf38bacSLuca Weiss 		.size		= 0x0098,
318*4bf38bacSLuca Weiss 		.canary_count	= 2,
319*4bf38bacSLuca Weiss 	},
320*4bf38bacSLuca Weiss 	{
321*4bf38bacSLuca Weiss 		.id		= IPA_MEM_V4_ROUTE,
322*4bf38bacSLuca Weiss 		.offset		= 0x0528,
323*4bf38bacSLuca Weiss 		.size		= 0x0098,
324*4bf38bacSLuca Weiss 		.canary_count	= 2,
325*4bf38bacSLuca Weiss 	},
326*4bf38bacSLuca Weiss 	{
327*4bf38bacSLuca Weiss 		.id		= IPA_MEM_V6_ROUTE_HASHED,
328*4bf38bacSLuca Weiss 		.offset		= 0x05c8,
329*4bf38bacSLuca Weiss 		.size		= 0x0098,
330*4bf38bacSLuca Weiss 		.canary_count	= 2,
331*4bf38bacSLuca Weiss 	},
332*4bf38bacSLuca Weiss 	{
333*4bf38bacSLuca Weiss 		.id		= IPA_MEM_V6_ROUTE,
334*4bf38bacSLuca Weiss 		.offset		= 0x0668,
335*4bf38bacSLuca Weiss 		.size		= 0x0098,
336*4bf38bacSLuca Weiss 		.canary_count	= 2,
337*4bf38bacSLuca Weiss 	},
338*4bf38bacSLuca Weiss 	{
339*4bf38bacSLuca Weiss 		.id		= IPA_MEM_MODEM_HEADER,
340*4bf38bacSLuca Weiss 		.offset		= 0x0708,
341*4bf38bacSLuca Weiss 		.size		= 0x0240,
342*4bf38bacSLuca Weiss 		.canary_count	= 2,
343*4bf38bacSLuca Weiss 	},
344*4bf38bacSLuca Weiss 	{
345*4bf38bacSLuca Weiss 		.id		= IPA_MEM_AP_HEADER,
346*4bf38bacSLuca Weiss 		.offset		= 0x0948,
347*4bf38bacSLuca Weiss 		.size		= 0x01e0,
348*4bf38bacSLuca Weiss 		.canary_count	= 0,
349*4bf38bacSLuca Weiss 	},
350*4bf38bacSLuca Weiss 	{
351*4bf38bacSLuca Weiss 		.id		= IPA_MEM_MODEM_PROC_CTX,
352*4bf38bacSLuca Weiss 		.offset		= 0x0b40,
353*4bf38bacSLuca Weiss 		.size		= 0x0b20,
354*4bf38bacSLuca Weiss 		.canary_count	= 2,
355*4bf38bacSLuca Weiss 	},
356*4bf38bacSLuca Weiss 	{
357*4bf38bacSLuca Weiss 		.id		= IPA_MEM_AP_PROC_CTX,
358*4bf38bacSLuca Weiss 		.offset		= 0x1660,
359*4bf38bacSLuca Weiss 		.size		= 0x0200,
360*4bf38bacSLuca Weiss 		.canary_count	= 0,
361*4bf38bacSLuca Weiss 	},
362*4bf38bacSLuca Weiss 	{
363*4bf38bacSLuca Weiss 		.id		= IPA_MEM_STATS_QUOTA_MODEM,
364*4bf38bacSLuca Weiss 		.offset		= 0x1868,
365*4bf38bacSLuca Weiss 		.size		= 0x0060,
366*4bf38bacSLuca Weiss 		.canary_count	= 2,
367*4bf38bacSLuca Weiss 	},
368*4bf38bacSLuca Weiss 	{
369*4bf38bacSLuca Weiss 		.id		= IPA_MEM_STATS_QUOTA_AP,
370*4bf38bacSLuca Weiss 		.offset		= 0x18c8,
371*4bf38bacSLuca Weiss 		.size		= 0x0048,
372*4bf38bacSLuca Weiss 		.canary_count	= 0,
373*4bf38bacSLuca Weiss 	},
374*4bf38bacSLuca Weiss 	{
375*4bf38bacSLuca Weiss 		.id		= IPA_MEM_STATS_TETHERING,
376*4bf38bacSLuca Weiss 		.offset		= 0x1910,
377*4bf38bacSLuca Weiss 		.size		= 0x03c0,
378*4bf38bacSLuca Weiss 		.canary_count	= 0,
379*4bf38bacSLuca Weiss 	},
380*4bf38bacSLuca Weiss 	{
381*4bf38bacSLuca Weiss 		.id		= IPA_MEM_STATS_FILTER_ROUTE,
382*4bf38bacSLuca Weiss 		.offset		= 0x1cd0,
383*4bf38bacSLuca Weiss 		.size		= 0x0ba0,
384*4bf38bacSLuca Weiss 		.canary_count	= 0,
385*4bf38bacSLuca Weiss 	},
386*4bf38bacSLuca Weiss 	{
387*4bf38bacSLuca Weiss 		.id		= IPA_MEM_STATS_DROP,
388*4bf38bacSLuca Weiss 		.offset		= 0x2870,
389*4bf38bacSLuca Weiss 		.size		= 0x0020,
390*4bf38bacSLuca Weiss 		.canary_count	= 0,
391*4bf38bacSLuca Weiss 	},
392*4bf38bacSLuca Weiss 	{
393*4bf38bacSLuca Weiss 		.id		= IPA_MEM_MODEM,
394*4bf38bacSLuca Weiss 		.offset		= 0x2898,
395*4bf38bacSLuca Weiss 		.size		= 0x0d48,
396*4bf38bacSLuca Weiss 		.canary_count	= 2,
397*4bf38bacSLuca Weiss 	},
398*4bf38bacSLuca Weiss 	{
399*4bf38bacSLuca Weiss 		.id		= IPA_MEM_NAT_TABLE,
400*4bf38bacSLuca Weiss 		.offset		= 0x35e0,
401*4bf38bacSLuca Weiss 		.size		= 0x0900,
402*4bf38bacSLuca Weiss 		.canary_count	= 0,
403*4bf38bacSLuca Weiss 	},
404*4bf38bacSLuca Weiss 	{
405*4bf38bacSLuca Weiss 		.id		= IPA_MEM_PDN_CONFIG,
406*4bf38bacSLuca Weiss 		.offset		= 0x3ee8,
407*4bf38bacSLuca Weiss 		.size		= 0x0100,
408*4bf38bacSLuca Weiss 		.canary_count	= 2,
409*4bf38bacSLuca Weiss 	},
410*4bf38bacSLuca Weiss };
411*4bf38bacSLuca Weiss 
412*4bf38bacSLuca Weiss /* Memory configuration data for an SoC having IPA v5.2 */
413*4bf38bacSLuca Weiss static const struct ipa_mem_data ipa_mem_data = {
414*4bf38bacSLuca Weiss 	.local_count	= ARRAY_SIZE(ipa_mem_local_data),
415*4bf38bacSLuca Weiss 	.local		= ipa_mem_local_data,
416*4bf38bacSLuca Weiss 	.smem_size	= 0x0000b000,
417*4bf38bacSLuca Weiss };
418*4bf38bacSLuca Weiss 
419*4bf38bacSLuca Weiss /* Interconnect rates are in 1000 byte/second units */
420*4bf38bacSLuca Weiss static const struct ipa_interconnect_data ipa_interconnect_data[] = {
421*4bf38bacSLuca Weiss 	{
422*4bf38bacSLuca Weiss 		.name			= "memory",
423*4bf38bacSLuca Weiss 		.peak_bandwidth		= 1300000,	/* 1.3 GBps */
424*4bf38bacSLuca Weiss 		.average_bandwidth	= 600000,	/* 600 MBps */
425*4bf38bacSLuca Weiss 	},
426*4bf38bacSLuca Weiss 	/* Average rate is unused for the next interconnect */
427*4bf38bacSLuca Weiss 	{
428*4bf38bacSLuca Weiss 		.name			= "config",
429*4bf38bacSLuca Weiss 		.peak_bandwidth		= 76800,	/* 76.8 MBps */
430*4bf38bacSLuca Weiss 		.average_bandwidth	= 0,		/* unused */
431*4bf38bacSLuca Weiss 	},
432*4bf38bacSLuca Weiss };
433*4bf38bacSLuca Weiss 
434*4bf38bacSLuca Weiss /* Clock and interconnect configuration data for an SoC having IPA v5.2 */
435*4bf38bacSLuca Weiss static const struct ipa_power_data ipa_power_data = {
436*4bf38bacSLuca Weiss 	.core_clock_rate	= 120 * 1000 * 1000,	/* Hz */
437*4bf38bacSLuca Weiss 	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),
438*4bf38bacSLuca Weiss 	.interconnect_data	= ipa_interconnect_data,
439*4bf38bacSLuca Weiss };
440*4bf38bacSLuca Weiss 
441*4bf38bacSLuca Weiss /* Configuration data for an SoC having IPA v5.2. */
442*4bf38bacSLuca Weiss const struct ipa_data ipa_data_v5_2 = {
443*4bf38bacSLuca Weiss 	.version		= IPA_VERSION_5_2,
444*4bf38bacSLuca Weiss 	.qsb_count		= ARRAY_SIZE(ipa_qsb_data),
445*4bf38bacSLuca Weiss 	.qsb_data		= ipa_qsb_data,
446*4bf38bacSLuca Weiss 	.modem_route_count	= 11,
447*4bf38bacSLuca Weiss 	.endpoint_count		= ARRAY_SIZE(ipa_gsi_endpoint_data),
448*4bf38bacSLuca Weiss 	.endpoint_data		= ipa_gsi_endpoint_data,
449*4bf38bacSLuca Weiss 	.resource_data		= &ipa_resource_data,
450*4bf38bacSLuca Weiss 	.mem_data		= &ipa_mem_data,
451*4bf38bacSLuca Weiss 	.power_data		= &ipa_power_data,
452*4bf38bacSLuca Weiss };
453