1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2023 Linaro Ltd. */ 4 5 #include <linux/log2.h> 6 7 #include "../gsi.h" 8 #include "../ipa_data.h" 9 #include "../ipa_endpoint.h" 10 #include "../ipa_mem.h" 11 12 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v5.0 */ 13 enum ipa_resource_type { 14 /* Source resource types; first must have value 0 */ 15 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 16 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 18 IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 19 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 20 21 /* Destination resource types; first must have value 0 */ 22 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 23 IPA_RESOURCE_TYPE_DST_DPS_DMARS, 24 IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS, 25 }; 26 27 /* Resource groups used for an SoC having IPA v5.0 */ 28 enum ipa_rsrc_group_id { 29 /* Source resource group identifiers */ 30 IPA_RSRC_GROUP_SRC_UL = 0, 31 IPA_RSRC_GROUP_SRC_DL, 32 IPA_RSRC_GROUP_SRC_UNUSED_2, 33 IPA_RSRC_GROUP_SRC_UNUSED_3, 34 IPA_RSRC_GROUP_SRC_URLLC, 35 IPA_RSRC_GROUP_SRC_U_RX_QC, 36 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 37 38 /* Destination resource group identifiers */ 39 IPA_RSRC_GROUP_DST_UL = 0, 40 IPA_RSRC_GROUP_DST_DL, 41 IPA_RSRC_GROUP_DST_DMA, 42 IPA_RSRC_GROUP_DST_QDSS, 43 IPA_RSRC_GROUP_DST_CV2X, 44 IPA_RSRC_GROUP_DST_UC, 45 IPA_RSRC_GROUP_DST_DRB_IP, 46 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 47 }; 48 49 /* QSB configuration data for an SoC having IPA v5.0 */ 50 static const struct ipa_qsb_data ipa_qsb_data[] = { 51 [IPA_QSB_MASTER_DDR] = { 52 .max_writes = 0, 53 .max_reads = 0, /* no limit (hardware max) */ 54 .max_reads_beats = 0, 55 }, 56 [IPA_QSB_MASTER_PCIE] = { 57 .max_writes = 0, 58 .max_reads = 0, /* no limit (hardware max) */ 59 .max_reads_beats = 0, 60 }, 61 }; 62 63 /* Endpoint configuration data for an SoC having IPA v5.0 */ 64 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 65 [IPA_ENDPOINT_AP_COMMAND_TX] = { 66 .ee_id = GSI_EE_AP, 67 .channel_id = 12, 68 .endpoint_id = 14, 69 .toward_ipa = true, 70 .channel = { 71 .tre_count = 256, 72 .event_count = 256, 73 .tlv_count = 20, 74 }, 75 .endpoint = { 76 .config = { 77 .resource_group = IPA_RSRC_GROUP_SRC_UL, 78 .dma_mode = true, 79 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 80 .tx = { 81 .seq_type = IPA_SEQ_DMA, 82 }, 83 }, 84 }, 85 }, 86 [IPA_ENDPOINT_AP_LAN_RX] = { 87 .ee_id = GSI_EE_AP, 88 .channel_id = 13, 89 .endpoint_id = 16, 90 .toward_ipa = false, 91 .channel = { 92 .tre_count = 256, 93 .event_count = 256, 94 .tlv_count = 9, 95 }, 96 .endpoint = { 97 .config = { 98 .resource_group = IPA_RSRC_GROUP_DST_UL, 99 .aggregation = true, 100 .status_enable = true, 101 .rx = { 102 .buffer_size = 8192, 103 .pad_align = ilog2(sizeof(u32)), 104 .aggr_time_limit = 500, 105 }, 106 }, 107 }, 108 }, 109 [IPA_ENDPOINT_AP_MODEM_TX] = { 110 .ee_id = GSI_EE_AP, 111 .channel_id = 11, 112 .endpoint_id = 2, 113 .toward_ipa = true, 114 .channel = { 115 .tre_count = 512, 116 .event_count = 512, 117 .tlv_count = 25, 118 }, 119 .endpoint = { 120 .filter_support = true, 121 .config = { 122 .resource_group = IPA_RSRC_GROUP_SRC_UL, 123 .checksum = true, 124 .qmap = true, 125 .status_enable = true, 126 .tx = { 127 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 128 .status_endpoint = 129 IPA_ENDPOINT_MODEM_AP_RX, 130 }, 131 }, 132 }, 133 }, 134 [IPA_ENDPOINT_AP_MODEM_RX] = { 135 .ee_id = GSI_EE_AP, 136 .channel_id = 1, 137 .endpoint_id = 23, 138 .toward_ipa = false, 139 .channel = { 140 .tre_count = 256, 141 .event_count = 256, 142 .tlv_count = 9, 143 }, 144 .endpoint = { 145 .config = { 146 .resource_group = IPA_RSRC_GROUP_DST_DL, 147 .checksum = true, 148 .qmap = true, 149 .aggregation = true, 150 .rx = { 151 .buffer_size = 8192, 152 .aggr_time_limit = 500, 153 .aggr_close_eof = true, 154 }, 155 }, 156 }, 157 }, 158 [IPA_ENDPOINT_MODEM_AP_TX] = { 159 .ee_id = GSI_EE_MODEM, 160 .channel_id = 0, 161 .endpoint_id = 12, 162 .toward_ipa = true, 163 .endpoint = { 164 .filter_support = true, 165 }, 166 }, 167 [IPA_ENDPOINT_MODEM_AP_RX] = { 168 .ee_id = GSI_EE_MODEM, 169 .channel_id = 7, 170 .endpoint_id = 21, 171 .toward_ipa = false, 172 }, 173 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 174 .ee_id = GSI_EE_MODEM, 175 .channel_id = 2, 176 .endpoint_id = 15, 177 .toward_ipa = true, 178 .endpoint = { 179 .filter_support = true, 180 }, 181 }, 182 }; 183 184 /* Source resource configuration data for an SoC having IPA v5.0 */ 185 static const struct ipa_resource ipa_resource_src[] = { 186 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 187 .limits[IPA_RSRC_GROUP_SRC_UL] = { 188 .min = 3, .max = 9, 189 }, 190 .limits[IPA_RSRC_GROUP_SRC_DL] = { 191 .min = 4, .max = 10, 192 }, 193 .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 194 .min = 1, .max = 63, 195 }, 196 .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = { 197 .min = 0, .max = 63, 198 }, 199 }, 200 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 201 .limits[IPA_RSRC_GROUP_SRC_UL] = { 202 .min = 9, .max = 9, 203 }, 204 .limits[IPA_RSRC_GROUP_SRC_DL] = { 205 .min = 12, .max = 12, 206 }, 207 .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 208 .min = 10, .max = 10, 209 }, 210 }, 211 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 212 .limits[IPA_RSRC_GROUP_SRC_UL] = { 213 .min = 9, .max = 9, 214 }, 215 .limits[IPA_RSRC_GROUP_SRC_DL] = { 216 .min = 24, .max = 24, 217 }, 218 .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 219 .min = 20, .max = 20, 220 }, 221 }, 222 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 223 .limits[IPA_RSRC_GROUP_SRC_UL] = { 224 .min = 0, .max = 63, 225 }, 226 .limits[IPA_RSRC_GROUP_SRC_DL] = { 227 .min = 0, .max = 63, 228 }, 229 .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 230 .min = 1, .max = 63, 231 }, 232 .limits[IPA_RSRC_GROUP_SRC_U_RX_QC] = { 233 .min = 0, .max = 63, 234 }, 235 }, 236 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 237 .limits[IPA_RSRC_GROUP_SRC_UL] = { 238 .min = 22, .max = 22, 239 }, 240 .limits[IPA_RSRC_GROUP_SRC_DL] = { 241 .min = 16, .max = 16, 242 }, 243 .limits[IPA_RSRC_GROUP_SRC_URLLC] = { 244 .min = 16, .max = 16, 245 }, 246 }, 247 }; 248 249 /* Destination resource configuration data for an SoC having IPA v5.0 */ 250 static const struct ipa_resource ipa_resource_dst[] = { 251 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 252 .limits[IPA_RSRC_GROUP_DST_UL] = { 253 .min = 6, .max = 6, 254 }, 255 .limits[IPA_RSRC_GROUP_DST_DL] = { 256 .min = 5, .max = 5, 257 }, 258 .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { 259 .min = 39, .max = 39, 260 }, 261 }, 262 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 263 .limits[IPA_RSRC_GROUP_DST_UL] = { 264 .min = 0, .max = 3, 265 }, 266 .limits[IPA_RSRC_GROUP_DST_DL] = { 267 .min = 0, .max = 3, 268 }, 269 }, 270 [IPA_RESOURCE_TYPE_DST_ULSO_SEGMENTS] = { 271 .limits[IPA_RSRC_GROUP_DST_UL] = { 272 .min = 0, .max = 63, 273 }, 274 .limits[IPA_RSRC_GROUP_DST_DL] = { 275 .min = 0, .max = 63, 276 }, 277 }, 278 }; 279 280 /* Resource configuration data for an SoC having IPA v5.0 */ 281 static const struct ipa_resource_data ipa_resource_data = { 282 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 283 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 284 .resource_src_count = ARRAY_SIZE(ipa_resource_src), 285 .resource_src = ipa_resource_src, 286 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 287 .resource_dst = ipa_resource_dst, 288 }; 289 290 /* IPA-resident memory region data for an SoC having IPA v5.0 */ 291 static const struct ipa_mem ipa_mem_local_data[] = { 292 { 293 .id = IPA_MEM_UC_EVENT_RING, 294 .offset = 0x0000, 295 .size = 0x1000, 296 .canary_count = 0, 297 }, 298 { 299 .id = IPA_MEM_UC_SHARED, 300 .offset = 0x1000, 301 .size = 0x0080, 302 .canary_count = 0, 303 }, 304 { 305 .id = IPA_MEM_UC_INFO, 306 .offset = 0x1080, 307 .size = 0x0200, 308 .canary_count = 0, 309 }, 310 { 311 .id = IPA_MEM_V4_FILTER_HASHED, 312 .offset = 0x1288, 313 .size = 0x0078, 314 .canary_count = 2, 315 }, 316 { 317 .id = IPA_MEM_V4_FILTER, 318 .offset = 0x1308, 319 .size = 0x0078, 320 .canary_count = 2, 321 }, 322 { 323 .id = IPA_MEM_V6_FILTER_HASHED, 324 .offset = 0x1388, 325 .size = 0x0078, 326 .canary_count = 2, 327 }, 328 { 329 .id = IPA_MEM_V6_FILTER, 330 .offset = 0x1408, 331 .size = 0x0078, 332 .canary_count = 2, 333 }, 334 { 335 .id = IPA_MEM_V4_ROUTE_HASHED, 336 .offset = 0x1488, 337 .size = 0x0098, 338 .canary_count = 2, 339 }, 340 { 341 .id = IPA_MEM_V4_ROUTE, 342 .offset = 0x1528, 343 .size = 0x0098, 344 .canary_count = 2, 345 }, 346 { 347 .id = IPA_MEM_V6_ROUTE_HASHED, 348 .offset = 0x15c8, 349 .size = 0x0098, 350 .canary_count = 2, 351 }, 352 { 353 .id = IPA_MEM_V6_ROUTE, 354 .offset = 0x1668, 355 .size = 0x0098, 356 .canary_count = 2, 357 }, 358 { 359 .id = IPA_MEM_MODEM_HEADER, 360 .offset = 0x1708, 361 .size = 0x0240, 362 .canary_count = 2, 363 }, 364 { 365 .id = IPA_MEM_AP_HEADER, 366 .offset = 0x1948, 367 .size = 0x01e0, 368 .canary_count = 0, 369 }, 370 { 371 .id = IPA_MEM_MODEM_PROC_CTX, 372 .offset = 0x1b40, 373 .size = 0x0b20, 374 .canary_count = 2, 375 }, 376 { 377 .id = IPA_MEM_AP_PROC_CTX, 378 .offset = 0x2660, 379 .size = 0x0200, 380 .canary_count = 0, 381 }, 382 { 383 .id = IPA_MEM_STATS_QUOTA_MODEM, 384 .offset = 0x2868, 385 .size = 0x0060, 386 .canary_count = 2, 387 }, 388 { 389 .id = IPA_MEM_STATS_QUOTA_AP, 390 .offset = 0x28c8, 391 .size = 0x0048, 392 .canary_count = 0, 393 }, 394 { 395 .id = IPA_MEM_AP_V4_FILTER, 396 .offset = 0x2918, 397 .size = 0x0118, 398 .canary_count = 2, 399 }, 400 { 401 .id = IPA_MEM_AP_V6_FILTER, 402 .offset = 0x2aa0, 403 .size = 0x0228, 404 .canary_count = 0, 405 }, 406 { 407 .id = IPA_MEM_STATS_FILTER_ROUTE, 408 .offset = 0x2cd0, 409 .size = 0x0ba0, 410 .canary_count = 2, 411 }, 412 { 413 .id = IPA_MEM_STATS_DROP, 414 .offset = 0x3870, 415 .size = 0x0020, 416 .canary_count = 0, 417 }, 418 { 419 .id = IPA_MEM_MODEM, 420 .offset = 0x3898, 421 .size = 0x0d48, 422 .canary_count = 2, 423 }, 424 { 425 .id = IPA_MEM_NAT_TABLE, 426 .offset = 0x45e0, 427 .size = 0x0900, 428 .canary_count = 0, 429 }, 430 { 431 .id = IPA_MEM_PDN_CONFIG, 432 .offset = 0x4ee8, 433 .size = 0x0100, 434 .canary_count = 2, 435 }, 436 }; 437 438 /* Memory configuration data for an SoC having IPA v5.0 */ 439 static const struct ipa_mem_data ipa_mem_data = { 440 .local_count = ARRAY_SIZE(ipa_mem_local_data), 441 .local = ipa_mem_local_data, 442 .imem_addr = 0x14688000, 443 .imem_size = 0x00003000, 444 .smem_id = 497, 445 .smem_size = 0x00009000, 446 }; 447 448 /* Interconnect rates are in 1000 byte/second units */ 449 static const struct ipa_interconnect_data ipa_interconnect_data[] = { 450 { 451 .name = "memory", 452 .peak_bandwidth = 1900000, /* 1.9 GBps */ 453 .average_bandwidth = 600000, /* 600 MBps */ 454 }, 455 /* Average rate is unused for the next interconnect */ 456 { 457 .name = "config", 458 .peak_bandwidth = 76800, /* 76.8 MBps */ 459 .average_bandwidth = 0, /* unused */ 460 }, 461 }; 462 463 /* Clock and interconnect configuration data for an SoC having IPA v5.0 */ 464 static const struct ipa_power_data ipa_power_data = { 465 .core_clock_rate = 120 * 1000 * 1000, /* Hz */ 466 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 467 .interconnect_data = ipa_interconnect_data, 468 }; 469 470 /* Configuration data for an SoC having IPA v5.0. */ 471 const struct ipa_data ipa_data_v5_0 = { 472 .version = IPA_VERSION_5_0, 473 .qsb_count = ARRAY_SIZE(ipa_qsb_data), 474 .qsb_data = ipa_qsb_data, 475 .modem_route_count = 11, 476 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 477 .endpoint_data = ipa_gsi_endpoint_data, 478 .resource_data = &ipa_resource_data, 479 .mem_data = &ipa_mem_data, 480 .power_data = &ipa_power_data, 481 }; 482