xref: /linux/drivers/net/ipa/data/ipa_data-v4.9.c (revision afeea2758b4f1210361ce2a91d8fa3e7df606ad2) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2021-2024 Linaro Ltd. */
4 
5 #include <linux/array_size.h>
6 #include <linux/log2.h>
7 
8 #include "../ipa_data.h"
9 #include "../ipa_endpoint.h"
10 #include "../ipa_mem.h"
11 #include "../ipa_version.h"
12 
13 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.9 */
14 enum ipa_resource_type {
15 	/* Source resource types; first must have value 0 */
16 	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,
17 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
18 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
19 	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
20 	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
21 
22 	/* Destination resource types; first must have value 0 */
23 	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,
24 	IPA_RESOURCE_TYPE_DST_DPS_DMARS,
25 };
26 
27 /* Resource groups used for an SoC having IPA v4.9 */
28 enum ipa_rsrc_group_id {
29 	/* Source resource group identifiers */
30 	IPA_RSRC_GROUP_SRC_UL_DL			= 0,
31 	IPA_RSRC_GROUP_SRC_DMA,
32 	IPA_RSRC_GROUP_SRC_UC_RX_Q,
33 	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */
34 
35 	/* Destination resource group identifiers */
36 	IPA_RSRC_GROUP_DST_UL_DL_DPL			= 0,
37 	IPA_RSRC_GROUP_DST_DMA,
38 	IPA_RSRC_GROUP_DST_UC,
39 	IPA_RSRC_GROUP_DST_DRB_IP,
40 	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */
41 };
42 
43 /* QSB configuration data for an SoC having IPA v4.9 */
44 static const struct ipa_qsb_data ipa_qsb_data[] = {
45 	[IPA_QSB_MASTER_DDR] = {
46 		.max_writes		= 8,
47 		.max_reads		= 0,	/* no limit (hardware max) */
48 		.max_reads_beats	= 120,
49 	},
50 };
51 
52 /* Endpoint configuration data for an SoC having IPA v4.9 */
53 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
54 	[IPA_ENDPOINT_AP_COMMAND_TX] = {
55 		.ee_id		= GSI_EE_AP,
56 		.channel_id	= 6,
57 		.endpoint_id	= 7,
58 		.toward_ipa	= true,
59 		.channel = {
60 			.tre_count	= 256,
61 			.event_count	= 256,
62 			.tlv_count	= 20,
63 		},
64 		.endpoint = {
65 			.config = {
66 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
67 				.dma_mode	= true,
68 				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,
69 				.tx = {
70 					.seq_type = IPA_SEQ_DMA,
71 				},
72 			},
73 		},
74 	},
75 	[IPA_ENDPOINT_AP_LAN_RX] = {
76 		.ee_id		= GSI_EE_AP,
77 		.channel_id	= 7,
78 		.endpoint_id	= 11,
79 		.toward_ipa	= false,
80 		.channel = {
81 			.tre_count	= 256,
82 			.event_count	= 256,
83 			.tlv_count	= 9,
84 		},
85 		.endpoint = {
86 			.config = {
87 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
88 				.aggregation	= true,
89 				.status_enable	= true,
90 				.rx = {
91 					.buffer_size	= 8192,
92 					.pad_align	= ilog2(sizeof(u32)),
93 					.aggr_time_limit = 500,
94 				},
95 			},
96 		},
97 	},
98 	[IPA_ENDPOINT_AP_MODEM_TX] = {
99 		.ee_id		= GSI_EE_AP,
100 		.channel_id	= 2,
101 		.endpoint_id	= 2,
102 		.toward_ipa	= true,
103 		.channel = {
104 			.tre_count	= 512,
105 			.event_count	= 512,
106 			.tlv_count	= 16,
107 		},
108 		.endpoint = {
109 			.filter_support	= true,
110 			.config = {
111 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
112 				.checksum       = true,
113 				.qmap		= true,
114 				.status_enable	= true,
115 				.tx = {
116 					.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
117 					.status_endpoint =
118 						IPA_ENDPOINT_MODEM_AP_RX,
119 				},
120 			},
121 		},
122 	},
123 	[IPA_ENDPOINT_AP_MODEM_RX] = {
124 		.ee_id		= GSI_EE_AP,
125 		.channel_id	= 12,
126 		.endpoint_id	= 20,
127 		.toward_ipa	= false,
128 		.channel = {
129 			.tre_count	= 256,
130 			.event_count	= 256,
131 			.tlv_count	= 9,
132 		},
133 		.endpoint = {
134 			.config = {
135 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
136 				.checksum       = true,
137 				.qmap		= true,
138 				.aggregation	= true,
139 				.rx = {
140 					.buffer_size	= 8192,
141 					.aggr_time_limit = 500,
142 					.aggr_close_eof	= true,
143 				},
144 			},
145 		},
146 	},
147 	[IPA_ENDPOINT_MODEM_AP_TX] = {
148 		.ee_id		= GSI_EE_MODEM,
149 		.channel_id	= 0,
150 		.endpoint_id	= 5,
151 		.toward_ipa	= true,
152 		.endpoint = {
153 			.filter_support	= true,
154 		},
155 	},
156 	[IPA_ENDPOINT_MODEM_AP_RX] = {
157 		.ee_id		= GSI_EE_MODEM,
158 		.channel_id	= 7,
159 		.endpoint_id	= 16,
160 		.toward_ipa	= false,
161 	},
162 	[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
163 		.ee_id		= GSI_EE_MODEM,
164 		.channel_id	= 2,
165 		.endpoint_id	= 8,
166 		.toward_ipa	= true,
167 		.endpoint = {
168 			.filter_support	= true,
169 		},
170 	},
171 };
172 
173 /* Source resource configuration data for an SoC having IPA v4.9 */
174 static const struct ipa_resource ipa_resource_src[] = {
175 	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
176 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
177 			.min = 1,	.max = 12,
178 		},
179 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
180 			.min = 1,	.max = 1,
181 		},
182 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
183 			.min = 1,	.max = 12,
184 		},
185 	},
186 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
187 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
188 			.min = 20,	.max = 20,
189 		},
190 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
191 			.min = 2,	.max = 2,
192 		},
193 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
194 			.min = 3,	.max = 3,
195 		},
196 	},
197 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
198 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
199 			.min = 38,	.max = 38,
200 		},
201 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
202 			.min = 4,	.max = 4,
203 		},
204 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
205 			.min = 8,	.max = 8,
206 		},
207 	},
208 	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
209 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
210 			.min = 0,	.max = 4,
211 		},
212 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
213 			.min = 0,	.max = 4,
214 		},
215 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
216 			.min = 0,	.max = 4,
217 		},
218 	},
219 	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
220 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
221 			.min = 30,	.max = 30,
222 		},
223 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
224 			.min = 8,	.max = 8,
225 		},
226 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
227 			.min = 8,	.max = 8,
228 		},
229 	},
230 };
231 
232 /* Destination resource configuration data for an SoC having IPA v4.9 */
233 static const struct ipa_resource ipa_resource_dst[] = {
234 	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
235 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
236 			.min = 9,	.max = 9,
237 		},
238 		.limits[IPA_RSRC_GROUP_DST_DMA] = {
239 			.min = 1,	.max = 1,
240 		},
241 		.limits[IPA_RSRC_GROUP_DST_UC] = {
242 			.min = 1,	.max = 1,
243 		},
244 		.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
245 			.min = 39,	.max = 39,
246 		},
247 	},
248 	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
249 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
250 			.min = 2,	.max = 3,
251 		},
252 		.limits[IPA_RSRC_GROUP_DST_DMA] = {
253 			.min = 1,	.max = 2,
254 		},
255 		.limits[IPA_RSRC_GROUP_DST_UC] = {
256 			.min = 0,	.max = 2,
257 		},
258 	},
259 };
260 
261 /* Resource configuration data for an SoC having IPA v4.9 */
262 static const struct ipa_resource_data ipa_resource_data = {
263 	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,
264 	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,
265 	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),
266 	.resource_src		= ipa_resource_src,
267 	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),
268 	.resource_dst		= ipa_resource_dst,
269 };
270 
271 /* IPA-resident memory region data for an SoC having IPA v4.9 */
272 static const struct ipa_mem ipa_mem_local_data[] = {
273 	{
274 		.id		= IPA_MEM_UC_SHARED,
275 		.offset		= 0x0000,
276 		.size		= 0x0080,
277 		.canary_count	= 0,
278 	},
279 	{
280 		.id		= IPA_MEM_UC_INFO,
281 		.offset		= 0x0080,
282 		.size		= 0x0200,
283 		.canary_count	= 0,
284 	},
285 	{
286 		.id		= IPA_MEM_V4_FILTER_HASHED,
287 		.offset		= 0x0288,
288 		.size		= 0x0078,
289 		.canary_count	= 2,
290 	},
291 	{
292 		.id		= IPA_MEM_V4_FILTER,
293 		.offset		= 0x0308,
294 		.size		= 0x0078,
295 		.canary_count	= 2,
296 	},
297 	{
298 		.id		= IPA_MEM_V6_FILTER_HASHED,
299 		.offset		= 0x0388,
300 		.size		= 0x0078,
301 		.canary_count	= 2,
302 	},
303 	{
304 		.id		= IPA_MEM_V6_FILTER,
305 		.offset		= 0x0408,
306 		.size		= 0x0078,
307 		.canary_count	= 2,
308 	},
309 	{
310 		.id		= IPA_MEM_V4_ROUTE_HASHED,
311 		.offset		= 0x0488,
312 		.size		= 0x0078,
313 		.canary_count	= 2,
314 	},
315 	{
316 		.id		= IPA_MEM_V4_ROUTE,
317 		.offset		= 0x0508,
318 		.size		= 0x0078,
319 		.canary_count	= 2,
320 	},
321 	{
322 		.id		= IPA_MEM_V6_ROUTE_HASHED,
323 		.offset		= 0x0588,
324 		.size		= 0x0078,
325 		.canary_count	= 2,
326 	},
327 	{
328 		.id		= IPA_MEM_V6_ROUTE,
329 		.offset		= 0x0608,
330 		.size		= 0x0078,
331 		.canary_count	= 2,
332 	},
333 	{
334 		.id		= IPA_MEM_MODEM_HEADER,
335 		.offset		= 0x0688,
336 		.size		= 0x0240,
337 		.canary_count	= 2,
338 	},
339 	{
340 		.id		= IPA_MEM_AP_HEADER,
341 		.offset		= 0x08c8,
342 		.size		= 0x0200,
343 		.canary_count	= 0,
344 	},
345 	{
346 		.id		= IPA_MEM_MODEM_PROC_CTX,
347 		.offset		= 0x0ad0,
348 		.size		= 0x0b20,
349 		.canary_count	= 2,
350 	},
351 	{
352 		.id		= IPA_MEM_AP_PROC_CTX,
353 		.offset		= 0x15f0,
354 		.size		= 0x0200,
355 		.canary_count	= 0,
356 	},
357 	{
358 		.id		= IPA_MEM_NAT_TABLE,
359 		.offset		= 0x1800,
360 		.size		= 0x0d00,
361 		.canary_count	= 4,
362 	},
363 	{
364 		.id		= IPA_MEM_STATS_QUOTA_MODEM,
365 		.offset		= 0x2510,
366 		.size		= 0x0030,
367 		.canary_count	= 4,
368 	},
369 	{
370 		.id		= IPA_MEM_STATS_QUOTA_AP,
371 		.offset		= 0x2540,
372 		.size		= 0x0048,
373 		.canary_count	= 0,
374 	},
375 	{
376 		.id		= IPA_MEM_STATS_TETHERING,
377 		.offset		= 0x2588,
378 		.size		= 0x0238,
379 		.canary_count	= 0,
380 	},
381 	{
382 		.id		= IPA_MEM_STATS_FILTER_ROUTE,
383 		.offset		= 0x27c0,
384 		.size		= 0x0800,
385 		.canary_count	= 0,
386 	},
387 	{
388 		.id		= IPA_MEM_STATS_DROP,
389 		.offset		= 0x2fc0,
390 		.size		= 0x0020,
391 		.canary_count	= 0,
392 	},
393 	{
394 		.id		= IPA_MEM_MODEM,
395 		.offset		= 0x2fe8,
396 		.size		= 0x0800,
397 		.canary_count	= 2,
398 	},
399 	{
400 		.id		= IPA_MEM_UC_EVENT_RING,
401 		.offset		= 0x3800,
402 		.size		= 0x1000,
403 		.canary_count	= 1,
404 	},
405 	{
406 		.id		= IPA_MEM_PDN_CONFIG,
407 		.offset		= 0x4800,
408 		.size		= 0x0050,
409 		.canary_count	= 0,
410 	},
411 };
412 
413 /* Memory configuration data for an SoC having IPA v4.9 */
414 static const struct ipa_mem_data ipa_mem_data = {
415 	.local_count	= ARRAY_SIZE(ipa_mem_local_data),
416 	.local		= ipa_mem_local_data,
417 	.imem_addr	= 0x146bd000,
418 	.imem_size	= 0x00002000,
419 	.smem_id	= 497,
420 	.smem_size	= 0x00009000,
421 };
422 
423 /* Interconnect rates are in 1000 byte/second units */
424 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
425 	{
426 		.name			= "memory",
427 		.peak_bandwidth		= 600000,	/* 600 MBps */
428 		.average_bandwidth	= 150000,	/* 150 MBps */
429 	},
430 	/* Average rate is unused for the next interconnect */
431 	{
432 		.name			= "config",
433 		.peak_bandwidth		= 74000,	/* 74 MBps */
434 		.average_bandwidth	= 0,		/* unused */
435 	},
436 
437 };
438 
439 /* Clock and interconnect configuration data for an SoC having IPA v4.9 */
440 static const struct ipa_power_data ipa_power_data = {
441 	.core_clock_rate	= 60 * 1000 * 1000,	/* Hz */
442 	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),
443 	.interconnect_data	= ipa_interconnect_data,
444 };
445 
446 /* Configuration data for an SoC having IPA v4.9. */
447 const struct ipa_data ipa_data_v4_9 = {
448 	.version		= IPA_VERSION_4_9,
449 	.qsb_count		= ARRAY_SIZE(ipa_qsb_data),
450 	.qsb_data		= ipa_qsb_data,
451 	.modem_route_count	= 8,
452 	.endpoint_count		= ARRAY_SIZE(ipa_gsi_endpoint_data),
453 	.endpoint_data		= ipa_gsi_endpoint_data,
454 	.resource_data		= &ipa_resource_data,
455 	.mem_data		= &ipa_mem_data,
456 	.power_data		= &ipa_power_data,
457 };
458