xref: /linux/drivers/net/ipa/data/ipa_data-v4.9.c (revision 0e9ab8e4d44ae9d9aaf213bfd2c90bbe7289337b) 
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /* Copyright (C) 2021 Linaro Ltd. */
4 
5 #include <linux/log2.h>
6 
7 #include "../gsi.h"
8 #include "../ipa_data.h"
9 #include "../ipa_endpoint.h"
10 #include "../ipa_mem.h"
11 
12 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.9 */
13 enum ipa_resource_type {
14 	/* Source resource types; first must have value 0 */
15 	IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS		= 0,
16 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
17 	IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
18 	IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
19 	IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
20 
21 	/* Destination resource types; first must have value 0 */
22 	IPA_RESOURCE_TYPE_DST_DATA_SECTORS		= 0,
23 	IPA_RESOURCE_TYPE_DST_DPS_DMARS,
24 };
25 
26 /* Resource groups used for an SoC having IPA v4.9 */
27 enum ipa_rsrc_group_id {
28 	/* Source resource group identifiers */
29 	IPA_RSRC_GROUP_SRC_UL_DL			= 0,
30 	IPA_RSRC_GROUP_SRC_DMA,
31 	IPA_RSRC_GROUP_SRC_UC_RX_Q,
32 	IPA_RSRC_GROUP_SRC_COUNT,	/* Last in set; not a source group */
33 
34 	/* Destination resource group identifiers */
35 	IPA_RSRC_GROUP_DST_UL_DL_DPL			= 0,
36 	IPA_RSRC_GROUP_DST_DMA,
37 	IPA_RSRC_GROUP_DST_UC,
38 	IPA_RSRC_GROUP_DST_DRB_IP,
39 	IPA_RSRC_GROUP_DST_COUNT,	/* Last; not a destination group */
40 };
41 
42 /* QSB configuration data for an SoC having IPA v4.9 */
43 static const struct ipa_qsb_data ipa_qsb_data[] = {
44 	[IPA_QSB_MASTER_DDR] = {
45 		.max_writes		= 8,
46 		.max_reads		= 0,	/* no limit (hardware max) */
47 		.max_reads_beats	= 120,
48 	},
49 };
50 
51 /* Endpoint configuration data for an SoC having IPA v4.9 */
52 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
53 	[IPA_ENDPOINT_AP_COMMAND_TX] = {
54 		.ee_id		= GSI_EE_AP,
55 		.channel_id	= 6,
56 		.endpoint_id	= 7,
57 		.toward_ipa	= true,
58 		.channel = {
59 			.tre_count	= 256,
60 			.event_count	= 256,
61 			.tlv_count	= 20,
62 		},
63 		.endpoint = {
64 			.config = {
65 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
66 				.dma_mode	= true,
67 				.dma_endpoint	= IPA_ENDPOINT_AP_LAN_RX,
68 				.tx = {
69 					.seq_type = IPA_SEQ_DMA,
70 				},
71 			},
72 		},
73 	},
74 	[IPA_ENDPOINT_AP_LAN_RX] = {
75 		.ee_id		= GSI_EE_AP,
76 		.channel_id	= 7,
77 		.endpoint_id	= 11,
78 		.toward_ipa	= false,
79 		.channel = {
80 			.tre_count	= 256,
81 			.event_count	= 256,
82 			.tlv_count	= 9,
83 		},
84 		.endpoint = {
85 			.config = {
86 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
87 				.aggregation	= true,
88 				.status_enable	= true,
89 				.rx = {
90 					.buffer_size	= 8192,
91 					.pad_align	= ilog2(sizeof(u32)),
92 					.aggr_time_limit = 500,
93 				},
94 			},
95 		},
96 	},
97 	[IPA_ENDPOINT_AP_MODEM_TX] = {
98 		.ee_id		= GSI_EE_AP,
99 		.channel_id	= 2,
100 		.endpoint_id	= 2,
101 		.toward_ipa	= true,
102 		.channel = {
103 			.tre_count	= 512,
104 			.event_count	= 512,
105 			.tlv_count	= 16,
106 		},
107 		.endpoint = {
108 			.filter_support	= true,
109 			.config = {
110 				.resource_group	= IPA_RSRC_GROUP_SRC_UL_DL,
111 				.checksum       = true,
112 				.qmap		= true,
113 				.status_enable	= true,
114 				.tx = {
115 					.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
116 					.status_endpoint =
117 						IPA_ENDPOINT_MODEM_AP_RX,
118 				},
119 			},
120 		},
121 	},
122 	[IPA_ENDPOINT_AP_MODEM_RX] = {
123 		.ee_id		= GSI_EE_AP,
124 		.channel_id	= 12,
125 		.endpoint_id	= 20,
126 		.toward_ipa	= false,
127 		.channel = {
128 			.tre_count	= 256,
129 			.event_count	= 256,
130 			.tlv_count	= 9,
131 		},
132 		.endpoint = {
133 			.config = {
134 				.resource_group	= IPA_RSRC_GROUP_DST_UL_DL_DPL,
135 				.checksum       = true,
136 				.qmap		= true,
137 				.aggregation	= true,
138 				.rx = {
139 					.buffer_size	= 8192,
140 					.aggr_time_limit = 500,
141 					.aggr_close_eof	= true,
142 				},
143 			},
144 		},
145 	},
146 	[IPA_ENDPOINT_MODEM_AP_TX] = {
147 		.ee_id		= GSI_EE_MODEM,
148 		.channel_id	= 0,
149 		.endpoint_id	= 5,
150 		.toward_ipa	= true,
151 		.endpoint = {
152 			.filter_support	= true,
153 		},
154 	},
155 	[IPA_ENDPOINT_MODEM_AP_RX] = {
156 		.ee_id		= GSI_EE_MODEM,
157 		.channel_id	= 7,
158 		.endpoint_id	= 16,
159 		.toward_ipa	= false,
160 	},
161 	[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
162 		.ee_id		= GSI_EE_MODEM,
163 		.channel_id	= 2,
164 		.endpoint_id	= 8,
165 		.toward_ipa	= true,
166 		.endpoint = {
167 			.filter_support	= true,
168 		},
169 	},
170 };
171 
172 /* Source resource configuration data for an SoC having IPA v4.9 */
173 static const struct ipa_resource ipa_resource_src[] = {
174 	[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
175 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
176 			.min = 1,	.max = 12,
177 		},
178 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
179 			.min = 1,	.max = 1,
180 		},
181 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
182 			.min = 1,	.max = 12,
183 		},
184 	},
185 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
186 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
187 			.min = 20,	.max = 20,
188 		},
189 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
190 			.min = 2,	.max = 2,
191 		},
192 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
193 			.min = 3,	.max = 3,
194 		},
195 	},
196 	[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
197 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
198 			.min = 38,	.max = 38,
199 		},
200 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
201 			.min = 4,	.max = 4,
202 		},
203 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
204 			.min = 8,	.max = 8,
205 		},
206 	},
207 	[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
208 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
209 			.min = 0,	.max = 4,
210 		},
211 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
212 			.min = 0,	.max = 4,
213 		},
214 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
215 			.min = 0,	.max = 4,
216 		},
217 	},
218 	[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
219 		.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
220 			.min = 30,	.max = 30,
221 		},
222 		.limits[IPA_RSRC_GROUP_SRC_DMA] = {
223 			.min = 8,	.max = 8,
224 		},
225 		.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
226 			.min = 8,	.max = 8,
227 		},
228 	},
229 };
230 
231 /* Destination resource configuration data for an SoC having IPA v4.9 */
232 static const struct ipa_resource ipa_resource_dst[] = {
233 	[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
234 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
235 			.min = 9,	.max = 9,
236 		},
237 		.limits[IPA_RSRC_GROUP_DST_DMA] = {
238 			.min = 1,	.max = 1,
239 		},
240 		.limits[IPA_RSRC_GROUP_DST_UC] = {
241 			.min = 1,	.max = 1,
242 		},
243 		.limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
244 			.min = 39,	.max = 39,
245 		},
246 	},
247 	[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
248 		.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
249 			.min = 2,	.max = 3,
250 		},
251 		.limits[IPA_RSRC_GROUP_DST_DMA] = {
252 			.min = 1,	.max = 2,
253 		},
254 		.limits[IPA_RSRC_GROUP_DST_UC] = {
255 			.min = 0,	.max = 2,
256 		},
257 	},
258 };
259 
260 /* Resource configuration data for an SoC having IPA v4.9 */
261 static const struct ipa_resource_data ipa_resource_data = {
262 	.rsrc_group_dst_count	= IPA_RSRC_GROUP_DST_COUNT,
263 	.rsrc_group_src_count	= IPA_RSRC_GROUP_SRC_COUNT,
264 	.resource_src_count	= ARRAY_SIZE(ipa_resource_src),
265 	.resource_src		= ipa_resource_src,
266 	.resource_dst_count	= ARRAY_SIZE(ipa_resource_dst),
267 	.resource_dst		= ipa_resource_dst,
268 };
269 
270 /* IPA-resident memory region data for an SoC having IPA v4.9 */
271 static const struct ipa_mem ipa_mem_local_data[] = {
272 	{
273 		.id		= IPA_MEM_UC_SHARED,
274 		.offset		= 0x0000,
275 		.size		= 0x0080,
276 		.canary_count	= 0,
277 	},
278 	{
279 		.id		= IPA_MEM_UC_INFO,
280 		.offset		= 0x0080,
281 		.size		= 0x0200,
282 		.canary_count	= 0,
283 	},
284 	{
285 		.id		= IPA_MEM_V4_FILTER_HASHED,
286 		.offset		= 0x0288,
287 		.size		= 0x0078,
288 		.canary_count	= 2,
289 	},
290 	{
291 		.id		= IPA_MEM_V4_FILTER,
292 		.offset		= 0x0308,
293 		.size		= 0x0078,
294 		.canary_count	= 2,
295 	},
296 	{
297 		.id		= IPA_MEM_V6_FILTER_HASHED,
298 		.offset		= 0x0388,
299 		.size		= 0x0078,
300 		.canary_count	= 2,
301 	},
302 	{
303 		.id		= IPA_MEM_V6_FILTER,
304 		.offset		= 0x0408,
305 		.size		= 0x0078,
306 		.canary_count	= 2,
307 	},
308 	{
309 		.id		= IPA_MEM_V4_ROUTE_HASHED,
310 		.offset		= 0x0488,
311 		.size		= 0x0078,
312 		.canary_count	= 2,
313 	},
314 	{
315 		.id		= IPA_MEM_V4_ROUTE,
316 		.offset		= 0x0508,
317 		.size		= 0x0078,
318 		.canary_count	= 2,
319 	},
320 	{
321 		.id		= IPA_MEM_V6_ROUTE_HASHED,
322 		.offset		= 0x0588,
323 		.size		= 0x0078,
324 		.canary_count	= 2,
325 	},
326 	{
327 		.id		= IPA_MEM_V6_ROUTE,
328 		.offset		= 0x0608,
329 		.size		= 0x0078,
330 		.canary_count	= 2,
331 	},
332 	{
333 		.id		= IPA_MEM_MODEM_HEADER,
334 		.offset		= 0x0688,
335 		.size		= 0x0240,
336 		.canary_count	= 2,
337 	},
338 	{
339 		.id		= IPA_MEM_AP_HEADER,
340 		.offset		= 0x08c8,
341 		.size		= 0x0200,
342 		.canary_count	= 0,
343 	},
344 	{
345 		.id		= IPA_MEM_MODEM_PROC_CTX,
346 		.offset		= 0x0ad0,
347 		.size		= 0x0b20,
348 		.canary_count	= 2,
349 	},
350 	{
351 		.id		= IPA_MEM_AP_PROC_CTX,
352 		.offset		= 0x15f0,
353 		.size		= 0x0200,
354 		.canary_count	= 0,
355 	},
356 	{
357 		.id		= IPA_MEM_NAT_TABLE,
358 		.offset		= 0x1800,
359 		.size		= 0x0d00,
360 		.canary_count	= 4,
361 	},
362 	{
363 		.id		= IPA_MEM_STATS_QUOTA_MODEM,
364 		.offset		= 0x2510,
365 		.size		= 0x0030,
366 		.canary_count	= 4,
367 	},
368 	{
369 		.id		= IPA_MEM_STATS_QUOTA_AP,
370 		.offset		= 0x2540,
371 		.size		= 0x0048,
372 		.canary_count	= 0,
373 	},
374 	{
375 		.id		= IPA_MEM_STATS_TETHERING,
376 		.offset		= 0x2588,
377 		.size		= 0x0238,
378 		.canary_count	= 0,
379 	},
380 	{
381 		.id		= IPA_MEM_STATS_FILTER_ROUTE,
382 		.offset		= 0x27c0,
383 		.size		= 0x0800,
384 		.canary_count	= 0,
385 	},
386 	{
387 		.id		= IPA_MEM_STATS_DROP,
388 		.offset		= 0x2fc0,
389 		.size		= 0x0020,
390 		.canary_count	= 0,
391 	},
392 	{
393 		.id		= IPA_MEM_MODEM,
394 		.offset		= 0x2fe8,
395 		.size		= 0x0800,
396 		.canary_count	= 2,
397 	},
398 	{
399 		.id		= IPA_MEM_UC_EVENT_RING,
400 		.offset		= 0x3800,
401 		.size		= 0x1000,
402 		.canary_count	= 1,
403 	},
404 	{
405 		.id		= IPA_MEM_PDN_CONFIG,
406 		.offset		= 0x4800,
407 		.size		= 0x0050,
408 		.canary_count	= 0,
409 	},
410 };
411 
412 /* Memory configuration data for an SoC having IPA v4.9 */
413 static const struct ipa_mem_data ipa_mem_data = {
414 	.local_count	= ARRAY_SIZE(ipa_mem_local_data),
415 	.local		= ipa_mem_local_data,
416 	.imem_addr	= 0x146bd000,
417 	.imem_size	= 0x00002000,
418 	.smem_id	= 497,
419 	.smem_size	= 0x00009000,
420 };
421 
422 /* Interconnect rates are in 1000 byte/second units */
423 static const struct ipa_interconnect_data ipa_interconnect_data[] = {
424 	{
425 		.name			= "memory",
426 		.peak_bandwidth		= 600000,	/* 600 MBps */
427 		.average_bandwidth	= 150000,	/* 150 MBps */
428 	},
429 	/* Average rate is unused for the next interconnect */
430 	{
431 		.name			= "config",
432 		.peak_bandwidth		= 74000,	/* 74 MBps */
433 		.average_bandwidth	= 0,		/* unused */
434 	},
435 
436 };
437 
438 /* Clock and interconnect configuration data for an SoC having IPA v4.9 */
439 static const struct ipa_power_data ipa_power_data = {
440 	.core_clock_rate	= 60 * 1000 * 1000,	/* Hz */
441 	.interconnect_count	= ARRAY_SIZE(ipa_interconnect_data),
442 	.interconnect_data	= ipa_interconnect_data,
443 };
444 
445 /* Configuration data for an SoC having IPA v4.9. */
446 const struct ipa_data ipa_data_v4_9 = {
447 	.version		= IPA_VERSION_4_9,
448 	.qsb_count		= ARRAY_SIZE(ipa_qsb_data),
449 	.qsb_data		= ipa_qsb_data,
450 	.modem_route_count	= 8,
451 	.endpoint_count		= ARRAY_SIZE(ipa_gsi_endpoint_data),
452 	.endpoint_data		= ipa_gsi_endpoint_data,
453 	.resource_data		= &ipa_resource_data,
454 	.mem_data		= &ipa_mem_data,
455 	.power_data		= &ipa_power_data,
456 };
457