1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022 Linaro Ltd. */ 4 5 #include <linux/log2.h> 6 7 #include "../gsi.h" 8 #include "../ipa_data.h" 9 #include "../ipa_endpoint.h" 10 #include "../ipa_mem.h" 11 12 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.7 */ 13 enum ipa_resource_type { 14 /* Source resource types; first must have value 0 */ 15 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 16 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 18 IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 19 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 20 21 /* Destination resource types; first must have value 0 */ 22 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 23 IPA_RESOURCE_TYPE_DST_DPS_DMARS, 24 }; 25 26 /* Resource groups used for an SoC having IPA v4.7 */ 27 enum ipa_rsrc_group_id { 28 /* Source resource group identifiers */ 29 IPA_RSRC_GROUP_SRC_UL_DL = 0, 30 IPA_RSRC_GROUP_SRC_UC_RX_Q, 31 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 32 33 /* Destination resource group identifiers */ 34 IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, 35 IPA_RSRC_GROUP_DST_UNUSED_1, 36 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 37 }; 38 39 /* QSB configuration data for an SoC having IPA v4.7 */ 40 static const struct ipa_qsb_data ipa_qsb_data[] = { 41 [IPA_QSB_MASTER_DDR] = { 42 .max_writes = 8, 43 .max_reads = 0, /* no limit (hardware max) */ 44 .max_reads_beats = 120, 45 }, 46 }; 47 48 /* Endpoint configuration data for an SoC having IPA v4.7 */ 49 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 50 [IPA_ENDPOINT_AP_COMMAND_TX] = { 51 .ee_id = GSI_EE_AP, 52 .channel_id = 5, 53 .endpoint_id = 7, 54 .toward_ipa = true, 55 .channel = { 56 .tre_count = 256, 57 .event_count = 256, 58 .tlv_count = 20, 59 }, 60 .endpoint = { 61 .config = { 62 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 63 .dma_mode = true, 64 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 65 .tx = { 66 .seq_type = IPA_SEQ_DMA, 67 }, 68 }, 69 }, 70 }, 71 [IPA_ENDPOINT_AP_LAN_RX] = { 72 .ee_id = GSI_EE_AP, 73 .channel_id = 14, 74 .endpoint_id = 9, 75 .toward_ipa = false, 76 .channel = { 77 .tre_count = 256, 78 .event_count = 256, 79 .tlv_count = 9, 80 }, 81 .endpoint = { 82 .config = { 83 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 84 .aggregation = true, 85 .status_enable = true, 86 .rx = { 87 .buffer_size = 8192, 88 .pad_align = ilog2(sizeof(u32)), 89 .aggr_time_limit = 500, 90 }, 91 }, 92 }, 93 }, 94 [IPA_ENDPOINT_AP_MODEM_TX] = { 95 .ee_id = GSI_EE_AP, 96 .channel_id = 2, 97 .endpoint_id = 2, 98 .toward_ipa = true, 99 .channel = { 100 .tre_count = 512, 101 .event_count = 512, 102 .tlv_count = 16, 103 }, 104 .endpoint = { 105 .filter_support = true, 106 .config = { 107 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 108 .qmap = true, 109 .status_enable = true, 110 .tx = { 111 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 112 .status_endpoint = 113 IPA_ENDPOINT_MODEM_AP_RX, 114 }, 115 }, 116 }, 117 }, 118 [IPA_ENDPOINT_AP_MODEM_RX] = { 119 .ee_id = GSI_EE_AP, 120 .channel_id = 7, 121 .endpoint_id = 16, 122 .toward_ipa = false, 123 .channel = { 124 .tre_count = 256, 125 .event_count = 256, 126 .tlv_count = 9, 127 }, 128 .endpoint = { 129 .config = { 130 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 131 .qmap = true, 132 .aggregation = true, 133 .rx = { 134 .buffer_size = 8192, 135 .aggr_time_limit = 500, 136 .aggr_close_eof = true, 137 }, 138 }, 139 }, 140 }, 141 [IPA_ENDPOINT_MODEM_AP_TX] = { 142 .ee_id = GSI_EE_MODEM, 143 .channel_id = 0, 144 .endpoint_id = 5, 145 .toward_ipa = true, 146 .endpoint = { 147 .filter_support = true, 148 }, 149 }, 150 [IPA_ENDPOINT_MODEM_AP_RX] = { 151 .ee_id = GSI_EE_MODEM, 152 .channel_id = 7, 153 .endpoint_id = 14, 154 .toward_ipa = false, 155 }, 156 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 157 .ee_id = GSI_EE_MODEM, 158 .channel_id = 2, 159 .endpoint_id = 8, 160 .toward_ipa = true, 161 .endpoint = { 162 .filter_support = true, 163 }, 164 }, 165 }; 166 167 /* Source resource configuration data for an SoC having IPA v4.7 */ 168 static const struct ipa_resource ipa_resource_src[] = { 169 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 170 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 171 .min = 8, .max = 8, 172 }, 173 }, 174 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 175 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 176 .min = 8, .max = 8, 177 }, 178 }, 179 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 180 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 181 .min = 18, .max = 18, 182 }, 183 }, 184 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 185 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 186 .min = 2, .max = 2, 187 }, 188 }, 189 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 190 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 191 .min = 15, .max = 15, 192 }, 193 }, 194 }; 195 196 /* Destination resource configuration data for an SoC having IPA v4.7 */ 197 static const struct ipa_resource ipa_resource_dst[] = { 198 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 199 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 200 .min = 7, .max = 7, 201 }, 202 }, 203 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 204 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 205 .min = 2, .max = 2, 206 }, 207 }, 208 }; 209 210 /* Resource configuration data for an SoC having IPA v4.7 */ 211 static const struct ipa_resource_data ipa_resource_data = { 212 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 213 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 214 .resource_src_count = ARRAY_SIZE(ipa_resource_src), 215 .resource_src = ipa_resource_src, 216 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 217 .resource_dst = ipa_resource_dst, 218 }; 219 220 /* IPA-resident memory region data for an SoC having IPA v4.7 */ 221 static const struct ipa_mem ipa_mem_local_data[] = { 222 { 223 .id = IPA_MEM_UC_SHARED, 224 .offset = 0x0000, 225 .size = 0x0080, 226 .canary_count = 0, 227 }, 228 { 229 .id = IPA_MEM_UC_INFO, 230 .offset = 0x0080, 231 .size = 0x0200, 232 .canary_count = 0, 233 }, 234 { 235 .id = IPA_MEM_V4_FILTER_HASHED, 236 .offset = 0x0288, 237 .size = 0x0078, 238 .canary_count = 2, 239 }, 240 { 241 .id = IPA_MEM_V4_FILTER, 242 .offset = 0x0308, 243 .size = 0x0078, 244 .canary_count = 2, 245 }, 246 { 247 .id = IPA_MEM_V6_FILTER_HASHED, 248 .offset = 0x0388, 249 .size = 0x0078, 250 .canary_count = 2, 251 }, 252 { 253 .id = IPA_MEM_V6_FILTER, 254 .offset = 0x0408, 255 .size = 0x0078, 256 .canary_count = 2, 257 }, 258 { 259 .id = IPA_MEM_V4_ROUTE_HASHED, 260 .offset = 0x0488, 261 .size = 0x0078, 262 .canary_count = 2, 263 }, 264 { 265 .id = IPA_MEM_V4_ROUTE, 266 .offset = 0x0508, 267 .size = 0x0078, 268 .canary_count = 2, 269 }, 270 { 271 .id = IPA_MEM_V6_ROUTE_HASHED, 272 .offset = 0x0588, 273 .size = 0x0078, 274 .canary_count = 2, 275 }, 276 { 277 .id = IPA_MEM_V6_ROUTE, 278 .offset = 0x0608, 279 .size = 0x0078, 280 .canary_count = 2, 281 }, 282 { 283 .id = IPA_MEM_MODEM_HEADER, 284 .offset = 0x0688, 285 .size = 0x0240, 286 .canary_count = 2, 287 }, 288 { 289 .id = IPA_MEM_AP_HEADER, 290 .offset = 0x08c8, 291 .size = 0x0200, 292 .canary_count = 0, 293 }, 294 { 295 .id = IPA_MEM_MODEM_PROC_CTX, 296 .offset = 0x0ad0, 297 .size = 0x0200, 298 .canary_count = 2, 299 }, 300 { 301 .id = IPA_MEM_AP_PROC_CTX, 302 .offset = 0x0cd0, 303 .size = 0x0200, 304 .canary_count = 0, 305 }, 306 { 307 .id = IPA_MEM_NAT_TABLE, 308 .offset = 0x0ee0, 309 .size = 0x0d00, 310 .canary_count = 4, 311 }, 312 { 313 .id = IPA_MEM_PDN_CONFIG, 314 .offset = 0x1be8, 315 .size = 0x0050, 316 .canary_count = 0, 317 }, 318 { 319 .id = IPA_MEM_STATS_QUOTA_MODEM, 320 .offset = 0x1c40, 321 .size = 0x0030, 322 .canary_count = 4, 323 }, 324 { 325 .id = IPA_MEM_STATS_QUOTA_AP, 326 .offset = 0x1c70, 327 .size = 0x0048, 328 .canary_count = 0, 329 }, 330 { 331 .id = IPA_MEM_STATS_TETHERING, 332 .offset = 0x1cb8, 333 .size = 0x0238, 334 .canary_count = 0, 335 }, 336 { 337 .id = IPA_MEM_STATS_DROP, 338 .offset = 0x1ef0, 339 .size = 0x0020, 340 .canary_count = 0, 341 }, 342 { 343 .id = IPA_MEM_MODEM, 344 .offset = 0x1f18, 345 .size = 0x100c, 346 .canary_count = 2, 347 }, 348 { 349 .id = IPA_MEM_END_MARKER, 350 .offset = 0x3000, 351 .size = 0x0000, 352 .canary_count = 1, 353 }, 354 }; 355 356 /* Memory configuration data for an SoC having IPA v4.7 */ 357 static const struct ipa_mem_data ipa_mem_data = { 358 .local_count = ARRAY_SIZE(ipa_mem_local_data), 359 .local = ipa_mem_local_data, 360 .imem_addr = 0x146a8000, 361 .imem_size = 0x00002000, 362 .smem_id = 497, 363 .smem_size = 0x00009000, 364 }; 365 366 /* Interconnect rates are in 1000 byte/second units */ 367 static const struct ipa_interconnect_data ipa_interconnect_data[] = { 368 { 369 .name = "memory", 370 .peak_bandwidth = 600000, /* 600 MBps */ 371 .average_bandwidth = 150000, /* 150 MBps */ 372 }, 373 /* Average rate is unused for the next two interconnects */ 374 { 375 .name = "imem", 376 .peak_bandwidth = 450000, /* 450 MBps */ 377 .average_bandwidth = 75000, /* 75 MBps (unused?) */ 378 }, 379 { 380 .name = "config", 381 .peak_bandwidth = 171400, /* 171.4 MBps */ 382 .average_bandwidth = 0, /* unused */ 383 }, 384 }; 385 386 /* Clock and interconnect configuration data for an SoC having IPA v4.7 */ 387 static const struct ipa_power_data ipa_power_data = { 388 /* XXX Downstream code says 150 MHz (DT SVS2), 60 MHz (code) */ 389 .core_clock_rate = 100 * 1000 * 1000, /* Hz (150? 60?) */ 390 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 391 .interconnect_data = ipa_interconnect_data, 392 }; 393 394 /* Configuration data for an SoC having IPA v4.7 */ 395 const struct ipa_data ipa_data_v4_7 = { 396 .version = IPA_VERSION_4_7, 397 .qsb_count = ARRAY_SIZE(ipa_qsb_data), 398 .qsb_data = ipa_qsb_data, 399 .modem_route_count = 8, 400 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 401 .endpoint_data = ipa_gsi_endpoint_data, 402 .resource_data = &ipa_resource_data, 403 .mem_data = &ipa_mem_data, 404 .power_data = &ipa_power_data, 405 }; 406