1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/log2.h> 7 8 #include "../ipa_data.h" 9 #include "../ipa_endpoint.h" 10 #include "../ipa_mem.h" 11 #include "../ipa_version.h" 12 13 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.7 */ 14 enum ipa_resource_type { 15 /* Source resource types; first must have value 0 */ 16 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 18 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 19 IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 20 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 21 22 /* Destination resource types; first must have value 0 */ 23 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 24 IPA_RESOURCE_TYPE_DST_DPS_DMARS, 25 }; 26 27 /* Resource groups used for an SoC having IPA v4.7 */ 28 enum ipa_rsrc_group_id { 29 /* Source resource group identifiers */ 30 IPA_RSRC_GROUP_SRC_UL_DL = 0, 31 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 32 33 /* Destination resource group identifiers */ 34 IPA_RSRC_GROUP_DST_UL_DL = 0, 35 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 36 }; 37 38 /* QSB configuration data for an SoC having IPA v4.7 */ 39 static const struct ipa_qsb_data ipa_qsb_data[] = { 40 [IPA_QSB_MASTER_DDR] = { 41 .max_writes = 8, 42 .max_reads = 0, /* no limit (hardware max) */ 43 .max_reads_beats = 120, 44 }, 45 }; 46 47 /* Endpoint configuration data for an SoC having IPA v4.7 */ 48 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 49 [IPA_ENDPOINT_AP_COMMAND_TX] = { 50 .ee_id = GSI_EE_AP, 51 .channel_id = 5, 52 .endpoint_id = 7, 53 .toward_ipa = true, 54 .channel = { 55 .tre_count = 256, 56 .event_count = 256, 57 .tlv_count = 20, 58 }, 59 .endpoint = { 60 .config = { 61 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 62 .dma_mode = true, 63 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 64 .tx = { 65 .seq_type = IPA_SEQ_DMA, 66 }, 67 }, 68 }, 69 }, 70 [IPA_ENDPOINT_AP_LAN_RX] = { 71 .ee_id = GSI_EE_AP, 72 .channel_id = 14, 73 .endpoint_id = 9, 74 .toward_ipa = false, 75 .channel = { 76 .tre_count = 256, 77 .event_count = 256, 78 .tlv_count = 9, 79 }, 80 .endpoint = { 81 .config = { 82 .resource_group = IPA_RSRC_GROUP_DST_UL_DL, 83 .aggregation = true, 84 .status_enable = true, 85 .rx = { 86 .buffer_size = 8192, 87 .pad_align = ilog2(sizeof(u32)), 88 .aggr_time_limit = 500, 89 }, 90 }, 91 }, 92 }, 93 [IPA_ENDPOINT_AP_MODEM_TX] = { 94 .ee_id = GSI_EE_AP, 95 .channel_id = 2, 96 .endpoint_id = 2, 97 .toward_ipa = true, 98 .channel = { 99 .tre_count = 512, 100 .event_count = 512, 101 .tlv_count = 16, 102 }, 103 .endpoint = { 104 .filter_support = true, 105 .config = { 106 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 107 .qmap = true, 108 .status_enable = true, 109 .tx = { 110 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 111 .status_endpoint = 112 IPA_ENDPOINT_MODEM_AP_RX, 113 }, 114 }, 115 }, 116 }, 117 [IPA_ENDPOINT_AP_MODEM_RX] = { 118 .ee_id = GSI_EE_AP, 119 .channel_id = 7, 120 .endpoint_id = 16, 121 .toward_ipa = false, 122 .channel = { 123 .tre_count = 256, 124 .event_count = 256, 125 .tlv_count = 9, 126 }, 127 .endpoint = { 128 .config = { 129 .resource_group = IPA_RSRC_GROUP_DST_UL_DL, 130 .qmap = true, 131 .aggregation = true, 132 .rx = { 133 .buffer_size = 8192, 134 .aggr_time_limit = 500, 135 .aggr_close_eof = true, 136 }, 137 }, 138 }, 139 }, 140 [IPA_ENDPOINT_MODEM_AP_TX] = { 141 .ee_id = GSI_EE_MODEM, 142 .channel_id = 0, 143 .endpoint_id = 5, 144 .toward_ipa = true, 145 .endpoint = { 146 .filter_support = true, 147 }, 148 }, 149 [IPA_ENDPOINT_MODEM_AP_RX] = { 150 .ee_id = GSI_EE_MODEM, 151 .channel_id = 7, 152 .endpoint_id = 14, 153 .toward_ipa = false, 154 }, 155 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 156 .ee_id = GSI_EE_MODEM, 157 .channel_id = 2, 158 .endpoint_id = 8, 159 .toward_ipa = true, 160 .endpoint = { 161 .filter_support = true, 162 }, 163 }, 164 }; 165 166 /* Source resource configuration data for an SoC having IPA v4.7 */ 167 static const struct ipa_resource ipa_resource_src[] = { 168 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 169 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 170 .min = 8, .max = 8, 171 }, 172 }, 173 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 174 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 175 .min = 8, .max = 8, 176 }, 177 }, 178 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 179 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 180 .min = 18, .max = 18, 181 }, 182 }, 183 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 184 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 185 .min = 2, .max = 2, 186 }, 187 }, 188 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 189 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 190 .min = 15, .max = 15, 191 }, 192 }, 193 }; 194 195 /* Destination resource configuration data for an SoC having IPA v4.7 */ 196 static const struct ipa_resource ipa_resource_dst[] = { 197 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 198 .limits[IPA_RSRC_GROUP_DST_UL_DL] = { 199 .min = 7, .max = 7, 200 }, 201 }, 202 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 203 .limits[IPA_RSRC_GROUP_DST_UL_DL] = { 204 .min = 2, .max = 2, 205 }, 206 }, 207 }; 208 209 /* Resource configuration data for an SoC having IPA v4.7 */ 210 static const struct ipa_resource_data ipa_resource_data = { 211 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 212 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 213 .resource_src_count = ARRAY_SIZE(ipa_resource_src), 214 .resource_src = ipa_resource_src, 215 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 216 .resource_dst = ipa_resource_dst, 217 }; 218 219 /* IPA-resident memory region data for an SoC having IPA v4.7 */ 220 static const struct ipa_mem ipa_mem_local_data[] = { 221 { 222 .id = IPA_MEM_UC_SHARED, 223 .offset = 0x0000, 224 .size = 0x0080, 225 .canary_count = 0, 226 }, 227 { 228 .id = IPA_MEM_UC_INFO, 229 .offset = 0x0080, 230 .size = 0x0200, 231 .canary_count = 0, 232 }, 233 { 234 .id = IPA_MEM_V4_FILTER_HASHED, 235 .offset = 0x0288, 236 .size = 0x0078, 237 .canary_count = 2, 238 }, 239 { 240 .id = IPA_MEM_V4_FILTER, 241 .offset = 0x0308, 242 .size = 0x0078, 243 .canary_count = 2, 244 }, 245 { 246 .id = IPA_MEM_V6_FILTER_HASHED, 247 .offset = 0x0388, 248 .size = 0x0078, 249 .canary_count = 2, 250 }, 251 { 252 .id = IPA_MEM_V6_FILTER, 253 .offset = 0x0408, 254 .size = 0x0078, 255 .canary_count = 2, 256 }, 257 { 258 .id = IPA_MEM_V4_ROUTE_HASHED, 259 .offset = 0x0488, 260 .size = 0x0078, 261 .canary_count = 2, 262 }, 263 { 264 .id = IPA_MEM_V4_ROUTE, 265 .offset = 0x0508, 266 .size = 0x0078, 267 .canary_count = 2, 268 }, 269 { 270 .id = IPA_MEM_V6_ROUTE_HASHED, 271 .offset = 0x0588, 272 .size = 0x0078, 273 .canary_count = 2, 274 }, 275 { 276 .id = IPA_MEM_V6_ROUTE, 277 .offset = 0x0608, 278 .size = 0x0078, 279 .canary_count = 2, 280 }, 281 { 282 .id = IPA_MEM_MODEM_HEADER, 283 .offset = 0x0688, 284 .size = 0x0240, 285 .canary_count = 2, 286 }, 287 { 288 .id = IPA_MEM_AP_HEADER, 289 .offset = 0x08c8, 290 .size = 0x0200, 291 .canary_count = 0, 292 }, 293 { 294 .id = IPA_MEM_MODEM_PROC_CTX, 295 .offset = 0x0ad0, 296 .size = 0x0200, 297 .canary_count = 2, 298 }, 299 { 300 .id = IPA_MEM_AP_PROC_CTX, 301 .offset = 0x0cd0, 302 .size = 0x0200, 303 .canary_count = 0, 304 }, 305 { 306 .id = IPA_MEM_NAT_TABLE, 307 .offset = 0x0ee0, 308 .size = 0x0d00, 309 .canary_count = 4, 310 }, 311 { 312 .id = IPA_MEM_PDN_CONFIG, 313 .offset = 0x1be8, 314 .size = 0x0050, 315 .canary_count = 0, 316 }, 317 { 318 .id = IPA_MEM_STATS_QUOTA_MODEM, 319 .offset = 0x1c40, 320 .size = 0x0030, 321 .canary_count = 4, 322 }, 323 { 324 .id = IPA_MEM_STATS_QUOTA_AP, 325 .offset = 0x1c70, 326 .size = 0x0048, 327 .canary_count = 0, 328 }, 329 { 330 .id = IPA_MEM_STATS_TETHERING, 331 .offset = 0x1cb8, 332 .size = 0x0238, 333 .canary_count = 0, 334 }, 335 { 336 .id = IPA_MEM_STATS_DROP, 337 .offset = 0x1ef0, 338 .size = 0x0020, 339 .canary_count = 0, 340 }, 341 { 342 .id = IPA_MEM_MODEM, 343 .offset = 0x1f18, 344 .size = 0x100c, 345 .canary_count = 2, 346 }, 347 { 348 .id = IPA_MEM_END_MARKER, 349 .offset = 0x3000, 350 .size = 0x0000, 351 .canary_count = 1, 352 }, 353 }; 354 355 /* Memory configuration data for an SoC having IPA v4.7 */ 356 static const struct ipa_mem_data ipa_mem_data = { 357 .local_count = ARRAY_SIZE(ipa_mem_local_data), 358 .local = ipa_mem_local_data, 359 .imem_addr = 0x146a8000, 360 .imem_size = 0x00002000, 361 .smem_id = 497, 362 .smem_size = 0x00009000, 363 }; 364 365 /* Interconnect rates are in 1000 byte/second units */ 366 static const struct ipa_interconnect_data ipa_interconnect_data[] = { 367 { 368 .name = "memory", 369 .peak_bandwidth = 600000, /* 600 MBps */ 370 .average_bandwidth = 150000, /* 150 MBps */ 371 }, 372 /* Average rate is unused for the next two interconnects */ 373 { 374 .name = "imem", 375 .peak_bandwidth = 450000, /* 450 MBps */ 376 .average_bandwidth = 75000, /* 75 MBps (unused?) */ 377 }, 378 { 379 .name = "config", 380 .peak_bandwidth = 171400, /* 171.4 MBps */ 381 .average_bandwidth = 0, /* unused */ 382 }, 383 }; 384 385 /* Clock and interconnect configuration data for an SoC having IPA v4.7 */ 386 static const struct ipa_power_data ipa_power_data = { 387 /* XXX Downstream code says 150 MHz (DT SVS2), 60 MHz (code) */ 388 .core_clock_rate = 100 * 1000 * 1000, /* Hz (150? 60?) */ 389 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 390 .interconnect_data = ipa_interconnect_data, 391 }; 392 393 /* Configuration data for an SoC having IPA v4.7 */ 394 const struct ipa_data ipa_data_v4_7 = { 395 .version = IPA_VERSION_4_7, 396 .qsb_count = ARRAY_SIZE(ipa_qsb_data), 397 .qsb_data = ipa_qsb_data, 398 .modem_route_count = 8, 399 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 400 .endpoint_data = ipa_gsi_endpoint_data, 401 .resource_data = &ipa_resource_data, 402 .mem_data = &ipa_mem_data, 403 .power_data = &ipa_power_data, 404 }; 405