1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2019-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/log2.h> 7 8 #include "../ipa_data.h" 9 #include "../ipa_endpoint.h" 10 #include "../ipa_mem.h" 11 #include "../ipa_version.h" 12 13 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.2 */ 14 enum ipa_resource_type { 15 /* Source resource types; first must have value 0 */ 16 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 18 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 19 IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 20 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 21 22 /* Destination resource types; first must have value 0 */ 23 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 24 IPA_RESOURCE_TYPE_DST_DPS_DMARS, 25 }; 26 27 /* Resource groups used for an SoC having IPA v4.2 */ 28 enum ipa_rsrc_group_id { 29 /* Source resource group identifiers */ 30 IPA_RSRC_GROUP_SRC_UL_DL = 0, 31 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 32 33 /* Destination resource group identifiers */ 34 IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, 35 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 36 }; 37 38 /* QSB configuration data for an SoC having IPA v4.2 */ 39 static const struct ipa_qsb_data ipa_qsb_data[] = { 40 [IPA_QSB_MASTER_DDR] = { 41 .max_writes = 8, 42 .max_reads = 12, 43 /* no outstanding read byte (beat) limit */ 44 }, 45 }; 46 47 /* Endpoint configuration data for an SoC having IPA v4.2 */ 48 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 49 [IPA_ENDPOINT_AP_COMMAND_TX] = { 50 .ee_id = GSI_EE_AP, 51 .channel_id = 1, 52 .endpoint_id = 6, 53 .toward_ipa = true, 54 .channel = { 55 .tre_count = 256, 56 .event_count = 256, 57 .tlv_count = 20, 58 }, 59 .endpoint = { 60 .config = { 61 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 62 .dma_mode = true, 63 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 64 .tx = { 65 .seq_type = IPA_SEQ_DMA, 66 }, 67 }, 68 }, 69 }, 70 [IPA_ENDPOINT_AP_LAN_RX] = { 71 .ee_id = GSI_EE_AP, 72 .channel_id = 2, 73 .endpoint_id = 8, 74 .toward_ipa = false, 75 .channel = { 76 .tre_count = 256, 77 .event_count = 256, 78 .tlv_count = 6, 79 }, 80 .endpoint = { 81 .config = { 82 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 83 .aggregation = true, 84 .status_enable = true, 85 .rx = { 86 .buffer_size = 8192, 87 .pad_align = ilog2(sizeof(u32)), 88 .aggr_time_limit = 500, 89 }, 90 }, 91 }, 92 }, 93 [IPA_ENDPOINT_AP_MODEM_TX] = { 94 .ee_id = GSI_EE_AP, 95 .channel_id = 0, 96 .endpoint_id = 1, 97 .toward_ipa = true, 98 .channel = { 99 .tre_count = 512, 100 .event_count = 512, 101 .tlv_count = 8, 102 }, 103 .endpoint = { 104 .filter_support = true, 105 .config = { 106 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 107 .checksum = true, 108 .qmap = true, 109 .status_enable = true, 110 .tx = { 111 .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC, 112 .seq_rep_type = IPA_SEQ_REP_DMA_PARSER, 113 .status_endpoint = 114 IPA_ENDPOINT_MODEM_AP_RX, 115 }, 116 }, 117 }, 118 }, 119 [IPA_ENDPOINT_AP_MODEM_RX] = { 120 .ee_id = GSI_EE_AP, 121 .channel_id = 3, 122 .endpoint_id = 9, 123 .toward_ipa = false, 124 .channel = { 125 .tre_count = 256, 126 .event_count = 256, 127 .tlv_count = 6, 128 }, 129 .endpoint = { 130 .config = { 131 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 132 .checksum = true, 133 .qmap = true, 134 .aggregation = true, 135 .rx = { 136 .buffer_size = 8192, 137 .aggr_time_limit = 500, 138 .aggr_close_eof = true, 139 }, 140 }, 141 }, 142 }, 143 [IPA_ENDPOINT_MODEM_COMMAND_TX] = { 144 .ee_id = GSI_EE_MODEM, 145 .channel_id = 1, 146 .endpoint_id = 5, 147 .toward_ipa = true, 148 }, 149 [IPA_ENDPOINT_MODEM_LAN_RX] = { 150 .ee_id = GSI_EE_MODEM, 151 .channel_id = 3, 152 .endpoint_id = 11, 153 .toward_ipa = false, 154 }, 155 [IPA_ENDPOINT_MODEM_AP_TX] = { 156 .ee_id = GSI_EE_MODEM, 157 .channel_id = 0, 158 .endpoint_id = 4, 159 .toward_ipa = true, 160 .endpoint = { 161 .filter_support = true, 162 }, 163 }, 164 [IPA_ENDPOINT_MODEM_AP_RX] = { 165 .ee_id = GSI_EE_MODEM, 166 .channel_id = 2, 167 .endpoint_id = 10, 168 .toward_ipa = false, 169 }, 170 }; 171 172 /* Source resource configuration data for an SoC having IPA v4.2 */ 173 static const struct ipa_resource ipa_resource_src[] = { 174 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 175 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 176 .min = 3, .max = 63, 177 }, 178 }, 179 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 180 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 181 .min = 3, .max = 3, 182 }, 183 }, 184 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 185 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 186 .min = 10, .max = 10, 187 }, 188 }, 189 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 190 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 191 .min = 1, .max = 1, 192 }, 193 }, 194 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 195 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 196 .min = 5, .max = 5, 197 }, 198 }, 199 }; 200 201 /* Destination resource configuration data for an SoC having IPA v4.2 */ 202 static const struct ipa_resource ipa_resource_dst[] = { 203 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 204 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 205 .min = 3, .max = 3, 206 }, 207 }, 208 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 209 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 210 .min = 1, .max = 63, 211 }, 212 }, 213 }; 214 215 /* Resource configuration data for an SoC having IPA v4.2 */ 216 static const struct ipa_resource_data ipa_resource_data = { 217 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 218 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 219 .resource_src_count = ARRAY_SIZE(ipa_resource_src), 220 .resource_src = ipa_resource_src, 221 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 222 .resource_dst = ipa_resource_dst, 223 }; 224 225 /* IPA-resident memory region data for an SoC having IPA v4.2 */ 226 static const struct ipa_mem ipa_mem_local_data[] = { 227 { 228 .id = IPA_MEM_UC_SHARED, 229 .offset = 0x0000, 230 .size = 0x0080, 231 .canary_count = 0, 232 }, 233 { 234 .id = IPA_MEM_UC_INFO, 235 .offset = 0x0080, 236 .size = 0x0200, 237 .canary_count = 0, 238 }, 239 { 240 .id = IPA_MEM_V4_FILTER_HASHED, 241 .offset = 0x0288, 242 .size = 0, 243 .canary_count = 2, 244 }, 245 { 246 .id = IPA_MEM_V4_FILTER, 247 .offset = 0x0290, 248 .size = 0x0078, 249 .canary_count = 2, 250 }, 251 { 252 .id = IPA_MEM_V6_FILTER_HASHED, 253 .offset = 0x0310, 254 .size = 0, 255 .canary_count = 2, 256 }, 257 { 258 .id = IPA_MEM_V6_FILTER, 259 .offset = 0x0318, 260 .size = 0x0078, 261 .canary_count = 2, 262 }, 263 { 264 .id = IPA_MEM_V4_ROUTE_HASHED, 265 .offset = 0x0398, 266 .size = 0, 267 .canary_count = 2, 268 }, 269 { 270 .id = IPA_MEM_V4_ROUTE, 271 .offset = 0x03a0, 272 .size = 0x0078, 273 .canary_count = 2, 274 }, 275 { 276 .id = IPA_MEM_V6_ROUTE_HASHED, 277 .offset = 0x0420, 278 .size = 0, 279 .canary_count = 2, 280 }, 281 { 282 .id = IPA_MEM_V6_ROUTE, 283 .offset = 0x0428, 284 .size = 0x0078, 285 .canary_count = 2, 286 }, 287 { 288 .id = IPA_MEM_MODEM_HEADER, 289 .offset = 0x04a8, 290 .size = 0x0140, 291 .canary_count = 2, 292 }, 293 { 294 .id = IPA_MEM_MODEM_PROC_CTX, 295 .offset = 0x05f0, 296 .size = 0x0200, 297 .canary_count = 2, 298 }, 299 { 300 .id = IPA_MEM_AP_PROC_CTX, 301 .offset = 0x07f0, 302 .size = 0x0200, 303 .canary_count = 0, 304 }, 305 { 306 .id = IPA_MEM_PDN_CONFIG, 307 .offset = 0x09f8, 308 .size = 0x0050, 309 .canary_count = 2, 310 }, 311 { 312 .id = IPA_MEM_STATS_QUOTA_MODEM, 313 .offset = 0x0a50, 314 .size = 0x0060, 315 .canary_count = 2, 316 }, 317 { 318 .id = IPA_MEM_STATS_TETHERING, 319 .offset = 0x0ab0, 320 .size = 0x0140, 321 .canary_count = 0, 322 }, 323 { 324 .id = IPA_MEM_MODEM, 325 .offset = 0x0bf0, 326 .size = 0x140c, 327 .canary_count = 0, 328 }, 329 { 330 .id = IPA_MEM_END_MARKER, 331 .offset = 0x2000, 332 .size = 0, 333 .canary_count = 1, 334 }, 335 }; 336 337 /* Memory configuration data for an SoC having IPA v4.2 */ 338 static const struct ipa_mem_data ipa_mem_data = { 339 .local_count = ARRAY_SIZE(ipa_mem_local_data), 340 .local = ipa_mem_local_data, 341 .imem_addr = 0x146a8000, 342 .imem_size = 0x00002000, 343 .smem_id = 497, 344 .smem_size = 0x00002000, 345 }; 346 347 /* Interconnect rates are in 1000 byte/second units */ 348 static const struct ipa_interconnect_data ipa_interconnect_data[] = { 349 { 350 .name = "memory", 351 .peak_bandwidth = 465000, /* 465 MBps */ 352 .average_bandwidth = 80000, /* 80 MBps */ 353 }, 354 /* Average bandwidth is unused for the next two interconnects */ 355 { 356 .name = "imem", 357 .peak_bandwidth = 68570, /* 68.570 MBps */ 358 .average_bandwidth = 0, /* unused */ 359 }, 360 { 361 .name = "config", 362 .peak_bandwidth = 30000, /* 30 MBps */ 363 .average_bandwidth = 0, /* unused */ 364 }, 365 }; 366 367 /* Clock and interconnect configuration data for an SoC having IPA v4.2 */ 368 static const struct ipa_power_data ipa_power_data = { 369 .core_clock_rate = 100 * 1000 * 1000, /* Hz */ 370 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 371 .interconnect_data = ipa_interconnect_data, 372 }; 373 374 /* Configuration data for an SoC having IPA v4.2 */ 375 const struct ipa_data ipa_data_v4_2 = { 376 .version = IPA_VERSION_4_2, 377 /* backward_compat value is 0 */ 378 .qsb_count = ARRAY_SIZE(ipa_qsb_data), 379 .qsb_data = ipa_qsb_data, 380 .modem_route_count = 8, 381 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 382 .endpoint_data = ipa_gsi_endpoint_data, 383 .resource_data = &ipa_resource_data, 384 .mem_data = &ipa_mem_data, 385 .power_data = &ipa_power_data, 386 }; 387