1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2021-2024 Linaro Ltd. */ 4 5 #include <linux/array_size.h> 6 #include <linux/log2.h> 7 8 #include "../ipa_data.h" 9 #include "../ipa_endpoint.h" 10 #include "../ipa_mem.h" 11 #include "../ipa_version.h" 12 13 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.11 */ 14 enum ipa_resource_type { 15 /* Source resource types; first must have value 0 */ 16 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 18 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 19 IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 20 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 21 22 /* Destination resource types; first must have value 0 */ 23 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 24 IPA_RESOURCE_TYPE_DST_DPS_DMARS, 25 }; 26 27 /* Resource groups used for an SoC having IPA v4.11 */ 28 enum ipa_rsrc_group_id { 29 /* Source resource group identifiers */ 30 IPA_RSRC_GROUP_SRC_UL_DL = 0, 31 IPA_RSRC_GROUP_SRC_UC_RX_Q, 32 IPA_RSRC_GROUP_SRC_UNUSED_2, 33 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 34 35 /* Destination resource group identifiers */ 36 IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, 37 IPA_RSRC_GROUP_DST_UNUSED_1, 38 IPA_RSRC_GROUP_DST_DRB_IP, 39 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 40 }; 41 42 /* QSB configuration data for an SoC having IPA v4.11 */ 43 static const struct ipa_qsb_data ipa_qsb_data[] = { 44 [IPA_QSB_MASTER_DDR] = { 45 .max_writes = 12, 46 .max_reads = 13, 47 .max_reads_beats = 120, 48 }, 49 }; 50 51 /* Endpoint configuration data for an SoC having IPA v4.11 */ 52 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 53 [IPA_ENDPOINT_AP_COMMAND_TX] = { 54 .ee_id = GSI_EE_AP, 55 .channel_id = 5, 56 .endpoint_id = 7, 57 .toward_ipa = true, 58 .channel = { 59 .tre_count = 256, 60 .event_count = 256, 61 .tlv_count = 20, 62 }, 63 .endpoint = { 64 .config = { 65 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 66 .dma_mode = true, 67 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 68 .tx = { 69 .seq_type = IPA_SEQ_DMA, 70 }, 71 }, 72 }, 73 }, 74 [IPA_ENDPOINT_AP_LAN_RX] = { 75 .ee_id = GSI_EE_AP, 76 .channel_id = 14, 77 .endpoint_id = 9, 78 .toward_ipa = false, 79 .channel = { 80 .tre_count = 256, 81 .event_count = 256, 82 .tlv_count = 9, 83 }, 84 .endpoint = { 85 .config = { 86 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 87 .aggregation = true, 88 .status_enable = true, 89 .rx = { 90 .buffer_size = 8192, 91 .pad_align = ilog2(sizeof(u32)), 92 .aggr_time_limit = 500, 93 }, 94 }, 95 }, 96 }, 97 [IPA_ENDPOINT_AP_MODEM_TX] = { 98 .ee_id = GSI_EE_AP, 99 .channel_id = 2, 100 .endpoint_id = 2, 101 .toward_ipa = true, 102 .channel = { 103 .tre_count = 512, 104 .event_count = 512, 105 .tlv_count = 16, 106 }, 107 .endpoint = { 108 .filter_support = true, 109 .config = { 110 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 111 .checksum = true, 112 .qmap = true, 113 .status_enable = true, 114 .tx = { 115 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 116 .status_endpoint = 117 IPA_ENDPOINT_MODEM_AP_RX, 118 }, 119 }, 120 }, 121 }, 122 [IPA_ENDPOINT_AP_MODEM_RX] = { 123 .ee_id = GSI_EE_AP, 124 .channel_id = 7, 125 .endpoint_id = 16, 126 .toward_ipa = false, 127 .channel = { 128 .tre_count = 256, 129 .event_count = 256, 130 .tlv_count = 9, 131 }, 132 .endpoint = { 133 .config = { 134 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 135 .checksum = true, 136 .qmap = true, 137 .aggregation = true, 138 .rx = { 139 .buffer_size = 32768, 140 .aggr_time_limit = 500, 141 .aggr_close_eof = true, 142 }, 143 }, 144 }, 145 }, 146 [IPA_ENDPOINT_MODEM_AP_TX] = { 147 .ee_id = GSI_EE_MODEM, 148 .channel_id = 0, 149 .endpoint_id = 5, 150 .toward_ipa = true, 151 .endpoint = { 152 .filter_support = true, 153 }, 154 }, 155 [IPA_ENDPOINT_MODEM_AP_RX] = { 156 .ee_id = GSI_EE_MODEM, 157 .channel_id = 7, 158 .endpoint_id = 14, 159 .toward_ipa = false, 160 }, 161 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 162 .ee_id = GSI_EE_MODEM, 163 .channel_id = 2, 164 .endpoint_id = 8, 165 .toward_ipa = true, 166 .endpoint = { 167 .filter_support = true, 168 }, 169 }, 170 }; 171 172 /* Source resource configuration data for an SoC having IPA v4.11 */ 173 static const struct ipa_resource ipa_resource_src[] = { 174 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 175 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 176 .min = 6, .max = 6, 177 }, 178 }, 179 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 180 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 181 .min = 8, .max = 8, 182 }, 183 }, 184 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 185 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 186 .min = 18, .max = 18, 187 }, 188 }, 189 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 190 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 191 .min = 2, .max = 2, 192 }, 193 }, 194 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 195 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 196 .min = 15, .max = 15, 197 }, 198 }, 199 }; 200 201 /* Destination resource configuration data for an SoC having IPA v4.11 */ 202 static const struct ipa_resource ipa_resource_dst[] = { 203 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 204 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 205 .min = 3, .max = 3, 206 }, 207 .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { 208 .min = 25, .max = 25, 209 }, 210 }, 211 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 212 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 213 .min = 2, .max = 2, 214 }, 215 }, 216 }; 217 218 /* Resource configuration data for an SoC having IPA v4.11 */ 219 static const struct ipa_resource_data ipa_resource_data = { 220 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 221 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 222 .resource_src_count = ARRAY_SIZE(ipa_resource_src), 223 .resource_src = ipa_resource_src, 224 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 225 .resource_dst = ipa_resource_dst, 226 }; 227 228 /* IPA-resident memory region data for an SoC having IPA v4.11 */ 229 static const struct ipa_mem ipa_mem_local_data[] = { 230 { 231 .id = IPA_MEM_UC_SHARED, 232 .offset = 0x0000, 233 .size = 0x0080, 234 .canary_count = 0, 235 }, 236 { 237 .id = IPA_MEM_UC_INFO, 238 .offset = 0x0080, 239 .size = 0x0200, 240 .canary_count = 0, 241 }, 242 { 243 .id = IPA_MEM_V4_FILTER_HASHED, 244 .offset = 0x0288, 245 .size = 0x0078, 246 .canary_count = 2, 247 }, 248 { 249 .id = IPA_MEM_V4_FILTER, 250 .offset = 0x0308, 251 .size = 0x0078, 252 .canary_count = 2, 253 }, 254 { 255 .id = IPA_MEM_V6_FILTER_HASHED, 256 .offset = 0x0388, 257 .size = 0x0078, 258 .canary_count = 2, 259 }, 260 { 261 .id = IPA_MEM_V6_FILTER, 262 .offset = 0x0408, 263 .size = 0x0078, 264 .canary_count = 2, 265 }, 266 { 267 .id = IPA_MEM_V4_ROUTE_HASHED, 268 .offset = 0x0488, 269 .size = 0x0078, 270 .canary_count = 2, 271 }, 272 { 273 .id = IPA_MEM_V4_ROUTE, 274 .offset = 0x0508, 275 .size = 0x0078, 276 .canary_count = 2, 277 }, 278 { 279 .id = IPA_MEM_V6_ROUTE_HASHED, 280 .offset = 0x0588, 281 .size = 0x0078, 282 .canary_count = 2, 283 }, 284 { 285 .id = IPA_MEM_V6_ROUTE, 286 .offset = 0x0608, 287 .size = 0x0078, 288 .canary_count = 2, 289 }, 290 { 291 .id = IPA_MEM_MODEM_HEADER, 292 .offset = 0x0688, 293 .size = 0x0240, 294 .canary_count = 2, 295 }, 296 { 297 .id = IPA_MEM_AP_HEADER, 298 .offset = 0x08c8, 299 .size = 0x0200, 300 .canary_count = 0, 301 }, 302 { 303 .id = IPA_MEM_MODEM_PROC_CTX, 304 .offset = 0x0ad0, 305 .size = 0x0200, 306 .canary_count = 2, 307 }, 308 { 309 .id = IPA_MEM_AP_PROC_CTX, 310 .offset = 0x0cd0, 311 .size = 0x0200, 312 .canary_count = 0, 313 }, 314 { 315 .id = IPA_MEM_NAT_TABLE, 316 .offset = 0x0ee0, 317 .size = 0x0d00, 318 .canary_count = 4, 319 }, 320 { 321 .id = IPA_MEM_PDN_CONFIG, 322 .offset = 0x1be8, 323 .size = 0x0050, 324 .canary_count = 0, 325 }, 326 { 327 .id = IPA_MEM_STATS_QUOTA_MODEM, 328 .offset = 0x1c40, 329 .size = 0x0030, 330 .canary_count = 4, 331 }, 332 { 333 .id = IPA_MEM_STATS_QUOTA_AP, 334 .offset = 0x1c70, 335 .size = 0x0048, 336 .canary_count = 0, 337 }, 338 { 339 .id = IPA_MEM_STATS_TETHERING, 340 .offset = 0x1cb8, 341 .size = 0x0238, 342 .canary_count = 0, 343 }, 344 { 345 .id = IPA_MEM_STATS_DROP, 346 .offset = 0x1ef0, 347 .size = 0x0020, 348 .canary_count = 0, 349 }, 350 { 351 .id = IPA_MEM_MODEM, 352 .offset = 0x1f18, 353 .size = 0x100c, 354 .canary_count = 2, 355 }, 356 { 357 .id = IPA_MEM_END_MARKER, 358 .offset = 0x3000, 359 .size = 0x0000, 360 .canary_count = 1, 361 }, 362 }; 363 364 /* Memory configuration data for an SoC having IPA v4.11 */ 365 static const struct ipa_mem_data ipa_mem_data = { 366 .local_count = ARRAY_SIZE(ipa_mem_local_data), 367 .local = ipa_mem_local_data, 368 .imem_addr = 0x146a8000, 369 .imem_size = 0x00002000, 370 .smem_id = 497, 371 .smem_size = 0x00009000, 372 }; 373 374 /* Interconnect rates are in 1000 byte/second units */ 375 static const struct ipa_interconnect_data ipa_interconnect_data[] = { 376 { 377 .name = "memory", 378 .peak_bandwidth = 600000, /* 600 MBps */ 379 .average_bandwidth = 150000, /* 150 MBps */ 380 }, 381 /* Average rate is unused for the next interconnect */ 382 { 383 .name = "config", 384 .peak_bandwidth = 74000, /* 74 MBps */ 385 .average_bandwidth = 0, /* unused */ 386 }, 387 }; 388 389 /* Clock and interconnect configuration data for an SoC having IPA v4.11 */ 390 static const struct ipa_power_data ipa_power_data = { 391 .core_clock_rate = 60 * 1000 * 1000, /* Hz */ 392 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 393 .interconnect_data = ipa_interconnect_data, 394 }; 395 396 /* Configuration data for an SoC having IPA v4.11 */ 397 const struct ipa_data ipa_data_v4_11 = { 398 .version = IPA_VERSION_4_11, 399 .qsb_count = ARRAY_SIZE(ipa_qsb_data), 400 .qsb_data = ipa_qsb_data, 401 .modem_route_count = 8, 402 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 403 .endpoint_data = ipa_gsi_endpoint_data, 404 .resource_data = &ipa_resource_data, 405 .mem_data = &ipa_mem_data, 406 .power_data = &ipa_power_data, 407 }; 408