1 /* 2 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller 3 * 4 * Copyright (C) 2012 Alan Ott <alan@signal11.us> 5 * Signal 11 Software 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/spi/spi.h> 19 #include <linux/interrupt.h> 20 #include <linux/module.h> 21 #include <linux/regmap.h> 22 #include <linux/ieee802154.h> 23 #include <linux/irq.h> 24 #include <net/cfg802154.h> 25 #include <net/mac802154.h> 26 27 /* MRF24J40 Short Address Registers */ 28 #define REG_RXMCR 0x00 /* Receive MAC control */ 29 #define BIT_PROMI BIT(0) 30 #define BIT_ERRPKT BIT(1) 31 #define BIT_NOACKRSP BIT(5) 32 #define BIT_PANCOORD BIT(3) 33 34 #define REG_PANIDL 0x01 /* PAN ID (low) */ 35 #define REG_PANIDH 0x02 /* PAN ID (high) */ 36 #define REG_SADRL 0x03 /* Short address (low) */ 37 #define REG_SADRH 0x04 /* Short address (high) */ 38 #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */ 39 #define REG_EADR1 0x06 40 #define REG_EADR2 0x07 41 #define REG_EADR3 0x08 42 #define REG_EADR4 0x09 43 #define REG_EADR5 0x0A 44 #define REG_EADR6 0x0B 45 #define REG_EADR7 0x0C 46 #define REG_RXFLUSH 0x0D 47 #define REG_ORDER 0x10 48 #define REG_TXMCR 0x11 /* Transmit MAC control */ 49 #define TXMCR_MIN_BE_SHIFT 3 50 #define TXMCR_MIN_BE_MASK 0x18 51 #define TXMCR_CSMA_RETRIES_SHIFT 0 52 #define TXMCR_CSMA_RETRIES_MASK 0x07 53 54 #define REG_ACKTMOUT 0x12 55 #define REG_ESLOTG1 0x13 56 #define REG_SYMTICKL 0x14 57 #define REG_SYMTICKH 0x15 58 #define REG_PACON0 0x16 /* Power Amplifier Control */ 59 #define REG_PACON1 0x17 /* Power Amplifier Control */ 60 #define REG_PACON2 0x18 /* Power Amplifier Control */ 61 #define REG_TXBCON0 0x1A 62 #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */ 63 #define BIT_TXNTRIG BIT(0) 64 #define BIT_TXNACKREQ BIT(2) 65 66 #define REG_TXG1CON 0x1C 67 #define REG_TXG2CON 0x1D 68 #define REG_ESLOTG23 0x1E 69 #define REG_ESLOTG45 0x1F 70 #define REG_ESLOTG67 0x20 71 #define REG_TXPEND 0x21 72 #define REG_WAKECON 0x22 73 #define REG_FROMOFFSET 0x23 74 #define REG_TXSTAT 0x24 /* TX MAC Status Register */ 75 #define REG_TXBCON1 0x25 76 #define REG_GATECLK 0x26 77 #define REG_TXTIME 0x27 78 #define REG_HSYMTMRL 0x28 79 #define REG_HSYMTMRH 0x29 80 #define REG_SOFTRST 0x2A /* Soft Reset */ 81 #define REG_SECCON0 0x2C 82 #define REG_SECCON1 0x2D 83 #define REG_TXSTBL 0x2E /* TX Stabilization */ 84 #define REG_RXSR 0x30 85 #define REG_INTSTAT 0x31 /* Interrupt Status */ 86 #define BIT_TXNIF BIT(0) 87 #define BIT_RXIF BIT(3) 88 89 #define REG_INTCON 0x32 /* Interrupt Control */ 90 #define BIT_TXNIE BIT(0) 91 #define BIT_RXIE BIT(3) 92 93 #define REG_GPIO 0x33 /* GPIO */ 94 #define REG_TRISGPIO 0x34 /* GPIO direction */ 95 #define REG_SLPACK 0x35 96 #define REG_RFCTL 0x36 /* RF Control Mode Register */ 97 #define BIT_RFRST BIT(2) 98 99 #define REG_SECCR2 0x37 100 #define REG_BBREG0 0x38 101 #define REG_BBREG1 0x39 /* Baseband Registers */ 102 #define BIT_RXDECINV BIT(2) 103 104 #define REG_BBREG2 0x3A /* */ 105 #define BBREG2_CCA_MODE_SHIFT 6 106 #define BBREG2_CCA_MODE_MASK 0xc0 107 108 #define REG_BBREG3 0x3B 109 #define REG_BBREG4 0x3C 110 #define REG_BBREG6 0x3E /* */ 111 #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */ 112 113 /* MRF24J40 Long Address Registers */ 114 #define REG_RFCON0 0x200 /* RF Control Registers */ 115 #define RFCON0_CH_SHIFT 4 116 #define RFCON0_CH_MASK 0xf0 117 #define RFOPT_RECOMMEND 3 118 119 #define REG_RFCON1 0x201 120 #define REG_RFCON2 0x202 121 #define REG_RFCON3 0x203 122 123 #define TXPWRL_MASK 0xc0 124 #define TXPWRL_SHIFT 6 125 #define TXPWRL_30 0x3 126 #define TXPWRL_20 0x2 127 #define TXPWRL_10 0x1 128 #define TXPWRL_0 0x0 129 130 #define TXPWRS_MASK 0x38 131 #define TXPWRS_SHIFT 3 132 #define TXPWRS_6_3 0x7 133 #define TXPWRS_4_9 0x6 134 #define TXPWRS_3_7 0x5 135 #define TXPWRS_2_8 0x4 136 #define TXPWRS_1_9 0x3 137 #define TXPWRS_1_2 0x2 138 #define TXPWRS_0_5 0x1 139 #define TXPWRS_0 0x0 140 141 #define REG_RFCON5 0x205 142 #define REG_RFCON6 0x206 143 #define REG_RFCON7 0x207 144 #define REG_RFCON8 0x208 145 #define REG_SLPCAL0 0x209 146 #define REG_SLPCAL1 0x20A 147 #define REG_SLPCAL2 0x20B 148 #define REG_RFSTATE 0x20F 149 #define REG_RSSI 0x210 150 #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */ 151 #define BIT_INTEDGE BIT(1) 152 153 #define REG_SLPCON1 0x220 154 #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */ 155 #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */ 156 #define REG_REMCNTL 0x224 157 #define REG_REMCNTH 0x225 158 #define REG_MAINCNT0 0x226 159 #define REG_MAINCNT1 0x227 160 #define REG_MAINCNT2 0x228 161 #define REG_MAINCNT3 0x229 162 #define REG_TESTMODE 0x22F /* Test mode */ 163 #define REG_ASSOEAR0 0x230 164 #define REG_ASSOEAR1 0x231 165 #define REG_ASSOEAR2 0x232 166 #define REG_ASSOEAR3 0x233 167 #define REG_ASSOEAR4 0x234 168 #define REG_ASSOEAR5 0x235 169 #define REG_ASSOEAR6 0x236 170 #define REG_ASSOEAR7 0x237 171 #define REG_ASSOSAR0 0x238 172 #define REG_ASSOSAR1 0x239 173 #define REG_UNONCE0 0x240 174 #define REG_UNONCE1 0x241 175 #define REG_UNONCE2 0x242 176 #define REG_UNONCE3 0x243 177 #define REG_UNONCE4 0x244 178 #define REG_UNONCE5 0x245 179 #define REG_UNONCE6 0x246 180 #define REG_UNONCE7 0x247 181 #define REG_UNONCE8 0x248 182 #define REG_UNONCE9 0x249 183 #define REG_UNONCE10 0x24A 184 #define REG_UNONCE11 0x24B 185 #define REG_UNONCE12 0x24C 186 #define REG_RX_FIFO 0x300 /* Receive FIFO */ 187 188 /* Device configuration: Only channels 11-26 on page 0 are supported. */ 189 #define MRF24J40_CHAN_MIN 11 190 #define MRF24J40_CHAN_MAX 26 191 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \ 192 - ((u32)1 << MRF24J40_CHAN_MIN)) 193 194 #define TX_FIFO_SIZE 128 /* From datasheet */ 195 #define RX_FIFO_SIZE 144 /* From datasheet */ 196 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */ 197 198 enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC }; 199 200 /* Device Private Data */ 201 struct mrf24j40 { 202 struct spi_device *spi; 203 struct ieee802154_hw *hw; 204 205 struct regmap *regmap_short; 206 struct regmap *regmap_long; 207 208 /* for writing txfifo */ 209 struct spi_message tx_msg; 210 u8 tx_hdr_buf[2]; 211 struct spi_transfer tx_hdr_trx; 212 u8 tx_len_buf[2]; 213 struct spi_transfer tx_len_trx; 214 struct spi_transfer tx_buf_trx; 215 struct sk_buff *tx_skb; 216 217 /* post transmit message to send frame out */ 218 struct spi_message tx_post_msg; 219 u8 tx_post_buf[2]; 220 struct spi_transfer tx_post_trx; 221 222 /* for protect/unprotect/read length rxfifo */ 223 struct spi_message rx_msg; 224 u8 rx_buf[3]; 225 struct spi_transfer rx_trx; 226 227 /* receive handling */ 228 struct spi_message rx_buf_msg; 229 u8 rx_addr_buf[2]; 230 struct spi_transfer rx_addr_trx; 231 u8 rx_lqi_buf[2]; 232 struct spi_transfer rx_lqi_trx; 233 u8 rx_fifo_buf[RX_FIFO_SIZE]; 234 struct spi_transfer rx_fifo_buf_trx; 235 236 /* isr handling for reading intstat */ 237 struct spi_message irq_msg; 238 u8 irq_buf[2]; 239 struct spi_transfer irq_trx; 240 }; 241 242 /* regmap information for short address register access */ 243 #define MRF24J40_SHORT_WRITE 0x01 244 #define MRF24J40_SHORT_READ 0x00 245 #define MRF24J40_SHORT_NUMREGS 0x3F 246 247 /* regmap information for long address register access */ 248 #define MRF24J40_LONG_ACCESS 0x80 249 #define MRF24J40_LONG_NUMREGS 0x38F 250 251 /* Read/Write SPI Commands for Short and Long Address registers. */ 252 #define MRF24J40_READSHORT(reg) ((reg) << 1) 253 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1) 254 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5) 255 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4) 256 257 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */ 258 #define MAX_SPI_SPEED_HZ 10000000 259 260 #define printdev(X) (&X->spi->dev) 261 262 static bool 263 mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg) 264 { 265 switch (reg) { 266 case REG_RXMCR: 267 case REG_PANIDL: 268 case REG_PANIDH: 269 case REG_SADRL: 270 case REG_SADRH: 271 case REG_EADR0: 272 case REG_EADR1: 273 case REG_EADR2: 274 case REG_EADR3: 275 case REG_EADR4: 276 case REG_EADR5: 277 case REG_EADR6: 278 case REG_EADR7: 279 case REG_RXFLUSH: 280 case REG_ORDER: 281 case REG_TXMCR: 282 case REG_ACKTMOUT: 283 case REG_ESLOTG1: 284 case REG_SYMTICKL: 285 case REG_SYMTICKH: 286 case REG_PACON0: 287 case REG_PACON1: 288 case REG_PACON2: 289 case REG_TXBCON0: 290 case REG_TXNCON: 291 case REG_TXG1CON: 292 case REG_TXG2CON: 293 case REG_ESLOTG23: 294 case REG_ESLOTG45: 295 case REG_ESLOTG67: 296 case REG_TXPEND: 297 case REG_WAKECON: 298 case REG_FROMOFFSET: 299 case REG_TXBCON1: 300 case REG_GATECLK: 301 case REG_TXTIME: 302 case REG_HSYMTMRL: 303 case REG_HSYMTMRH: 304 case REG_SOFTRST: 305 case REG_SECCON0: 306 case REG_SECCON1: 307 case REG_TXSTBL: 308 case REG_RXSR: 309 case REG_INTCON: 310 case REG_TRISGPIO: 311 case REG_GPIO: 312 case REG_RFCTL: 313 case REG_SECCR2: 314 case REG_SLPACK: 315 case REG_BBREG0: 316 case REG_BBREG1: 317 case REG_BBREG2: 318 case REG_BBREG3: 319 case REG_BBREG4: 320 case REG_BBREG6: 321 case REG_CCAEDTH: 322 return true; 323 default: 324 return false; 325 } 326 } 327 328 static bool 329 mrf24j40_short_reg_readable(struct device *dev, unsigned int reg) 330 { 331 bool rc; 332 333 /* all writeable are also readable */ 334 rc = mrf24j40_short_reg_writeable(dev, reg); 335 if (rc) 336 return rc; 337 338 /* readonly regs */ 339 switch (reg) { 340 case REG_TXSTAT: 341 case REG_INTSTAT: 342 return true; 343 default: 344 return false; 345 } 346 } 347 348 static bool 349 mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg) 350 { 351 /* can be changed during runtime */ 352 switch (reg) { 353 case REG_TXSTAT: 354 case REG_INTSTAT: 355 case REG_RXFLUSH: 356 case REG_TXNCON: 357 case REG_SOFTRST: 358 case REG_RFCTL: 359 case REG_TXBCON0: 360 case REG_TXG1CON: 361 case REG_TXG2CON: 362 case REG_TXBCON1: 363 case REG_SECCON0: 364 case REG_RXSR: 365 case REG_SLPACK: 366 case REG_SECCR2: 367 case REG_BBREG6: 368 /* use them in spi_async and regmap so it's volatile */ 369 case REG_BBREG1: 370 return true; 371 default: 372 return false; 373 } 374 } 375 376 static bool 377 mrf24j40_short_reg_precious(struct device *dev, unsigned int reg) 378 { 379 /* don't clear irq line on read */ 380 switch (reg) { 381 case REG_INTSTAT: 382 return true; 383 default: 384 return false; 385 } 386 } 387 388 static const struct regmap_config mrf24j40_short_regmap = { 389 .name = "mrf24j40_short", 390 .reg_bits = 7, 391 .val_bits = 8, 392 .pad_bits = 1, 393 .write_flag_mask = MRF24J40_SHORT_WRITE, 394 .read_flag_mask = MRF24J40_SHORT_READ, 395 .cache_type = REGCACHE_RBTREE, 396 .max_register = MRF24J40_SHORT_NUMREGS, 397 .writeable_reg = mrf24j40_short_reg_writeable, 398 .readable_reg = mrf24j40_short_reg_readable, 399 .volatile_reg = mrf24j40_short_reg_volatile, 400 .precious_reg = mrf24j40_short_reg_precious, 401 }; 402 403 static bool 404 mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg) 405 { 406 switch (reg) { 407 case REG_RFCON0: 408 case REG_RFCON1: 409 case REG_RFCON2: 410 case REG_RFCON3: 411 case REG_RFCON5: 412 case REG_RFCON6: 413 case REG_RFCON7: 414 case REG_RFCON8: 415 case REG_SLPCAL2: 416 case REG_SLPCON0: 417 case REG_SLPCON1: 418 case REG_WAKETIMEL: 419 case REG_WAKETIMEH: 420 case REG_REMCNTL: 421 case REG_REMCNTH: 422 case REG_MAINCNT0: 423 case REG_MAINCNT1: 424 case REG_MAINCNT2: 425 case REG_MAINCNT3: 426 case REG_TESTMODE: 427 case REG_ASSOEAR0: 428 case REG_ASSOEAR1: 429 case REG_ASSOEAR2: 430 case REG_ASSOEAR3: 431 case REG_ASSOEAR4: 432 case REG_ASSOEAR5: 433 case REG_ASSOEAR6: 434 case REG_ASSOEAR7: 435 case REG_ASSOSAR0: 436 case REG_ASSOSAR1: 437 case REG_UNONCE0: 438 case REG_UNONCE1: 439 case REG_UNONCE2: 440 case REG_UNONCE3: 441 case REG_UNONCE4: 442 case REG_UNONCE5: 443 case REG_UNONCE6: 444 case REG_UNONCE7: 445 case REG_UNONCE8: 446 case REG_UNONCE9: 447 case REG_UNONCE10: 448 case REG_UNONCE11: 449 case REG_UNONCE12: 450 return true; 451 default: 452 return false; 453 } 454 } 455 456 static bool 457 mrf24j40_long_reg_readable(struct device *dev, unsigned int reg) 458 { 459 bool rc; 460 461 /* all writeable are also readable */ 462 rc = mrf24j40_long_reg_writeable(dev, reg); 463 if (rc) 464 return rc; 465 466 /* readonly regs */ 467 switch (reg) { 468 case REG_SLPCAL0: 469 case REG_SLPCAL1: 470 case REG_RFSTATE: 471 case REG_RSSI: 472 return true; 473 default: 474 return false; 475 } 476 } 477 478 static bool 479 mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg) 480 { 481 /* can be changed during runtime */ 482 switch (reg) { 483 case REG_SLPCAL0: 484 case REG_SLPCAL1: 485 case REG_SLPCAL2: 486 case REG_RFSTATE: 487 case REG_RSSI: 488 case REG_MAINCNT3: 489 return true; 490 default: 491 return false; 492 } 493 } 494 495 static const struct regmap_config mrf24j40_long_regmap = { 496 .name = "mrf24j40_long", 497 .reg_bits = 11, 498 .val_bits = 8, 499 .pad_bits = 5, 500 .write_flag_mask = MRF24J40_LONG_ACCESS, 501 .read_flag_mask = MRF24J40_LONG_ACCESS, 502 .cache_type = REGCACHE_RBTREE, 503 .max_register = MRF24J40_LONG_NUMREGS, 504 .writeable_reg = mrf24j40_long_reg_writeable, 505 .readable_reg = mrf24j40_long_reg_readable, 506 .volatile_reg = mrf24j40_long_reg_volatile, 507 }; 508 509 static int mrf24j40_long_regmap_write(void *context, const void *data, 510 size_t count) 511 { 512 struct spi_device *spi = context; 513 u8 buf[3]; 514 515 if (count > 3) 516 return -EINVAL; 517 518 /* regmap supports read/write mask only in frist byte 519 * long write access need to set the 12th bit, so we 520 * make special handling for write. 521 */ 522 memcpy(buf, data, count); 523 buf[1] |= (1 << 4); 524 525 return spi_write(spi, buf, count); 526 } 527 528 static int 529 mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size, 530 void *val, size_t val_size) 531 { 532 struct spi_device *spi = context; 533 534 return spi_write_then_read(spi, reg, reg_size, val, val_size); 535 } 536 537 static const struct regmap_bus mrf24j40_long_regmap_bus = { 538 .write = mrf24j40_long_regmap_write, 539 .read = mrf24j40_long_regmap_read, 540 .reg_format_endian_default = REGMAP_ENDIAN_BIG, 541 .val_format_endian_default = REGMAP_ENDIAN_BIG, 542 }; 543 544 static void write_tx_buf_complete(void *context) 545 { 546 struct mrf24j40 *devrec = context; 547 __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb); 548 u8 val = BIT_TXNTRIG; 549 int ret; 550 551 if (ieee802154_is_ackreq(fc)) 552 val |= BIT_TXNACKREQ; 553 554 devrec->tx_post_msg.complete = NULL; 555 devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON); 556 devrec->tx_post_buf[1] = val; 557 558 ret = spi_async(devrec->spi, &devrec->tx_post_msg); 559 if (ret) 560 dev_err(printdev(devrec), "SPI write Failed for transmit buf\n"); 561 } 562 563 /* This function relies on an undocumented write method. Once a write command 564 and address is set, as many bytes of data as desired can be clocked into 565 the device. The datasheet only shows setting one byte at a time. */ 566 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg, 567 const u8 *data, size_t length) 568 { 569 u16 cmd; 570 int ret; 571 572 /* Range check the length. 2 bytes are used for the length fields.*/ 573 if (length > TX_FIFO_SIZE-2) { 574 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n"); 575 length = TX_FIFO_SIZE-2; 576 } 577 578 cmd = MRF24J40_WRITELONG(reg); 579 devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff; 580 devrec->tx_hdr_buf[1] = cmd & 0xff; 581 devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */ 582 devrec->tx_len_buf[1] = length; /* Total length */ 583 devrec->tx_buf_trx.tx_buf = data; 584 devrec->tx_buf_trx.len = length; 585 586 ret = spi_async(devrec->spi, &devrec->tx_msg); 587 if (ret) 588 dev_err(printdev(devrec), "SPI write Failed for TX buf\n"); 589 590 return ret; 591 } 592 593 static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb) 594 { 595 struct mrf24j40 *devrec = hw->priv; 596 597 dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len); 598 devrec->tx_skb = skb; 599 600 return write_tx_buf(devrec, 0x000, skb->data, skb->len); 601 } 602 603 static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level) 604 { 605 /* TODO: */ 606 pr_warn("mrf24j40: ed not implemented\n"); 607 *level = 0; 608 return 0; 609 } 610 611 static int mrf24j40_start(struct ieee802154_hw *hw) 612 { 613 struct mrf24j40 *devrec = hw->priv; 614 615 dev_dbg(printdev(devrec), "start\n"); 616 617 /* Clear TXNIE and RXIE. Enable interrupts */ 618 return regmap_update_bits(devrec->regmap_short, REG_INTCON, 619 BIT_TXNIE | BIT_RXIE, 0); 620 } 621 622 static void mrf24j40_stop(struct ieee802154_hw *hw) 623 { 624 struct mrf24j40 *devrec = hw->priv; 625 626 dev_dbg(printdev(devrec), "stop\n"); 627 628 /* Set TXNIE and RXIE. Disable Interrupts */ 629 regmap_update_bits(devrec->regmap_short, REG_INTCON, 630 BIT_TXNIE | BIT_TXNIE, BIT_TXNIE | BIT_TXNIE); 631 } 632 633 static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel) 634 { 635 struct mrf24j40 *devrec = hw->priv; 636 u8 val; 637 int ret; 638 639 dev_dbg(printdev(devrec), "Set Channel %d\n", channel); 640 641 WARN_ON(page != 0); 642 WARN_ON(channel < MRF24J40_CHAN_MIN); 643 WARN_ON(channel > MRF24J40_CHAN_MAX); 644 645 /* Set Channel TODO */ 646 val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND; 647 ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, 648 RFCON0_CH_MASK, val); 649 if (ret) 650 return ret; 651 652 /* RF Reset */ 653 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 654 BIT_RFRST); 655 if (ret) 656 return ret; 657 658 ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0); 659 if (!ret) 660 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */ 661 662 return ret; 663 } 664 665 static int mrf24j40_filter(struct ieee802154_hw *hw, 666 struct ieee802154_hw_addr_filt *filt, 667 unsigned long changed) 668 { 669 struct mrf24j40 *devrec = hw->priv; 670 671 dev_dbg(printdev(devrec), "filter\n"); 672 673 if (changed & IEEE802154_AFILT_SADDR_CHANGED) { 674 /* Short Addr */ 675 u8 addrh, addrl; 676 677 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff; 678 addrl = le16_to_cpu(filt->short_addr) & 0xff; 679 680 regmap_write(devrec->regmap_short, REG_SADRH, addrh); 681 regmap_write(devrec->regmap_short, REG_SADRL, addrl); 682 dev_dbg(printdev(devrec), 683 "Set short addr to %04hx\n", filt->short_addr); 684 } 685 686 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { 687 /* Device Address */ 688 u8 i, addr[8]; 689 690 memcpy(addr, &filt->ieee_addr, 8); 691 for (i = 0; i < 8; i++) 692 regmap_write(devrec->regmap_short, REG_EADR0 + i, 693 addr[i]); 694 695 #ifdef DEBUG 696 pr_debug("Set long addr to: "); 697 for (i = 0; i < 8; i++) 698 pr_debug("%02hhx ", addr[7 - i]); 699 pr_debug("\n"); 700 #endif 701 } 702 703 if (changed & IEEE802154_AFILT_PANID_CHANGED) { 704 /* PAN ID */ 705 u8 panidl, panidh; 706 707 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff; 708 panidl = le16_to_cpu(filt->pan_id) & 0xff; 709 regmap_write(devrec->regmap_short, REG_PANIDH, panidh); 710 regmap_write(devrec->regmap_short, REG_PANIDL, panidl); 711 712 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id); 713 } 714 715 if (changed & IEEE802154_AFILT_PANC_CHANGED) { 716 /* Pan Coordinator */ 717 u8 val; 718 int ret; 719 720 if (filt->pan_coord) 721 val = BIT_PANCOORD; 722 else 723 val = 0; 724 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 725 BIT_PANCOORD, val); 726 if (ret) 727 return ret; 728 729 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA). 730 * REG_ORDER is maintained as default (no beacon/superframe). 731 */ 732 733 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n", 734 filt->pan_coord ? "on" : "off"); 735 } 736 737 return 0; 738 } 739 740 static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec) 741 { 742 int ret; 743 744 /* Turn back on reception of packets off the air. */ 745 devrec->rx_msg.complete = NULL; 746 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1); 747 devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */ 748 ret = spi_async(devrec->spi, &devrec->rx_msg); 749 if (ret) 750 dev_err(printdev(devrec), "failed to unlock rx buffer\n"); 751 } 752 753 static void mrf24j40_handle_rx_read_buf_complete(void *context) 754 { 755 struct mrf24j40 *devrec = context; 756 u8 len = devrec->rx_buf[2]; 757 u8 rx_local_buf[RX_FIFO_SIZE]; 758 struct sk_buff *skb; 759 760 memcpy(rx_local_buf, devrec->rx_fifo_buf, len); 761 mrf24j40_handle_rx_read_buf_unlock(devrec); 762 763 skb = dev_alloc_skb(IEEE802154_MTU); 764 if (!skb) { 765 dev_err(printdev(devrec), "failed to allocate skb\n"); 766 return; 767 } 768 769 memcpy(skb_put(skb, len), rx_local_buf, len); 770 ieee802154_rx_irqsafe(devrec->hw, skb, 0); 771 772 #ifdef DEBUG 773 print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1, 774 rx_local_buf, len, 0); 775 pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n", 776 devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]); 777 #endif 778 } 779 780 static void mrf24j40_handle_rx_read_buf(void *context) 781 { 782 struct mrf24j40 *devrec = context; 783 u16 cmd; 784 int ret; 785 786 /* if length is invalid read the full MTU */ 787 if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2])) 788 devrec->rx_buf[2] = IEEE802154_MTU; 789 790 cmd = MRF24J40_READLONG(REG_RX_FIFO + 1); 791 devrec->rx_addr_buf[0] = cmd >> 8 & 0xff; 792 devrec->rx_addr_buf[1] = cmd & 0xff; 793 devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2]; 794 ret = spi_async(devrec->spi, &devrec->rx_buf_msg); 795 if (ret) { 796 dev_err(printdev(devrec), "failed to read rx buffer\n"); 797 mrf24j40_handle_rx_read_buf_unlock(devrec); 798 } 799 } 800 801 static void mrf24j40_handle_rx_read_len(void *context) 802 { 803 struct mrf24j40 *devrec = context; 804 u16 cmd; 805 int ret; 806 807 /* read the length of received frame */ 808 devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf; 809 devrec->rx_trx.len = 3; 810 cmd = MRF24J40_READLONG(REG_RX_FIFO); 811 devrec->rx_buf[0] = cmd >> 8 & 0xff; 812 devrec->rx_buf[1] = cmd & 0xff; 813 814 ret = spi_async(devrec->spi, &devrec->rx_msg); 815 if (ret) { 816 dev_err(printdev(devrec), "failed to read rx buffer length\n"); 817 mrf24j40_handle_rx_read_buf_unlock(devrec); 818 } 819 } 820 821 static int mrf24j40_handle_rx(struct mrf24j40 *devrec) 822 { 823 /* Turn off reception of packets off the air. This prevents the 824 * device from overwriting the buffer while we're reading it. 825 */ 826 devrec->rx_msg.complete = mrf24j40_handle_rx_read_len; 827 devrec->rx_trx.len = 2; 828 devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1); 829 devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */ 830 831 return spi_async(devrec->spi, &devrec->rx_msg); 832 } 833 834 static int 835 mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be, 836 u8 retries) 837 { 838 struct mrf24j40 *devrec = hw->priv; 839 u8 val; 840 841 /* min_be */ 842 val = min_be << TXMCR_MIN_BE_SHIFT; 843 /* csma backoffs */ 844 val |= retries << TXMCR_CSMA_RETRIES_SHIFT; 845 846 return regmap_update_bits(devrec->regmap_short, REG_TXMCR, 847 TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK, 848 val); 849 } 850 851 static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw, 852 const struct wpan_phy_cca *cca) 853 { 854 struct mrf24j40 *devrec = hw->priv; 855 u8 val; 856 857 /* mapping 802.15.4 to driver spec */ 858 switch (cca->mode) { 859 case NL802154_CCA_ENERGY: 860 val = 2; 861 break; 862 case NL802154_CCA_CARRIER: 863 val = 1; 864 break; 865 case NL802154_CCA_ENERGY_CARRIER: 866 switch (cca->opt) { 867 case NL802154_CCA_OPT_ENERGY_CARRIER_AND: 868 val = 3; 869 break; 870 default: 871 return -EINVAL; 872 } 873 break; 874 default: 875 return -EINVAL; 876 } 877 878 return regmap_update_bits(devrec->regmap_short, REG_BBREG2, 879 BBREG2_CCA_MODE_MASK, 880 val << BBREG2_CCA_MODE_SHIFT); 881 } 882 883 /* array for representing ed levels */ 884 static const s32 mrf24j40_ed_levels[] = { 885 -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100, 886 -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100, 887 -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100, 888 -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100, 889 -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100, 890 -4000, -3900, -3800, -3700, -3600, -3500 891 }; 892 893 /* map ed levels to register value */ 894 static const s32 mrf24j40_ed_levels_map[][2] = { 895 { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 }, 896 { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 }, 897 { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 }, 898 { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 }, 899 { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 }, 900 { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 }, 901 { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 }, 902 { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 }, 903 { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 }, 904 { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 }, 905 { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 }, 906 { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 }, 907 { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 }, 908 { -3700, 253 }, { -3600, 254 }, { -3500, 255 }, 909 }; 910 911 static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm) 912 { 913 struct mrf24j40 *devrec = hw->priv; 914 int i; 915 916 for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) { 917 if (mrf24j40_ed_levels_map[i][0] == mbm) 918 return regmap_write(devrec->regmap_short, REG_CCAEDTH, 919 mrf24j40_ed_levels_map[i][1]); 920 } 921 922 return -EINVAL; 923 } 924 925 static const s32 mrf24j40ma_powers[] = { 926 0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190, 927 -1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370, 928 -2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630, 929 }; 930 931 static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm) 932 { 933 struct mrf24j40 *devrec = hw->priv; 934 s32 small_scale; 935 u8 val; 936 937 if (0 >= mbm && mbm > -1000) { 938 val = TXPWRL_0 << TXPWRL_SHIFT; 939 small_scale = mbm; 940 } else if (-1000 >= mbm && mbm > -2000) { 941 val = TXPWRL_10 << TXPWRL_SHIFT; 942 small_scale = mbm + 1000; 943 } else if (-2000 >= mbm && mbm > -3000) { 944 val = TXPWRL_20 << TXPWRL_SHIFT; 945 small_scale = mbm + 2000; 946 } else if (-3000 >= mbm && mbm > -4000) { 947 val = TXPWRL_30 << TXPWRL_SHIFT; 948 small_scale = mbm + 3000; 949 } else { 950 return -EINVAL; 951 } 952 953 switch (small_scale) { 954 case 0: 955 val |= (TXPWRS_0 << TXPWRS_SHIFT); 956 break; 957 case -50: 958 val |= (TXPWRS_0_5 << TXPWRS_SHIFT); 959 break; 960 case -120: 961 val |= (TXPWRS_1_2 << TXPWRS_SHIFT); 962 break; 963 case -190: 964 val |= (TXPWRS_1_9 << TXPWRS_SHIFT); 965 break; 966 case -280: 967 val |= (TXPWRS_2_8 << TXPWRS_SHIFT); 968 break; 969 case -370: 970 val |= (TXPWRS_3_7 << TXPWRS_SHIFT); 971 break; 972 case -490: 973 val |= (TXPWRS_4_9 << TXPWRS_SHIFT); 974 break; 975 case -630: 976 val |= (TXPWRS_6_3 << TXPWRS_SHIFT); 977 break; 978 default: 979 return -EINVAL; 980 } 981 982 return regmap_update_bits(devrec->regmap_long, REG_RFCON3, 983 TXPWRL_MASK | TXPWRS_MASK, val); 984 } 985 986 static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on) 987 { 988 struct mrf24j40 *devrec = hw->priv; 989 int ret; 990 991 if (on) { 992 /* set PROMI, ERRPKT and NOACKRSP */ 993 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 994 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP, 995 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP); 996 } else { 997 /* clear PROMI, ERRPKT and NOACKRSP */ 998 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 999 BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP, 1000 0); 1001 } 1002 1003 return ret; 1004 } 1005 1006 static const struct ieee802154_ops mrf24j40_ops = { 1007 .owner = THIS_MODULE, 1008 .xmit_async = mrf24j40_tx, 1009 .ed = mrf24j40_ed, 1010 .start = mrf24j40_start, 1011 .stop = mrf24j40_stop, 1012 .set_channel = mrf24j40_set_channel, 1013 .set_hw_addr_filt = mrf24j40_filter, 1014 .set_csma_params = mrf24j40_csma_params, 1015 .set_cca_mode = mrf24j40_set_cca_mode, 1016 .set_cca_ed_level = mrf24j40_set_cca_ed_level, 1017 .set_txpower = mrf24j40_set_txpower, 1018 .set_promiscuous_mode = mrf24j40_set_promiscuous_mode, 1019 }; 1020 1021 static void mrf24j40_intstat_complete(void *context) 1022 { 1023 struct mrf24j40 *devrec = context; 1024 u8 intstat = devrec->irq_buf[1]; 1025 1026 enable_irq(devrec->spi->irq); 1027 1028 /* Check for TX complete */ 1029 if (intstat & BIT_TXNIF) 1030 ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false); 1031 1032 /* Check for Rx */ 1033 if (intstat & BIT_RXIF) 1034 mrf24j40_handle_rx(devrec); 1035 } 1036 1037 static irqreturn_t mrf24j40_isr(int irq, void *data) 1038 { 1039 struct mrf24j40 *devrec = data; 1040 int ret; 1041 1042 disable_irq_nosync(irq); 1043 1044 devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT); 1045 /* Read the interrupt status */ 1046 ret = spi_async(devrec->spi, &devrec->irq_msg); 1047 if (ret) { 1048 enable_irq(irq); 1049 return IRQ_NONE; 1050 } 1051 1052 return IRQ_HANDLED; 1053 } 1054 1055 static int mrf24j40_hw_init(struct mrf24j40 *devrec) 1056 { 1057 u32 irq_type; 1058 int ret; 1059 1060 /* Initialize the device. 1061 From datasheet section 3.2: Initialization. */ 1062 ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07); 1063 if (ret) 1064 goto err_ret; 1065 1066 ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98); 1067 if (ret) 1068 goto err_ret; 1069 1070 ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95); 1071 if (ret) 1072 goto err_ret; 1073 1074 ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03); 1075 if (ret) 1076 goto err_ret; 1077 1078 ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01); 1079 if (ret) 1080 goto err_ret; 1081 1082 ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80); 1083 if (ret) 1084 goto err_ret; 1085 1086 ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90); 1087 if (ret) 1088 goto err_ret; 1089 1090 ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80); 1091 if (ret) 1092 goto err_ret; 1093 1094 ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10); 1095 if (ret) 1096 goto err_ret; 1097 1098 ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21); 1099 if (ret) 1100 goto err_ret; 1101 1102 ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80); 1103 if (ret) 1104 goto err_ret; 1105 1106 ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60); 1107 if (ret) 1108 goto err_ret; 1109 1110 ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40); 1111 if (ret) 1112 goto err_ret; 1113 1114 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04); 1115 if (ret) 1116 goto err_ret; 1117 1118 ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0); 1119 if (ret) 1120 goto err_ret; 1121 1122 udelay(192); 1123 1124 /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */ 1125 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00); 1126 if (ret) 1127 goto err_ret; 1128 1129 if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) { 1130 /* Enable external amplifier. 1131 * From MRF24J40MC datasheet section 1.3: Operation. 1132 */ 1133 regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07, 1134 0x07); 1135 1136 /* Set GPIO3 as output. */ 1137 regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08, 1138 0x08); 1139 1140 /* Set GPIO3 HIGH to enable U5 voltage regulator */ 1141 regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08); 1142 1143 /* Reduce TX pwr to meet FCC requirements. 1144 * From MRF24J40MC datasheet section 3.1.1 1145 */ 1146 regmap_write(devrec->regmap_long, REG_RFCON3, 0x28); 1147 } 1148 1149 irq_type = irq_get_trigger_type(devrec->spi->irq); 1150 if (irq_type == IRQ_TYPE_EDGE_RISING || 1151 irq_type == IRQ_TYPE_EDGE_FALLING) 1152 dev_warn(&devrec->spi->dev, 1153 "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n"); 1154 switch (irq_type) { 1155 case IRQ_TYPE_EDGE_RISING: 1156 case IRQ_TYPE_LEVEL_HIGH: 1157 /* set interrupt polarity to rising */ 1158 ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0, 1159 BIT_INTEDGE, BIT_INTEDGE); 1160 if (ret) 1161 goto err_ret; 1162 break; 1163 default: 1164 /* default is falling edge */ 1165 break; 1166 } 1167 1168 return 0; 1169 1170 err_ret: 1171 return ret; 1172 } 1173 1174 static void 1175 mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec) 1176 { 1177 spi_message_init(&devrec->tx_msg); 1178 devrec->tx_msg.context = devrec; 1179 devrec->tx_msg.complete = write_tx_buf_complete; 1180 devrec->tx_hdr_trx.len = 2; 1181 devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf; 1182 spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg); 1183 devrec->tx_len_trx.len = 2; 1184 devrec->tx_len_trx.tx_buf = devrec->tx_len_buf; 1185 spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg); 1186 spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg); 1187 1188 spi_message_init(&devrec->tx_post_msg); 1189 devrec->tx_post_msg.context = devrec; 1190 devrec->tx_post_trx.len = 2; 1191 devrec->tx_post_trx.tx_buf = devrec->tx_post_buf; 1192 spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg); 1193 } 1194 1195 static void 1196 mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec) 1197 { 1198 spi_message_init(&devrec->rx_msg); 1199 devrec->rx_msg.context = devrec; 1200 devrec->rx_trx.len = 2; 1201 devrec->rx_trx.tx_buf = devrec->rx_buf; 1202 devrec->rx_trx.rx_buf = devrec->rx_buf; 1203 spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg); 1204 1205 spi_message_init(&devrec->rx_buf_msg); 1206 devrec->rx_buf_msg.context = devrec; 1207 devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete; 1208 devrec->rx_addr_trx.len = 2; 1209 devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf; 1210 spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg); 1211 devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf; 1212 spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg); 1213 devrec->rx_lqi_trx.len = 2; 1214 devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf; 1215 spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg); 1216 } 1217 1218 static void 1219 mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec) 1220 { 1221 spi_message_init(&devrec->irq_msg); 1222 devrec->irq_msg.context = devrec; 1223 devrec->irq_msg.complete = mrf24j40_intstat_complete; 1224 devrec->irq_trx.len = 2; 1225 devrec->irq_trx.tx_buf = devrec->irq_buf; 1226 devrec->irq_trx.rx_buf = devrec->irq_buf; 1227 spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg); 1228 } 1229 1230 static void mrf24j40_phy_setup(struct mrf24j40 *devrec) 1231 { 1232 ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr); 1233 devrec->hw->phy->current_channel = 11; 1234 1235 /* mrf24j40 supports max_minbe 0 - 3 */ 1236 devrec->hw->phy->supported.max_minbe = 3; 1237 /* datasheet doesn't say anything about max_be, but we have min_be 1238 * So we assume the max_be default. 1239 */ 1240 devrec->hw->phy->supported.min_maxbe = 5; 1241 devrec->hw->phy->supported.max_maxbe = 5; 1242 1243 devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER; 1244 devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | 1245 BIT(NL802154_CCA_CARRIER) | 1246 BIT(NL802154_CCA_ENERGY_CARRIER); 1247 devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND); 1248 1249 devrec->hw->phy->cca_ed_level = -6900; 1250 devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels; 1251 devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels); 1252 1253 switch (spi_get_device_id(devrec->spi)->driver_data) { 1254 case MRF24J40: 1255 case MRF24J40MA: 1256 devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers; 1257 devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers); 1258 devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER; 1259 break; 1260 default: 1261 break; 1262 } 1263 } 1264 1265 static int mrf24j40_probe(struct spi_device *spi) 1266 { 1267 int ret = -ENOMEM, irq_type; 1268 struct ieee802154_hw *hw; 1269 struct mrf24j40 *devrec; 1270 1271 dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq); 1272 1273 /* Register with the 802154 subsystem */ 1274 1275 hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops); 1276 if (!hw) 1277 goto err_ret; 1278 1279 devrec = hw->priv; 1280 devrec->spi = spi; 1281 spi_set_drvdata(spi, devrec); 1282 devrec->hw = hw; 1283 devrec->hw->parent = &spi->dev; 1284 devrec->hw->phy->supported.channels[0] = CHANNEL_MASK; 1285 devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT | 1286 IEEE802154_HW_CSMA_PARAMS | 1287 IEEE802154_HW_PROMISCUOUS; 1288 1289 devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE | 1290 WPAN_PHY_FLAG_CCA_ED_LEVEL; 1291 1292 mrf24j40_setup_tx_spi_messages(devrec); 1293 mrf24j40_setup_rx_spi_messages(devrec); 1294 mrf24j40_setup_irq_spi_messages(devrec); 1295 1296 devrec->regmap_short = devm_regmap_init_spi(spi, 1297 &mrf24j40_short_regmap); 1298 if (IS_ERR(devrec->regmap_short)) { 1299 ret = PTR_ERR(devrec->regmap_short); 1300 dev_err(&spi->dev, "Failed to allocate short register map: %d\n", 1301 ret); 1302 goto err_register_device; 1303 } 1304 1305 devrec->regmap_long = devm_regmap_init(&spi->dev, 1306 &mrf24j40_long_regmap_bus, 1307 spi, &mrf24j40_long_regmap); 1308 if (IS_ERR(devrec->regmap_long)) { 1309 ret = PTR_ERR(devrec->regmap_long); 1310 dev_err(&spi->dev, "Failed to allocate long register map: %d\n", 1311 ret); 1312 goto err_register_device; 1313 } 1314 1315 if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) { 1316 dev_warn(&spi->dev, "spi clock above possible maximum: %d", 1317 MAX_SPI_SPEED_HZ); 1318 return -EINVAL; 1319 } 1320 1321 ret = mrf24j40_hw_init(devrec); 1322 if (ret) 1323 goto err_register_device; 1324 1325 mrf24j40_phy_setup(devrec); 1326 1327 /* request IRQF_TRIGGER_LOW as fallback default */ 1328 irq_type = irq_get_trigger_type(spi->irq); 1329 if (!irq_type) 1330 irq_type = IRQF_TRIGGER_LOW; 1331 1332 ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr, 1333 irq_type, dev_name(&spi->dev), devrec); 1334 if (ret) { 1335 dev_err(printdev(devrec), "Unable to get IRQ"); 1336 goto err_register_device; 1337 } 1338 1339 dev_dbg(printdev(devrec), "registered mrf24j40\n"); 1340 ret = ieee802154_register_hw(devrec->hw); 1341 if (ret) 1342 goto err_register_device; 1343 1344 return 0; 1345 1346 err_register_device: 1347 ieee802154_free_hw(devrec->hw); 1348 err_ret: 1349 return ret; 1350 } 1351 1352 static int mrf24j40_remove(struct spi_device *spi) 1353 { 1354 struct mrf24j40 *devrec = spi_get_drvdata(spi); 1355 1356 dev_dbg(printdev(devrec), "remove\n"); 1357 1358 ieee802154_unregister_hw(devrec->hw); 1359 ieee802154_free_hw(devrec->hw); 1360 /* TODO: Will ieee802154_free_device() wait until ->xmit() is 1361 * complete? */ 1362 1363 return 0; 1364 } 1365 1366 static const struct of_device_id mrf24j40_of_match[] = { 1367 { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 }, 1368 { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA }, 1369 { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC }, 1370 { }, 1371 }; 1372 MODULE_DEVICE_TABLE(of, mrf24j40_of_match); 1373 1374 static const struct spi_device_id mrf24j40_ids[] = { 1375 { "mrf24j40", MRF24J40 }, 1376 { "mrf24j40ma", MRF24J40MA }, 1377 { "mrf24j40mc", MRF24J40MC }, 1378 { }, 1379 }; 1380 MODULE_DEVICE_TABLE(spi, mrf24j40_ids); 1381 1382 static struct spi_driver mrf24j40_driver = { 1383 .driver = { 1384 .of_match_table = of_match_ptr(mrf24j40_of_match), 1385 .name = "mrf24j40", 1386 }, 1387 .id_table = mrf24j40_ids, 1388 .probe = mrf24j40_probe, 1389 .remove = mrf24j40_remove, 1390 }; 1391 1392 module_spi_driver(mrf24j40_driver); 1393 1394 MODULE_LICENSE("GPL"); 1395 MODULE_AUTHOR("Alan Ott"); 1396 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver"); 1397