17490b008SAlexander Aring /* 27490b008SAlexander Aring * AT86RF230/RF231 driver 37490b008SAlexander Aring * 47490b008SAlexander Aring * Copyright (C) 2009-2012 Siemens AG 57490b008SAlexander Aring * 67490b008SAlexander Aring * This program is free software; you can redistribute it and/or modify 77490b008SAlexander Aring * it under the terms of the GNU General Public License version 2 87490b008SAlexander Aring * as published by the Free Software Foundation. 97490b008SAlexander Aring * 107490b008SAlexander Aring * This program is distributed in the hope that it will be useful, 117490b008SAlexander Aring * but WITHOUT ANY WARRANTY; without even the implied warranty of 127490b008SAlexander Aring * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 137490b008SAlexander Aring * GNU General Public License for more details. 147490b008SAlexander Aring * 157490b008SAlexander Aring * Written by: 167490b008SAlexander Aring * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> 177490b008SAlexander Aring * Alexander Smirnov <alex.bluesman.smirnov@gmail.com> 187490b008SAlexander Aring */ 197490b008SAlexander Aring 207490b008SAlexander Aring #ifndef _AT86RF230_H 217490b008SAlexander Aring #define _AT86RF230_H 227490b008SAlexander Aring 237490b008SAlexander Aring #define RG_TRX_STATUS (0x01) 247490b008SAlexander Aring #define SR_TRX_STATUS 0x01, 0x1f, 0 257490b008SAlexander Aring #define SR_RESERVED_01_3 0x01, 0x20, 5 267490b008SAlexander Aring #define SR_CCA_STATUS 0x01, 0x40, 6 277490b008SAlexander Aring #define SR_CCA_DONE 0x01, 0x80, 7 287490b008SAlexander Aring #define RG_TRX_STATE (0x02) 297490b008SAlexander Aring #define SR_TRX_CMD 0x02, 0x1f, 0 307490b008SAlexander Aring #define SR_TRAC_STATUS 0x02, 0xe0, 5 317490b008SAlexander Aring #define RG_TRX_CTRL_0 (0x03) 327490b008SAlexander Aring #define SR_CLKM_CTRL 0x03, 0x07, 0 337490b008SAlexander Aring #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 347490b008SAlexander Aring #define SR_PAD_IO_CLKM 0x03, 0x30, 4 357490b008SAlexander Aring #define SR_PAD_IO 0x03, 0xc0, 6 367490b008SAlexander Aring #define RG_TRX_CTRL_1 (0x04) 377490b008SAlexander Aring #define SR_IRQ_POLARITY 0x04, 0x01, 0 387490b008SAlexander Aring #define SR_IRQ_MASK_MODE 0x04, 0x02, 1 397490b008SAlexander Aring #define SR_SPI_CMD_MODE 0x04, 0x0c, 2 407490b008SAlexander Aring #define SR_RX_BL_CTRL 0x04, 0x10, 4 417490b008SAlexander Aring #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 427490b008SAlexander Aring #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 437490b008SAlexander Aring #define SR_PA_EXT_EN 0x04, 0x80, 7 447490b008SAlexander Aring #define RG_PHY_TX_PWR (0x05) 457490b008SAlexander Aring #define SR_TX_PWR_23X 0x05, 0x0f, 0 467490b008SAlexander Aring #define SR_PA_LT_230 0x05, 0x30, 4 477490b008SAlexander Aring #define SR_PA_BUF_LT_230 0x05, 0xc0, 6 487490b008SAlexander Aring #define SR_TX_PWR_212 0x05, 0x1f, 0 497490b008SAlexander Aring #define SR_GC_PA_212 0x05, 0x60, 5 507490b008SAlexander Aring #define SR_PA_BOOST_LT_212 0x05, 0x80, 7 517490b008SAlexander Aring #define RG_PHY_RSSI (0x06) 527490b008SAlexander Aring #define SR_RSSI 0x06, 0x1f, 0 537490b008SAlexander Aring #define SR_RND_VALUE 0x06, 0x60, 5 547490b008SAlexander Aring #define SR_RX_CRC_VALID 0x06, 0x80, 7 557490b008SAlexander Aring #define RG_PHY_ED_LEVEL (0x07) 567490b008SAlexander Aring #define SR_ED_LEVEL 0x07, 0xff, 0 577490b008SAlexander Aring #define RG_PHY_CC_CCA (0x08) 587490b008SAlexander Aring #define SR_CHANNEL 0x08, 0x1f, 0 597490b008SAlexander Aring #define SR_CCA_MODE 0x08, 0x60, 5 607490b008SAlexander Aring #define SR_CCA_REQUEST 0x08, 0x80, 7 617490b008SAlexander Aring #define RG_CCA_THRES (0x09) 627490b008SAlexander Aring #define SR_CCA_ED_THRES 0x09, 0x0f, 0 637490b008SAlexander Aring #define SR_RESERVED_09_1 0x09, 0xf0, 4 647490b008SAlexander Aring #define RG_RX_CTRL (0x0a) 657490b008SAlexander Aring #define SR_PDT_THRES 0x0a, 0x0f, 0 667490b008SAlexander Aring #define SR_RESERVED_0a_1 0x0a, 0xf0, 4 677490b008SAlexander Aring #define RG_SFD_VALUE (0x0b) 687490b008SAlexander Aring #define SR_SFD_VALUE 0x0b, 0xff, 0 697490b008SAlexander Aring #define RG_TRX_CTRL_2 (0x0c) 707490b008SAlexander Aring #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0 717490b008SAlexander Aring #define SR_SUB_MODE 0x0c, 0x04, 2 727490b008SAlexander Aring #define SR_BPSK_QPSK 0x0c, 0x08, 3 737490b008SAlexander Aring #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4 747490b008SAlexander Aring #define SR_RESERVED_0c_5 0x0c, 0x60, 5 757490b008SAlexander Aring #define SR_RX_SAFE_MODE 0x0c, 0x80, 7 767490b008SAlexander Aring #define RG_ANT_DIV (0x0d) 777490b008SAlexander Aring #define SR_ANT_CTRL 0x0d, 0x03, 0 787490b008SAlexander Aring #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2 797490b008SAlexander Aring #define SR_ANT_DIV_EN 0x0d, 0x08, 3 807490b008SAlexander Aring #define SR_RESERVED_0d_2 0x0d, 0x70, 4 817490b008SAlexander Aring #define SR_ANT_SEL 0x0d, 0x80, 7 827490b008SAlexander Aring #define RG_IRQ_MASK (0x0e) 837490b008SAlexander Aring #define SR_IRQ_MASK 0x0e, 0xff, 0 847490b008SAlexander Aring #define RG_IRQ_STATUS (0x0f) 857490b008SAlexander Aring #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 867490b008SAlexander Aring #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 877490b008SAlexander Aring #define SR_IRQ_2_RX_START 0x0f, 0x04, 2 887490b008SAlexander Aring #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 897490b008SAlexander Aring #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4 907490b008SAlexander Aring #define SR_IRQ_5_AMI 0x0f, 0x20, 5 917490b008SAlexander Aring #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 927490b008SAlexander Aring #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 937490b008SAlexander Aring #define RG_VREG_CTRL (0x10) 947490b008SAlexander Aring #define SR_RESERVED_10_6 0x10, 0x03, 0 957490b008SAlexander Aring #define SR_DVDD_OK 0x10, 0x04, 2 967490b008SAlexander Aring #define SR_DVREG_EXT 0x10, 0x08, 3 977490b008SAlexander Aring #define SR_RESERVED_10_3 0x10, 0x30, 4 987490b008SAlexander Aring #define SR_AVDD_OK 0x10, 0x40, 6 997490b008SAlexander Aring #define SR_AVREG_EXT 0x10, 0x80, 7 1007490b008SAlexander Aring #define RG_BATMON (0x11) 1017490b008SAlexander Aring #define SR_BATMON_VTH 0x11, 0x0f, 0 1027490b008SAlexander Aring #define SR_BATMON_HR 0x11, 0x10, 4 1037490b008SAlexander Aring #define SR_BATMON_OK 0x11, 0x20, 5 1047490b008SAlexander Aring #define SR_RESERVED_11_1 0x11, 0xc0, 6 1057490b008SAlexander Aring #define RG_XOSC_CTRL (0x12) 1067490b008SAlexander Aring #define SR_XTAL_TRIM 0x12, 0x0f, 0 1077490b008SAlexander Aring #define SR_XTAL_MODE 0x12, 0xf0, 4 1087490b008SAlexander Aring #define RG_RX_SYN (0x15) 1097490b008SAlexander Aring #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0 1107490b008SAlexander Aring #define SR_RESERVED_15_2 0x15, 0x70, 4 1117490b008SAlexander Aring #define SR_RX_PDT_DIS 0x15, 0x80, 7 1127490b008SAlexander Aring #define RG_XAH_CTRL_1 (0x17) 1137490b008SAlexander Aring #define SR_RESERVED_17_8 0x17, 0x01, 0 1147490b008SAlexander Aring #define SR_AACK_PROM_MODE 0x17, 0x02, 1 1157490b008SAlexander Aring #define SR_AACK_ACK_TIME 0x17, 0x04, 2 1167490b008SAlexander Aring #define SR_RESERVED_17_5 0x17, 0x08, 3 1177490b008SAlexander Aring #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 1187490b008SAlexander Aring #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 1197490b008SAlexander Aring #define SR_CSMA_LBT_MODE 0x17, 0x40, 6 1207490b008SAlexander Aring #define SR_RESERVED_17_1 0x17, 0x80, 7 1217490b008SAlexander Aring #define RG_FTN_CTRL (0x18) 1227490b008SAlexander Aring #define SR_RESERVED_18_2 0x18, 0x7f, 0 1237490b008SAlexander Aring #define SR_FTN_START 0x18, 0x80, 7 1247490b008SAlexander Aring #define RG_PLL_CF (0x1a) 1257490b008SAlexander Aring #define SR_RESERVED_1a_2 0x1a, 0x7f, 0 1267490b008SAlexander Aring #define SR_PLL_CF_START 0x1a, 0x80, 7 1277490b008SAlexander Aring #define RG_PLL_DCU (0x1b) 1287490b008SAlexander Aring #define SR_RESERVED_1b_3 0x1b, 0x3f, 0 1297490b008SAlexander Aring #define SR_RESERVED_1b_2 0x1b, 0x40, 6 1307490b008SAlexander Aring #define SR_PLL_DCU_START 0x1b, 0x80, 7 1317490b008SAlexander Aring #define RG_PART_NUM (0x1c) 1327490b008SAlexander Aring #define SR_PART_NUM 0x1c, 0xff, 0 1337490b008SAlexander Aring #define RG_VERSION_NUM (0x1d) 1347490b008SAlexander Aring #define SR_VERSION_NUM 0x1d, 0xff, 0 1357490b008SAlexander Aring #define RG_MAN_ID_0 (0x1e) 1367490b008SAlexander Aring #define SR_MAN_ID_0 0x1e, 0xff, 0 1377490b008SAlexander Aring #define RG_MAN_ID_1 (0x1f) 1387490b008SAlexander Aring #define SR_MAN_ID_1 0x1f, 0xff, 0 1397490b008SAlexander Aring #define RG_SHORT_ADDR_0 (0x20) 1407490b008SAlexander Aring #define SR_SHORT_ADDR_0 0x20, 0xff, 0 1417490b008SAlexander Aring #define RG_SHORT_ADDR_1 (0x21) 1427490b008SAlexander Aring #define SR_SHORT_ADDR_1 0x21, 0xff, 0 1437490b008SAlexander Aring #define RG_PAN_ID_0 (0x22) 1447490b008SAlexander Aring #define SR_PAN_ID_0 0x22, 0xff, 0 1457490b008SAlexander Aring #define RG_PAN_ID_1 (0x23) 1467490b008SAlexander Aring #define SR_PAN_ID_1 0x23, 0xff, 0 1477490b008SAlexander Aring #define RG_IEEE_ADDR_0 (0x24) 1487490b008SAlexander Aring #define SR_IEEE_ADDR_0 0x24, 0xff, 0 1497490b008SAlexander Aring #define RG_IEEE_ADDR_1 (0x25) 1507490b008SAlexander Aring #define SR_IEEE_ADDR_1 0x25, 0xff, 0 1517490b008SAlexander Aring #define RG_IEEE_ADDR_2 (0x26) 1527490b008SAlexander Aring #define SR_IEEE_ADDR_2 0x26, 0xff, 0 1537490b008SAlexander Aring #define RG_IEEE_ADDR_3 (0x27) 1547490b008SAlexander Aring #define SR_IEEE_ADDR_3 0x27, 0xff, 0 1557490b008SAlexander Aring #define RG_IEEE_ADDR_4 (0x28) 1567490b008SAlexander Aring #define SR_IEEE_ADDR_4 0x28, 0xff, 0 1577490b008SAlexander Aring #define RG_IEEE_ADDR_5 (0x29) 1587490b008SAlexander Aring #define SR_IEEE_ADDR_5 0x29, 0xff, 0 1597490b008SAlexander Aring #define RG_IEEE_ADDR_6 (0x2a) 1607490b008SAlexander Aring #define SR_IEEE_ADDR_6 0x2a, 0xff, 0 1617490b008SAlexander Aring #define RG_IEEE_ADDR_7 (0x2b) 1627490b008SAlexander Aring #define SR_IEEE_ADDR_7 0x2b, 0xff, 0 1637490b008SAlexander Aring #define RG_XAH_CTRL_0 (0x2c) 1647490b008SAlexander Aring #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0 1657490b008SAlexander Aring #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 1667490b008SAlexander Aring #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 1677490b008SAlexander Aring #define RG_CSMA_SEED_0 (0x2d) 1687490b008SAlexander Aring #define SR_CSMA_SEED_0 0x2d, 0xff, 0 1697490b008SAlexander Aring #define RG_CSMA_SEED_1 (0x2e) 1707490b008SAlexander Aring #define SR_CSMA_SEED_1 0x2e, 0x07, 0 1717490b008SAlexander Aring #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3 1727490b008SAlexander Aring #define SR_AACK_DIS_ACK 0x2e, 0x10, 4 1737490b008SAlexander Aring #define SR_AACK_SET_PD 0x2e, 0x20, 5 1747490b008SAlexander Aring #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6 1757490b008SAlexander Aring #define RG_CSMA_BE (0x2f) 1767490b008SAlexander Aring #define SR_MIN_BE 0x2f, 0x0f, 0 1777490b008SAlexander Aring #define SR_MAX_BE 0x2f, 0xf0, 4 1787490b008SAlexander Aring 1797490b008SAlexander Aring #define CMD_REG 0x80 1807490b008SAlexander Aring #define CMD_REG_MASK 0x3f 1817490b008SAlexander Aring #define CMD_WRITE 0x40 1827490b008SAlexander Aring #define CMD_FB 0x20 1837490b008SAlexander Aring 1847490b008SAlexander Aring #define IRQ_BAT_LOW BIT(7) 1857490b008SAlexander Aring #define IRQ_TRX_UR BIT(6) 1867490b008SAlexander Aring #define IRQ_AMI BIT(5) 1877490b008SAlexander Aring #define IRQ_CCA_ED BIT(4) 1887490b008SAlexander Aring #define IRQ_TRX_END BIT(3) 1897490b008SAlexander Aring #define IRQ_RX_START BIT(2) 1907490b008SAlexander Aring #define IRQ_PLL_UNL BIT(1) 1917490b008SAlexander Aring #define IRQ_PLL_LOCK BIT(0) 1927490b008SAlexander Aring 1937490b008SAlexander Aring #define IRQ_ACTIVE_HIGH 0 1947490b008SAlexander Aring #define IRQ_ACTIVE_LOW 1 1957490b008SAlexander Aring 1967490b008SAlexander Aring #define STATE_P_ON 0x00 /* BUSY */ 1977490b008SAlexander Aring #define STATE_BUSY_RX 0x01 1987490b008SAlexander Aring #define STATE_BUSY_TX 0x02 1997490b008SAlexander Aring #define STATE_FORCE_TRX_OFF 0x03 2007490b008SAlexander Aring #define STATE_FORCE_TX_ON 0x04 /* IDLE */ 2017490b008SAlexander Aring /* 0x05 */ /* INVALID_PARAMETER */ 2027490b008SAlexander Aring #define STATE_RX_ON 0x06 2037490b008SAlexander Aring /* 0x07 */ /* SUCCESS */ 2047490b008SAlexander Aring #define STATE_TRX_OFF 0x08 2057490b008SAlexander Aring #define STATE_TX_ON 0x09 2067490b008SAlexander Aring /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */ 2077490b008SAlexander Aring #define STATE_SLEEP 0x0F 2087490b008SAlexander Aring #define STATE_PREP_DEEP_SLEEP 0x10 2097490b008SAlexander Aring #define STATE_BUSY_RX_AACK 0x11 2107490b008SAlexander Aring #define STATE_BUSY_TX_ARET 0x12 2117490b008SAlexander Aring #define STATE_RX_AACK_ON 0x16 2127490b008SAlexander Aring #define STATE_TX_ARET_ON 0x19 2137490b008SAlexander Aring #define STATE_RX_ON_NOCLK 0x1C 2147490b008SAlexander Aring #define STATE_RX_AACK_ON_NOCLK 0x1D 2157490b008SAlexander Aring #define STATE_BUSY_RX_AACK_NOCLK 0x1E 2167490b008SAlexander Aring #define STATE_TRANSITION_IN_PROGRESS 0x1F 2177490b008SAlexander Aring 2187490b008SAlexander Aring #define TRX_STATE_MASK (0x1F) 219*493bc90aSAlexander Aring #define TRAC_MASK(x) ((x & 0xe0) >> 5) 220*493bc90aSAlexander Aring 221*493bc90aSAlexander Aring #define TRAC_SUCCESS 0 222*493bc90aSAlexander Aring #define TRAC_SUCCESS_DATA_PENDING 1 223*493bc90aSAlexander Aring #define TRAC_SUCCESS_WAIT_FOR_ACK 2 224*493bc90aSAlexander Aring #define TRAC_CHANNEL_ACCESS_FAILURE 3 225*493bc90aSAlexander Aring #define TRAC_NO_ACK 5 226*493bc90aSAlexander Aring #define TRAC_INVALID 7 2277490b008SAlexander Aring 2287490b008SAlexander Aring #endif /* !_AT86RF230_H */ 229