1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /****************************************************************************** 3 * 4 * (C)Copyright 1998,1999 SysKonnect, 5 * a business unit of Schneider & Koch & Co. Datensysteme GmbH. 6 * 7 * The information in this file is provided "AS IS" without warranty. 8 * 9 ******************************************************************************/ 10 11 #ifndef _SKFBI_H_ 12 #define _SKFBI_H_ 13 14 /* 15 * FDDI-Fx (x := {I(SA), P(CI)}) 16 * address calculation & function defines 17 */ 18 19 /*--------------------------------------------------------------------------*/ 20 #ifdef PCI 21 22 /* 23 * (DV) = only defined for Da Vinci 24 * (ML) = only defined for Monalisa 25 */ 26 27 28 /* 29 * I2C Address (PCI Config) 30 * 31 * Note: The temperature and voltage sensors are relocated on a different 32 * I2C bus. 33 */ 34 #define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */ 35 36 37 #define PCI_ERRBITS (PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY) 38 39 40 41 /* 42 * Control Register File: 43 * Bank 0 44 */ 45 #define B0_RAP 0x0000 /* 8 bit register address port */ 46 /* 0x0001 - 0x0003: reserved */ 47 #define B0_CTRL 0x0004 /* 8 bit control register */ 48 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */ 49 #define B0_LED 0x0006 /* 8 Bit LED register */ 50 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */ 51 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */ 52 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */ 53 54 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ 55 #define B0_CMDREG1 0x0010 /* write command reg 1 instruction */ 56 #define B0_CMDREG2 0x0014 /* write command reg 2 instruction */ 57 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */ 58 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */ 59 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */ 60 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */ 61 62 #define B0_MARR 0x0020 /* r/w the memory read addr register */ 63 #define B0_MARW 0x0024 /* r/w the memory write addr register*/ 64 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */ 65 #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */ 66 67 #define B0_MDREG3 0x0030 /* r/w Mode Register 3 */ 68 #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */ 69 #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */ 70 #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */ 71 #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */ 72 #define B0_IVR 0x0044 /* read Interrupt Vector register */ 73 #define B0_IMR 0x0048 /* r/w Interrupt mask register */ 74 /* 0x4c Hidden */ 75 76 #define B0_CNTRL_A 0x0050 /* control register A (r/w) */ 77 #define B0_CNTRL_B 0x0054 /* control register B (r/w) */ 78 #define B0_INTR_MASK 0x0058 /* interrupt mask (r/w) */ 79 #define B0_XMIT_VECTOR 0x005c /* transmit vector register (r/w) */ 80 81 #define B0_STATUS_A 0x0060 /* status register A (read only) */ 82 #define B0_STATUS_B 0x0064 /* status register B (read only) */ 83 #define B0_CNTRL_C 0x0068 /* control register C (r/w) */ 84 #define B0_MDREG1 0x006c /* r/w Mode Register 1 */ 85 86 #define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */ 87 #define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/ 88 #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */ 89 #define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */ 90 91 /* 92 * Bank 1 93 * - completely empty (this is the RAP Block window) 94 * Note: if RAP = 1 this page is reserved 95 */ 96 97 /* 98 * Bank 2 99 */ 100 #define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */ 101 #define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */ 102 #define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */ 103 #define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */ 104 #define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */ 105 #define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */ 106 #define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */ 107 #define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */ 108 109 #define B2_CONN_TYP 0x0108 /* 8 bit Connector type */ 110 #define B2_PMD_TYP 0x0109 /* 8 bit PMD type */ 111 /* 0x010a - 0x010b: reserved */ 112 /* Eprom registers are currently of no use */ 113 #define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */ 114 #define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */ 115 #define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */ 116 #define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */ 117 #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */ 118 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */ 119 /* 0x0115 - 0x0117: reserved */ 120 #define B2_LD_CRTL 0x0118 /* 8 bit loader control */ 121 #define B2_LD_TEST 0x0119 /* 8 bit loader test */ 122 /* 0x011a - 0x011f: reserved */ 123 #define B2_TI_INI 0x0120 /* 32 bit Timer init value */ 124 #define B2_TI_VAL 0x0124 /* 32 bit Timer value */ 125 #define B2_TI_CRTL 0x0128 /* 8 bit Timer control */ 126 #define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */ 127 /* 0x012a - 0x012f: reserved */ 128 #define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */ 129 #define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */ 130 #define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */ 131 #define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */ 132 /* 0x013a - 0x013f: reserved */ 133 #define B2_RTM_INI 0x0140 /* 32 bit RTM init value */ 134 #define B2_RTM_VAL 0x0144 /* 32 bit RTM value */ 135 #define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */ 136 #define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */ 137 138 #define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */ 139 #define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */ 140 #define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */ 141 #define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */ 142 /* 0x0156: reserved */ 143 #define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */ 144 #define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */ 145 #define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */ 146 147 #define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */ 148 #define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */ 149 #define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */ 150 #define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */ 151 /* 0x016a - 0x017f: reserved */ 152 153 /* 154 * Bank 3 155 */ 156 /* 157 * This is a copy of the Configuration register file (lower half) 158 */ 159 #define B3_CFG_SPC 0x180 160 161 /* 162 * Bank 4 163 */ 164 #define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */ 165 #define B4_R1_DA 0x0210 /* 32 bit current rec desc address */ 166 #define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */ 167 #define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */ 168 #define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */ 169 #define B4_R1_F 0x0220 /* 32 bit flag register */ 170 #define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */ 171 #define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */ 172 #define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */ 173 #define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */ 174 #define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */ 175 #define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */ 176 #define B4_R1_T3 0x022c /* 32 bit Test Register 3 */ 177 #define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */ 178 #define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */ 179 /* 0x0238 - 0x023f: reserved */ 180 /* Receive queue 2 is removed on Monalisa */ 181 #define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */ 182 #define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */ 183 #define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */ 184 #define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */ 185 #define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */ 186 #define B4_R2_F 0x0260 /* 32 bit flag register (q2) */ 187 #define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */ 188 #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */ 189 #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */ 190 #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */ 191 #define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */ 192 #define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */ 193 #define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */ 194 /* 0x0270 - 0x027c: reserved */ 195 196 /* 197 * Bank 5 198 */ 199 #define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */ 200 #define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */ 201 #define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */ 202 #define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */ 203 #define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */ 204 #define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */ 205 #define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */ 206 #define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */ 207 #define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */ 208 #define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */ 209 #define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */ 210 #define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */ 211 #define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */ 212 #define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */ 213 #define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */ 214 /* 0x02b8 - 0x02bc: reserved */ 215 #define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */ 216 #define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */ 217 #define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */ 218 #define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */ 219 #define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */ 220 #define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */ 221 #define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */ 222 #define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */ 223 #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */ 224 #define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */ 225 #define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */ 226 #define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */ 227 #define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */ 228 #define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */ 229 #define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */ 230 /* 0x02f8 - 0x02fc: reserved */ 231 232 /* 233 * Bank 6 234 */ 235 /* External PLC-S registers (SN2 compatibility for DV) */ 236 /* External registers (ML) */ 237 #define B6_EXT_REG 0x300 238 239 /* 240 * Bank 7 241 */ 242 /* DAS PLC-S Registers */ 243 244 /* 245 * Bank 8 - 15 246 */ 247 /* IFCP registers */ 248 249 /*---------------------------------------------------------------------------*/ 250 /* Definitions of the Bits in the registers */ 251 252 /* B0_RAP 16 bit register address port */ 253 #define RAP_RAP 0x0f /* Bit 3..0: 0 = block0, .., f = block15 */ 254 255 /* B0_CTRL 8 bit control register */ 256 #define CTRL_FDDI_CLR (1<<7) /* Bit 7: (ML) Clear FDDI Reset */ 257 #define CTRL_FDDI_SET (1<<6) /* Bit 6: (ML) Set FDDI Reset */ 258 #define CTRL_HPI_CLR (1<<5) /* Bit 5: Clear HPI SM reset */ 259 #define CTRL_HPI_SET (1<<4) /* Bit 4: Set HPI SM reset */ 260 #define CTRL_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */ 261 #define CTRL_MRST_SET (1<<2) /* Bit 2: Set Master reset */ 262 #define CTRL_RST_CLR (1<<1) /* Bit 1: Clear Software reset */ 263 #define CTRL_RST_SET (1<<0) /* Bit 0: Set Software reset */ 264 265 /* B0_DAS 8 Bit control register (DAS) */ 266 #define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */ 267 #define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/ 268 /* Bit 5..4: reserved */ 269 #define DAS_AVAIL (1<<3) /* Bit 3: 1 = DAS, 0 = SAS */ 270 #define DAS_BYP_ST (1<<2) /* Bit 2: 1 = avail,SAS, 0 = not avail */ 271 #define DAS_BYP_INS (1<<1) /* Bit 1: 1 = insert Bypass */ 272 #define DAS_BYP_RMV (1<<0) /* Bit 0: 1 = remove Bypass */ 273 274 /* B0_LED 8 Bit LED register */ 275 /* Bit 7..6: reserved */ 276 #define LED_2_ON (1<<5) /* Bit 5: 1 = switch LED_2 on (left,gn)*/ 277 #define LED_2_OFF (1<<4) /* Bit 4: 1 = switch LED_2 off */ 278 #define LED_1_ON (1<<3) /* Bit 3: 1 = switch LED_1 on (mid,yel)*/ 279 #define LED_1_OFF (1<<2) /* Bit 2: 1 = switch LED_1 off */ 280 #define LED_0_ON (1<<1) /* Bit 1: 1 = switch LED_0 on (rght,gn)*/ 281 #define LED_0_OFF (1<<0) /* Bit 0: 1 = switch LED_0 off */ 282 /* This hardware defines are very ugly therefore we define some others */ 283 284 #define LED_GA_ON LED_2_ON /* S port = A port */ 285 #define LED_GA_OFF LED_2_OFF /* S port = A port */ 286 #define LED_MY_ON LED_1_ON 287 #define LED_MY_OFF LED_1_OFF 288 #define LED_GB_ON LED_0_ON 289 #define LED_GB_OFF LED_0_OFF 290 291 /* B0_TST_CTRL 8 bit test control register */ 292 #define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RE. */ 293 #define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR. */ 294 #define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RE. */ 295 #define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR. */ 296 #define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */ 297 #define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */ 298 #define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */ 299 #define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */ 300 301 /* B0_ISRC 32 bit Interrupt source register */ 302 /* Bit 31..28: reserved */ 303 #define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ 304 #define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ 305 #define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ 306 #define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */ 307 /* PERR, RMABORT, RTABORT DATAPERR */ 308 #define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ 309 /* RMABORT, RTABORT, DATAPERR */ 310 #define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */ 311 #define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */ 312 /* 313 * Note: The DAS is our First Port (!=PA) 314 */ 315 #define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */ 316 #define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ 317 #define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ 318 #define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ 319 #define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ 320 /* Receive Queue 1 */ 321 #define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ 322 #define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ 323 #define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ 324 #define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ 325 /* Receive Queue 2 */ 326 #define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ 327 #define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ 328 #define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ 329 #define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ 330 /* Asynchronous Transmit queue */ 331 /* Bit 7: reserved */ 332 #define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ 333 #define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ 334 #define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ 335 /* Synchronous Transmit queue */ 336 /* Bit 3: reserved */ 337 #define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ 338 #define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ 339 #define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ 340 341 /* 342 * Define all valid interrupt source Bits from GET_ISR () 343 */ 344 #define ALL_IRSR 0x01ffff77L /* (DV) */ 345 #define ALL_IRSR_ML 0x0ffff077L /* (ML) */ 346 347 348 /* B0_IMSK 32 bit Interrupt mask register */ 349 /* 350 * The Bit definnition of this register are the same as of the interrupt 351 * source register. These definition are directly derived from the Hardware 352 * spec. 353 */ 354 /* Bit 31..28: reserved */ 355 #define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */ 356 #define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */ 357 #define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/ 358 #define IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */ 359 /* PERR, RMABORT, RTABORT DATAPERR */ 360 #define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */ 361 /* RMABORT, RTABORT, DATAPERR */ 362 #define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */ 363 #define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */ 364 #define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */ 365 #define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */ 366 #define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */ 367 #define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */ 368 #define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */ 369 /* Receive Queue 1 */ 370 #define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */ 371 #define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */ 372 #define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */ 373 #define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */ 374 /* Receive Queue 2 */ 375 #define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */ 376 #define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */ 377 #define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */ 378 #define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */ 379 /* Asynchronous Transmit queue */ 380 /* Bit 7: reserved */ 381 #define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */ 382 #define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */ 383 #define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */ 384 /* Synchronous Transmit queue */ 385 /* Bit 3: reserved */ 386 #define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */ 387 #define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */ 388 #define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */ 389 390 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */ 391 /* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */ 392 /* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */ 393 /* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */ 394 /* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */ 395 /* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */ 396 397 /* B2_MAC_0 8 bit MAC address Byte 0 */ 398 /* B2_MAC_1 8 bit MAC address Byte 1 */ 399 /* B2_MAC_2 8 bit MAC address Byte 2 */ 400 /* B2_MAC_3 8 bit MAC address Byte 3 */ 401 /* B2_MAC_4 8 bit MAC address Byte 4 */ 402 /* B2_MAC_5 8 bit MAC address Byte 5 */ 403 /* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */ 404 /* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */ 405 406 /* B2_CONN_TYP 8 bit Connector type */ 407 /* B2_PMD_TYP 8 bit PMD type */ 408 /* Values of connector and PMD type comply to SysKonnect internal std */ 409 410 /* The EPROM register are currently of no use */ 411 /* B2_E_0 8 bit EPROM Byte 0 */ 412 /* B2_E_1 8 bit EPROM Byte 1 */ 413 /* B2_E_2 8 bit EPROM Byte 2 */ 414 /* B2_E_3 8 bit EPROM Byte 3 */ 415 416 /* B2_FAR 32 bit Flash-Prom Address Register/Counter */ 417 #define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */ 418 419 /* B2_FDP 8 bit Flash-Prom Data Port */ 420 421 /* B2_LD_CRTL 8 bit loader control */ 422 /* Bits are currently reserved */ 423 424 /* B2_LD_TEST 8 bit loader test */ 425 #define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */ 426 #define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */ 427 #define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */ 428 #define LD_START (1<<0) /* Bit 0: Start loading FPROM */ 429 430 /* B2_TI_INI 32 bit Timer init value */ 431 /* B2_TI_VAL 32 bit Timer value */ 432 /* B2_TI_CRTL 8 bit Timer control */ 433 /* B2_TI_TEST 8 Bit Timer Test */ 434 /* B2_WDOG_INI 32 bit Watchdog init value */ 435 /* B2_WDOG_VAL 32 bit Watchdog value */ 436 /* B2_WDOG_CRTL 8 bit Watchdog control */ 437 /* B2_WDOG_TEST 8 Bit Watchdog Test */ 438 /* B2_RTM_INI 32 bit RTM init value */ 439 /* B2_RTM_VAL 32 bit RTM value */ 440 /* B2_RTM_CRTL 8 bit RTM control */ 441 /* B2_RTM_TEST 8 Bit RTM Test */ 442 /* B2_<TIM>_CRTL 8 bit <TIM> control */ 443 /* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */ 444 /* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */ 445 /* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */ 446 /* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */ 447 #define GET_TOK_CT (1<<4) /* Bit 4: Get the Token Counter (RTM) */ 448 #define TIM_RES_TOK (1<<3) /* Bit 3: RTM Status: 1 == restricted */ 449 #define TIM_ALARM (1<<3) /* Bit 3: Timer Alarm (WDOG) */ 450 #define TIM_START (1<<2) /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/ 451 #define TIM_STOP (1<<1) /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */ 452 #define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */ 453 /* B2_<TIM>_TEST 8 Bit <TIM> Test */ 454 #define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */ 455 #define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */ 456 #define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */ 457 458 /* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */ 459 /* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */ 460 /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */ 461 /* Bit 7..5: reserved */ 462 #define CTRL_CL_I2C_IRQ (1<<4) /* Bit 4: Clear I2C IRQ */ 463 #define CTRL_ST_SW_IRQ (1<<3) /* Bit 3: Set IRQ SW Request */ 464 #define CTRL_CL_SW_IRQ (1<<2) /* Bit 2: Clear IRQ SW Request */ 465 #define CTRL_STOP_DONE (1<<1) /* Bit 1: Stop Master is finished */ 466 #define CTRL_STOP_MAST (1<<0) /* Bit 0: Command Bit to stop the master*/ 467 468 /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */ 469 /* Bit 7..3: reserved */ 470 #define IF_I2C_DATA_DIR (1<<2) /* Bit 2: direction of IF_I2C_DATA*/ 471 #define IF_I2C_DATA (1<<1) /* Bit 1: I2C Data Port */ 472 #define IF_I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */ 473 474 /* 0x0156: reserved */ 475 /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */ 476 /* Bit 7..4: reserved */ 477 /* force the following error on */ 478 /* the next master read/write */ 479 #define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */ 480 #define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */ 481 #define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */ 482 #define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */ 483 484 /* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */ 485 #define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */ 486 #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be read/written*/ 487 #define I2C_DEV_SEL (0x7fL<<9) /* Bit 9..15: I2C Device Select */ 488 /* Bit 5.. 8: reserved */ 489 #define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */ 490 #define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */ 491 #define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/ 492 #define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */ 493 #define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */ 494 #define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */ 495 #define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */ 496 #define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */ 497 #define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */ 498 #define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */ 499 #define I2C_STOP_BIT (1<<0) /* Bit 0: Interrupt I2C transfer */ 500 501 /* 502 * I2C Addresses 503 * 504 * The temperature sensor and the voltage sensor are on the same I2C bus. 505 * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1 506 * in PCI_OUR_REG 1. 507 */ 508 #define I2C_ADDR_TEMP 0x90 /* I2C Address Temperature Sensor */ 509 510 /* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */ 511 512 /* B4_R1_D 4*32 bit current receive Descriptor (q1) */ 513 /* B4_R1_DA 32 bit current rec desc address (q1) */ 514 /* B4_R1_AC 32 bit current receive Address Count (q1) */ 515 /* B4_R1_BC 32 bit current receive Byte Counter (q1) */ 516 /* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */ 517 /* B4_R1_F 32 bit flag register (q1) */ 518 /* B4_R1_T1 32 bit Test Register 1 (q1) */ 519 /* B4_R1_T2 32 bit Test Register 2 (q1) */ 520 /* B4_R1_T3 32 bit Test Register 3 (q1) */ 521 /* B4_R2_D 4*32 bit current receive Descriptor (q2) */ 522 /* B4_R2_DA 32 bit current rec desc address (q2) */ 523 /* B4_R2_AC 32 bit current receive Address Count (q2) */ 524 /* B4_R2_BC 32 bit current receive Byte Counter (q2) */ 525 /* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */ 526 /* B4_R2_F 32 bit flag register (q2) */ 527 /* B4_R2_T1 32 bit Test Register 1 (q2) */ 528 /* B4_R2_T2 32 bit Test Register 2 (q2) */ 529 /* B4_R2_T3 32 bit Test Register 3 (q2) */ 530 /* B5_XA_D 4*32 bit current receive Descriptor (xa) */ 531 /* B5_XA_DA 32 bit current rec desc address (xa) */ 532 /* B5_XA_AC 32 bit current receive Address Count (xa) */ 533 /* B5_XA_BC 32 bit current receive Byte Counter (xa) */ 534 /* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */ 535 /* B5_XA_F 32 bit flag register (xa) */ 536 /* B5_XA_T1 32 bit Test Register 1 (xa) */ 537 /* B5_XA_T2 32 bit Test Register 2 (xa) */ 538 /* B5_XA_T3 32 bit Test Register 3 (xa) */ 539 /* B5_XS_D 4*32 bit current receive Descriptor (xs) */ 540 /* B5_XS_DA 32 bit current rec desc address (xs) */ 541 /* B5_XS_AC 32 bit current receive Address Count (xs) */ 542 /* B5_XS_BC 32 bit current receive Byte Counter (xs) */ 543 /* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */ 544 /* B5_XS_F 32 bit flag register (xs) */ 545 /* B5_XS_T1 32 bit Test Register 1 (xs) */ 546 /* B5_XS_T2 32 bit Test Register 2 (xs) */ 547 /* B5_XS_T3 32 bit Test Register 3 (xs) */ 548 /* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */ 549 #define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */ 550 #define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */ 551 #define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */ 552 #define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */ 553 #define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */ 554 #define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */ 555 #define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */ 556 #define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */ 557 #define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */ 558 #define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */ 559 #define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */ 560 #define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */ 561 #define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */ 562 #define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */ 563 /* Bit 7..5: reserved */ 564 #define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */ 565 #define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */ 566 #define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */ 567 #define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */ 568 #define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */ 569 570 #define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\ 571 CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST) 572 #define CSR_CLR_RESET (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\ 573 CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN) 574 575 576 /* B5_<xx>_F 32 bit flag register (xx) */ 577 /* Bit 28..31: reserved */ 578 #define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */ 579 #define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */ 580 #define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */ 581 #define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/ 582 /* Bit 23: reserved */ 583 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/ 584 /* Bit 8..15: reserved */ 585 #define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */ 586 #define FLAG_WATER 0x00001fL /* Bit 4..0:(DV) Level of req data tr.*/ 587 588 /* B5_<xx>_T1 32 bit Test Register 1 (xx) */ 589 /* Holds four State Machine control Bytes */ 590 #define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */ 591 #define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */ 592 #define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */ 593 #define SM_CRTL_TR (0xffL<<0) /* Bit 7..0: Control Transfer SM */ 594 595 /* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */ 596 /* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */ 597 /* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */ 598 /* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */ 599 /* The control status byte of each machine looks like ... */ 600 #define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */ 601 #define SM_LOAD 0x08 /* Bit 3: Load the SM with SM_STATE */ 602 #define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */ 603 #define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */ 604 #define SM_STEP 0x01 /* Bit 0: Step the State Machine */ 605 606 /* The coding of the states */ 607 #define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */ 608 #define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */ 609 #define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */ 610 #define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */ 611 #define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */ 612 #define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */ 613 #define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */ 614 615 #define SM_RD_IDLE 0x0 /* Read Desc. Idle Tr/Re */ 616 #define SM_RD_LOAD 0x1 /* Read Desc. Load Tr/Re */ 617 #define SM_RD_WAIT_TC 0x3 /* Read Desc. Wait_TC Tr/Re */ 618 #define SM_RD_RST_EOF 0x6 /* Read Desc. Reset_EOF Re */ 619 #define SM_RD_WDONE_R 0x2 /* Read Desc. Wait_Done Re */ 620 #define SM_RD_WDONE_T 0x4 /* Read Desc. Wait_Done Tr */ 621 622 #define SM_TR_IDLE 0x0 /* Trans. Data Idle Tr/Re */ 623 #define SM_TR_LOAD 0x3 /* Trans. Data Load Tr/Re */ 624 #define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */ 625 #define SM_TR_WAIT_TC 0x2 /* Trans. Data Wait_TC Tr/Re */ 626 #define SM_TR_WDONE 0x4 /* Trans. Data Wait_Done Tr/Re */ 627 628 #define SM_WR_IDLE 0x0 /* Write Desc. Idle Tr/Re */ 629 #define SM_WR_ABLEN 0x1 /* Write Desc. Act_Buf_Length Tr/Re */ 630 #define SM_WR_LD_A4 0x2 /* Write Desc. Load_A4 Re */ 631 #define SM_WR_RES_OWN 0x2 /* Write Desc. Res_OWN Tr */ 632 #define SM_WR_WAIT_EOF 0x3 /* Write Desc. Wait_EOF Re */ 633 #define SM_WR_LD_N2C_R 0x4 /* Write Desc. Load_N2C Re */ 634 #define SM_WR_WAIT_TC_R 0x5 /* Write Desc. Wait_TC Re */ 635 #define SM_WR_WAIT_TC4 0x6 /* Write Desc. Wait_TC4 Re */ 636 #define SM_WR_LD_A_T 0x6 /* Write Desc. Load_A Tr */ 637 #define SM_WR_LD_A_R 0x7 /* Write Desc. Load_A Re */ 638 #define SM_WR_WAIT_TC_T 0x7 /* Write Desc. Wait_TC Tr */ 639 #define SM_WR_LD_N2C_T 0xc /* Write Desc. Load_N2C Tr */ 640 #define SM_WR_WDONE_T 0x9 /* Write Desc. Wait_Done Tr */ 641 #define SM_WR_WDONE_R 0xc /* Write Desc. Wait_Done Re */ 642 #define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */ 643 #define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */ 644 645 /* B5_<xx>_T2 32 bit Test Register 2 (xx) */ 646 /* Note: This register is only defined for the transmit queues */ 647 /* Bit 31..8: reserved */ 648 #define AC_TEST_ON (1<<7) /* Bit 7: Address Counter Test Mode on */ 649 #define AC_TEST_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/ 650 #define BC_TEST_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */ 651 #define BC_TEST_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */ 652 #define TEST_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */ 653 #define TEST_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */ 654 #define TEST_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */ 655 #define TEST_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */ 656 657 /* B5_<xx>_T3 32 bit Test Register 3 (xx) */ 658 /* Note: This register is only defined for the transmit queues */ 659 /* Bit 31..8: reserved */ 660 #define T3_MUX_2 (1<<7) /* Bit 7: (ML) Mux position MSB */ 661 #define T3_VRAM_2 (1<<6) /* Bit 6: (ML) Virtual RAM buffer addr MSB */ 662 #define T3_LOOP (1<<5) /* Bit 5: Set Loopback (Xmit) */ 663 #define T3_UNLOOP (1<<4) /* Bit 4: Unset Loopback (Xmit) */ 664 #define T3_MUX (3<<2) /* Bit 3..2: Mux position */ 665 #define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */ 666 667 668 /* 669 * address transmission from logical to physical offset address on board 670 */ 671 #define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */ 672 #define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */ 673 #define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */ 674 #define PRA(a) (B2_MAC_0 + (a)) /* configuration PROM (MAC address) */ 675 676 /* 677 * FlashProm specification 678 */ 679 #define MAX_PAGES 0x20000L /* Every byte has a single page */ 680 #define MAX_FADDR 1 /* 1 byte per page */ 681 682 /* 683 * Receive / Transmit Buffer Control word 684 */ 685 #define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */ 686 #define BMU_STF (1L<<30) /* Start of Frame ? */ 687 #define BMU_EOF (1L<<29) /* End of Frame ? */ 688 #define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */ 689 #define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */ 690 #define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */ 691 #define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */ 692 #define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */ 693 #define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */ 694 #define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */ 695 #define BMU_CHECK 0x00550000L /* To identify the control word */ 696 #define BMU_BBC 0x0000FFFFL /* R/T Buffer Byte Count */ 697 698 /* 699 * physical address offset + IO-Port base address 700 */ 701 #ifdef MEM_MAPPED_IO 702 #define ADDR(a) (char far *) smc->hw.iop+(a) 703 #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a) 704 #else 705 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \ 706 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ 707 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) 708 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \ 709 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \ 710 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) 711 #endif 712 713 /* 714 * Define a macro to access the configuration space 715 */ 716 #define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */ 717 718 #define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */ 719 720 /* 721 * Define some values needed for the MAC address (PROM) 722 */ 723 #define SA_MAC (0) /* start addr. MAC_AD within the PROM */ 724 #define PRA_OFF (0) /* offset correction when 4th byte reading */ 725 726 #define SKFDDI_PSZ 8 /* address PROM size */ 727 728 #define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */ 729 #define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */ 730 #define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */ 731 #define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */ 732 733 /* 734 * Macro to read the PROM 735 */ 736 #define READ_PROM(a) ((u_char)inp(a)) 737 738 #define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank) 739 #define VPP_ON() 740 #define VPP_OFF() 741 742 /* 743 * Note: Values of the Interrupt Source Register are defined above 744 */ 745 #define ISR_A ADDR(B0_ISRC) 746 #define GET_ISR() inpd(ISR_A) 747 #define GET_ISR_SMP(iop) inpd((iop)+B0_ISRC) 748 #define CHECK_ISR() (inpd(ISR_A) & inpd(ADDR(B0_IMSK))) 749 #define CHECK_ISR_SMP(iop) (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK)) 750 751 #define BUS_CHECK() 752 753 /* 754 * CLI_FBI: Disable Board Interrupts 755 * STI_FBI: Enable Board Interrupts 756 */ 757 #ifndef UNIX 758 #define CLI_FBI() outpd(ADDR(B0_IMSK),0) 759 #else 760 #define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0) 761 #endif 762 763 #ifndef UNIX 764 #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask) 765 #else 766 #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask) 767 #endif 768 769 #define CLI_FBI_SMP(iop) outpd((iop)+B0_IMSK,0) 770 #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask) 771 772 #endif /* PCI */ 773 /*--------------------------------------------------------------------------*/ 774 775 /* 776 * 12 bit transfer (dword) counter: 777 * (ISA: 2*trc = number of byte) 778 * (EISA: 4*trc = number of byte) 779 * (MCA: 4*trc = number of byte) 780 */ 781 #define MAX_TRANS (0x0fff) 782 783 /* 784 * PC PIC 785 */ 786 #define MST_8259 (0x20) 787 #define SLV_8259 (0xA0) 788 789 #define TPS (18) /* ticks per second */ 790 791 /* 792 * error timer defs 793 */ 794 #define TN (4) /* number of supported timer = TN+1 */ 795 #define SNPPND_TIME (5) /* buffer memory access over mem. data reg. */ 796 797 #define MAC_AD 0x405a0000 798 799 #define MODR1 FM_A(FM_MDREG1) /* mode register 1 */ 800 #define MODR2 FM_A(FM_MDREG2) /* mode register 2 */ 801 802 #define CMDR1 FM_A(FM_CMDREG1) /* command register 1 */ 803 #define CMDR2 FM_A(FM_CMDREG2) /* command register 2 */ 804 805 806 /* 807 * function defines 808 */ 809 #define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask))) 810 #define SET(io,mask) outpw((io),inpw(io)|(mask)) 811 #define GET(io,mask) (inpw(io)&(mask)) 812 #define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val)) 813 814 /* 815 * PHY Port A (PA) = PLC 1 816 * With SuperNet 3 PHY-A and PHY S are identical. 817 */ 818 #define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg)) 819 820 /* 821 * set memory address register for write and read 822 */ 823 #define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma)) 824 #define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma)) 825 826 /* 827 * read/write from/to memory data register 828 */ 829 /* write double word */ 830 #define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\ 831 outpw(FM_A(FM_MDRL),(unsigned int)(dd)) 832 833 #ifndef WINNT 834 /* read double word */ 835 #define MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL))) 836 837 /* read FORMAC+ 32-bit status register */ 838 #define GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L))) 839 #define GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L))) 840 #ifdef SUPERNET_3 841 #define GET_ST3() (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L))) 842 #endif 843 #else 844 /* read double word */ 845 #define MDRR() inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL))) 846 847 /* read FORMAC+ 32-bit status register */ 848 #define GET_ST1() inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L))) 849 #define GET_ST2() inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L))) 850 #ifdef SUPERNET_3 851 #define GET_ST3() inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L))) 852 #endif 853 #endif 854 855 /* Special timer macro for 82c54 */ 856 /* timer access over data bus bit 8..15 */ 857 #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8) 858 #define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff) 859 860 861 #ifdef DEBUG 862 #define DB_MAC(mac,st) {if (debug_mac & 0x1)\ 863 printf("M") ;\ 864 if (debug_mac & 0x2)\ 865 printf("\tMAC %d status 0x%08lx\n",mac,st) ;\ 866 if (debug_mac & 0x4)\ 867 dp_mac(mac,st) ;\ 868 } 869 870 #define DB_PLC(p,iev) { if (debug_plc & 0x1)\ 871 printf("P") ;\ 872 if (debug_plc & 0x2)\ 873 printf("\tPLC %s Int 0x%04x\n", \ 874 (p == PA) ? "A" : "B", iev) ;\ 875 if (debug_plc & 0x4)\ 876 dp_plc(p,iev) ;\ 877 } 878 879 #define DB_TIMER() { if (debug_timer & 0x1)\ 880 printf("T") ;\ 881 if (debug_timer & 0x2)\ 882 printf("\tTimer ISR\n") ;\ 883 } 884 885 #else /* no DEBUG */ 886 887 #define DB_MAC(mac,st) 888 #define DB_PLC(p,iev) 889 #define DB_TIMER() 890 891 #endif /* no DEBUG */ 892 893 #define INC_PTR(sp,cp,ep) if (++cp == ep) cp = sp 894 /* 895 * timer defs 896 */ 897 #define COUNT(t) ((t)<<6) /* counter */ 898 #define RW_OP(o) ((o)<<4) /* read/write operation */ 899 #define TMODE(m) ((m)<<1) /* timer mode */ 900 901 #endif 902