1 /* 2 * File Name: 3 * defxx.c 4 * 5 * Copyright Information: 6 * Copyright Digital Equipment Corporation 1996. 7 * 8 * This software may be used and distributed according to the terms of 9 * the GNU General Public License, incorporated herein by reference. 10 * 11 * Abstract: 12 * A Linux device driver supporting the Digital Equipment Corporation 13 * FDDI TURBOchannel, EISA and PCI controller families. Supported 14 * adapters include: 15 * 16 * DEC FDDIcontroller/TURBOchannel (DEFTA) 17 * DEC FDDIcontroller/EISA (DEFEA) 18 * DEC FDDIcontroller/PCI (DEFPA) 19 * 20 * The original author: 21 * LVS Lawrence V. Stefani <lstefani@yahoo.com> 22 * 23 * Maintainers: 24 * macro Maciej W. Rozycki <macro@linux-mips.org> 25 * 26 * Credits: 27 * I'd like to thank Patricia Cross for helping me get started with 28 * Linux, David Davies for a lot of help upgrading and configuring 29 * my development system and for answering many OS and driver 30 * development questions, and Alan Cox for recommendations and 31 * integration help on getting FDDI support into Linux. LVS 32 * 33 * Driver Architecture: 34 * The driver architecture is largely based on previous driver work 35 * for other operating systems. The upper edge interface and 36 * functions were largely taken from existing Linux device drivers 37 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C 38 * driver. 39 * 40 * Adapter Probe - 41 * The driver scans for supported EISA adapters by reading the 42 * SLOT ID register for each EISA slot and making a match 43 * against the expected value. 44 * 45 * Bus-Specific Initialization - 46 * This driver currently supports both EISA and PCI controller 47 * families. While the custom DMA chip and FDDI logic is similar 48 * or identical, the bus logic is very different. After 49 * initialization, the only bus-specific differences is in how the 50 * driver enables and disables interrupts. Other than that, the 51 * run-time critical code behaves the same on both families. 52 * It's important to note that both adapter families are configured 53 * to I/O map, rather than memory map, the adapter registers. 54 * 55 * Driver Open/Close - 56 * In the driver open routine, the driver ISR (interrupt service 57 * routine) is registered and the adapter is brought to an 58 * operational state. In the driver close routine, the opposite 59 * occurs; the driver ISR is deregistered and the adapter is 60 * brought to a safe, but closed state. Users may use consecutive 61 * commands to bring the adapter up and down as in the following 62 * example: 63 * ifconfig fddi0 up 64 * ifconfig fddi0 down 65 * ifconfig fddi0 up 66 * 67 * Driver Shutdown - 68 * Apparently, there is no shutdown or halt routine support under 69 * Linux. This routine would be called during "reboot" or 70 * "shutdown" to allow the driver to place the adapter in a safe 71 * state before a warm reboot occurs. To be really safe, the user 72 * should close the adapter before shutdown (eg. ifconfig fddi0 down) 73 * to ensure that the adapter DMA engine is taken off-line. However, 74 * the current driver code anticipates this problem and always issues 75 * a soft reset of the adapter at the beginning of driver initialization. 76 * A future driver enhancement in this area may occur in 2.1.X where 77 * Alan indicated that a shutdown handler may be implemented. 78 * 79 * Interrupt Service Routine - 80 * The driver supports shared interrupts, so the ISR is registered for 81 * each board with the appropriate flag and the pointer to that board's 82 * device structure. This provides the context during interrupt 83 * processing to support shared interrupts and multiple boards. 84 * 85 * Interrupt enabling/disabling can occur at many levels. At the host 86 * end, you can disable system interrupts, or disable interrupts at the 87 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters 88 * have a bus-logic chip interrupt enable/disable as well as a DMA 89 * controller interrupt enable/disable. 90 * 91 * The driver currently enables and disables adapter interrupts at the 92 * bus-logic chip and assumes that Linux will take care of clearing or 93 * acknowledging any host-based interrupt chips. 94 * 95 * Control Functions - 96 * Control functions are those used to support functions such as adding 97 * or deleting multicast addresses, enabling or disabling packet 98 * reception filters, or other custom/proprietary commands. Presently, 99 * the driver supports the "get statistics", "set multicast list", and 100 * "set mac address" functions defined by Linux. A list of possible 101 * enhancements include: 102 * 103 * - Custom ioctl interface for executing port interface commands 104 * - Custom ioctl interface for adding unicast addresses to 105 * adapter CAM (to support bridge functions). 106 * - Custom ioctl interface for supporting firmware upgrades. 107 * 108 * Hardware (port interface) Support Routines - 109 * The driver function names that start with "dfx_hw_" represent 110 * low-level port interface routines that are called frequently. They 111 * include issuing a DMA or port control command to the adapter, 112 * resetting the adapter, or reading the adapter state. Since the 113 * driver initialization and run-time code must make calls into the 114 * port interface, these routines were written to be as generic and 115 * usable as possible. 116 * 117 * Receive Path - 118 * The adapter DMA engine supports a 256 entry receive descriptor block 119 * of which up to 255 entries can be used at any given time. The 120 * architecture is a standard producer, consumer, completion model in 121 * which the driver "produces" receive buffers to the adapter, the 122 * adapter "consumes" the receive buffers by DMAing incoming packet data, 123 * and the driver "completes" the receive buffers by servicing the 124 * incoming packet, then "produces" a new buffer and starts the cycle 125 * again. Receive buffers can be fragmented in up to 16 fragments 126 * (descriptor entries). For simplicity, this driver posts 127 * single-fragment receive buffers of 4608 bytes, then allocates a 128 * sk_buff, copies the data, then reposts the buffer. To reduce CPU 129 * utilization, a better approach would be to pass up the receive 130 * buffer (no extra copy) then allocate and post a replacement buffer. 131 * This is a performance enhancement that should be looked into at 132 * some point. 133 * 134 * Transmit Path - 135 * Like the receive path, the adapter DMA engine supports a 256 entry 136 * transmit descriptor block of which up to 255 entries can be used at 137 * any given time. Transmit buffers can be fragmented in up to 255 138 * fragments (descriptor entries). This driver always posts one 139 * fragment per transmit packet request. 140 * 141 * The fragment contains the entire packet from FC to end of data. 142 * Before posting the buffer to the adapter, the driver sets a three-byte 143 * packet request header (PRH) which is required by the Motorola MAC chip 144 * used on the adapters. The PRH tells the MAC the type of token to 145 * receive/send, whether or not to generate and append the CRC, whether 146 * synchronous or asynchronous framing is used, etc. Since the PRH 147 * definition is not necessarily consistent across all FDDI chipsets, 148 * the driver, rather than the common FDDI packet handler routines, 149 * sets these bytes. 150 * 151 * To reduce the amount of descriptor fetches needed per transmit request, 152 * the driver takes advantage of the fact that there are at least three 153 * bytes available before the skb->data field on the outgoing transmit 154 * request. This is guaranteed by having fddi_setup() in net_init.c set 155 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest 156 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad" 157 * bytes which we'll use to store the PRH. 158 * 159 * There's a subtle advantage to adding these pad bytes to the 160 * hard_header_len, it ensures that the data portion of the packet for 161 * an 802.2 SNAP frame is longword aligned. Other FDDI driver 162 * implementations may not need the extra padding and can start copying 163 * or DMAing directly from the FC byte which starts at skb->data. Should 164 * another driver implementation need ADDITIONAL padding, the net_init.c 165 * module should be updated and dev->hard_header_len should be increased. 166 * NOTE: To maintain the alignment on the data portion of the packet, 167 * dev->hard_header_len should always be evenly divisible by 4 and at 168 * least 24 bytes in size. 169 * 170 * Modification History: 171 * Date Name Description 172 * 16-Aug-96 LVS Created. 173 * 20-Aug-96 LVS Updated dfx_probe so that version information 174 * string is only displayed if 1 or more cards are 175 * found. Changed dfx_rcv_queue_process to copy 176 * 3 NULL bytes before FC to ensure that data is 177 * longword aligned in receive buffer. 178 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable 179 * LLC group promiscuous mode if multicast list 180 * is too large. LLC individual/group promiscuous 181 * mode is now disabled if IFF_PROMISC flag not set. 182 * dfx_xmt_queue_pkt no longer checks for NULL skb 183 * on Alan Cox recommendation. Added node address 184 * override support. 185 * 12-Sep-96 LVS Reset current address to factory address during 186 * device open. Updated transmit path to post a 187 * single fragment which includes PRH->end of data. 188 * Mar 2000 AC Did various cleanups for 2.3.x 189 * Jun 2000 jgarzik PCI and resource alloc cleanups 190 * Jul 2000 tjeerd Much cleanup and some bug fixes 191 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup 192 * Feb 2001 Skb allocation fixes 193 * Feb 2001 davej PCI enable cleanups. 194 * 04 Aug 2003 macro Converted to the DMA API. 195 * 14 Aug 2004 macro Fix device names reported. 196 * 14 Jun 2005 macro Use irqreturn_t. 197 * 23 Oct 2006 macro Big-endian host support. 198 * 14 Dec 2006 macro TURBOchannel support. 199 */ 200 201 /* Include files */ 202 #include <linux/bitops.h> 203 #include <linux/compiler.h> 204 #include <linux/delay.h> 205 #include <linux/dma-mapping.h> 206 #include <linux/eisa.h> 207 #include <linux/errno.h> 208 #include <linux/fddidevice.h> 209 #include <linux/init.h> 210 #include <linux/interrupt.h> 211 #include <linux/ioport.h> 212 #include <linux/kernel.h> 213 #include <linux/module.h> 214 #include <linux/netdevice.h> 215 #include <linux/pci.h> 216 #include <linux/skbuff.h> 217 #include <linux/slab.h> 218 #include <linux/string.h> 219 #include <linux/tc.h> 220 221 #include <asm/byteorder.h> 222 #include <asm/io.h> 223 224 #include "defxx.h" 225 226 /* Version information string should be updated prior to each new release! */ 227 #define DRV_NAME "defxx" 228 #define DRV_VERSION "v1.10" 229 #define DRV_RELDATE "2006/12/14" 230 231 static char version[] = 232 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE 233 " Lawrence V. Stefani and others\n"; 234 235 #define DYNAMIC_BUFFERS 1 236 237 #define SKBUFF_RX_COPYBREAK 200 238 /* 239 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte 240 * alignment for compatibility with old EISA boards. 241 */ 242 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128) 243 244 #ifdef CONFIG_PCI 245 #define DFX_BUS_PCI(dev) (dev->bus == &pci_bus_type) 246 #else 247 #define DFX_BUS_PCI(dev) 0 248 #endif 249 250 #ifdef CONFIG_EISA 251 #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type) 252 #else 253 #define DFX_BUS_EISA(dev) 0 254 #endif 255 256 #ifdef CONFIG_TC 257 #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type) 258 #else 259 #define DFX_BUS_TC(dev) 0 260 #endif 261 262 #ifdef CONFIG_DEFXX_MMIO 263 #define DFX_MMIO 1 264 #else 265 #define DFX_MMIO 0 266 #endif 267 268 /* Define module-wide (static) routines */ 269 270 static void dfx_bus_init(struct net_device *dev); 271 static void dfx_bus_uninit(struct net_device *dev); 272 static void dfx_bus_config_check(DFX_board_t *bp); 273 274 static int dfx_driver_init(struct net_device *dev, 275 const char *print_name, 276 resource_size_t bar_start); 277 static int dfx_adap_init(DFX_board_t *bp, int get_buffers); 278 279 static int dfx_open(struct net_device *dev); 280 static int dfx_close(struct net_device *dev); 281 282 static void dfx_int_pr_halt_id(DFX_board_t *bp); 283 static void dfx_int_type_0_process(DFX_board_t *bp); 284 static void dfx_int_common(struct net_device *dev); 285 static irqreturn_t dfx_interrupt(int irq, void *dev_id); 286 287 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev); 288 static void dfx_ctl_set_multicast_list(struct net_device *dev); 289 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr); 290 static int dfx_ctl_update_cam(DFX_board_t *bp); 291 static int dfx_ctl_update_filters(DFX_board_t *bp); 292 293 static int dfx_hw_dma_cmd_req(DFX_board_t *bp); 294 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data); 295 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type); 296 static int dfx_hw_adap_state_rd(DFX_board_t *bp); 297 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type); 298 299 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers); 300 static void dfx_rcv_queue_process(DFX_board_t *bp); 301 static void dfx_rcv_flush(DFX_board_t *bp); 302 303 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 304 struct net_device *dev); 305 static int dfx_xmt_done(DFX_board_t *bp); 306 static void dfx_xmt_flush(DFX_board_t *bp); 307 308 /* Define module-wide (static) variables */ 309 310 static struct pci_driver dfx_pci_driver; 311 static struct eisa_driver dfx_eisa_driver; 312 static struct tc_driver dfx_tc_driver; 313 314 315 /* 316 * ======================= 317 * = dfx_port_write_long = 318 * = dfx_port_read_long = 319 * ======================= 320 * 321 * Overview: 322 * Routines for reading and writing values from/to adapter 323 * 324 * Returns: 325 * None 326 * 327 * Arguments: 328 * bp - pointer to board information 329 * offset - register offset from base I/O address 330 * data - for dfx_port_write_long, this is a value to write; 331 * for dfx_port_read_long, this is a pointer to store 332 * the read value 333 * 334 * Functional Description: 335 * These routines perform the correct operation to read or write 336 * the adapter register. 337 * 338 * EISA port block base addresses are based on the slot number in which the 339 * controller is installed. For example, if the EISA controller is installed 340 * in slot 4, the port block base address is 0x4000. If the controller is 341 * installed in slot 2, the port block base address is 0x2000, and so on. 342 * This port block can be used to access PDQ, ESIC, and DEFEA on-board 343 * registers using the register offsets defined in DEFXX.H. 344 * 345 * PCI port block base addresses are assigned by the PCI BIOS or system 346 * firmware. There is one 128 byte port block which can be accessed. It 347 * allows for I/O mapping of both PDQ and PFI registers using the register 348 * offsets defined in DEFXX.H. 349 * 350 * Return Codes: 351 * None 352 * 353 * Assumptions: 354 * bp->base is a valid base I/O address for this adapter. 355 * offset is a valid register offset for this adapter. 356 * 357 * Side Effects: 358 * Rather than produce macros for these functions, these routines 359 * are defined using "inline" to ensure that the compiler will 360 * generate inline code and not waste a procedure call and return. 361 * This provides all the benefits of macros, but with the 362 * advantage of strict data type checking. 363 */ 364 365 static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data) 366 { 367 writel(data, bp->base.mem + offset); 368 mb(); 369 } 370 371 static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data) 372 { 373 outl(data, bp->base.port + offset); 374 } 375 376 static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data) 377 { 378 struct device __maybe_unused *bdev = bp->bus_dev; 379 int dfx_bus_tc = DFX_BUS_TC(bdev); 380 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 381 382 if (dfx_use_mmio) 383 dfx_writel(bp, offset, data); 384 else 385 dfx_outl(bp, offset, data); 386 } 387 388 389 static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data) 390 { 391 mb(); 392 *data = readl(bp->base.mem + offset); 393 } 394 395 static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data) 396 { 397 *data = inl(bp->base.port + offset); 398 } 399 400 static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data) 401 { 402 struct device __maybe_unused *bdev = bp->bus_dev; 403 int dfx_bus_tc = DFX_BUS_TC(bdev); 404 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 405 406 if (dfx_use_mmio) 407 dfx_readl(bp, offset, data); 408 else 409 dfx_inl(bp, offset, data); 410 } 411 412 413 /* 414 * ================ 415 * = dfx_get_bars = 416 * ================ 417 * 418 * Overview: 419 * Retrieves the address range used to access control and status 420 * registers. 421 * 422 * Returns: 423 * None 424 * 425 * Arguments: 426 * bdev - pointer to device information 427 * bar_start - pointer to store the start address 428 * bar_len - pointer to store the length of the area 429 * 430 * Assumptions: 431 * I am sure there are some. 432 * 433 * Side Effects: 434 * None 435 */ 436 static void dfx_get_bars(struct device *bdev, 437 resource_size_t *bar_start, resource_size_t *bar_len) 438 { 439 int dfx_bus_pci = DFX_BUS_PCI(bdev); 440 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 441 int dfx_bus_tc = DFX_BUS_TC(bdev); 442 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 443 444 if (dfx_bus_pci) { 445 int num = dfx_use_mmio ? 0 : 1; 446 447 *bar_start = pci_resource_start(to_pci_dev(bdev), num); 448 *bar_len = pci_resource_len(to_pci_dev(bdev), num); 449 } 450 if (dfx_bus_eisa) { 451 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 452 resource_size_t bar; 453 454 if (dfx_use_mmio) { 455 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2); 456 bar <<= 8; 457 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1); 458 bar <<= 8; 459 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0); 460 bar <<= 16; 461 *bar_start = bar; 462 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2); 463 bar <<= 8; 464 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1); 465 bar <<= 8; 466 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0); 467 bar <<= 16; 468 *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1; 469 } else { 470 *bar_start = base_addr; 471 *bar_len = PI_ESIC_K_CSR_IO_LEN; 472 } 473 } 474 if (dfx_bus_tc) { 475 *bar_start = to_tc_dev(bdev)->resource.start + 476 PI_TC_K_CSR_OFFSET; 477 *bar_len = PI_TC_K_CSR_LEN; 478 } 479 } 480 481 static const struct net_device_ops dfx_netdev_ops = { 482 .ndo_open = dfx_open, 483 .ndo_stop = dfx_close, 484 .ndo_start_xmit = dfx_xmt_queue_pkt, 485 .ndo_get_stats = dfx_ctl_get_stats, 486 .ndo_set_rx_mode = dfx_ctl_set_multicast_list, 487 .ndo_set_mac_address = dfx_ctl_set_mac_address, 488 }; 489 490 /* 491 * ================ 492 * = dfx_register = 493 * ================ 494 * 495 * Overview: 496 * Initializes a supported FDDI controller 497 * 498 * Returns: 499 * Condition code 500 * 501 * Arguments: 502 * bdev - pointer to device information 503 * 504 * Functional Description: 505 * 506 * Return Codes: 507 * 0 - This device (fddi0, fddi1, etc) configured successfully 508 * -EBUSY - Failed to get resources, or dfx_driver_init failed. 509 * 510 * Assumptions: 511 * It compiles so it should work :-( (PCI cards do :-) 512 * 513 * Side Effects: 514 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 515 * initialized and the board resources are read and stored in 516 * the device structure. 517 */ 518 static int dfx_register(struct device *bdev) 519 { 520 static int version_disp; 521 int dfx_bus_pci = DFX_BUS_PCI(bdev); 522 int dfx_bus_tc = DFX_BUS_TC(bdev); 523 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 524 const char *print_name = dev_name(bdev); 525 struct net_device *dev; 526 DFX_board_t *bp; /* board pointer */ 527 resource_size_t bar_start = 0; /* pointer to port */ 528 resource_size_t bar_len = 0; /* resource length */ 529 int alloc_size; /* total buffer size used */ 530 struct resource *region; 531 int err = 0; 532 533 if (!version_disp) { /* display version info if adapter is found */ 534 version_disp = 1; /* set display flag to TRUE so that */ 535 printk(version); /* we only display this string ONCE */ 536 } 537 538 dev = alloc_fddidev(sizeof(*bp)); 539 if (!dev) { 540 printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n", 541 print_name); 542 return -ENOMEM; 543 } 544 545 /* Enable PCI device. */ 546 if (dfx_bus_pci && pci_enable_device(to_pci_dev(bdev))) { 547 printk(KERN_ERR "%s: Cannot enable PCI device, aborting\n", 548 print_name); 549 goto err_out; 550 } 551 552 SET_NETDEV_DEV(dev, bdev); 553 554 bp = netdev_priv(dev); 555 bp->bus_dev = bdev; 556 dev_set_drvdata(bdev, dev); 557 558 dfx_get_bars(bdev, &bar_start, &bar_len); 559 560 if (dfx_use_mmio) 561 region = request_mem_region(bar_start, bar_len, print_name); 562 else 563 region = request_region(bar_start, bar_len, print_name); 564 if (!region) { 565 printk(KERN_ERR "%s: Cannot reserve I/O resource " 566 "0x%lx @ 0x%lx, aborting\n", 567 print_name, (long)bar_len, (long)bar_start); 568 err = -EBUSY; 569 goto err_out_disable; 570 } 571 572 /* Set up I/O base address. */ 573 if (dfx_use_mmio) { 574 bp->base.mem = ioremap_nocache(bar_start, bar_len); 575 if (!bp->base.mem) { 576 printk(KERN_ERR "%s: Cannot map MMIO\n", print_name); 577 err = -ENOMEM; 578 goto err_out_region; 579 } 580 } else { 581 bp->base.port = bar_start; 582 dev->base_addr = bar_start; 583 } 584 585 /* Initialize new device structure */ 586 dev->netdev_ops = &dfx_netdev_ops; 587 588 if (dfx_bus_pci) 589 pci_set_master(to_pci_dev(bdev)); 590 591 if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) { 592 err = -ENODEV; 593 goto err_out_unmap; 594 } 595 596 err = register_netdev(dev); 597 if (err) 598 goto err_out_kfree; 599 600 printk("%s: registered as %s\n", print_name, dev->name); 601 return 0; 602 603 err_out_kfree: 604 alloc_size = sizeof(PI_DESCR_BLOCK) + 605 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 606 #ifndef DYNAMIC_BUFFERS 607 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 608 #endif 609 sizeof(PI_CONSUMER_BLOCK) + 610 (PI_ALIGN_K_DESC_BLK - 1); 611 if (bp->kmalloced) 612 dma_free_coherent(bdev, alloc_size, 613 bp->kmalloced, bp->kmalloced_dma); 614 615 err_out_unmap: 616 if (dfx_use_mmio) 617 iounmap(bp->base.mem); 618 619 err_out_region: 620 if (dfx_use_mmio) 621 release_mem_region(bar_start, bar_len); 622 else 623 release_region(bar_start, bar_len); 624 625 err_out_disable: 626 if (dfx_bus_pci) 627 pci_disable_device(to_pci_dev(bdev)); 628 629 err_out: 630 free_netdev(dev); 631 return err; 632 } 633 634 635 /* 636 * ================ 637 * = dfx_bus_init = 638 * ================ 639 * 640 * Overview: 641 * Initializes the bus-specific controller logic. 642 * 643 * Returns: 644 * None 645 * 646 * Arguments: 647 * dev - pointer to device information 648 * 649 * Functional Description: 650 * Determine and save adapter IRQ in device table, 651 * then perform bus-specific logic initialization. 652 * 653 * Return Codes: 654 * None 655 * 656 * Assumptions: 657 * bp->base has already been set with the proper 658 * base I/O address for this device. 659 * 660 * Side Effects: 661 * Interrupts are enabled at the adapter bus-specific logic. 662 * Note: Interrupts at the DMA engine (PDQ chip) are not 663 * enabled yet. 664 */ 665 666 static void dfx_bus_init(struct net_device *dev) 667 { 668 DFX_board_t *bp = netdev_priv(dev); 669 struct device *bdev = bp->bus_dev; 670 int dfx_bus_pci = DFX_BUS_PCI(bdev); 671 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 672 int dfx_bus_tc = DFX_BUS_TC(bdev); 673 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 674 u8 val; 675 676 DBG_printk("In dfx_bus_init...\n"); 677 678 /* Initialize a pointer back to the net_device struct */ 679 bp->dev = dev; 680 681 /* Initialize adapter based on bus type */ 682 683 if (dfx_bus_tc) 684 dev->irq = to_tc_dev(bdev)->interrupt; 685 if (dfx_bus_eisa) { 686 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 687 688 /* Get the interrupt level from the ESIC chip. */ 689 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 690 val &= PI_CONFIG_STAT_0_M_IRQ; 691 val >>= PI_CONFIG_STAT_0_V_IRQ; 692 693 switch (val) { 694 case PI_CONFIG_STAT_0_IRQ_K_9: 695 dev->irq = 9; 696 break; 697 698 case PI_CONFIG_STAT_0_IRQ_K_10: 699 dev->irq = 10; 700 break; 701 702 case PI_CONFIG_STAT_0_IRQ_K_11: 703 dev->irq = 11; 704 break; 705 706 case PI_CONFIG_STAT_0_IRQ_K_15: 707 dev->irq = 15; 708 break; 709 } 710 711 /* 712 * Enable memory decoding (MEMCS0) and/or port decoding 713 * (IOCS1/IOCS0) as appropriate in Function Control 714 * Register. One of the port chip selects seems to be 715 * used for the Burst Holdoff register, but this bit of 716 * documentation is missing and as yet it has not been 717 * determined which of the two. This is also the reason 718 * the size of the decoded port range is twice as large 719 * as one required by the PDQ. 720 */ 721 722 /* Set the decode range of the board. */ 723 val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT); 724 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val); 725 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0); 726 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val); 727 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0); 728 val = PI_ESIC_K_CSR_IO_LEN - 1; 729 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff); 730 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff); 731 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff); 732 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff); 733 734 /* Enable the decoders. */ 735 val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0; 736 if (dfx_use_mmio) 737 val |= PI_FUNCTION_CNTRL_M_MEMCS0; 738 outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val); 739 740 /* 741 * Enable access to the rest of the module 742 * (including PDQ and packet memory). 743 */ 744 val = PI_SLOT_CNTRL_M_ENB; 745 outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val); 746 747 /* 748 * Map PDQ registers into memory or port space. This is 749 * done with a bit in the Burst Holdoff register. 750 */ 751 val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); 752 if (dfx_use_mmio) 753 val |= PI_BURST_HOLDOFF_V_MEM_MAP; 754 else 755 val &= ~PI_BURST_HOLDOFF_V_MEM_MAP; 756 outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val); 757 758 /* Enable interrupts at EISA bus interface chip (ESIC) */ 759 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 760 val |= PI_CONFIG_STAT_0_M_INT_ENB; 761 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 762 } 763 if (dfx_bus_pci) { 764 struct pci_dev *pdev = to_pci_dev(bdev); 765 766 /* Get the interrupt level from the PCI Configuration Table */ 767 768 dev->irq = pdev->irq; 769 770 /* Check Latency Timer and set if less than minimal */ 771 772 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); 773 if (val < PFI_K_LAT_TIMER_MIN) { 774 val = PFI_K_LAT_TIMER_DEF; 775 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); 776 } 777 778 /* Enable interrupts at PCI bus interface chip (PFI) */ 779 val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB; 780 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val); 781 } 782 } 783 784 /* 785 * ================== 786 * = dfx_bus_uninit = 787 * ================== 788 * 789 * Overview: 790 * Uninitializes the bus-specific controller logic. 791 * 792 * Returns: 793 * None 794 * 795 * Arguments: 796 * dev - pointer to device information 797 * 798 * Functional Description: 799 * Perform bus-specific logic uninitialization. 800 * 801 * Return Codes: 802 * None 803 * 804 * Assumptions: 805 * bp->base has already been set with the proper 806 * base I/O address for this device. 807 * 808 * Side Effects: 809 * Interrupts are disabled at the adapter bus-specific logic. 810 */ 811 812 static void dfx_bus_uninit(struct net_device *dev) 813 { 814 DFX_board_t *bp = netdev_priv(dev); 815 struct device *bdev = bp->bus_dev; 816 int dfx_bus_pci = DFX_BUS_PCI(bdev); 817 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 818 u8 val; 819 820 DBG_printk("In dfx_bus_uninit...\n"); 821 822 /* Uninitialize adapter based on bus type */ 823 824 if (dfx_bus_eisa) { 825 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 826 827 /* Disable interrupts at EISA bus interface chip (ESIC) */ 828 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 829 val &= ~PI_CONFIG_STAT_0_M_INT_ENB; 830 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 831 } 832 if (dfx_bus_pci) { 833 /* Disable interrupts at PCI bus interface chip (PFI) */ 834 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0); 835 } 836 } 837 838 839 /* 840 * ======================== 841 * = dfx_bus_config_check = 842 * ======================== 843 * 844 * Overview: 845 * Checks the configuration (burst size, full-duplex, etc.) If any parameters 846 * are illegal, then this routine will set new defaults. 847 * 848 * Returns: 849 * None 850 * 851 * Arguments: 852 * bp - pointer to board information 853 * 854 * Functional Description: 855 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later 856 * PDQ, and all FDDI PCI controllers, all values are legal. 857 * 858 * Return Codes: 859 * None 860 * 861 * Assumptions: 862 * dfx_adap_init has NOT been called yet so burst size and other items have 863 * not been set. 864 * 865 * Side Effects: 866 * None 867 */ 868 869 static void dfx_bus_config_check(DFX_board_t *bp) 870 { 871 struct device __maybe_unused *bdev = bp->bus_dev; 872 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 873 int status; /* return code from adapter port control call */ 874 u32 host_data; /* LW data returned from port control call */ 875 876 DBG_printk("In dfx_bus_config_check...\n"); 877 878 /* Configuration check only valid for EISA adapter */ 879 880 if (dfx_bus_eisa) { 881 /* 882 * First check if revision 2 EISA controller. Rev. 1 cards used 883 * PDQ revision B, so no workaround needed in this case. Rev. 3 884 * cards used PDQ revision E, so no workaround needed in this 885 * case, either. Only Rev. 2 cards used either Rev. D or E 886 * chips, so we must verify the chip revision on Rev. 2 cards. 887 */ 888 if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) { 889 /* 890 * Revision 2 FDDI EISA controller found, 891 * so let's check PDQ revision of adapter. 892 */ 893 status = dfx_hw_port_ctrl_req(bp, 894 PI_PCTRL_M_SUB_CMD, 895 PI_SUB_CMD_K_PDQ_REV_GET, 896 0, 897 &host_data); 898 if ((status != DFX_K_SUCCESS) || (host_data == 2)) 899 { 900 /* 901 * Either we couldn't determine the PDQ revision, or 902 * we determined that it is at revision D. In either case, 903 * we need to implement the workaround. 904 */ 905 906 /* Ensure that the burst size is set to 8 longwords or less */ 907 908 switch (bp->burst_size) 909 { 910 case PI_PDATA_B_DMA_BURST_SIZE_32: 911 case PI_PDATA_B_DMA_BURST_SIZE_16: 912 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8; 913 break; 914 915 default: 916 break; 917 } 918 919 /* Ensure that full-duplex mode is not enabled */ 920 921 bp->full_duplex_enb = PI_SNMP_K_FALSE; 922 } 923 } 924 } 925 } 926 927 928 /* 929 * =================== 930 * = dfx_driver_init = 931 * =================== 932 * 933 * Overview: 934 * Initializes remaining adapter board structure information 935 * and makes sure adapter is in a safe state prior to dfx_open(). 936 * 937 * Returns: 938 * Condition code 939 * 940 * Arguments: 941 * dev - pointer to device information 942 * print_name - printable device name 943 * 944 * Functional Description: 945 * This function allocates additional resources such as the host memory 946 * blocks needed by the adapter (eg. descriptor and consumer blocks). 947 * Remaining bus initialization steps are also completed. The adapter 948 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS 949 * must call dfx_open() to open the adapter and bring it on-line. 950 * 951 * Return Codes: 952 * DFX_K_SUCCESS - initialization succeeded 953 * DFX_K_FAILURE - initialization failed - could not allocate memory 954 * or read adapter MAC address 955 * 956 * Assumptions: 957 * Memory allocated from pci_alloc_consistent() call is physically 958 * contiguous, locked memory. 959 * 960 * Side Effects: 961 * Adapter is reset and should be in DMA_UNAVAILABLE state before 962 * returning from this routine. 963 */ 964 965 static int dfx_driver_init(struct net_device *dev, const char *print_name, 966 resource_size_t bar_start) 967 { 968 DFX_board_t *bp = netdev_priv(dev); 969 struct device *bdev = bp->bus_dev; 970 int dfx_bus_pci = DFX_BUS_PCI(bdev); 971 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 972 int dfx_bus_tc = DFX_BUS_TC(bdev); 973 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 974 int alloc_size; /* total buffer size needed */ 975 char *top_v, *curr_v; /* virtual addrs into memory block */ 976 dma_addr_t top_p, curr_p; /* physical addrs into memory block */ 977 u32 data; /* host data register value */ 978 __le32 le32; 979 char *board_name = NULL; 980 981 DBG_printk("In dfx_driver_init...\n"); 982 983 /* Initialize bus-specific hardware registers */ 984 985 dfx_bus_init(dev); 986 987 /* 988 * Initialize default values for configurable parameters 989 * 990 * Note: All of these parameters are ones that a user may 991 * want to customize. It'd be nice to break these 992 * out into Space.c or someplace else that's more 993 * accessible/understandable than this file. 994 */ 995 996 bp->full_duplex_enb = PI_SNMP_K_FALSE; 997 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */ 998 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF; 999 bp->rcv_bufs_to_post = RCV_BUFS_DEF; 1000 1001 /* 1002 * Ensure that HW configuration is OK 1003 * 1004 * Note: Depending on the hardware revision, we may need to modify 1005 * some of the configurable parameters to workaround hardware 1006 * limitations. We'll perform this configuration check AFTER 1007 * setting the parameters to their default values. 1008 */ 1009 1010 dfx_bus_config_check(bp); 1011 1012 /* Disable PDQ interrupts first */ 1013 1014 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1015 1016 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1017 1018 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1019 1020 /* Read the factory MAC address from the adapter then save it */ 1021 1022 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, 1023 &data) != DFX_K_SUCCESS) { 1024 printk("%s: Could not read adapter factory MAC address!\n", 1025 print_name); 1026 return DFX_K_FAILURE; 1027 } 1028 le32 = cpu_to_le32(data); 1029 memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32)); 1030 1031 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, 1032 &data) != DFX_K_SUCCESS) { 1033 printk("%s: Could not read adapter factory MAC address!\n", 1034 print_name); 1035 return DFX_K_FAILURE; 1036 } 1037 le32 = cpu_to_le32(data); 1038 memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16)); 1039 1040 /* 1041 * Set current address to factory address 1042 * 1043 * Note: Node address override support is handled through 1044 * dfx_ctl_set_mac_address. 1045 */ 1046 1047 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1048 if (dfx_bus_tc) 1049 board_name = "DEFTA"; 1050 if (dfx_bus_eisa) 1051 board_name = "DEFEA"; 1052 if (dfx_bus_pci) 1053 board_name = "DEFPA"; 1054 pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, Hardware addr = %pMF\n", 1055 print_name, board_name, dfx_use_mmio ? "" : "I/O ", 1056 (long long)bar_start, dev->irq, dev->dev_addr); 1057 1058 /* 1059 * Get memory for descriptor block, consumer block, and other buffers 1060 * that need to be DMA read or written to by the adapter. 1061 */ 1062 1063 alloc_size = sizeof(PI_DESCR_BLOCK) + 1064 PI_CMD_REQ_K_SIZE_MAX + 1065 PI_CMD_RSP_K_SIZE_MAX + 1066 #ifndef DYNAMIC_BUFFERS 1067 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 1068 #endif 1069 sizeof(PI_CONSUMER_BLOCK) + 1070 (PI_ALIGN_K_DESC_BLK - 1); 1071 bp->kmalloced = top_v = dma_zalloc_coherent(bp->bus_dev, alloc_size, 1072 &bp->kmalloced_dma, 1073 GFP_ATOMIC); 1074 if (top_v == NULL) 1075 return DFX_K_FAILURE; 1076 1077 top_p = bp->kmalloced_dma; /* get physical address of buffer */ 1078 1079 /* 1080 * To guarantee the 8K alignment required for the descriptor block, 8K - 1 1081 * plus the amount of memory needed was allocated. The physical address 1082 * is now 8K aligned. By carving up the memory in a specific order, 1083 * we'll guarantee the alignment requirements for all other structures. 1084 * 1085 * Note: If the assumptions change regarding the non-paged, non-cached, 1086 * physically contiguous nature of the memory block or the address 1087 * alignments, then we'll need to implement a different algorithm 1088 * for allocating the needed memory. 1089 */ 1090 1091 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); 1092 curr_v = top_v + (curr_p - top_p); 1093 1094 /* Reserve space for descriptor block */ 1095 1096 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v; 1097 bp->descr_block_phys = curr_p; 1098 curr_v += sizeof(PI_DESCR_BLOCK); 1099 curr_p += sizeof(PI_DESCR_BLOCK); 1100 1101 /* Reserve space for command request buffer */ 1102 1103 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v; 1104 bp->cmd_req_phys = curr_p; 1105 curr_v += PI_CMD_REQ_K_SIZE_MAX; 1106 curr_p += PI_CMD_REQ_K_SIZE_MAX; 1107 1108 /* Reserve space for command response buffer */ 1109 1110 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v; 1111 bp->cmd_rsp_phys = curr_p; 1112 curr_v += PI_CMD_RSP_K_SIZE_MAX; 1113 curr_p += PI_CMD_RSP_K_SIZE_MAX; 1114 1115 /* Reserve space for the LLC host receive queue buffers */ 1116 1117 bp->rcv_block_virt = curr_v; 1118 bp->rcv_block_phys = curr_p; 1119 1120 #ifndef DYNAMIC_BUFFERS 1121 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1122 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1123 #endif 1124 1125 /* Reserve space for the consumer block */ 1126 1127 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v; 1128 bp->cons_block_phys = curr_p; 1129 1130 /* Display virtual and physical addresses if debug driver */ 1131 1132 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", 1133 print_name, 1134 (long)bp->descr_block_virt, bp->descr_block_phys); 1135 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", 1136 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys); 1137 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", 1138 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); 1139 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", 1140 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys); 1141 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", 1142 print_name, (long)bp->cons_block_virt, bp->cons_block_phys); 1143 1144 return DFX_K_SUCCESS; 1145 } 1146 1147 1148 /* 1149 * ================= 1150 * = dfx_adap_init = 1151 * ================= 1152 * 1153 * Overview: 1154 * Brings the adapter to the link avail/link unavailable state. 1155 * 1156 * Returns: 1157 * Condition code 1158 * 1159 * Arguments: 1160 * bp - pointer to board information 1161 * get_buffers - non-zero if buffers to be allocated 1162 * 1163 * Functional Description: 1164 * Issues the low-level firmware/hardware calls necessary to bring 1165 * the adapter up, or to properly reset and restore adapter during 1166 * run-time. 1167 * 1168 * Return Codes: 1169 * DFX_K_SUCCESS - Adapter brought up successfully 1170 * DFX_K_FAILURE - Adapter initialization failed 1171 * 1172 * Assumptions: 1173 * bp->reset_type should be set to a valid reset type value before 1174 * calling this routine. 1175 * 1176 * Side Effects: 1177 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1178 * upon a successful return of this routine. 1179 */ 1180 1181 static int dfx_adap_init(DFX_board_t *bp, int get_buffers) 1182 { 1183 DBG_printk("In dfx_adap_init...\n"); 1184 1185 /* Disable PDQ interrupts first */ 1186 1187 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1188 1189 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1190 1191 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS) 1192 { 1193 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name); 1194 return DFX_K_FAILURE; 1195 } 1196 1197 /* 1198 * When the PDQ is reset, some false Type 0 interrupts may be pending, 1199 * so we'll acknowledge all Type 0 interrupts now before continuing. 1200 */ 1201 1202 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0); 1203 1204 /* 1205 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state 1206 * 1207 * Note: We only need to clear host copies of these registers. The PDQ reset 1208 * takes care of the on-board register values. 1209 */ 1210 1211 bp->cmd_req_reg.lword = 0; 1212 bp->cmd_rsp_reg.lword = 0; 1213 bp->rcv_xmt_reg.lword = 0; 1214 1215 /* Clear consumer block before going to DMA_AVAILABLE state */ 1216 1217 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1218 1219 /* Initialize the DMA Burst Size */ 1220 1221 if (dfx_hw_port_ctrl_req(bp, 1222 PI_PCTRL_M_SUB_CMD, 1223 PI_SUB_CMD_K_BURST_SIZE_SET, 1224 bp->burst_size, 1225 NULL) != DFX_K_SUCCESS) 1226 { 1227 printk("%s: Could not set adapter burst size!\n", bp->dev->name); 1228 return DFX_K_FAILURE; 1229 } 1230 1231 /* 1232 * Set base address of Consumer Block 1233 * 1234 * Assumption: 32-bit physical address of consumer block is 64 byte 1235 * aligned. That is, bits 0-5 of the address must be zero. 1236 */ 1237 1238 if (dfx_hw_port_ctrl_req(bp, 1239 PI_PCTRL_M_CONS_BLOCK, 1240 bp->cons_block_phys, 1241 0, 1242 NULL) != DFX_K_SUCCESS) 1243 { 1244 printk("%s: Could not set consumer block address!\n", bp->dev->name); 1245 return DFX_K_FAILURE; 1246 } 1247 1248 /* 1249 * Set the base address of Descriptor Block and bring adapter 1250 * to DMA_AVAILABLE state. 1251 * 1252 * Note: We also set the literal and data swapping requirements 1253 * in this command. 1254 * 1255 * Assumption: 32-bit physical address of descriptor block 1256 * is 8Kbyte aligned. 1257 */ 1258 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT, 1259 (u32)(bp->descr_block_phys | 1260 PI_PDATA_A_INIT_M_BSWAP_INIT), 1261 0, NULL) != DFX_K_SUCCESS) { 1262 printk("%s: Could not set descriptor block address!\n", 1263 bp->dev->name); 1264 return DFX_K_FAILURE; 1265 } 1266 1267 /* Set transmit flush timeout value */ 1268 1269 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET; 1270 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME; 1271 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */ 1272 bp->cmd_req_virt->char_set.item[0].item_index = 0; 1273 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL; 1274 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1275 { 1276 printk("%s: DMA command request failed!\n", bp->dev->name); 1277 return DFX_K_FAILURE; 1278 } 1279 1280 /* Set the initial values for eFDXEnable and MACTReq MIB objects */ 1281 1282 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET; 1283 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS; 1284 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb; 1285 bp->cmd_req_virt->snmp_set.item[0].item_index = 0; 1286 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ; 1287 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt; 1288 bp->cmd_req_virt->snmp_set.item[1].item_index = 0; 1289 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL; 1290 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1291 { 1292 printk("%s: DMA command request failed!\n", bp->dev->name); 1293 return DFX_K_FAILURE; 1294 } 1295 1296 /* Initialize adapter CAM */ 1297 1298 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 1299 { 1300 printk("%s: Adapter CAM update failed!\n", bp->dev->name); 1301 return DFX_K_FAILURE; 1302 } 1303 1304 /* Initialize adapter filters */ 1305 1306 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 1307 { 1308 printk("%s: Adapter filters update failed!\n", bp->dev->name); 1309 return DFX_K_FAILURE; 1310 } 1311 1312 /* 1313 * Remove any existing dynamic buffers (i.e. if the adapter is being 1314 * reinitialized) 1315 */ 1316 1317 if (get_buffers) 1318 dfx_rcv_flush(bp); 1319 1320 /* Initialize receive descriptor block and produce buffers */ 1321 1322 if (dfx_rcv_init(bp, get_buffers)) 1323 { 1324 printk("%s: Receive buffer allocation failed\n", bp->dev->name); 1325 if (get_buffers) 1326 dfx_rcv_flush(bp); 1327 return DFX_K_FAILURE; 1328 } 1329 1330 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */ 1331 1332 bp->cmd_req_virt->cmd_type = PI_CMD_K_START; 1333 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1334 { 1335 printk("%s: Start command failed\n", bp->dev->name); 1336 if (get_buffers) 1337 dfx_rcv_flush(bp); 1338 return DFX_K_FAILURE; 1339 } 1340 1341 /* Initialization succeeded, reenable PDQ interrupts */ 1342 1343 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS); 1344 return DFX_K_SUCCESS; 1345 } 1346 1347 1348 /* 1349 * ============ 1350 * = dfx_open = 1351 * ============ 1352 * 1353 * Overview: 1354 * Opens the adapter 1355 * 1356 * Returns: 1357 * Condition code 1358 * 1359 * Arguments: 1360 * dev - pointer to device information 1361 * 1362 * Functional Description: 1363 * This function brings the adapter to an operational state. 1364 * 1365 * Return Codes: 1366 * 0 - Adapter was successfully opened 1367 * -EAGAIN - Could not register IRQ or adapter initialization failed 1368 * 1369 * Assumptions: 1370 * This routine should only be called for a device that was 1371 * initialized successfully. 1372 * 1373 * Side Effects: 1374 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1375 * if the open is successful. 1376 */ 1377 1378 static int dfx_open(struct net_device *dev) 1379 { 1380 DFX_board_t *bp = netdev_priv(dev); 1381 int ret; 1382 1383 DBG_printk("In dfx_open...\n"); 1384 1385 /* Register IRQ - support shared interrupts by passing device ptr */ 1386 1387 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, 1388 dev); 1389 if (ret) { 1390 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); 1391 return ret; 1392 } 1393 1394 /* 1395 * Set current address to factory MAC address 1396 * 1397 * Note: We've already done this step in dfx_driver_init. 1398 * However, it's possible that a user has set a node 1399 * address override, then closed and reopened the 1400 * adapter. Unless we reset the device address field 1401 * now, we'll continue to use the existing modified 1402 * address. 1403 */ 1404 1405 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1406 1407 /* Clear local unicast/multicast address tables and counts */ 1408 1409 memset(bp->uc_table, 0, sizeof(bp->uc_table)); 1410 memset(bp->mc_table, 0, sizeof(bp->mc_table)); 1411 bp->uc_count = 0; 1412 bp->mc_count = 0; 1413 1414 /* Disable promiscuous filter settings */ 1415 1416 bp->ind_group_prom = PI_FSTATE_K_BLOCK; 1417 bp->group_prom = PI_FSTATE_K_BLOCK; 1418 1419 spin_lock_init(&bp->lock); 1420 1421 /* Reset and initialize adapter */ 1422 1423 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */ 1424 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS) 1425 { 1426 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name); 1427 free_irq(dev->irq, dev); 1428 return -EAGAIN; 1429 } 1430 1431 /* Set device structure info */ 1432 netif_start_queue(dev); 1433 return 0; 1434 } 1435 1436 1437 /* 1438 * ============= 1439 * = dfx_close = 1440 * ============= 1441 * 1442 * Overview: 1443 * Closes the device/module. 1444 * 1445 * Returns: 1446 * Condition code 1447 * 1448 * Arguments: 1449 * dev - pointer to device information 1450 * 1451 * Functional Description: 1452 * This routine closes the adapter and brings it to a safe state. 1453 * The interrupt service routine is deregistered with the OS. 1454 * The adapter can be opened again with another call to dfx_open(). 1455 * 1456 * Return Codes: 1457 * Always return 0. 1458 * 1459 * Assumptions: 1460 * No further requests for this adapter are made after this routine is 1461 * called. dfx_open() can be called to reset and reinitialize the 1462 * adapter. 1463 * 1464 * Side Effects: 1465 * Adapter should be in DMA_UNAVAILABLE state upon completion of this 1466 * routine. 1467 */ 1468 1469 static int dfx_close(struct net_device *dev) 1470 { 1471 DFX_board_t *bp = netdev_priv(dev); 1472 1473 DBG_printk("In dfx_close...\n"); 1474 1475 /* Disable PDQ interrupts first */ 1476 1477 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1478 1479 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1480 1481 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1482 1483 /* 1484 * Flush any pending transmit buffers 1485 * 1486 * Note: It's important that we flush the transmit buffers 1487 * BEFORE we clear our copy of the Type 2 register. 1488 * Otherwise, we'll have no idea how many buffers 1489 * we need to free. 1490 */ 1491 1492 dfx_xmt_flush(bp); 1493 1494 /* 1495 * Clear Type 1 and Type 2 registers after adapter reset 1496 * 1497 * Note: Even though we're closing the adapter, it's 1498 * possible that an interrupt will occur after 1499 * dfx_close is called. Without some assurance to 1500 * the contrary we want to make sure that we don't 1501 * process receive and transmit LLC frames and update 1502 * the Type 2 register with bad information. 1503 */ 1504 1505 bp->cmd_req_reg.lword = 0; 1506 bp->cmd_rsp_reg.lword = 0; 1507 bp->rcv_xmt_reg.lword = 0; 1508 1509 /* Clear consumer block for the same reason given above */ 1510 1511 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1512 1513 /* Release all dynamically allocate skb in the receive ring. */ 1514 1515 dfx_rcv_flush(bp); 1516 1517 /* Clear device structure flags */ 1518 1519 netif_stop_queue(dev); 1520 1521 /* Deregister (free) IRQ */ 1522 1523 free_irq(dev->irq, dev); 1524 1525 return 0; 1526 } 1527 1528 1529 /* 1530 * ====================== 1531 * = dfx_int_pr_halt_id = 1532 * ====================== 1533 * 1534 * Overview: 1535 * Displays halt id's in string form. 1536 * 1537 * Returns: 1538 * None 1539 * 1540 * Arguments: 1541 * bp - pointer to board information 1542 * 1543 * Functional Description: 1544 * Determine current halt id and display appropriate string. 1545 * 1546 * Return Codes: 1547 * None 1548 * 1549 * Assumptions: 1550 * None 1551 * 1552 * Side Effects: 1553 * None 1554 */ 1555 1556 static void dfx_int_pr_halt_id(DFX_board_t *bp) 1557 { 1558 PI_UINT32 port_status; /* PDQ port status register value */ 1559 PI_UINT32 halt_id; /* PDQ port status halt ID */ 1560 1561 /* Read the latest port status */ 1562 1563 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1564 1565 /* Display halt state transition information */ 1566 1567 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID; 1568 switch (halt_id) 1569 { 1570 case PI_HALT_ID_K_SELFTEST_TIMEOUT: 1571 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name); 1572 break; 1573 1574 case PI_HALT_ID_K_PARITY_ERROR: 1575 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name); 1576 break; 1577 1578 case PI_HALT_ID_K_HOST_DIR_HALT: 1579 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name); 1580 break; 1581 1582 case PI_HALT_ID_K_SW_FAULT: 1583 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name); 1584 break; 1585 1586 case PI_HALT_ID_K_HW_FAULT: 1587 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name); 1588 break; 1589 1590 case PI_HALT_ID_K_PC_TRACE: 1591 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name); 1592 break; 1593 1594 case PI_HALT_ID_K_DMA_ERROR: 1595 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name); 1596 break; 1597 1598 case PI_HALT_ID_K_IMAGE_CRC_ERROR: 1599 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name); 1600 break; 1601 1602 case PI_HALT_ID_K_BUS_EXCEPTION: 1603 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name); 1604 break; 1605 1606 default: 1607 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id); 1608 break; 1609 } 1610 } 1611 1612 1613 /* 1614 * ========================== 1615 * = dfx_int_type_0_process = 1616 * ========================== 1617 * 1618 * Overview: 1619 * Processes Type 0 interrupts. 1620 * 1621 * Returns: 1622 * None 1623 * 1624 * Arguments: 1625 * bp - pointer to board information 1626 * 1627 * Functional Description: 1628 * Processes all enabled Type 0 interrupts. If the reason for the interrupt 1629 * is a serious fault on the adapter, then an error message is displayed 1630 * and the adapter is reset. 1631 * 1632 * One tricky potential timing window is the rapid succession of "link avail" 1633 * "link unavail" state change interrupts. The acknowledgement of the Type 0 1634 * interrupt must be done before reading the state from the Port Status 1635 * register. This is true because a state change could occur after reading 1636 * the data, but before acknowledging the interrupt. If this state change 1637 * does happen, it would be lost because the driver is using the old state, 1638 * and it will never know about the new state because it subsequently 1639 * acknowledges the state change interrupt. 1640 * 1641 * INCORRECT CORRECT 1642 * read type 0 int reasons read type 0 int reasons 1643 * read adapter state ack type 0 interrupts 1644 * ack type 0 interrupts read adapter state 1645 * ... process interrupt ... ... process interrupt ... 1646 * 1647 * Return Codes: 1648 * None 1649 * 1650 * Assumptions: 1651 * None 1652 * 1653 * Side Effects: 1654 * An adapter reset may occur if the adapter has any Type 0 error interrupts 1655 * or if the port status indicates that the adapter is halted. The driver 1656 * is responsible for reinitializing the adapter with the current CAM 1657 * contents and adapter filter settings. 1658 */ 1659 1660 static void dfx_int_type_0_process(DFX_board_t *bp) 1661 1662 { 1663 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */ 1664 PI_UINT32 state; /* current adap state (from port status) */ 1665 1666 /* 1667 * Read host interrupt Type 0 register to determine which Type 0 1668 * interrupts are pending. Immediately write it back out to clear 1669 * those interrupts. 1670 */ 1671 1672 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status); 1673 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status); 1674 1675 /* Check for Type 0 error interrupts */ 1676 1677 if (type_0_status & (PI_TYPE_0_STAT_M_NXM | 1678 PI_TYPE_0_STAT_M_PM_PAR_ERR | 1679 PI_TYPE_0_STAT_M_BUS_PAR_ERR)) 1680 { 1681 /* Check for Non-Existent Memory error */ 1682 1683 if (type_0_status & PI_TYPE_0_STAT_M_NXM) 1684 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name); 1685 1686 /* Check for Packet Memory Parity error */ 1687 1688 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR) 1689 printk("%s: Packet Memory Parity Error\n", bp->dev->name); 1690 1691 /* Check for Host Bus Parity error */ 1692 1693 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR) 1694 printk("%s: Host Bus Parity Error\n", bp->dev->name); 1695 1696 /* Reset adapter and bring it back on-line */ 1697 1698 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1699 bp->reset_type = 0; /* rerun on-board diagnostics */ 1700 printk("%s: Resetting adapter...\n", bp->dev->name); 1701 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1702 { 1703 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1704 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1705 return; 1706 } 1707 printk("%s: Adapter reset successful!\n", bp->dev->name); 1708 return; 1709 } 1710 1711 /* Check for transmit flush interrupt */ 1712 1713 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH) 1714 { 1715 /* Flush any pending xmt's and acknowledge the flush interrupt */ 1716 1717 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1718 dfx_xmt_flush(bp); /* flush any outstanding packets */ 1719 (void) dfx_hw_port_ctrl_req(bp, 1720 PI_PCTRL_M_XMT_DATA_FLUSH_DONE, 1721 0, 1722 0, 1723 NULL); 1724 } 1725 1726 /* Check for adapter state change */ 1727 1728 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE) 1729 { 1730 /* Get latest adapter state */ 1731 1732 state = dfx_hw_adap_state_rd(bp); /* get adapter state */ 1733 if (state == PI_STATE_K_HALTED) 1734 { 1735 /* 1736 * Adapter has transitioned to HALTED state, try to reset 1737 * adapter to bring it back on-line. If reset fails, 1738 * leave the adapter in the broken state. 1739 */ 1740 1741 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name); 1742 dfx_int_pr_halt_id(bp); /* display halt id as string */ 1743 1744 /* Reset adapter and bring it back on-line */ 1745 1746 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1747 bp->reset_type = 0; /* rerun on-board diagnostics */ 1748 printk("%s: Resetting adapter...\n", bp->dev->name); 1749 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1750 { 1751 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1752 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1753 return; 1754 } 1755 printk("%s: Adapter reset successful!\n", bp->dev->name); 1756 } 1757 else if (state == PI_STATE_K_LINK_AVAIL) 1758 { 1759 bp->link_available = PI_K_TRUE; /* set link available flag */ 1760 } 1761 } 1762 } 1763 1764 1765 /* 1766 * ================== 1767 * = dfx_int_common = 1768 * ================== 1769 * 1770 * Overview: 1771 * Interrupt service routine (ISR) 1772 * 1773 * Returns: 1774 * None 1775 * 1776 * Arguments: 1777 * bp - pointer to board information 1778 * 1779 * Functional Description: 1780 * This is the ISR which processes incoming adapter interrupts. 1781 * 1782 * Return Codes: 1783 * None 1784 * 1785 * Assumptions: 1786 * This routine assumes PDQ interrupts have not been disabled. 1787 * When interrupts are disabled at the PDQ, the Port Status register 1788 * is automatically cleared. This routine uses the Port Status 1789 * register value to determine whether a Type 0 interrupt occurred, 1790 * so it's important that adapter interrupts are not normally 1791 * enabled/disabled at the PDQ. 1792 * 1793 * It's vital that this routine is NOT reentered for the 1794 * same board and that the OS is not in another section of 1795 * code (eg. dfx_xmt_queue_pkt) for the same board on a 1796 * different thread. 1797 * 1798 * Side Effects: 1799 * Pending interrupts are serviced. Depending on the type of 1800 * interrupt, acknowledging and clearing the interrupt at the 1801 * PDQ involves writing a register to clear the interrupt bit 1802 * or updating completion indices. 1803 */ 1804 1805 static void dfx_int_common(struct net_device *dev) 1806 { 1807 DFX_board_t *bp = netdev_priv(dev); 1808 PI_UINT32 port_status; /* Port Status register */ 1809 1810 /* Process xmt interrupts - frequent case, so always call this routine */ 1811 1812 if(dfx_xmt_done(bp)) /* free consumed xmt packets */ 1813 netif_wake_queue(dev); 1814 1815 /* Process rcv interrupts - frequent case, so always call this routine */ 1816 1817 dfx_rcv_queue_process(bp); /* service received LLC frames */ 1818 1819 /* 1820 * Transmit and receive producer and completion indices are updated on the 1821 * adapter by writing to the Type 2 Producer register. Since the frequent 1822 * case is that we'll be processing either LLC transmit or receive buffers, 1823 * we'll optimize I/O writes by doing a single register write here. 1824 */ 1825 1826 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 1827 1828 /* Read PDQ Port Status register to find out which interrupts need processing */ 1829 1830 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1831 1832 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */ 1833 1834 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING) 1835 dfx_int_type_0_process(bp); /* process Type 0 interrupts */ 1836 } 1837 1838 1839 /* 1840 * ================= 1841 * = dfx_interrupt = 1842 * ================= 1843 * 1844 * Overview: 1845 * Interrupt processing routine 1846 * 1847 * Returns: 1848 * Whether a valid interrupt was seen. 1849 * 1850 * Arguments: 1851 * irq - interrupt vector 1852 * dev_id - pointer to device information 1853 * 1854 * Functional Description: 1855 * This routine calls the interrupt processing routine for this adapter. It 1856 * disables and reenables adapter interrupts, as appropriate. We can support 1857 * shared interrupts since the incoming dev_id pointer provides our device 1858 * structure context. 1859 * 1860 * Return Codes: 1861 * IRQ_HANDLED - an IRQ was handled. 1862 * IRQ_NONE - no IRQ was handled. 1863 * 1864 * Assumptions: 1865 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC 1866 * on Intel-based systems) is done by the operating system outside this 1867 * routine. 1868 * 1869 * System interrupts are enabled through this call. 1870 * 1871 * Side Effects: 1872 * Interrupts are disabled, then reenabled at the adapter. 1873 */ 1874 1875 static irqreturn_t dfx_interrupt(int irq, void *dev_id) 1876 { 1877 struct net_device *dev = dev_id; 1878 DFX_board_t *bp = netdev_priv(dev); 1879 struct device *bdev = bp->bus_dev; 1880 int dfx_bus_pci = DFX_BUS_PCI(bdev); 1881 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 1882 int dfx_bus_tc = DFX_BUS_TC(bdev); 1883 1884 /* Service adapter interrupts */ 1885 1886 if (dfx_bus_pci) { 1887 u32 status; 1888 1889 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status); 1890 if (!(status & PFI_STATUS_M_PDQ_INT)) 1891 return IRQ_NONE; 1892 1893 spin_lock(&bp->lock); 1894 1895 /* Disable PDQ-PFI interrupts at PFI */ 1896 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1897 PFI_MODE_M_DMA_ENB); 1898 1899 /* Call interrupt service routine for this adapter */ 1900 dfx_int_common(dev); 1901 1902 /* Clear PDQ interrupt status bit and reenable interrupts */ 1903 dfx_port_write_long(bp, PFI_K_REG_STATUS, 1904 PFI_STATUS_M_PDQ_INT); 1905 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1906 (PFI_MODE_M_PDQ_INT_ENB | 1907 PFI_MODE_M_DMA_ENB)); 1908 1909 spin_unlock(&bp->lock); 1910 } 1911 if (dfx_bus_eisa) { 1912 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 1913 u8 status; 1914 1915 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1916 if (!(status & PI_CONFIG_STAT_0_M_PEND)) 1917 return IRQ_NONE; 1918 1919 spin_lock(&bp->lock); 1920 1921 /* Disable interrupts at the ESIC */ 1922 status &= ~PI_CONFIG_STAT_0_M_INT_ENB; 1923 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1924 1925 /* Call interrupt service routine for this adapter */ 1926 dfx_int_common(dev); 1927 1928 /* Reenable interrupts at the ESIC */ 1929 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1930 status |= PI_CONFIG_STAT_0_M_INT_ENB; 1931 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1932 1933 spin_unlock(&bp->lock); 1934 } 1935 if (dfx_bus_tc) { 1936 u32 status; 1937 1938 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status); 1939 if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING | 1940 PI_PSTATUS_M_XMT_DATA_PENDING | 1941 PI_PSTATUS_M_SMT_HOST_PENDING | 1942 PI_PSTATUS_M_UNSOL_PENDING | 1943 PI_PSTATUS_M_CMD_RSP_PENDING | 1944 PI_PSTATUS_M_CMD_REQ_PENDING | 1945 PI_PSTATUS_M_TYPE_0_PENDING))) 1946 return IRQ_NONE; 1947 1948 spin_lock(&bp->lock); 1949 1950 /* Call interrupt service routine for this adapter */ 1951 dfx_int_common(dev); 1952 1953 spin_unlock(&bp->lock); 1954 } 1955 1956 return IRQ_HANDLED; 1957 } 1958 1959 1960 /* 1961 * ===================== 1962 * = dfx_ctl_get_stats = 1963 * ===================== 1964 * 1965 * Overview: 1966 * Get statistics for FDDI adapter 1967 * 1968 * Returns: 1969 * Pointer to FDDI statistics structure 1970 * 1971 * Arguments: 1972 * dev - pointer to device information 1973 * 1974 * Functional Description: 1975 * Gets current MIB objects from adapter, then 1976 * returns FDDI statistics structure as defined 1977 * in if_fddi.h. 1978 * 1979 * Note: Since the FDDI statistics structure is 1980 * still new and the device structure doesn't 1981 * have an FDDI-specific get statistics handler, 1982 * we'll return the FDDI statistics structure as 1983 * a pointer to an Ethernet statistics structure. 1984 * That way, at least the first part of the statistics 1985 * structure can be decoded properly, and it allows 1986 * "smart" applications to perform a second cast to 1987 * decode the FDDI-specific statistics. 1988 * 1989 * We'll have to pay attention to this routine as the 1990 * device structure becomes more mature and LAN media 1991 * independent. 1992 * 1993 * Return Codes: 1994 * None 1995 * 1996 * Assumptions: 1997 * None 1998 * 1999 * Side Effects: 2000 * None 2001 */ 2002 2003 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev) 2004 { 2005 DFX_board_t *bp = netdev_priv(dev); 2006 2007 /* Fill the bp->stats structure with driver-maintained counters */ 2008 2009 bp->stats.gen.rx_packets = bp->rcv_total_frames; 2010 bp->stats.gen.tx_packets = bp->xmt_total_frames; 2011 bp->stats.gen.rx_bytes = bp->rcv_total_bytes; 2012 bp->stats.gen.tx_bytes = bp->xmt_total_bytes; 2013 bp->stats.gen.rx_errors = bp->rcv_crc_errors + 2014 bp->rcv_frame_status_errors + 2015 bp->rcv_length_errors; 2016 bp->stats.gen.tx_errors = bp->xmt_length_errors; 2017 bp->stats.gen.rx_dropped = bp->rcv_discards; 2018 bp->stats.gen.tx_dropped = bp->xmt_discards; 2019 bp->stats.gen.multicast = bp->rcv_multicast_frames; 2020 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */ 2021 2022 /* Get FDDI SMT MIB objects */ 2023 2024 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET; 2025 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2026 return (struct net_device_stats *)&bp->stats; 2027 2028 /* Fill the bp->stats structure with the SMT MIB object values */ 2029 2030 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id)); 2031 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id; 2032 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id; 2033 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id; 2034 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data)); 2035 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id; 2036 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct; 2037 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct; 2038 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct; 2039 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths; 2040 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities; 2041 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy; 2042 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy; 2043 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify; 2044 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy; 2045 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration; 2046 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present; 2047 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state; 2048 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state; 2049 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag; 2050 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status; 2051 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag; 2052 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls; 2053 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls; 2054 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions; 2055 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability; 2056 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability; 2057 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths; 2058 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path; 2059 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN); 2060 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN); 2061 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN); 2062 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN); 2063 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test; 2064 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths; 2065 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type; 2066 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN); 2067 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req; 2068 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg; 2069 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max; 2070 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value; 2071 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold; 2072 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio; 2073 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state; 2074 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag; 2075 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag; 2076 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag; 2077 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available; 2078 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present; 2079 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable; 2080 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound; 2081 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound; 2082 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req; 2083 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration)); 2084 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0]; 2085 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1]; 2086 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0]; 2087 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1]; 2088 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0]; 2089 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1]; 2090 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0]; 2091 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1]; 2092 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0]; 2093 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1]; 2094 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3); 2095 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3); 2096 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0]; 2097 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1]; 2098 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0]; 2099 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1]; 2100 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0]; 2101 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1]; 2102 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0]; 2103 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1]; 2104 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0]; 2105 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1]; 2106 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0]; 2107 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1]; 2108 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0]; 2109 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1]; 2110 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0]; 2111 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1]; 2112 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0]; 2113 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1]; 2114 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0]; 2115 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1]; 2116 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0]; 2117 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1]; 2118 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0]; 2119 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1]; 2120 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0]; 2121 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1]; 2122 2123 /* Get FDDI counters */ 2124 2125 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET; 2126 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2127 return (struct net_device_stats *)&bp->stats; 2128 2129 /* Fill the bp->stats structure with the FDDI counter values */ 2130 2131 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls; 2132 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls; 2133 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls; 2134 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls; 2135 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls; 2136 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls; 2137 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls; 2138 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls; 2139 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls; 2140 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls; 2141 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls; 2142 2143 return (struct net_device_stats *)&bp->stats; 2144 } 2145 2146 2147 /* 2148 * ============================== 2149 * = dfx_ctl_set_multicast_list = 2150 * ============================== 2151 * 2152 * Overview: 2153 * Enable/Disable LLC frame promiscuous mode reception 2154 * on the adapter and/or update multicast address table. 2155 * 2156 * Returns: 2157 * None 2158 * 2159 * Arguments: 2160 * dev - pointer to device information 2161 * 2162 * Functional Description: 2163 * This routine follows a fairly simple algorithm for setting the 2164 * adapter filters and CAM: 2165 * 2166 * if IFF_PROMISC flag is set 2167 * enable LLC individual/group promiscuous mode 2168 * else 2169 * disable LLC individual/group promiscuous mode 2170 * if number of incoming multicast addresses > 2171 * (CAM max size - number of unicast addresses in CAM) 2172 * enable LLC group promiscuous mode 2173 * set driver-maintained multicast address count to zero 2174 * else 2175 * disable LLC group promiscuous mode 2176 * set driver-maintained multicast address count to incoming count 2177 * update adapter CAM 2178 * update adapter filters 2179 * 2180 * Return Codes: 2181 * None 2182 * 2183 * Assumptions: 2184 * Multicast addresses are presented in canonical (LSB) format. 2185 * 2186 * Side Effects: 2187 * On-board adapter CAM and filters are updated. 2188 */ 2189 2190 static void dfx_ctl_set_multicast_list(struct net_device *dev) 2191 { 2192 DFX_board_t *bp = netdev_priv(dev); 2193 int i; /* used as index in for loop */ 2194 struct netdev_hw_addr *ha; 2195 2196 /* Enable LLC frame promiscuous mode, if necessary */ 2197 2198 if (dev->flags & IFF_PROMISC) 2199 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */ 2200 2201 /* Else, update multicast address table */ 2202 2203 else 2204 { 2205 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */ 2206 /* 2207 * Check whether incoming multicast address count exceeds table size 2208 * 2209 * Note: The adapters utilize an on-board 64 entry CAM for 2210 * supporting perfect filtering of multicast packets 2211 * and bridge functions when adding unicast addresses. 2212 * There is no hash function available. To support 2213 * additional multicast addresses, the all multicast 2214 * filter (LLC group promiscuous mode) must be enabled. 2215 * 2216 * The firmware reserves two CAM entries for SMT-related 2217 * multicast addresses, which leaves 62 entries available. 2218 * The following code ensures that we're not being asked 2219 * to add more than 62 addresses to the CAM. If we are, 2220 * the driver will enable the all multicast filter. 2221 * Should the number of multicast addresses drop below 2222 * the high water mark, the filter will be disabled and 2223 * perfect filtering will be used. 2224 */ 2225 2226 if (netdev_mc_count(dev) > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count)) 2227 { 2228 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2229 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2230 } 2231 else 2232 { 2233 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */ 2234 bp->mc_count = netdev_mc_count(dev); /* Add mc addrs to CAM */ 2235 } 2236 2237 /* Copy addresses to multicast address table, then update adapter CAM */ 2238 2239 i = 0; 2240 netdev_for_each_mc_addr(ha, dev) 2241 memcpy(&bp->mc_table[i++ * FDDI_K_ALEN], 2242 ha->addr, FDDI_K_ALEN); 2243 2244 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2245 { 2246 DBG_printk("%s: Could not update multicast address table!\n", dev->name); 2247 } 2248 else 2249 { 2250 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count); 2251 } 2252 } 2253 2254 /* Update adapter filters */ 2255 2256 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2257 { 2258 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2259 } 2260 else 2261 { 2262 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2263 } 2264 } 2265 2266 2267 /* 2268 * =========================== 2269 * = dfx_ctl_set_mac_address = 2270 * =========================== 2271 * 2272 * Overview: 2273 * Add node address override (unicast address) to adapter 2274 * CAM and update dev_addr field in device table. 2275 * 2276 * Returns: 2277 * None 2278 * 2279 * Arguments: 2280 * dev - pointer to device information 2281 * addr - pointer to sockaddr structure containing unicast address to add 2282 * 2283 * Functional Description: 2284 * The adapter supports node address overrides by adding one or more 2285 * unicast addresses to the adapter CAM. This is similar to adding 2286 * multicast addresses. In this routine we'll update the driver and 2287 * device structures with the new address, then update the adapter CAM 2288 * to ensure that the adapter will copy and strip frames destined and 2289 * sourced by that address. 2290 * 2291 * Return Codes: 2292 * Always returns zero. 2293 * 2294 * Assumptions: 2295 * The address pointed to by addr->sa_data is a valid unicast 2296 * address and is presented in canonical (LSB) format. 2297 * 2298 * Side Effects: 2299 * On-board adapter CAM is updated. On-board adapter filters 2300 * may be updated. 2301 */ 2302 2303 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr) 2304 { 2305 struct sockaddr *p_sockaddr = (struct sockaddr *)addr; 2306 DFX_board_t *bp = netdev_priv(dev); 2307 2308 /* Copy unicast address to driver-maintained structs and update count */ 2309 2310 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */ 2311 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */ 2312 bp->uc_count = 1; 2313 2314 /* 2315 * Verify we're not exceeding the CAM size by adding unicast address 2316 * 2317 * Note: It's possible that before entering this routine we've 2318 * already filled the CAM with 62 multicast addresses. 2319 * Since we need to place the node address override into 2320 * the CAM, we have to check to see that we're not 2321 * exceeding the CAM size. If we are, we have to enable 2322 * the LLC group (multicast) promiscuous mode filter as 2323 * in dfx_ctl_set_multicast_list. 2324 */ 2325 2326 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE) 2327 { 2328 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2329 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2330 2331 /* Update adapter filters */ 2332 2333 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2334 { 2335 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2336 } 2337 else 2338 { 2339 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2340 } 2341 } 2342 2343 /* Update adapter CAM with new unicast address */ 2344 2345 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2346 { 2347 DBG_printk("%s: Could not set new MAC address!\n", dev->name); 2348 } 2349 else 2350 { 2351 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name); 2352 } 2353 return 0; /* always return zero */ 2354 } 2355 2356 2357 /* 2358 * ====================== 2359 * = dfx_ctl_update_cam = 2360 * ====================== 2361 * 2362 * Overview: 2363 * Procedure to update adapter CAM (Content Addressable Memory) 2364 * with desired unicast and multicast address entries. 2365 * 2366 * Returns: 2367 * Condition code 2368 * 2369 * Arguments: 2370 * bp - pointer to board information 2371 * 2372 * Functional Description: 2373 * Updates adapter CAM with current contents of board structure 2374 * unicast and multicast address tables. Since there are only 62 2375 * free entries in CAM, this routine ensures that the command 2376 * request buffer is not overrun. 2377 * 2378 * Return Codes: 2379 * DFX_K_SUCCESS - Request succeeded 2380 * DFX_K_FAILURE - Request failed 2381 * 2382 * Assumptions: 2383 * All addresses being added (unicast and multicast) are in canonical 2384 * order. 2385 * 2386 * Side Effects: 2387 * On-board adapter CAM is updated. 2388 */ 2389 2390 static int dfx_ctl_update_cam(DFX_board_t *bp) 2391 { 2392 int i; /* used as index */ 2393 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */ 2394 2395 /* 2396 * Fill in command request information 2397 * 2398 * Note: Even though both the unicast and multicast address 2399 * table entries are stored as contiguous 6 byte entries, 2400 * the firmware address filter set command expects each 2401 * entry to be two longwords (8 bytes total). We must be 2402 * careful to only copy the six bytes of each unicast and 2403 * multicast table entry into each command entry. This 2404 * is also why we must first clear the entire command 2405 * request buffer. 2406 */ 2407 2408 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */ 2409 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET; 2410 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0]; 2411 2412 /* Now add unicast addresses to command request buffer, if any */ 2413 2414 for (i=0; i < (int)bp->uc_count; i++) 2415 { 2416 if (i < PI_CMD_ADDR_FILTER_K_SIZE) 2417 { 2418 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2419 p_addr++; /* point to next command entry */ 2420 } 2421 } 2422 2423 /* Now add multicast addresses to command request buffer, if any */ 2424 2425 for (i=0; i < (int)bp->mc_count; i++) 2426 { 2427 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE) 2428 { 2429 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2430 p_addr++; /* point to next command entry */ 2431 } 2432 } 2433 2434 /* Issue command to update adapter CAM, then return */ 2435 2436 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2437 return DFX_K_FAILURE; 2438 return DFX_K_SUCCESS; 2439 } 2440 2441 2442 /* 2443 * ========================== 2444 * = dfx_ctl_update_filters = 2445 * ========================== 2446 * 2447 * Overview: 2448 * Procedure to update adapter filters with desired 2449 * filter settings. 2450 * 2451 * Returns: 2452 * Condition code 2453 * 2454 * Arguments: 2455 * bp - pointer to board information 2456 * 2457 * Functional Description: 2458 * Enables or disables filter using current filter settings. 2459 * 2460 * Return Codes: 2461 * DFX_K_SUCCESS - Request succeeded. 2462 * DFX_K_FAILURE - Request failed. 2463 * 2464 * Assumptions: 2465 * We must always pass up packets destined to the broadcast 2466 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the 2467 * broadcast filter enabled. 2468 * 2469 * Side Effects: 2470 * On-board adapter filters are updated. 2471 */ 2472 2473 static int dfx_ctl_update_filters(DFX_board_t *bp) 2474 { 2475 int i = 0; /* used as index */ 2476 2477 /* Fill in command request information */ 2478 2479 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET; 2480 2481 /* Initialize Broadcast filter - * ALWAYS ENABLED * */ 2482 2483 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST; 2484 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS; 2485 2486 /* Initialize LLC Individual/Group Promiscuous filter */ 2487 2488 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM; 2489 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom; 2490 2491 /* Initialize LLC Group Promiscuous filter */ 2492 2493 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM; 2494 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom; 2495 2496 /* Terminate the item code list */ 2497 2498 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL; 2499 2500 /* Issue command to update adapter filters, then return */ 2501 2502 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2503 return DFX_K_FAILURE; 2504 return DFX_K_SUCCESS; 2505 } 2506 2507 2508 /* 2509 * ====================== 2510 * = dfx_hw_dma_cmd_req = 2511 * ====================== 2512 * 2513 * Overview: 2514 * Sends PDQ DMA command to adapter firmware 2515 * 2516 * Returns: 2517 * Condition code 2518 * 2519 * Arguments: 2520 * bp - pointer to board information 2521 * 2522 * Functional Description: 2523 * The command request and response buffers are posted to the adapter in the manner 2524 * described in the PDQ Port Specification: 2525 * 2526 * 1. Command Response Buffer is posted to adapter. 2527 * 2. Command Request Buffer is posted to adapter. 2528 * 3. Command Request consumer index is polled until it indicates that request 2529 * buffer has been DMA'd to adapter. 2530 * 4. Command Response consumer index is polled until it indicates that response 2531 * buffer has been DMA'd from adapter. 2532 * 2533 * This ordering ensures that a response buffer is already available for the firmware 2534 * to use once it's done processing the request buffer. 2535 * 2536 * Return Codes: 2537 * DFX_K_SUCCESS - DMA command succeeded 2538 * DFX_K_OUTSTATE - Adapter is NOT in proper state 2539 * DFX_K_HW_TIMEOUT - DMA command timed out 2540 * 2541 * Assumptions: 2542 * Command request buffer has already been filled with desired DMA command. 2543 * 2544 * Side Effects: 2545 * None 2546 */ 2547 2548 static int dfx_hw_dma_cmd_req(DFX_board_t *bp) 2549 { 2550 int status; /* adapter status */ 2551 int timeout_cnt; /* used in for loops */ 2552 2553 /* Make sure the adapter is in a state that we can issue the DMA command in */ 2554 2555 status = dfx_hw_adap_state_rd(bp); 2556 if ((status == PI_STATE_K_RESET) || 2557 (status == PI_STATE_K_HALTED) || 2558 (status == PI_STATE_K_DMA_UNAVAIL) || 2559 (status == PI_STATE_K_UPGRADE)) 2560 return DFX_K_OUTSTATE; 2561 2562 /* Put response buffer on the command response queue */ 2563 2564 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2565 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2566 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys; 2567 2568 /* Bump (and wrap) the producer index and write out to register */ 2569 2570 bp->cmd_rsp_reg.index.prod += 1; 2571 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2572 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2573 2574 /* Put request buffer on the command request queue */ 2575 2576 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP | 2577 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN)); 2578 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys; 2579 2580 /* Bump (and wrap) the producer index and write out to register */ 2581 2582 bp->cmd_req_reg.index.prod += 1; 2583 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2584 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2585 2586 /* 2587 * Here we wait for the command request consumer index to be equal 2588 * to the producer, indicating that the adapter has DMAed the request. 2589 */ 2590 2591 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2592 { 2593 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req)) 2594 break; 2595 udelay(100); /* wait for 100 microseconds */ 2596 } 2597 if (timeout_cnt == 0) 2598 return DFX_K_HW_TIMEOUT; 2599 2600 /* Bump (and wrap) the completion index and write out to register */ 2601 2602 bp->cmd_req_reg.index.comp += 1; 2603 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2604 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2605 2606 /* 2607 * Here we wait for the command response consumer index to be equal 2608 * to the producer, indicating that the adapter has DMAed the response. 2609 */ 2610 2611 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2612 { 2613 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp)) 2614 break; 2615 udelay(100); /* wait for 100 microseconds */ 2616 } 2617 if (timeout_cnt == 0) 2618 return DFX_K_HW_TIMEOUT; 2619 2620 /* Bump (and wrap) the completion index and write out to register */ 2621 2622 bp->cmd_rsp_reg.index.comp += 1; 2623 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2624 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2625 return DFX_K_SUCCESS; 2626 } 2627 2628 2629 /* 2630 * ======================== 2631 * = dfx_hw_port_ctrl_req = 2632 * ======================== 2633 * 2634 * Overview: 2635 * Sends PDQ port control command to adapter firmware 2636 * 2637 * Returns: 2638 * Host data register value in host_data if ptr is not NULL 2639 * 2640 * Arguments: 2641 * bp - pointer to board information 2642 * command - port control command 2643 * data_a - port data A register value 2644 * data_b - port data B register value 2645 * host_data - ptr to host data register value 2646 * 2647 * Functional Description: 2648 * Send generic port control command to adapter by writing 2649 * to various PDQ port registers, then polling for completion. 2650 * 2651 * Return Codes: 2652 * DFX_K_SUCCESS - port control command succeeded 2653 * DFX_K_HW_TIMEOUT - port control command timed out 2654 * 2655 * Assumptions: 2656 * None 2657 * 2658 * Side Effects: 2659 * None 2660 */ 2661 2662 static int dfx_hw_port_ctrl_req( 2663 DFX_board_t *bp, 2664 PI_UINT32 command, 2665 PI_UINT32 data_a, 2666 PI_UINT32 data_b, 2667 PI_UINT32 *host_data 2668 ) 2669 2670 { 2671 PI_UINT32 port_cmd; /* Port Control command register value */ 2672 int timeout_cnt; /* used in for loops */ 2673 2674 /* Set Command Error bit in command longword */ 2675 2676 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR); 2677 2678 /* Issue port command to the adapter */ 2679 2680 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a); 2681 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b); 2682 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd); 2683 2684 /* Now wait for command to complete */ 2685 2686 if (command == PI_PCTRL_M_BLAST_FLASH) 2687 timeout_cnt = 600000; /* set command timeout count to 60 seconds */ 2688 else 2689 timeout_cnt = 20000; /* set command timeout count to 2 seconds */ 2690 2691 for (; timeout_cnt > 0; timeout_cnt--) 2692 { 2693 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd); 2694 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR)) 2695 break; 2696 udelay(100); /* wait for 100 microseconds */ 2697 } 2698 if (timeout_cnt == 0) 2699 return DFX_K_HW_TIMEOUT; 2700 2701 /* 2702 * If the address of host_data is non-zero, assume caller has supplied a 2703 * non NULL pointer, and return the contents of the HOST_DATA register in 2704 * it. 2705 */ 2706 2707 if (host_data != NULL) 2708 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data); 2709 return DFX_K_SUCCESS; 2710 } 2711 2712 2713 /* 2714 * ===================== 2715 * = dfx_hw_adap_reset = 2716 * ===================== 2717 * 2718 * Overview: 2719 * Resets adapter 2720 * 2721 * Returns: 2722 * None 2723 * 2724 * Arguments: 2725 * bp - pointer to board information 2726 * type - type of reset to perform 2727 * 2728 * Functional Description: 2729 * Issue soft reset to adapter by writing to PDQ Port Reset 2730 * register. Use incoming reset type to tell adapter what 2731 * kind of reset operation to perform. 2732 * 2733 * Return Codes: 2734 * None 2735 * 2736 * Assumptions: 2737 * This routine merely issues a soft reset to the adapter. 2738 * It is expected that after this routine returns, the caller 2739 * will appropriately poll the Port Status register for the 2740 * adapter to enter the proper state. 2741 * 2742 * Side Effects: 2743 * Internal adapter registers are cleared. 2744 */ 2745 2746 static void dfx_hw_adap_reset( 2747 DFX_board_t *bp, 2748 PI_UINT32 type 2749 ) 2750 2751 { 2752 /* Set Reset type and assert reset */ 2753 2754 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */ 2755 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET); 2756 2757 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */ 2758 2759 udelay(20); 2760 2761 /* Deassert reset */ 2762 2763 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0); 2764 } 2765 2766 2767 /* 2768 * ======================== 2769 * = dfx_hw_adap_state_rd = 2770 * ======================== 2771 * 2772 * Overview: 2773 * Returns current adapter state 2774 * 2775 * Returns: 2776 * Adapter state per PDQ Port Specification 2777 * 2778 * Arguments: 2779 * bp - pointer to board information 2780 * 2781 * Functional Description: 2782 * Reads PDQ Port Status register and returns adapter state. 2783 * 2784 * Return Codes: 2785 * None 2786 * 2787 * Assumptions: 2788 * None 2789 * 2790 * Side Effects: 2791 * None 2792 */ 2793 2794 static int dfx_hw_adap_state_rd(DFX_board_t *bp) 2795 { 2796 PI_UINT32 port_status; /* Port Status register value */ 2797 2798 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 2799 return (port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE; 2800 } 2801 2802 2803 /* 2804 * ===================== 2805 * = dfx_hw_dma_uninit = 2806 * ===================== 2807 * 2808 * Overview: 2809 * Brings adapter to DMA_UNAVAILABLE state 2810 * 2811 * Returns: 2812 * Condition code 2813 * 2814 * Arguments: 2815 * bp - pointer to board information 2816 * type - type of reset to perform 2817 * 2818 * Functional Description: 2819 * Bring adapter to DMA_UNAVAILABLE state by performing the following: 2820 * 1. Set reset type bit in Port Data A Register then reset adapter. 2821 * 2. Check that adapter is in DMA_UNAVAILABLE state. 2822 * 2823 * Return Codes: 2824 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state 2825 * DFX_K_HW_TIMEOUT - adapter did not reset properly 2826 * 2827 * Assumptions: 2828 * None 2829 * 2830 * Side Effects: 2831 * Internal adapter registers are cleared. 2832 */ 2833 2834 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type) 2835 { 2836 int timeout_cnt; /* used in for loops */ 2837 2838 /* Set reset type bit and reset adapter */ 2839 2840 dfx_hw_adap_reset(bp, type); 2841 2842 /* Now wait for adapter to enter DMA_UNAVAILABLE state */ 2843 2844 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--) 2845 { 2846 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL) 2847 break; 2848 udelay(100); /* wait for 100 microseconds */ 2849 } 2850 if (timeout_cnt == 0) 2851 return DFX_K_HW_TIMEOUT; 2852 return DFX_K_SUCCESS; 2853 } 2854 2855 /* 2856 * Align an sk_buff to a boundary power of 2 2857 * 2858 */ 2859 2860 static void my_skb_align(struct sk_buff *skb, int n) 2861 { 2862 unsigned long x = (unsigned long)skb->data; 2863 unsigned long v; 2864 2865 v = ALIGN(x, n); /* Where we want to be */ 2866 2867 skb_reserve(skb, v - x); 2868 } 2869 2870 2871 /* 2872 * ================ 2873 * = dfx_rcv_init = 2874 * ================ 2875 * 2876 * Overview: 2877 * Produces buffers to adapter LLC Host receive descriptor block 2878 * 2879 * Returns: 2880 * None 2881 * 2882 * Arguments: 2883 * bp - pointer to board information 2884 * get_buffers - non-zero if buffers to be allocated 2885 * 2886 * Functional Description: 2887 * This routine can be called during dfx_adap_init() or during an adapter 2888 * reset. It initializes the descriptor block and produces all allocated 2889 * LLC Host queue receive buffers. 2890 * 2891 * Return Codes: 2892 * Return 0 on success or -ENOMEM if buffer allocation failed (when using 2893 * dynamic buffer allocation). If the buffer allocation failed, the 2894 * already allocated buffers will not be released and the caller should do 2895 * this. 2896 * 2897 * Assumptions: 2898 * The PDQ has been reset and the adapter and driver maintained Type 2 2899 * register indices are cleared. 2900 * 2901 * Side Effects: 2902 * Receive buffers are posted to the adapter LLC queue and the adapter 2903 * is notified. 2904 */ 2905 2906 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers) 2907 { 2908 int i, j; /* used in for loop */ 2909 2910 /* 2911 * Since each receive buffer is a single fragment of same length, initialize 2912 * first longword in each receive descriptor for entire LLC Host descriptor 2913 * block. Also initialize second longword in each receive descriptor with 2914 * physical address of receive buffer. We'll always allocate receive 2915 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor 2916 * block and produce new receive buffers by simply updating the receive 2917 * producer index. 2918 * 2919 * Assumptions: 2920 * To support all shipping versions of PDQ, the receive buffer size 2921 * must be mod 128 in length and the physical address must be 128 byte 2922 * aligned. In other words, bits 0-6 of the length and address must 2923 * be zero for the following descriptor field entries to be correct on 2924 * all PDQ-based boards. We guaranteed both requirements during 2925 * driver initialization when we allocated memory for the receive buffers. 2926 */ 2927 2928 if (get_buffers) { 2929 #ifdef DYNAMIC_BUFFERS 2930 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 2931 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2932 { 2933 struct sk_buff *newskb = __netdev_alloc_skb(bp->dev, NEW_SKB_SIZE, GFP_NOIO); 2934 if (!newskb) 2935 return -ENOMEM; 2936 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2937 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2938 /* 2939 * align to 128 bytes for compatibility with 2940 * the old EISA boards. 2941 */ 2942 2943 my_skb_align(newskb, 128); 2944 bp->descr_block_virt->rcv_data[i + j].long_1 = 2945 (u32)dma_map_single(bp->bus_dev, newskb->data, 2946 NEW_SKB_SIZE, 2947 DMA_FROM_DEVICE); 2948 /* 2949 * p_rcv_buff_va is only used inside the 2950 * kernel so we put the skb pointer here. 2951 */ 2952 bp->p_rcv_buff_va[i+j] = (char *) newskb; 2953 } 2954 #else 2955 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++) 2956 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2957 { 2958 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2959 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2960 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX)); 2961 bp->p_rcv_buff_va[i+j] = (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX)); 2962 } 2963 #endif 2964 } 2965 2966 /* Update receive producer and Type 2 register */ 2967 2968 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post; 2969 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 2970 return 0; 2971 } 2972 2973 2974 /* 2975 * ========================= 2976 * = dfx_rcv_queue_process = 2977 * ========================= 2978 * 2979 * Overview: 2980 * Process received LLC frames. 2981 * 2982 * Returns: 2983 * None 2984 * 2985 * Arguments: 2986 * bp - pointer to board information 2987 * 2988 * Functional Description: 2989 * Received LLC frames are processed until there are no more consumed frames. 2990 * Once all frames are processed, the receive buffers are returned to the 2991 * adapter. Note that this algorithm fixes the length of time that can be spent 2992 * in this routine, because there are a fixed number of receive buffers to 2993 * process and buffers are not produced until this routine exits and returns 2994 * to the ISR. 2995 * 2996 * Return Codes: 2997 * None 2998 * 2999 * Assumptions: 3000 * None 3001 * 3002 * Side Effects: 3003 * None 3004 */ 3005 3006 static void dfx_rcv_queue_process( 3007 DFX_board_t *bp 3008 ) 3009 3010 { 3011 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3012 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */ 3013 u32 descr, pkt_len; /* FMC descriptor field and packet length */ 3014 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */ 3015 3016 /* Service all consumed LLC receive frames */ 3017 3018 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3019 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons) 3020 { 3021 /* Process any errors */ 3022 3023 int entry; 3024 3025 entry = bp->rcv_xmt_reg.index.rcv_comp; 3026 #ifdef DYNAMIC_BUFFERS 3027 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data); 3028 #else 3029 p_buff = bp->p_rcv_buff_va[entry]; 3030 #endif 3031 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32)); 3032 3033 if (descr & PI_FMC_DESCR_M_RCC_FLUSH) 3034 { 3035 if (descr & PI_FMC_DESCR_M_RCC_CRC) 3036 bp->rcv_crc_errors++; 3037 else 3038 bp->rcv_frame_status_errors++; 3039 } 3040 else 3041 { 3042 int rx_in_place = 0; 3043 3044 /* The frame was received without errors - verify packet length */ 3045 3046 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN); 3047 pkt_len -= 4; /* subtract 4 byte CRC */ 3048 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3049 bp->rcv_length_errors++; 3050 else{ 3051 #ifdef DYNAMIC_BUFFERS 3052 if (pkt_len > SKBUFF_RX_COPYBREAK) { 3053 struct sk_buff *newskb; 3054 3055 newskb = dev_alloc_skb(NEW_SKB_SIZE); 3056 if (newskb){ 3057 rx_in_place = 1; 3058 3059 my_skb_align(newskb, 128); 3060 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; 3061 dma_unmap_single(bp->bus_dev, 3062 bp->descr_block_virt->rcv_data[entry].long_1, 3063 NEW_SKB_SIZE, 3064 DMA_FROM_DEVICE); 3065 skb_reserve(skb, RCV_BUFF_K_PADDING); 3066 bp->p_rcv_buff_va[entry] = (char *)newskb; 3067 bp->descr_block_virt->rcv_data[entry].long_1 = 3068 (u32)dma_map_single(bp->bus_dev, 3069 newskb->data, 3070 NEW_SKB_SIZE, 3071 DMA_FROM_DEVICE); 3072 } else 3073 skb = NULL; 3074 } else 3075 #endif 3076 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */ 3077 if (skb == NULL) 3078 { 3079 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name); 3080 bp->rcv_discards++; 3081 break; 3082 } 3083 else { 3084 #ifndef DYNAMIC_BUFFERS 3085 if (! rx_in_place) 3086 #endif 3087 { 3088 /* Receive buffer allocated, pass receive packet up */ 3089 3090 skb_copy_to_linear_data(skb, 3091 p_buff + RCV_BUFF_K_PADDING, 3092 pkt_len + 3); 3093 } 3094 3095 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */ 3096 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */ 3097 skb->protocol = fddi_type_trans(skb, bp->dev); 3098 bp->rcv_total_bytes += skb->len; 3099 netif_rx(skb); 3100 3101 /* Update the rcv counters */ 3102 bp->rcv_total_frames++; 3103 if (*(p_buff + RCV_BUFF_K_DA) & 0x01) 3104 bp->rcv_multicast_frames++; 3105 } 3106 } 3107 } 3108 3109 /* 3110 * Advance the producer (for recycling) and advance the completion 3111 * (for servicing received frames). Note that it is okay to 3112 * advance the producer without checking that it passes the 3113 * completion index because they are both advanced at the same 3114 * rate. 3115 */ 3116 3117 bp->rcv_xmt_reg.index.rcv_prod += 1; 3118 bp->rcv_xmt_reg.index.rcv_comp += 1; 3119 } 3120 } 3121 3122 3123 /* 3124 * ===================== 3125 * = dfx_xmt_queue_pkt = 3126 * ===================== 3127 * 3128 * Overview: 3129 * Queues packets for transmission 3130 * 3131 * Returns: 3132 * Condition code 3133 * 3134 * Arguments: 3135 * skb - pointer to sk_buff to queue for transmission 3136 * dev - pointer to device information 3137 * 3138 * Functional Description: 3139 * Here we assume that an incoming skb transmit request 3140 * is contained in a single physically contiguous buffer 3141 * in which the virtual address of the start of packet 3142 * (skb->data) can be converted to a physical address 3143 * by using pci_map_single(). 3144 * 3145 * Since the adapter architecture requires a three byte 3146 * packet request header to prepend the start of packet, 3147 * we'll write the three byte field immediately prior to 3148 * the FC byte. This assumption is valid because we've 3149 * ensured that dev->hard_header_len includes three pad 3150 * bytes. By posting a single fragment to the adapter, 3151 * we'll reduce the number of descriptor fetches and 3152 * bus traffic needed to send the request. 3153 * 3154 * Also, we can't free the skb until after it's been DMA'd 3155 * out by the adapter, so we'll queue it in the driver and 3156 * return it in dfx_xmt_done. 3157 * 3158 * Return Codes: 3159 * 0 - driver queued packet, link is unavailable, or skbuff was bad 3160 * 1 - caller should requeue the sk_buff for later transmission 3161 * 3162 * Assumptions: 3163 * First and foremost, we assume the incoming skb pointer 3164 * is NOT NULL and is pointing to a valid sk_buff structure. 3165 * 3166 * The outgoing packet is complete, starting with the 3167 * frame control byte including the last byte of data, 3168 * but NOT including the 4 byte CRC. We'll let the 3169 * adapter hardware generate and append the CRC. 3170 * 3171 * The entire packet is stored in one physically 3172 * contiguous buffer which is not cached and whose 3173 * 32-bit physical address can be determined. 3174 * 3175 * It's vital that this routine is NOT reentered for the 3176 * same board and that the OS is not in another section of 3177 * code (eg. dfx_int_common) for the same board on a 3178 * different thread. 3179 * 3180 * Side Effects: 3181 * None 3182 */ 3183 3184 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 3185 struct net_device *dev) 3186 { 3187 DFX_board_t *bp = netdev_priv(dev); 3188 u8 prod; /* local transmit producer index */ 3189 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */ 3190 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3191 unsigned long flags; 3192 3193 netif_stop_queue(dev); 3194 3195 /* 3196 * Verify that incoming transmit request is OK 3197 * 3198 * Note: The packet size check is consistent with other 3199 * Linux device drivers, although the correct packet 3200 * size should be verified before calling the 3201 * transmit routine. 3202 */ 3203 3204 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3205 { 3206 printk("%s: Invalid packet length - %u bytes\n", 3207 dev->name, skb->len); 3208 bp->xmt_length_errors++; /* bump error counter */ 3209 netif_wake_queue(dev); 3210 dev_kfree_skb(skb); 3211 return NETDEV_TX_OK; /* return "success" */ 3212 } 3213 /* 3214 * See if adapter link is available, if not, free buffer 3215 * 3216 * Note: If the link isn't available, free buffer and return 0 3217 * rather than tell the upper layer to requeue the packet. 3218 * The methodology here is that by the time the link 3219 * becomes available, the packet to be sent will be 3220 * fairly stale. By simply dropping the packet, the 3221 * higher layer protocols will eventually time out 3222 * waiting for response packets which it won't receive. 3223 */ 3224 3225 if (bp->link_available == PI_K_FALSE) 3226 { 3227 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */ 3228 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */ 3229 else 3230 { 3231 bp->xmt_discards++; /* bump error counter */ 3232 dev_kfree_skb(skb); /* free sk_buff now */ 3233 netif_wake_queue(dev); 3234 return NETDEV_TX_OK; /* return "success" */ 3235 } 3236 } 3237 3238 spin_lock_irqsave(&bp->lock, flags); 3239 3240 /* Get the current producer and the next free xmt data descriptor */ 3241 3242 prod = bp->rcv_xmt_reg.index.xmt_prod; 3243 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]); 3244 3245 /* 3246 * Get pointer to auxiliary queue entry to contain information 3247 * for this packet. 3248 * 3249 * Note: The current xmt producer index will become the 3250 * current xmt completion index when we complete this 3251 * packet later on. So, we'll get the pointer to the 3252 * next auxiliary queue entry now before we bump the 3253 * producer index. 3254 */ 3255 3256 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */ 3257 3258 /* Write the three PRH bytes immediately before the FC byte */ 3259 3260 skb_push(skb,3); 3261 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */ 3262 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */ 3263 skb->data[2] = DFX_PRH2_BYTE; /* specification */ 3264 3265 /* 3266 * Write the descriptor with buffer info and bump producer 3267 * 3268 * Note: Since we need to start DMA from the packet request 3269 * header, we'll add 3 bytes to the DMA buffer length, 3270 * and we'll determine the physical address of the 3271 * buffer from the PRH, not skb->data. 3272 * 3273 * Assumptions: 3274 * 1. Packet starts with the frame control (FC) byte 3275 * at skb->data. 3276 * 2. The 4-byte CRC is not appended to the buffer or 3277 * included in the length. 3278 * 3. Packet length (skb->len) is from FC to end of 3279 * data, inclusive. 3280 * 4. The packet length does not exceed the maximum 3281 * FDDI LLC frame length of 4491 bytes. 3282 * 5. The entire packet is contained in a physically 3283 * contiguous, non-cached, locked memory space 3284 * comprised of a single buffer pointed to by 3285 * skb->data. 3286 * 6. The physical address of the start of packet 3287 * can be determined from the virtual address 3288 * by using pci_map_single() and is only 32-bits 3289 * wide. 3290 */ 3291 3292 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); 3293 p_xmt_descr->long_1 = (u32)dma_map_single(bp->bus_dev, skb->data, 3294 skb->len, DMA_TO_DEVICE); 3295 3296 /* 3297 * Verify that descriptor is actually available 3298 * 3299 * Note: If descriptor isn't available, return 1 which tells 3300 * the upper layer to requeue the packet for later 3301 * transmission. 3302 * 3303 * We need to ensure that the producer never reaches the 3304 * completion, except to indicate that the queue is empty. 3305 */ 3306 3307 if (prod == bp->rcv_xmt_reg.index.xmt_comp) 3308 { 3309 skb_pull(skb,3); 3310 spin_unlock_irqrestore(&bp->lock, flags); 3311 return NETDEV_TX_BUSY; /* requeue packet for later */ 3312 } 3313 3314 /* 3315 * Save info for this packet for xmt done indication routine 3316 * 3317 * Normally, we'd save the producer index in the p_xmt_drv_descr 3318 * structure so that we'd have it handy when we complete this 3319 * packet later (in dfx_xmt_done). However, since the current 3320 * transmit architecture guarantees a single fragment for the 3321 * entire packet, we can simply bump the completion index by 3322 * one (1) for each completed packet. 3323 * 3324 * Note: If this assumption changes and we're presented with 3325 * an inconsistent number of transmit fragments for packet 3326 * data, we'll need to modify this code to save the current 3327 * transmit producer index. 3328 */ 3329 3330 p_xmt_drv_descr->p_skb = skb; 3331 3332 /* Update Type 2 register */ 3333 3334 bp->rcv_xmt_reg.index.xmt_prod = prod; 3335 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 3336 spin_unlock_irqrestore(&bp->lock, flags); 3337 netif_wake_queue(dev); 3338 return NETDEV_TX_OK; /* packet queued to adapter */ 3339 } 3340 3341 3342 /* 3343 * ================ 3344 * = dfx_xmt_done = 3345 * ================ 3346 * 3347 * Overview: 3348 * Processes all frames that have been transmitted. 3349 * 3350 * Returns: 3351 * None 3352 * 3353 * Arguments: 3354 * bp - pointer to board information 3355 * 3356 * Functional Description: 3357 * For all consumed transmit descriptors that have not 3358 * yet been completed, we'll free the skb we were holding 3359 * onto using dev_kfree_skb and bump the appropriate 3360 * counters. 3361 * 3362 * Return Codes: 3363 * None 3364 * 3365 * Assumptions: 3366 * The Type 2 register is not updated in this routine. It is 3367 * assumed that it will be updated in the ISR when dfx_xmt_done 3368 * returns. 3369 * 3370 * Side Effects: 3371 * None 3372 */ 3373 3374 static int dfx_xmt_done(DFX_board_t *bp) 3375 { 3376 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3377 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3378 u8 comp; /* local transmit completion index */ 3379 int freed = 0; /* buffers freed */ 3380 3381 /* Service all consumed transmit frames */ 3382 3383 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3384 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons) 3385 { 3386 /* Get pointer to the transmit driver descriptor block information */ 3387 3388 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3389 3390 /* Increment transmit counters */ 3391 3392 bp->xmt_total_frames++; 3393 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; 3394 3395 /* Return skb to operating system */ 3396 comp = bp->rcv_xmt_reg.index.xmt_comp; 3397 dma_unmap_single(bp->bus_dev, 3398 bp->descr_block_virt->xmt_data[comp].long_1, 3399 p_xmt_drv_descr->p_skb->len, 3400 DMA_TO_DEVICE); 3401 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); 3402 3403 /* 3404 * Move to start of next packet by updating completion index 3405 * 3406 * Here we assume that a transmit packet request is always 3407 * serviced by posting one fragment. We can therefore 3408 * simplify the completion code by incrementing the 3409 * completion index by one. This code will need to be 3410 * modified if this assumption changes. See comments 3411 * in dfx_xmt_queue_pkt for more details. 3412 */ 3413 3414 bp->rcv_xmt_reg.index.xmt_comp += 1; 3415 freed++; 3416 } 3417 return freed; 3418 } 3419 3420 3421 /* 3422 * ================= 3423 * = dfx_rcv_flush = 3424 * ================= 3425 * 3426 * Overview: 3427 * Remove all skb's in the receive ring. 3428 * 3429 * Returns: 3430 * None 3431 * 3432 * Arguments: 3433 * bp - pointer to board information 3434 * 3435 * Functional Description: 3436 * Free's all the dynamically allocated skb's that are 3437 * currently attached to the device receive ring. This 3438 * function is typically only used when the device is 3439 * initialized or reinitialized. 3440 * 3441 * Return Codes: 3442 * None 3443 * 3444 * Side Effects: 3445 * None 3446 */ 3447 #ifdef DYNAMIC_BUFFERS 3448 static void dfx_rcv_flush( DFX_board_t *bp ) 3449 { 3450 int i, j; 3451 3452 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 3453 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 3454 { 3455 struct sk_buff *skb; 3456 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j]; 3457 if (skb) 3458 dev_kfree_skb(skb); 3459 bp->p_rcv_buff_va[i+j] = NULL; 3460 } 3461 3462 } 3463 #else 3464 static inline void dfx_rcv_flush( DFX_board_t *bp ) 3465 { 3466 } 3467 #endif /* DYNAMIC_BUFFERS */ 3468 3469 /* 3470 * ================= 3471 * = dfx_xmt_flush = 3472 * ================= 3473 * 3474 * Overview: 3475 * Processes all frames whether they've been transmitted 3476 * or not. 3477 * 3478 * Returns: 3479 * None 3480 * 3481 * Arguments: 3482 * bp - pointer to board information 3483 * 3484 * Functional Description: 3485 * For all produced transmit descriptors that have not 3486 * yet been completed, we'll free the skb we were holding 3487 * onto using dev_kfree_skb and bump the appropriate 3488 * counters. Of course, it's possible that some of 3489 * these transmit requests actually did go out, but we 3490 * won't make that distinction here. Finally, we'll 3491 * update the consumer index to match the producer. 3492 * 3493 * Return Codes: 3494 * None 3495 * 3496 * Assumptions: 3497 * This routine does NOT update the Type 2 register. It 3498 * is assumed that this routine is being called during a 3499 * transmit flush interrupt, or a shutdown or close routine. 3500 * 3501 * Side Effects: 3502 * None 3503 */ 3504 3505 static void dfx_xmt_flush( DFX_board_t *bp ) 3506 { 3507 u32 prod_cons; /* rcv/xmt consumer block longword */ 3508 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3509 u8 comp; /* local transmit completion index */ 3510 3511 /* Flush all outstanding transmit frames */ 3512 3513 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod) 3514 { 3515 /* Get pointer to the transmit driver descriptor block information */ 3516 3517 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3518 3519 /* Return skb to operating system */ 3520 comp = bp->rcv_xmt_reg.index.xmt_comp; 3521 dma_unmap_single(bp->bus_dev, 3522 bp->descr_block_virt->xmt_data[comp].long_1, 3523 p_xmt_drv_descr->p_skb->len, 3524 DMA_TO_DEVICE); 3525 dev_kfree_skb(p_xmt_drv_descr->p_skb); 3526 3527 /* Increment transmit error counter */ 3528 3529 bp->xmt_discards++; 3530 3531 /* 3532 * Move to start of next packet by updating completion index 3533 * 3534 * Here we assume that a transmit packet request is always 3535 * serviced by posting one fragment. We can therefore 3536 * simplify the completion code by incrementing the 3537 * completion index by one. This code will need to be 3538 * modified if this assumption changes. See comments 3539 * in dfx_xmt_queue_pkt for more details. 3540 */ 3541 3542 bp->rcv_xmt_reg.index.xmt_comp += 1; 3543 } 3544 3545 /* Update the transmit consumer index in the consumer block */ 3546 3547 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX); 3548 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX); 3549 bp->cons_block_virt->xmt_rcv_data = prod_cons; 3550 } 3551 3552 /* 3553 * ================== 3554 * = dfx_unregister = 3555 * ================== 3556 * 3557 * Overview: 3558 * Shuts down an FDDI controller 3559 * 3560 * Returns: 3561 * Condition code 3562 * 3563 * Arguments: 3564 * bdev - pointer to device information 3565 * 3566 * Functional Description: 3567 * 3568 * Return Codes: 3569 * None 3570 * 3571 * Assumptions: 3572 * It compiles so it should work :-( (PCI cards do :-) 3573 * 3574 * Side Effects: 3575 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 3576 * freed. 3577 */ 3578 static void dfx_unregister(struct device *bdev) 3579 { 3580 struct net_device *dev = dev_get_drvdata(bdev); 3581 DFX_board_t *bp = netdev_priv(dev); 3582 int dfx_bus_pci = DFX_BUS_PCI(bdev); 3583 int dfx_bus_tc = DFX_BUS_TC(bdev); 3584 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 3585 resource_size_t bar_start = 0; /* pointer to port */ 3586 resource_size_t bar_len = 0; /* resource length */ 3587 int alloc_size; /* total buffer size used */ 3588 3589 unregister_netdev(dev); 3590 3591 alloc_size = sizeof(PI_DESCR_BLOCK) + 3592 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 3593 #ifndef DYNAMIC_BUFFERS 3594 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 3595 #endif 3596 sizeof(PI_CONSUMER_BLOCK) + 3597 (PI_ALIGN_K_DESC_BLK - 1); 3598 if (bp->kmalloced) 3599 dma_free_coherent(bdev, alloc_size, 3600 bp->kmalloced, bp->kmalloced_dma); 3601 3602 dfx_bus_uninit(dev); 3603 3604 dfx_get_bars(bdev, &bar_start, &bar_len); 3605 if (dfx_use_mmio) { 3606 iounmap(bp->base.mem); 3607 release_mem_region(bar_start, bar_len); 3608 } else 3609 release_region(bar_start, bar_len); 3610 3611 if (dfx_bus_pci) 3612 pci_disable_device(to_pci_dev(bdev)); 3613 3614 free_netdev(dev); 3615 } 3616 3617 3618 static int __maybe_unused dfx_dev_register(struct device *); 3619 static int __maybe_unused dfx_dev_unregister(struct device *); 3620 3621 #ifdef CONFIG_PCI 3622 static int dfx_pci_register(struct pci_dev *, const struct pci_device_id *); 3623 static void dfx_pci_unregister(struct pci_dev *); 3624 3625 static DEFINE_PCI_DEVICE_TABLE(dfx_pci_table) = { 3626 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) }, 3627 { } 3628 }; 3629 MODULE_DEVICE_TABLE(pci, dfx_pci_table); 3630 3631 static struct pci_driver dfx_pci_driver = { 3632 .name = "defxx", 3633 .id_table = dfx_pci_table, 3634 .probe = dfx_pci_register, 3635 .remove = dfx_pci_unregister, 3636 }; 3637 3638 static int dfx_pci_register(struct pci_dev *pdev, 3639 const struct pci_device_id *ent) 3640 { 3641 return dfx_register(&pdev->dev); 3642 } 3643 3644 static void dfx_pci_unregister(struct pci_dev *pdev) 3645 { 3646 dfx_unregister(&pdev->dev); 3647 } 3648 #endif /* CONFIG_PCI */ 3649 3650 #ifdef CONFIG_EISA 3651 static struct eisa_device_id dfx_eisa_table[] = { 3652 { "DEC3001", DEFEA_PROD_ID_1 }, 3653 { "DEC3002", DEFEA_PROD_ID_2 }, 3654 { "DEC3003", DEFEA_PROD_ID_3 }, 3655 { "DEC3004", DEFEA_PROD_ID_4 }, 3656 { } 3657 }; 3658 MODULE_DEVICE_TABLE(eisa, dfx_eisa_table); 3659 3660 static struct eisa_driver dfx_eisa_driver = { 3661 .id_table = dfx_eisa_table, 3662 .driver = { 3663 .name = "defxx", 3664 .bus = &eisa_bus_type, 3665 .probe = dfx_dev_register, 3666 .remove = dfx_dev_unregister, 3667 }, 3668 }; 3669 #endif /* CONFIG_EISA */ 3670 3671 #ifdef CONFIG_TC 3672 static struct tc_device_id const dfx_tc_table[] = { 3673 { "DEC ", "PMAF-FA " }, 3674 { "DEC ", "PMAF-FD " }, 3675 { "DEC ", "PMAF-FS " }, 3676 { "DEC ", "PMAF-FU " }, 3677 { } 3678 }; 3679 MODULE_DEVICE_TABLE(tc, dfx_tc_table); 3680 3681 static struct tc_driver dfx_tc_driver = { 3682 .id_table = dfx_tc_table, 3683 .driver = { 3684 .name = "defxx", 3685 .bus = &tc_bus_type, 3686 .probe = dfx_dev_register, 3687 .remove = dfx_dev_unregister, 3688 }, 3689 }; 3690 #endif /* CONFIG_TC */ 3691 3692 static int __maybe_unused dfx_dev_register(struct device *dev) 3693 { 3694 int status; 3695 3696 status = dfx_register(dev); 3697 if (!status) 3698 get_device(dev); 3699 return status; 3700 } 3701 3702 static int __maybe_unused dfx_dev_unregister(struct device *dev) 3703 { 3704 put_device(dev); 3705 dfx_unregister(dev); 3706 return 0; 3707 } 3708 3709 3710 static int dfx_init(void) 3711 { 3712 int status; 3713 3714 status = pci_register_driver(&dfx_pci_driver); 3715 if (!status) 3716 status = eisa_driver_register(&dfx_eisa_driver); 3717 if (!status) 3718 status = tc_register_driver(&dfx_tc_driver); 3719 return status; 3720 } 3721 3722 static void dfx_cleanup(void) 3723 { 3724 tc_unregister_driver(&dfx_tc_driver); 3725 eisa_driver_unregister(&dfx_eisa_driver); 3726 pci_unregister_driver(&dfx_pci_driver); 3727 } 3728 3729 module_init(dfx_init); 3730 module_exit(dfx_cleanup); 3731 MODULE_AUTHOR("Lawrence V. Stefani"); 3732 MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver " 3733 DRV_VERSION " " DRV_RELDATE); 3734 MODULE_LICENSE("GPL"); 3735