1 /* 2 * File Name: 3 * defxx.c 4 * 5 * Copyright Information: 6 * Copyright Digital Equipment Corporation 1996. 7 * 8 * This software may be used and distributed according to the terms of 9 * the GNU General Public License, incorporated herein by reference. 10 * 11 * Abstract: 12 * A Linux device driver supporting the Digital Equipment Corporation 13 * FDDI TURBOchannel, EISA and PCI controller families. Supported 14 * adapters include: 15 * 16 * DEC FDDIcontroller/TURBOchannel (DEFTA) 17 * DEC FDDIcontroller/EISA (DEFEA) 18 * DEC FDDIcontroller/PCI (DEFPA) 19 * 20 * The original author: 21 * LVS Lawrence V. Stefani <lstefani@yahoo.com> 22 * 23 * Maintainers: 24 * macro Maciej W. Rozycki <macro@linux-mips.org> 25 * 26 * Credits: 27 * I'd like to thank Patricia Cross for helping me get started with 28 * Linux, David Davies for a lot of help upgrading and configuring 29 * my development system and for answering many OS and driver 30 * development questions, and Alan Cox for recommendations and 31 * integration help on getting FDDI support into Linux. LVS 32 * 33 * Driver Architecture: 34 * The driver architecture is largely based on previous driver work 35 * for other operating systems. The upper edge interface and 36 * functions were largely taken from existing Linux device drivers 37 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C 38 * driver. 39 * 40 * Adapter Probe - 41 * The driver scans for supported EISA adapters by reading the 42 * SLOT ID register for each EISA slot and making a match 43 * against the expected value. 44 * 45 * Bus-Specific Initialization - 46 * This driver currently supports both EISA and PCI controller 47 * families. While the custom DMA chip and FDDI logic is similar 48 * or identical, the bus logic is very different. After 49 * initialization, the only bus-specific differences is in how the 50 * driver enables and disables interrupts. Other than that, the 51 * run-time critical code behaves the same on both families. 52 * It's important to note that both adapter families are configured 53 * to I/O map, rather than memory map, the adapter registers. 54 * 55 * Driver Open/Close - 56 * In the driver open routine, the driver ISR (interrupt service 57 * routine) is registered and the adapter is brought to an 58 * operational state. In the driver close routine, the opposite 59 * occurs; the driver ISR is deregistered and the adapter is 60 * brought to a safe, but closed state. Users may use consecutive 61 * commands to bring the adapter up and down as in the following 62 * example: 63 * ifconfig fddi0 up 64 * ifconfig fddi0 down 65 * ifconfig fddi0 up 66 * 67 * Driver Shutdown - 68 * Apparently, there is no shutdown or halt routine support under 69 * Linux. This routine would be called during "reboot" or 70 * "shutdown" to allow the driver to place the adapter in a safe 71 * state before a warm reboot occurs. To be really safe, the user 72 * should close the adapter before shutdown (eg. ifconfig fddi0 down) 73 * to ensure that the adapter DMA engine is taken off-line. However, 74 * the current driver code anticipates this problem and always issues 75 * a soft reset of the adapter at the beginning of driver initialization. 76 * A future driver enhancement in this area may occur in 2.1.X where 77 * Alan indicated that a shutdown handler may be implemented. 78 * 79 * Interrupt Service Routine - 80 * The driver supports shared interrupts, so the ISR is registered for 81 * each board with the appropriate flag and the pointer to that board's 82 * device structure. This provides the context during interrupt 83 * processing to support shared interrupts and multiple boards. 84 * 85 * Interrupt enabling/disabling can occur at many levels. At the host 86 * end, you can disable system interrupts, or disable interrupts at the 87 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters 88 * have a bus-logic chip interrupt enable/disable as well as a DMA 89 * controller interrupt enable/disable. 90 * 91 * The driver currently enables and disables adapter interrupts at the 92 * bus-logic chip and assumes that Linux will take care of clearing or 93 * acknowledging any host-based interrupt chips. 94 * 95 * Control Functions - 96 * Control functions are those used to support functions such as adding 97 * or deleting multicast addresses, enabling or disabling packet 98 * reception filters, or other custom/proprietary commands. Presently, 99 * the driver supports the "get statistics", "set multicast list", and 100 * "set mac address" functions defined by Linux. A list of possible 101 * enhancements include: 102 * 103 * - Custom ioctl interface for executing port interface commands 104 * - Custom ioctl interface for adding unicast addresses to 105 * adapter CAM (to support bridge functions). 106 * - Custom ioctl interface for supporting firmware upgrades. 107 * 108 * Hardware (port interface) Support Routines - 109 * The driver function names that start with "dfx_hw_" represent 110 * low-level port interface routines that are called frequently. They 111 * include issuing a DMA or port control command to the adapter, 112 * resetting the adapter, or reading the adapter state. Since the 113 * driver initialization and run-time code must make calls into the 114 * port interface, these routines were written to be as generic and 115 * usable as possible. 116 * 117 * Receive Path - 118 * The adapter DMA engine supports a 256 entry receive descriptor block 119 * of which up to 255 entries can be used at any given time. The 120 * architecture is a standard producer, consumer, completion model in 121 * which the driver "produces" receive buffers to the adapter, the 122 * adapter "consumes" the receive buffers by DMAing incoming packet data, 123 * and the driver "completes" the receive buffers by servicing the 124 * incoming packet, then "produces" a new buffer and starts the cycle 125 * again. Receive buffers can be fragmented in up to 16 fragments 126 * (descriptor entries). For simplicity, this driver posts 127 * single-fragment receive buffers of 4608 bytes, then allocates a 128 * sk_buff, copies the data, then reposts the buffer. To reduce CPU 129 * utilization, a better approach would be to pass up the receive 130 * buffer (no extra copy) then allocate and post a replacement buffer. 131 * This is a performance enhancement that should be looked into at 132 * some point. 133 * 134 * Transmit Path - 135 * Like the receive path, the adapter DMA engine supports a 256 entry 136 * transmit descriptor block of which up to 255 entries can be used at 137 * any given time. Transmit buffers can be fragmented in up to 255 138 * fragments (descriptor entries). This driver always posts one 139 * fragment per transmit packet request. 140 * 141 * The fragment contains the entire packet from FC to end of data. 142 * Before posting the buffer to the adapter, the driver sets a three-byte 143 * packet request header (PRH) which is required by the Motorola MAC chip 144 * used on the adapters. The PRH tells the MAC the type of token to 145 * receive/send, whether or not to generate and append the CRC, whether 146 * synchronous or asynchronous framing is used, etc. Since the PRH 147 * definition is not necessarily consistent across all FDDI chipsets, 148 * the driver, rather than the common FDDI packet handler routines, 149 * sets these bytes. 150 * 151 * To reduce the amount of descriptor fetches needed per transmit request, 152 * the driver takes advantage of the fact that there are at least three 153 * bytes available before the skb->data field on the outgoing transmit 154 * request. This is guaranteed by having fddi_setup() in net_init.c set 155 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest 156 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad" 157 * bytes which we'll use to store the PRH. 158 * 159 * There's a subtle advantage to adding these pad bytes to the 160 * hard_header_len, it ensures that the data portion of the packet for 161 * an 802.2 SNAP frame is longword aligned. Other FDDI driver 162 * implementations may not need the extra padding and can start copying 163 * or DMAing directly from the FC byte which starts at skb->data. Should 164 * another driver implementation need ADDITIONAL padding, the net_init.c 165 * module should be updated and dev->hard_header_len should be increased. 166 * NOTE: To maintain the alignment on the data portion of the packet, 167 * dev->hard_header_len should always be evenly divisible by 4 and at 168 * least 24 bytes in size. 169 * 170 * Modification History: 171 * Date Name Description 172 * 16-Aug-96 LVS Created. 173 * 20-Aug-96 LVS Updated dfx_probe so that version information 174 * string is only displayed if 1 or more cards are 175 * found. Changed dfx_rcv_queue_process to copy 176 * 3 NULL bytes before FC to ensure that data is 177 * longword aligned in receive buffer. 178 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable 179 * LLC group promiscuous mode if multicast list 180 * is too large. LLC individual/group promiscuous 181 * mode is now disabled if IFF_PROMISC flag not set. 182 * dfx_xmt_queue_pkt no longer checks for NULL skb 183 * on Alan Cox recommendation. Added node address 184 * override support. 185 * 12-Sep-96 LVS Reset current address to factory address during 186 * device open. Updated transmit path to post a 187 * single fragment which includes PRH->end of data. 188 * Mar 2000 AC Did various cleanups for 2.3.x 189 * Jun 2000 jgarzik PCI and resource alloc cleanups 190 * Jul 2000 tjeerd Much cleanup and some bug fixes 191 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup 192 * Feb 2001 Skb allocation fixes 193 * Feb 2001 davej PCI enable cleanups. 194 * 04 Aug 2003 macro Converted to the DMA API. 195 * 14 Aug 2004 macro Fix device names reported. 196 * 14 Jun 2005 macro Use irqreturn_t. 197 * 23 Oct 2006 macro Big-endian host support. 198 * 14 Dec 2006 macro TURBOchannel support. 199 */ 200 201 /* Include files */ 202 #include <linux/bitops.h> 203 #include <linux/compiler.h> 204 #include <linux/delay.h> 205 #include <linux/dma-mapping.h> 206 #include <linux/eisa.h> 207 #include <linux/errno.h> 208 #include <linux/fddidevice.h> 209 #include <linux/init.h> 210 #include <linux/interrupt.h> 211 #include <linux/ioport.h> 212 #include <linux/kernel.h> 213 #include <linux/module.h> 214 #include <linux/netdevice.h> 215 #include <linux/pci.h> 216 #include <linux/skbuff.h> 217 #include <linux/slab.h> 218 #include <linux/string.h> 219 #include <linux/tc.h> 220 221 #include <asm/byteorder.h> 222 #include <asm/io.h> 223 224 #include "defxx.h" 225 226 /* Version information string should be updated prior to each new release! */ 227 #define DRV_NAME "defxx" 228 #define DRV_VERSION "v1.10" 229 #define DRV_RELDATE "2006/12/14" 230 231 static char version[] = 232 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE 233 " Lawrence V. Stefani and others\n"; 234 235 #define DYNAMIC_BUFFERS 1 236 237 #define SKBUFF_RX_COPYBREAK 200 238 /* 239 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte 240 * alignment for compatibility with old EISA boards. 241 */ 242 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128) 243 244 #ifdef CONFIG_PCI 245 #define DFX_BUS_PCI(dev) (dev->bus == &pci_bus_type) 246 #else 247 #define DFX_BUS_PCI(dev) 0 248 #endif 249 250 #ifdef CONFIG_EISA 251 #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type) 252 #else 253 #define DFX_BUS_EISA(dev) 0 254 #endif 255 256 #ifdef CONFIG_TC 257 #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type) 258 #else 259 #define DFX_BUS_TC(dev) 0 260 #endif 261 262 #ifdef CONFIG_DEFXX_MMIO 263 #define DFX_MMIO 1 264 #else 265 #define DFX_MMIO 0 266 #endif 267 268 /* Define module-wide (static) routines */ 269 270 static void dfx_bus_init(struct net_device *dev); 271 static void dfx_bus_uninit(struct net_device *dev); 272 static void dfx_bus_config_check(DFX_board_t *bp); 273 274 static int dfx_driver_init(struct net_device *dev, 275 const char *print_name, 276 resource_size_t bar_start); 277 static int dfx_adap_init(DFX_board_t *bp, int get_buffers); 278 279 static int dfx_open(struct net_device *dev); 280 static int dfx_close(struct net_device *dev); 281 282 static void dfx_int_pr_halt_id(DFX_board_t *bp); 283 static void dfx_int_type_0_process(DFX_board_t *bp); 284 static void dfx_int_common(struct net_device *dev); 285 static irqreturn_t dfx_interrupt(int irq, void *dev_id); 286 287 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev); 288 static void dfx_ctl_set_multicast_list(struct net_device *dev); 289 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr); 290 static int dfx_ctl_update_cam(DFX_board_t *bp); 291 static int dfx_ctl_update_filters(DFX_board_t *bp); 292 293 static int dfx_hw_dma_cmd_req(DFX_board_t *bp); 294 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data); 295 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type); 296 static int dfx_hw_adap_state_rd(DFX_board_t *bp); 297 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type); 298 299 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers); 300 static void dfx_rcv_queue_process(DFX_board_t *bp); 301 static void dfx_rcv_flush(DFX_board_t *bp); 302 303 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 304 struct net_device *dev); 305 static int dfx_xmt_done(DFX_board_t *bp); 306 static void dfx_xmt_flush(DFX_board_t *bp); 307 308 /* Define module-wide (static) variables */ 309 310 static struct pci_driver dfx_pci_driver; 311 static struct eisa_driver dfx_eisa_driver; 312 static struct tc_driver dfx_tc_driver; 313 314 315 /* 316 * ======================= 317 * = dfx_port_write_long = 318 * = dfx_port_read_long = 319 * ======================= 320 * 321 * Overview: 322 * Routines for reading and writing values from/to adapter 323 * 324 * Returns: 325 * None 326 * 327 * Arguments: 328 * bp - pointer to board information 329 * offset - register offset from base I/O address 330 * data - for dfx_port_write_long, this is a value to write; 331 * for dfx_port_read_long, this is a pointer to store 332 * the read value 333 * 334 * Functional Description: 335 * These routines perform the correct operation to read or write 336 * the adapter register. 337 * 338 * EISA port block base addresses are based on the slot number in which the 339 * controller is installed. For example, if the EISA controller is installed 340 * in slot 4, the port block base address is 0x4000. If the controller is 341 * installed in slot 2, the port block base address is 0x2000, and so on. 342 * This port block can be used to access PDQ, ESIC, and DEFEA on-board 343 * registers using the register offsets defined in DEFXX.H. 344 * 345 * PCI port block base addresses are assigned by the PCI BIOS or system 346 * firmware. There is one 128 byte port block which can be accessed. It 347 * allows for I/O mapping of both PDQ and PFI registers using the register 348 * offsets defined in DEFXX.H. 349 * 350 * Return Codes: 351 * None 352 * 353 * Assumptions: 354 * bp->base is a valid base I/O address for this adapter. 355 * offset is a valid register offset for this adapter. 356 * 357 * Side Effects: 358 * Rather than produce macros for these functions, these routines 359 * are defined using "inline" to ensure that the compiler will 360 * generate inline code and not waste a procedure call and return. 361 * This provides all the benefits of macros, but with the 362 * advantage of strict data type checking. 363 */ 364 365 static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data) 366 { 367 writel(data, bp->base.mem + offset); 368 mb(); 369 } 370 371 static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data) 372 { 373 outl(data, bp->base.port + offset); 374 } 375 376 static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data) 377 { 378 struct device __maybe_unused *bdev = bp->bus_dev; 379 int dfx_bus_tc = DFX_BUS_TC(bdev); 380 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 381 382 if (dfx_use_mmio) 383 dfx_writel(bp, offset, data); 384 else 385 dfx_outl(bp, offset, data); 386 } 387 388 389 static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data) 390 { 391 mb(); 392 *data = readl(bp->base.mem + offset); 393 } 394 395 static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data) 396 { 397 *data = inl(bp->base.port + offset); 398 } 399 400 static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data) 401 { 402 struct device __maybe_unused *bdev = bp->bus_dev; 403 int dfx_bus_tc = DFX_BUS_TC(bdev); 404 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 405 406 if (dfx_use_mmio) 407 dfx_readl(bp, offset, data); 408 else 409 dfx_inl(bp, offset, data); 410 } 411 412 413 /* 414 * ================ 415 * = dfx_get_bars = 416 * ================ 417 * 418 * Overview: 419 * Retrieves the address range used to access control and status 420 * registers. 421 * 422 * Returns: 423 * None 424 * 425 * Arguments: 426 * bdev - pointer to device information 427 * bar_start - pointer to store the start address 428 * bar_len - pointer to store the length of the area 429 * 430 * Assumptions: 431 * I am sure there are some. 432 * 433 * Side Effects: 434 * None 435 */ 436 static void dfx_get_bars(struct device *bdev, 437 resource_size_t *bar_start, resource_size_t *bar_len) 438 { 439 int dfx_bus_pci = DFX_BUS_PCI(bdev); 440 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 441 int dfx_bus_tc = DFX_BUS_TC(bdev); 442 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 443 444 if (dfx_bus_pci) { 445 int num = dfx_use_mmio ? 0 : 1; 446 447 *bar_start = pci_resource_start(to_pci_dev(bdev), num); 448 *bar_len = pci_resource_len(to_pci_dev(bdev), num); 449 } 450 if (dfx_bus_eisa) { 451 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 452 resource_size_t bar; 453 454 if (dfx_use_mmio) { 455 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2); 456 bar <<= 8; 457 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1); 458 bar <<= 8; 459 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0); 460 bar <<= 16; 461 *bar_start = bar; 462 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2); 463 bar <<= 8; 464 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1); 465 bar <<= 8; 466 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0); 467 bar <<= 16; 468 *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1; 469 } else { 470 *bar_start = base_addr; 471 *bar_len = PI_ESIC_K_CSR_IO_LEN; 472 } 473 } 474 if (dfx_bus_tc) { 475 *bar_start = to_tc_dev(bdev)->resource.start + 476 PI_TC_K_CSR_OFFSET; 477 *bar_len = PI_TC_K_CSR_LEN; 478 } 479 } 480 481 static const struct net_device_ops dfx_netdev_ops = { 482 .ndo_open = dfx_open, 483 .ndo_stop = dfx_close, 484 .ndo_start_xmit = dfx_xmt_queue_pkt, 485 .ndo_get_stats = dfx_ctl_get_stats, 486 .ndo_set_rx_mode = dfx_ctl_set_multicast_list, 487 .ndo_set_mac_address = dfx_ctl_set_mac_address, 488 }; 489 490 /* 491 * ================ 492 * = dfx_register = 493 * ================ 494 * 495 * Overview: 496 * Initializes a supported FDDI controller 497 * 498 * Returns: 499 * Condition code 500 * 501 * Arguments: 502 * bdev - pointer to device information 503 * 504 * Functional Description: 505 * 506 * Return Codes: 507 * 0 - This device (fddi0, fddi1, etc) configured successfully 508 * -EBUSY - Failed to get resources, or dfx_driver_init failed. 509 * 510 * Assumptions: 511 * It compiles so it should work :-( (PCI cards do :-) 512 * 513 * Side Effects: 514 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 515 * initialized and the board resources are read and stored in 516 * the device structure. 517 */ 518 static int dfx_register(struct device *bdev) 519 { 520 static int version_disp; 521 int dfx_bus_pci = DFX_BUS_PCI(bdev); 522 int dfx_bus_tc = DFX_BUS_TC(bdev); 523 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 524 const char *print_name = dev_name(bdev); 525 struct net_device *dev; 526 DFX_board_t *bp; /* board pointer */ 527 resource_size_t bar_start = 0; /* pointer to port */ 528 resource_size_t bar_len = 0; /* resource length */ 529 int alloc_size; /* total buffer size used */ 530 struct resource *region; 531 int err = 0; 532 533 if (!version_disp) { /* display version info if adapter is found */ 534 version_disp = 1; /* set display flag to TRUE so that */ 535 printk(version); /* we only display this string ONCE */ 536 } 537 538 dev = alloc_fddidev(sizeof(*bp)); 539 if (!dev) { 540 printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n", 541 print_name); 542 return -ENOMEM; 543 } 544 545 /* Enable PCI device. */ 546 if (dfx_bus_pci && pci_enable_device(to_pci_dev(bdev))) { 547 printk(KERN_ERR "%s: Cannot enable PCI device, aborting\n", 548 print_name); 549 goto err_out; 550 } 551 552 SET_NETDEV_DEV(dev, bdev); 553 554 bp = netdev_priv(dev); 555 bp->bus_dev = bdev; 556 dev_set_drvdata(bdev, dev); 557 558 dfx_get_bars(bdev, &bar_start, &bar_len); 559 560 if (dfx_use_mmio) 561 region = request_mem_region(bar_start, bar_len, print_name); 562 else 563 region = request_region(bar_start, bar_len, print_name); 564 if (!region) { 565 printk(KERN_ERR "%s: Cannot reserve I/O resource " 566 "0x%lx @ 0x%lx, aborting\n", 567 print_name, (long)bar_len, (long)bar_start); 568 err = -EBUSY; 569 goto err_out_disable; 570 } 571 572 /* Set up I/O base address. */ 573 if (dfx_use_mmio) { 574 bp->base.mem = ioremap_nocache(bar_start, bar_len); 575 if (!bp->base.mem) { 576 printk(KERN_ERR "%s: Cannot map MMIO\n", print_name); 577 err = -ENOMEM; 578 goto err_out_region; 579 } 580 } else { 581 bp->base.port = bar_start; 582 dev->base_addr = bar_start; 583 } 584 585 /* Initialize new device structure */ 586 dev->netdev_ops = &dfx_netdev_ops; 587 588 if (dfx_bus_pci) 589 pci_set_master(to_pci_dev(bdev)); 590 591 if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) { 592 err = -ENODEV; 593 goto err_out_unmap; 594 } 595 596 err = register_netdev(dev); 597 if (err) 598 goto err_out_kfree; 599 600 printk("%s: registered as %s\n", print_name, dev->name); 601 return 0; 602 603 err_out_kfree: 604 alloc_size = sizeof(PI_DESCR_BLOCK) + 605 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 606 #ifndef DYNAMIC_BUFFERS 607 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 608 #endif 609 sizeof(PI_CONSUMER_BLOCK) + 610 (PI_ALIGN_K_DESC_BLK - 1); 611 if (bp->kmalloced) 612 dma_free_coherent(bdev, alloc_size, 613 bp->kmalloced, bp->kmalloced_dma); 614 615 err_out_unmap: 616 if (dfx_use_mmio) 617 iounmap(bp->base.mem); 618 619 err_out_region: 620 if (dfx_use_mmio) 621 release_mem_region(bar_start, bar_len); 622 else 623 release_region(bar_start, bar_len); 624 625 err_out_disable: 626 if (dfx_bus_pci) 627 pci_disable_device(to_pci_dev(bdev)); 628 629 err_out: 630 free_netdev(dev); 631 return err; 632 } 633 634 635 /* 636 * ================ 637 * = dfx_bus_init = 638 * ================ 639 * 640 * Overview: 641 * Initializes the bus-specific controller logic. 642 * 643 * Returns: 644 * None 645 * 646 * Arguments: 647 * dev - pointer to device information 648 * 649 * Functional Description: 650 * Determine and save adapter IRQ in device table, 651 * then perform bus-specific logic initialization. 652 * 653 * Return Codes: 654 * None 655 * 656 * Assumptions: 657 * bp->base has already been set with the proper 658 * base I/O address for this device. 659 * 660 * Side Effects: 661 * Interrupts are enabled at the adapter bus-specific logic. 662 * Note: Interrupts at the DMA engine (PDQ chip) are not 663 * enabled yet. 664 */ 665 666 static void dfx_bus_init(struct net_device *dev) 667 { 668 DFX_board_t *bp = netdev_priv(dev); 669 struct device *bdev = bp->bus_dev; 670 int dfx_bus_pci = DFX_BUS_PCI(bdev); 671 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 672 int dfx_bus_tc = DFX_BUS_TC(bdev); 673 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 674 u8 val; 675 676 DBG_printk("In dfx_bus_init...\n"); 677 678 /* Initialize a pointer back to the net_device struct */ 679 bp->dev = dev; 680 681 /* Initialize adapter based on bus type */ 682 683 if (dfx_bus_tc) 684 dev->irq = to_tc_dev(bdev)->interrupt; 685 if (dfx_bus_eisa) { 686 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 687 688 /* Get the interrupt level from the ESIC chip. */ 689 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 690 val &= PI_CONFIG_STAT_0_M_IRQ; 691 val >>= PI_CONFIG_STAT_0_V_IRQ; 692 693 switch (val) { 694 case PI_CONFIG_STAT_0_IRQ_K_9: 695 dev->irq = 9; 696 break; 697 698 case PI_CONFIG_STAT_0_IRQ_K_10: 699 dev->irq = 10; 700 break; 701 702 case PI_CONFIG_STAT_0_IRQ_K_11: 703 dev->irq = 11; 704 break; 705 706 case PI_CONFIG_STAT_0_IRQ_K_15: 707 dev->irq = 15; 708 break; 709 } 710 711 /* 712 * Enable memory decoding (MEMCS0) and/or port decoding 713 * (IOCS1/IOCS0) as appropriate in Function Control 714 * Register. One of the port chip selects seems to be 715 * used for the Burst Holdoff register, but this bit of 716 * documentation is missing and as yet it has not been 717 * determined which of the two. This is also the reason 718 * the size of the decoded port range is twice as large 719 * as one required by the PDQ. 720 */ 721 722 /* Set the decode range of the board. */ 723 val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT); 724 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val); 725 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0); 726 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val); 727 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0); 728 val = PI_ESIC_K_CSR_IO_LEN - 1; 729 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff); 730 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff); 731 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff); 732 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff); 733 734 /* Enable the decoders. */ 735 val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0; 736 if (dfx_use_mmio) 737 val |= PI_FUNCTION_CNTRL_M_MEMCS0; 738 outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val); 739 740 /* 741 * Enable access to the rest of the module 742 * (including PDQ and packet memory). 743 */ 744 val = PI_SLOT_CNTRL_M_ENB; 745 outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val); 746 747 /* 748 * Map PDQ registers into memory or port space. This is 749 * done with a bit in the Burst Holdoff register. 750 */ 751 val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); 752 if (dfx_use_mmio) 753 val |= PI_BURST_HOLDOFF_V_MEM_MAP; 754 else 755 val &= ~PI_BURST_HOLDOFF_V_MEM_MAP; 756 outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val); 757 758 /* Enable interrupts at EISA bus interface chip (ESIC) */ 759 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 760 val |= PI_CONFIG_STAT_0_M_INT_ENB; 761 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 762 } 763 if (dfx_bus_pci) { 764 struct pci_dev *pdev = to_pci_dev(bdev); 765 766 /* Get the interrupt level from the PCI Configuration Table */ 767 768 dev->irq = pdev->irq; 769 770 /* Check Latency Timer and set if less than minimal */ 771 772 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); 773 if (val < PFI_K_LAT_TIMER_MIN) { 774 val = PFI_K_LAT_TIMER_DEF; 775 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); 776 } 777 778 /* Enable interrupts at PCI bus interface chip (PFI) */ 779 val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB; 780 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val); 781 } 782 } 783 784 /* 785 * ================== 786 * = dfx_bus_uninit = 787 * ================== 788 * 789 * Overview: 790 * Uninitializes the bus-specific controller logic. 791 * 792 * Returns: 793 * None 794 * 795 * Arguments: 796 * dev - pointer to device information 797 * 798 * Functional Description: 799 * Perform bus-specific logic uninitialization. 800 * 801 * Return Codes: 802 * None 803 * 804 * Assumptions: 805 * bp->base has already been set with the proper 806 * base I/O address for this device. 807 * 808 * Side Effects: 809 * Interrupts are disabled at the adapter bus-specific logic. 810 */ 811 812 static void dfx_bus_uninit(struct net_device *dev) 813 { 814 DFX_board_t *bp = netdev_priv(dev); 815 struct device *bdev = bp->bus_dev; 816 int dfx_bus_pci = DFX_BUS_PCI(bdev); 817 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 818 u8 val; 819 820 DBG_printk("In dfx_bus_uninit...\n"); 821 822 /* Uninitialize adapter based on bus type */ 823 824 if (dfx_bus_eisa) { 825 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 826 827 /* Disable interrupts at EISA bus interface chip (ESIC) */ 828 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 829 val &= ~PI_CONFIG_STAT_0_M_INT_ENB; 830 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 831 } 832 if (dfx_bus_pci) { 833 /* Disable interrupts at PCI bus interface chip (PFI) */ 834 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0); 835 } 836 } 837 838 839 /* 840 * ======================== 841 * = dfx_bus_config_check = 842 * ======================== 843 * 844 * Overview: 845 * Checks the configuration (burst size, full-duplex, etc.) If any parameters 846 * are illegal, then this routine will set new defaults. 847 * 848 * Returns: 849 * None 850 * 851 * Arguments: 852 * bp - pointer to board information 853 * 854 * Functional Description: 855 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later 856 * PDQ, and all FDDI PCI controllers, all values are legal. 857 * 858 * Return Codes: 859 * None 860 * 861 * Assumptions: 862 * dfx_adap_init has NOT been called yet so burst size and other items have 863 * not been set. 864 * 865 * Side Effects: 866 * None 867 */ 868 869 static void dfx_bus_config_check(DFX_board_t *bp) 870 { 871 struct device __maybe_unused *bdev = bp->bus_dev; 872 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 873 int status; /* return code from adapter port control call */ 874 u32 host_data; /* LW data returned from port control call */ 875 876 DBG_printk("In dfx_bus_config_check...\n"); 877 878 /* Configuration check only valid for EISA adapter */ 879 880 if (dfx_bus_eisa) { 881 /* 882 * First check if revision 2 EISA controller. Rev. 1 cards used 883 * PDQ revision B, so no workaround needed in this case. Rev. 3 884 * cards used PDQ revision E, so no workaround needed in this 885 * case, either. Only Rev. 2 cards used either Rev. D or E 886 * chips, so we must verify the chip revision on Rev. 2 cards. 887 */ 888 if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) { 889 /* 890 * Revision 2 FDDI EISA controller found, 891 * so let's check PDQ revision of adapter. 892 */ 893 status = dfx_hw_port_ctrl_req(bp, 894 PI_PCTRL_M_SUB_CMD, 895 PI_SUB_CMD_K_PDQ_REV_GET, 896 0, 897 &host_data); 898 if ((status != DFX_K_SUCCESS) || (host_data == 2)) 899 { 900 /* 901 * Either we couldn't determine the PDQ revision, or 902 * we determined that it is at revision D. In either case, 903 * we need to implement the workaround. 904 */ 905 906 /* Ensure that the burst size is set to 8 longwords or less */ 907 908 switch (bp->burst_size) 909 { 910 case PI_PDATA_B_DMA_BURST_SIZE_32: 911 case PI_PDATA_B_DMA_BURST_SIZE_16: 912 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8; 913 break; 914 915 default: 916 break; 917 } 918 919 /* Ensure that full-duplex mode is not enabled */ 920 921 bp->full_duplex_enb = PI_SNMP_K_FALSE; 922 } 923 } 924 } 925 } 926 927 928 /* 929 * =================== 930 * = dfx_driver_init = 931 * =================== 932 * 933 * Overview: 934 * Initializes remaining adapter board structure information 935 * and makes sure adapter is in a safe state prior to dfx_open(). 936 * 937 * Returns: 938 * Condition code 939 * 940 * Arguments: 941 * dev - pointer to device information 942 * print_name - printable device name 943 * 944 * Functional Description: 945 * This function allocates additional resources such as the host memory 946 * blocks needed by the adapter (eg. descriptor and consumer blocks). 947 * Remaining bus initialization steps are also completed. The adapter 948 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS 949 * must call dfx_open() to open the adapter and bring it on-line. 950 * 951 * Return Codes: 952 * DFX_K_SUCCESS - initialization succeeded 953 * DFX_K_FAILURE - initialization failed - could not allocate memory 954 * or read adapter MAC address 955 * 956 * Assumptions: 957 * Memory allocated from pci_alloc_consistent() call is physically 958 * contiguous, locked memory. 959 * 960 * Side Effects: 961 * Adapter is reset and should be in DMA_UNAVAILABLE state before 962 * returning from this routine. 963 */ 964 965 static int dfx_driver_init(struct net_device *dev, const char *print_name, 966 resource_size_t bar_start) 967 { 968 DFX_board_t *bp = netdev_priv(dev); 969 struct device *bdev = bp->bus_dev; 970 int dfx_bus_pci = DFX_BUS_PCI(bdev); 971 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 972 int dfx_bus_tc = DFX_BUS_TC(bdev); 973 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 974 int alloc_size; /* total buffer size needed */ 975 char *top_v, *curr_v; /* virtual addrs into memory block */ 976 dma_addr_t top_p, curr_p; /* physical addrs into memory block */ 977 u32 data; /* host data register value */ 978 __le32 le32; 979 char *board_name = NULL; 980 981 DBG_printk("In dfx_driver_init...\n"); 982 983 /* Initialize bus-specific hardware registers */ 984 985 dfx_bus_init(dev); 986 987 /* 988 * Initialize default values for configurable parameters 989 * 990 * Note: All of these parameters are ones that a user may 991 * want to customize. It'd be nice to break these 992 * out into Space.c or someplace else that's more 993 * accessible/understandable than this file. 994 */ 995 996 bp->full_duplex_enb = PI_SNMP_K_FALSE; 997 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */ 998 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF; 999 bp->rcv_bufs_to_post = RCV_BUFS_DEF; 1000 1001 /* 1002 * Ensure that HW configuration is OK 1003 * 1004 * Note: Depending on the hardware revision, we may need to modify 1005 * some of the configurable parameters to workaround hardware 1006 * limitations. We'll perform this configuration check AFTER 1007 * setting the parameters to their default values. 1008 */ 1009 1010 dfx_bus_config_check(bp); 1011 1012 /* Disable PDQ interrupts first */ 1013 1014 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1015 1016 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1017 1018 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1019 1020 /* Read the factory MAC address from the adapter then save it */ 1021 1022 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, 1023 &data) != DFX_K_SUCCESS) { 1024 printk("%s: Could not read adapter factory MAC address!\n", 1025 print_name); 1026 return DFX_K_FAILURE; 1027 } 1028 le32 = cpu_to_le32(data); 1029 memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32)); 1030 1031 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, 1032 &data) != DFX_K_SUCCESS) { 1033 printk("%s: Could not read adapter factory MAC address!\n", 1034 print_name); 1035 return DFX_K_FAILURE; 1036 } 1037 le32 = cpu_to_le32(data); 1038 memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16)); 1039 1040 /* 1041 * Set current address to factory address 1042 * 1043 * Note: Node address override support is handled through 1044 * dfx_ctl_set_mac_address. 1045 */ 1046 1047 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1048 if (dfx_bus_tc) 1049 board_name = "DEFTA"; 1050 if (dfx_bus_eisa) 1051 board_name = "DEFEA"; 1052 if (dfx_bus_pci) 1053 board_name = "DEFPA"; 1054 pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, Hardware addr = %pMF\n", 1055 print_name, board_name, dfx_use_mmio ? "" : "I/O ", 1056 (long long)bar_start, dev->irq, dev->dev_addr); 1057 1058 /* 1059 * Get memory for descriptor block, consumer block, and other buffers 1060 * that need to be DMA read or written to by the adapter. 1061 */ 1062 1063 alloc_size = sizeof(PI_DESCR_BLOCK) + 1064 PI_CMD_REQ_K_SIZE_MAX + 1065 PI_CMD_RSP_K_SIZE_MAX + 1066 #ifndef DYNAMIC_BUFFERS 1067 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 1068 #endif 1069 sizeof(PI_CONSUMER_BLOCK) + 1070 (PI_ALIGN_K_DESC_BLK - 1); 1071 bp->kmalloced = top_v = dma_alloc_coherent(bp->bus_dev, alloc_size, 1072 &bp->kmalloced_dma, 1073 GFP_ATOMIC); 1074 if (top_v == NULL) { 1075 printk("%s: Could not allocate memory for host buffers " 1076 "and structures!\n", print_name); 1077 return DFX_K_FAILURE; 1078 } 1079 memset(top_v, 0, alloc_size); /* zero out memory before continuing */ 1080 top_p = bp->kmalloced_dma; /* get physical address of buffer */ 1081 1082 /* 1083 * To guarantee the 8K alignment required for the descriptor block, 8K - 1 1084 * plus the amount of memory needed was allocated. The physical address 1085 * is now 8K aligned. By carving up the memory in a specific order, 1086 * we'll guarantee the alignment requirements for all other structures. 1087 * 1088 * Note: If the assumptions change regarding the non-paged, non-cached, 1089 * physically contiguous nature of the memory block or the address 1090 * alignments, then we'll need to implement a different algorithm 1091 * for allocating the needed memory. 1092 */ 1093 1094 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); 1095 curr_v = top_v + (curr_p - top_p); 1096 1097 /* Reserve space for descriptor block */ 1098 1099 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v; 1100 bp->descr_block_phys = curr_p; 1101 curr_v += sizeof(PI_DESCR_BLOCK); 1102 curr_p += sizeof(PI_DESCR_BLOCK); 1103 1104 /* Reserve space for command request buffer */ 1105 1106 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v; 1107 bp->cmd_req_phys = curr_p; 1108 curr_v += PI_CMD_REQ_K_SIZE_MAX; 1109 curr_p += PI_CMD_REQ_K_SIZE_MAX; 1110 1111 /* Reserve space for command response buffer */ 1112 1113 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v; 1114 bp->cmd_rsp_phys = curr_p; 1115 curr_v += PI_CMD_RSP_K_SIZE_MAX; 1116 curr_p += PI_CMD_RSP_K_SIZE_MAX; 1117 1118 /* Reserve space for the LLC host receive queue buffers */ 1119 1120 bp->rcv_block_virt = curr_v; 1121 bp->rcv_block_phys = curr_p; 1122 1123 #ifndef DYNAMIC_BUFFERS 1124 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1125 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1126 #endif 1127 1128 /* Reserve space for the consumer block */ 1129 1130 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v; 1131 bp->cons_block_phys = curr_p; 1132 1133 /* Display virtual and physical addresses if debug driver */ 1134 1135 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", 1136 print_name, 1137 (long)bp->descr_block_virt, bp->descr_block_phys); 1138 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", 1139 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys); 1140 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", 1141 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); 1142 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", 1143 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys); 1144 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", 1145 print_name, (long)bp->cons_block_virt, bp->cons_block_phys); 1146 1147 return DFX_K_SUCCESS; 1148 } 1149 1150 1151 /* 1152 * ================= 1153 * = dfx_adap_init = 1154 * ================= 1155 * 1156 * Overview: 1157 * Brings the adapter to the link avail/link unavailable state. 1158 * 1159 * Returns: 1160 * Condition code 1161 * 1162 * Arguments: 1163 * bp - pointer to board information 1164 * get_buffers - non-zero if buffers to be allocated 1165 * 1166 * Functional Description: 1167 * Issues the low-level firmware/hardware calls necessary to bring 1168 * the adapter up, or to properly reset and restore adapter during 1169 * run-time. 1170 * 1171 * Return Codes: 1172 * DFX_K_SUCCESS - Adapter brought up successfully 1173 * DFX_K_FAILURE - Adapter initialization failed 1174 * 1175 * Assumptions: 1176 * bp->reset_type should be set to a valid reset type value before 1177 * calling this routine. 1178 * 1179 * Side Effects: 1180 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1181 * upon a successful return of this routine. 1182 */ 1183 1184 static int dfx_adap_init(DFX_board_t *bp, int get_buffers) 1185 { 1186 DBG_printk("In dfx_adap_init...\n"); 1187 1188 /* Disable PDQ interrupts first */ 1189 1190 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1191 1192 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1193 1194 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS) 1195 { 1196 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name); 1197 return DFX_K_FAILURE; 1198 } 1199 1200 /* 1201 * When the PDQ is reset, some false Type 0 interrupts may be pending, 1202 * so we'll acknowledge all Type 0 interrupts now before continuing. 1203 */ 1204 1205 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0); 1206 1207 /* 1208 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state 1209 * 1210 * Note: We only need to clear host copies of these registers. The PDQ reset 1211 * takes care of the on-board register values. 1212 */ 1213 1214 bp->cmd_req_reg.lword = 0; 1215 bp->cmd_rsp_reg.lword = 0; 1216 bp->rcv_xmt_reg.lword = 0; 1217 1218 /* Clear consumer block before going to DMA_AVAILABLE state */ 1219 1220 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1221 1222 /* Initialize the DMA Burst Size */ 1223 1224 if (dfx_hw_port_ctrl_req(bp, 1225 PI_PCTRL_M_SUB_CMD, 1226 PI_SUB_CMD_K_BURST_SIZE_SET, 1227 bp->burst_size, 1228 NULL) != DFX_K_SUCCESS) 1229 { 1230 printk("%s: Could not set adapter burst size!\n", bp->dev->name); 1231 return DFX_K_FAILURE; 1232 } 1233 1234 /* 1235 * Set base address of Consumer Block 1236 * 1237 * Assumption: 32-bit physical address of consumer block is 64 byte 1238 * aligned. That is, bits 0-5 of the address must be zero. 1239 */ 1240 1241 if (dfx_hw_port_ctrl_req(bp, 1242 PI_PCTRL_M_CONS_BLOCK, 1243 bp->cons_block_phys, 1244 0, 1245 NULL) != DFX_K_SUCCESS) 1246 { 1247 printk("%s: Could not set consumer block address!\n", bp->dev->name); 1248 return DFX_K_FAILURE; 1249 } 1250 1251 /* 1252 * Set the base address of Descriptor Block and bring adapter 1253 * to DMA_AVAILABLE state. 1254 * 1255 * Note: We also set the literal and data swapping requirements 1256 * in this command. 1257 * 1258 * Assumption: 32-bit physical address of descriptor block 1259 * is 8Kbyte aligned. 1260 */ 1261 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT, 1262 (u32)(bp->descr_block_phys | 1263 PI_PDATA_A_INIT_M_BSWAP_INIT), 1264 0, NULL) != DFX_K_SUCCESS) { 1265 printk("%s: Could not set descriptor block address!\n", 1266 bp->dev->name); 1267 return DFX_K_FAILURE; 1268 } 1269 1270 /* Set transmit flush timeout value */ 1271 1272 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET; 1273 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME; 1274 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */ 1275 bp->cmd_req_virt->char_set.item[0].item_index = 0; 1276 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL; 1277 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1278 { 1279 printk("%s: DMA command request failed!\n", bp->dev->name); 1280 return DFX_K_FAILURE; 1281 } 1282 1283 /* Set the initial values for eFDXEnable and MACTReq MIB objects */ 1284 1285 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET; 1286 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS; 1287 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb; 1288 bp->cmd_req_virt->snmp_set.item[0].item_index = 0; 1289 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ; 1290 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt; 1291 bp->cmd_req_virt->snmp_set.item[1].item_index = 0; 1292 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL; 1293 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1294 { 1295 printk("%s: DMA command request failed!\n", bp->dev->name); 1296 return DFX_K_FAILURE; 1297 } 1298 1299 /* Initialize adapter CAM */ 1300 1301 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 1302 { 1303 printk("%s: Adapter CAM update failed!\n", bp->dev->name); 1304 return DFX_K_FAILURE; 1305 } 1306 1307 /* Initialize adapter filters */ 1308 1309 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 1310 { 1311 printk("%s: Adapter filters update failed!\n", bp->dev->name); 1312 return DFX_K_FAILURE; 1313 } 1314 1315 /* 1316 * Remove any existing dynamic buffers (i.e. if the adapter is being 1317 * reinitialized) 1318 */ 1319 1320 if (get_buffers) 1321 dfx_rcv_flush(bp); 1322 1323 /* Initialize receive descriptor block and produce buffers */ 1324 1325 if (dfx_rcv_init(bp, get_buffers)) 1326 { 1327 printk("%s: Receive buffer allocation failed\n", bp->dev->name); 1328 if (get_buffers) 1329 dfx_rcv_flush(bp); 1330 return DFX_K_FAILURE; 1331 } 1332 1333 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */ 1334 1335 bp->cmd_req_virt->cmd_type = PI_CMD_K_START; 1336 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1337 { 1338 printk("%s: Start command failed\n", bp->dev->name); 1339 if (get_buffers) 1340 dfx_rcv_flush(bp); 1341 return DFX_K_FAILURE; 1342 } 1343 1344 /* Initialization succeeded, reenable PDQ interrupts */ 1345 1346 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS); 1347 return DFX_K_SUCCESS; 1348 } 1349 1350 1351 /* 1352 * ============ 1353 * = dfx_open = 1354 * ============ 1355 * 1356 * Overview: 1357 * Opens the adapter 1358 * 1359 * Returns: 1360 * Condition code 1361 * 1362 * Arguments: 1363 * dev - pointer to device information 1364 * 1365 * Functional Description: 1366 * This function brings the adapter to an operational state. 1367 * 1368 * Return Codes: 1369 * 0 - Adapter was successfully opened 1370 * -EAGAIN - Could not register IRQ or adapter initialization failed 1371 * 1372 * Assumptions: 1373 * This routine should only be called for a device that was 1374 * initialized successfully. 1375 * 1376 * Side Effects: 1377 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1378 * if the open is successful. 1379 */ 1380 1381 static int dfx_open(struct net_device *dev) 1382 { 1383 DFX_board_t *bp = netdev_priv(dev); 1384 int ret; 1385 1386 DBG_printk("In dfx_open...\n"); 1387 1388 /* Register IRQ - support shared interrupts by passing device ptr */ 1389 1390 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, 1391 dev); 1392 if (ret) { 1393 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); 1394 return ret; 1395 } 1396 1397 /* 1398 * Set current address to factory MAC address 1399 * 1400 * Note: We've already done this step in dfx_driver_init. 1401 * However, it's possible that a user has set a node 1402 * address override, then closed and reopened the 1403 * adapter. Unless we reset the device address field 1404 * now, we'll continue to use the existing modified 1405 * address. 1406 */ 1407 1408 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1409 1410 /* Clear local unicast/multicast address tables and counts */ 1411 1412 memset(bp->uc_table, 0, sizeof(bp->uc_table)); 1413 memset(bp->mc_table, 0, sizeof(bp->mc_table)); 1414 bp->uc_count = 0; 1415 bp->mc_count = 0; 1416 1417 /* Disable promiscuous filter settings */ 1418 1419 bp->ind_group_prom = PI_FSTATE_K_BLOCK; 1420 bp->group_prom = PI_FSTATE_K_BLOCK; 1421 1422 spin_lock_init(&bp->lock); 1423 1424 /* Reset and initialize adapter */ 1425 1426 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */ 1427 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS) 1428 { 1429 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name); 1430 free_irq(dev->irq, dev); 1431 return -EAGAIN; 1432 } 1433 1434 /* Set device structure info */ 1435 netif_start_queue(dev); 1436 return 0; 1437 } 1438 1439 1440 /* 1441 * ============= 1442 * = dfx_close = 1443 * ============= 1444 * 1445 * Overview: 1446 * Closes the device/module. 1447 * 1448 * Returns: 1449 * Condition code 1450 * 1451 * Arguments: 1452 * dev - pointer to device information 1453 * 1454 * Functional Description: 1455 * This routine closes the adapter and brings it to a safe state. 1456 * The interrupt service routine is deregistered with the OS. 1457 * The adapter can be opened again with another call to dfx_open(). 1458 * 1459 * Return Codes: 1460 * Always return 0. 1461 * 1462 * Assumptions: 1463 * No further requests for this adapter are made after this routine is 1464 * called. dfx_open() can be called to reset and reinitialize the 1465 * adapter. 1466 * 1467 * Side Effects: 1468 * Adapter should be in DMA_UNAVAILABLE state upon completion of this 1469 * routine. 1470 */ 1471 1472 static int dfx_close(struct net_device *dev) 1473 { 1474 DFX_board_t *bp = netdev_priv(dev); 1475 1476 DBG_printk("In dfx_close...\n"); 1477 1478 /* Disable PDQ interrupts first */ 1479 1480 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1481 1482 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1483 1484 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1485 1486 /* 1487 * Flush any pending transmit buffers 1488 * 1489 * Note: It's important that we flush the transmit buffers 1490 * BEFORE we clear our copy of the Type 2 register. 1491 * Otherwise, we'll have no idea how many buffers 1492 * we need to free. 1493 */ 1494 1495 dfx_xmt_flush(bp); 1496 1497 /* 1498 * Clear Type 1 and Type 2 registers after adapter reset 1499 * 1500 * Note: Even though we're closing the adapter, it's 1501 * possible that an interrupt will occur after 1502 * dfx_close is called. Without some assurance to 1503 * the contrary we want to make sure that we don't 1504 * process receive and transmit LLC frames and update 1505 * the Type 2 register with bad information. 1506 */ 1507 1508 bp->cmd_req_reg.lword = 0; 1509 bp->cmd_rsp_reg.lword = 0; 1510 bp->rcv_xmt_reg.lword = 0; 1511 1512 /* Clear consumer block for the same reason given above */ 1513 1514 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1515 1516 /* Release all dynamically allocate skb in the receive ring. */ 1517 1518 dfx_rcv_flush(bp); 1519 1520 /* Clear device structure flags */ 1521 1522 netif_stop_queue(dev); 1523 1524 /* Deregister (free) IRQ */ 1525 1526 free_irq(dev->irq, dev); 1527 1528 return 0; 1529 } 1530 1531 1532 /* 1533 * ====================== 1534 * = dfx_int_pr_halt_id = 1535 * ====================== 1536 * 1537 * Overview: 1538 * Displays halt id's in string form. 1539 * 1540 * Returns: 1541 * None 1542 * 1543 * Arguments: 1544 * bp - pointer to board information 1545 * 1546 * Functional Description: 1547 * Determine current halt id and display appropriate string. 1548 * 1549 * Return Codes: 1550 * None 1551 * 1552 * Assumptions: 1553 * None 1554 * 1555 * Side Effects: 1556 * None 1557 */ 1558 1559 static void dfx_int_pr_halt_id(DFX_board_t *bp) 1560 { 1561 PI_UINT32 port_status; /* PDQ port status register value */ 1562 PI_UINT32 halt_id; /* PDQ port status halt ID */ 1563 1564 /* Read the latest port status */ 1565 1566 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1567 1568 /* Display halt state transition information */ 1569 1570 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID; 1571 switch (halt_id) 1572 { 1573 case PI_HALT_ID_K_SELFTEST_TIMEOUT: 1574 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name); 1575 break; 1576 1577 case PI_HALT_ID_K_PARITY_ERROR: 1578 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name); 1579 break; 1580 1581 case PI_HALT_ID_K_HOST_DIR_HALT: 1582 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name); 1583 break; 1584 1585 case PI_HALT_ID_K_SW_FAULT: 1586 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name); 1587 break; 1588 1589 case PI_HALT_ID_K_HW_FAULT: 1590 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name); 1591 break; 1592 1593 case PI_HALT_ID_K_PC_TRACE: 1594 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name); 1595 break; 1596 1597 case PI_HALT_ID_K_DMA_ERROR: 1598 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name); 1599 break; 1600 1601 case PI_HALT_ID_K_IMAGE_CRC_ERROR: 1602 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name); 1603 break; 1604 1605 case PI_HALT_ID_K_BUS_EXCEPTION: 1606 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name); 1607 break; 1608 1609 default: 1610 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id); 1611 break; 1612 } 1613 } 1614 1615 1616 /* 1617 * ========================== 1618 * = dfx_int_type_0_process = 1619 * ========================== 1620 * 1621 * Overview: 1622 * Processes Type 0 interrupts. 1623 * 1624 * Returns: 1625 * None 1626 * 1627 * Arguments: 1628 * bp - pointer to board information 1629 * 1630 * Functional Description: 1631 * Processes all enabled Type 0 interrupts. If the reason for the interrupt 1632 * is a serious fault on the adapter, then an error message is displayed 1633 * and the adapter is reset. 1634 * 1635 * One tricky potential timing window is the rapid succession of "link avail" 1636 * "link unavail" state change interrupts. The acknowledgement of the Type 0 1637 * interrupt must be done before reading the state from the Port Status 1638 * register. This is true because a state change could occur after reading 1639 * the data, but before acknowledging the interrupt. If this state change 1640 * does happen, it would be lost because the driver is using the old state, 1641 * and it will never know about the new state because it subsequently 1642 * acknowledges the state change interrupt. 1643 * 1644 * INCORRECT CORRECT 1645 * read type 0 int reasons read type 0 int reasons 1646 * read adapter state ack type 0 interrupts 1647 * ack type 0 interrupts read adapter state 1648 * ... process interrupt ... ... process interrupt ... 1649 * 1650 * Return Codes: 1651 * None 1652 * 1653 * Assumptions: 1654 * None 1655 * 1656 * Side Effects: 1657 * An adapter reset may occur if the adapter has any Type 0 error interrupts 1658 * or if the port status indicates that the adapter is halted. The driver 1659 * is responsible for reinitializing the adapter with the current CAM 1660 * contents and adapter filter settings. 1661 */ 1662 1663 static void dfx_int_type_0_process(DFX_board_t *bp) 1664 1665 { 1666 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */ 1667 PI_UINT32 state; /* current adap state (from port status) */ 1668 1669 /* 1670 * Read host interrupt Type 0 register to determine which Type 0 1671 * interrupts are pending. Immediately write it back out to clear 1672 * those interrupts. 1673 */ 1674 1675 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status); 1676 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status); 1677 1678 /* Check for Type 0 error interrupts */ 1679 1680 if (type_0_status & (PI_TYPE_0_STAT_M_NXM | 1681 PI_TYPE_0_STAT_M_PM_PAR_ERR | 1682 PI_TYPE_0_STAT_M_BUS_PAR_ERR)) 1683 { 1684 /* Check for Non-Existent Memory error */ 1685 1686 if (type_0_status & PI_TYPE_0_STAT_M_NXM) 1687 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name); 1688 1689 /* Check for Packet Memory Parity error */ 1690 1691 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR) 1692 printk("%s: Packet Memory Parity Error\n", bp->dev->name); 1693 1694 /* Check for Host Bus Parity error */ 1695 1696 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR) 1697 printk("%s: Host Bus Parity Error\n", bp->dev->name); 1698 1699 /* Reset adapter and bring it back on-line */ 1700 1701 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1702 bp->reset_type = 0; /* rerun on-board diagnostics */ 1703 printk("%s: Resetting adapter...\n", bp->dev->name); 1704 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1705 { 1706 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1707 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1708 return; 1709 } 1710 printk("%s: Adapter reset successful!\n", bp->dev->name); 1711 return; 1712 } 1713 1714 /* Check for transmit flush interrupt */ 1715 1716 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH) 1717 { 1718 /* Flush any pending xmt's and acknowledge the flush interrupt */ 1719 1720 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1721 dfx_xmt_flush(bp); /* flush any outstanding packets */ 1722 (void) dfx_hw_port_ctrl_req(bp, 1723 PI_PCTRL_M_XMT_DATA_FLUSH_DONE, 1724 0, 1725 0, 1726 NULL); 1727 } 1728 1729 /* Check for adapter state change */ 1730 1731 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE) 1732 { 1733 /* Get latest adapter state */ 1734 1735 state = dfx_hw_adap_state_rd(bp); /* get adapter state */ 1736 if (state == PI_STATE_K_HALTED) 1737 { 1738 /* 1739 * Adapter has transitioned to HALTED state, try to reset 1740 * adapter to bring it back on-line. If reset fails, 1741 * leave the adapter in the broken state. 1742 */ 1743 1744 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name); 1745 dfx_int_pr_halt_id(bp); /* display halt id as string */ 1746 1747 /* Reset adapter and bring it back on-line */ 1748 1749 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1750 bp->reset_type = 0; /* rerun on-board diagnostics */ 1751 printk("%s: Resetting adapter...\n", bp->dev->name); 1752 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1753 { 1754 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1755 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1756 return; 1757 } 1758 printk("%s: Adapter reset successful!\n", bp->dev->name); 1759 } 1760 else if (state == PI_STATE_K_LINK_AVAIL) 1761 { 1762 bp->link_available = PI_K_TRUE; /* set link available flag */ 1763 } 1764 } 1765 } 1766 1767 1768 /* 1769 * ================== 1770 * = dfx_int_common = 1771 * ================== 1772 * 1773 * Overview: 1774 * Interrupt service routine (ISR) 1775 * 1776 * Returns: 1777 * None 1778 * 1779 * Arguments: 1780 * bp - pointer to board information 1781 * 1782 * Functional Description: 1783 * This is the ISR which processes incoming adapter interrupts. 1784 * 1785 * Return Codes: 1786 * None 1787 * 1788 * Assumptions: 1789 * This routine assumes PDQ interrupts have not been disabled. 1790 * When interrupts are disabled at the PDQ, the Port Status register 1791 * is automatically cleared. This routine uses the Port Status 1792 * register value to determine whether a Type 0 interrupt occurred, 1793 * so it's important that adapter interrupts are not normally 1794 * enabled/disabled at the PDQ. 1795 * 1796 * It's vital that this routine is NOT reentered for the 1797 * same board and that the OS is not in another section of 1798 * code (eg. dfx_xmt_queue_pkt) for the same board on a 1799 * different thread. 1800 * 1801 * Side Effects: 1802 * Pending interrupts are serviced. Depending on the type of 1803 * interrupt, acknowledging and clearing the interrupt at the 1804 * PDQ involves writing a register to clear the interrupt bit 1805 * or updating completion indices. 1806 */ 1807 1808 static void dfx_int_common(struct net_device *dev) 1809 { 1810 DFX_board_t *bp = netdev_priv(dev); 1811 PI_UINT32 port_status; /* Port Status register */ 1812 1813 /* Process xmt interrupts - frequent case, so always call this routine */ 1814 1815 if(dfx_xmt_done(bp)) /* free consumed xmt packets */ 1816 netif_wake_queue(dev); 1817 1818 /* Process rcv interrupts - frequent case, so always call this routine */ 1819 1820 dfx_rcv_queue_process(bp); /* service received LLC frames */ 1821 1822 /* 1823 * Transmit and receive producer and completion indices are updated on the 1824 * adapter by writing to the Type 2 Producer register. Since the frequent 1825 * case is that we'll be processing either LLC transmit or receive buffers, 1826 * we'll optimize I/O writes by doing a single register write here. 1827 */ 1828 1829 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 1830 1831 /* Read PDQ Port Status register to find out which interrupts need processing */ 1832 1833 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1834 1835 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */ 1836 1837 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING) 1838 dfx_int_type_0_process(bp); /* process Type 0 interrupts */ 1839 } 1840 1841 1842 /* 1843 * ================= 1844 * = dfx_interrupt = 1845 * ================= 1846 * 1847 * Overview: 1848 * Interrupt processing routine 1849 * 1850 * Returns: 1851 * Whether a valid interrupt was seen. 1852 * 1853 * Arguments: 1854 * irq - interrupt vector 1855 * dev_id - pointer to device information 1856 * 1857 * Functional Description: 1858 * This routine calls the interrupt processing routine for this adapter. It 1859 * disables and reenables adapter interrupts, as appropriate. We can support 1860 * shared interrupts since the incoming dev_id pointer provides our device 1861 * structure context. 1862 * 1863 * Return Codes: 1864 * IRQ_HANDLED - an IRQ was handled. 1865 * IRQ_NONE - no IRQ was handled. 1866 * 1867 * Assumptions: 1868 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC 1869 * on Intel-based systems) is done by the operating system outside this 1870 * routine. 1871 * 1872 * System interrupts are enabled through this call. 1873 * 1874 * Side Effects: 1875 * Interrupts are disabled, then reenabled at the adapter. 1876 */ 1877 1878 static irqreturn_t dfx_interrupt(int irq, void *dev_id) 1879 { 1880 struct net_device *dev = dev_id; 1881 DFX_board_t *bp = netdev_priv(dev); 1882 struct device *bdev = bp->bus_dev; 1883 int dfx_bus_pci = DFX_BUS_PCI(bdev); 1884 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 1885 int dfx_bus_tc = DFX_BUS_TC(bdev); 1886 1887 /* Service adapter interrupts */ 1888 1889 if (dfx_bus_pci) { 1890 u32 status; 1891 1892 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status); 1893 if (!(status & PFI_STATUS_M_PDQ_INT)) 1894 return IRQ_NONE; 1895 1896 spin_lock(&bp->lock); 1897 1898 /* Disable PDQ-PFI interrupts at PFI */ 1899 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1900 PFI_MODE_M_DMA_ENB); 1901 1902 /* Call interrupt service routine for this adapter */ 1903 dfx_int_common(dev); 1904 1905 /* Clear PDQ interrupt status bit and reenable interrupts */ 1906 dfx_port_write_long(bp, PFI_K_REG_STATUS, 1907 PFI_STATUS_M_PDQ_INT); 1908 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1909 (PFI_MODE_M_PDQ_INT_ENB | 1910 PFI_MODE_M_DMA_ENB)); 1911 1912 spin_unlock(&bp->lock); 1913 } 1914 if (dfx_bus_eisa) { 1915 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 1916 u8 status; 1917 1918 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1919 if (!(status & PI_CONFIG_STAT_0_M_PEND)) 1920 return IRQ_NONE; 1921 1922 spin_lock(&bp->lock); 1923 1924 /* Disable interrupts at the ESIC */ 1925 status &= ~PI_CONFIG_STAT_0_M_INT_ENB; 1926 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1927 1928 /* Call interrupt service routine for this adapter */ 1929 dfx_int_common(dev); 1930 1931 /* Reenable interrupts at the ESIC */ 1932 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1933 status |= PI_CONFIG_STAT_0_M_INT_ENB; 1934 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1935 1936 spin_unlock(&bp->lock); 1937 } 1938 if (dfx_bus_tc) { 1939 u32 status; 1940 1941 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status); 1942 if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING | 1943 PI_PSTATUS_M_XMT_DATA_PENDING | 1944 PI_PSTATUS_M_SMT_HOST_PENDING | 1945 PI_PSTATUS_M_UNSOL_PENDING | 1946 PI_PSTATUS_M_CMD_RSP_PENDING | 1947 PI_PSTATUS_M_CMD_REQ_PENDING | 1948 PI_PSTATUS_M_TYPE_0_PENDING))) 1949 return IRQ_NONE; 1950 1951 spin_lock(&bp->lock); 1952 1953 /* Call interrupt service routine for this adapter */ 1954 dfx_int_common(dev); 1955 1956 spin_unlock(&bp->lock); 1957 } 1958 1959 return IRQ_HANDLED; 1960 } 1961 1962 1963 /* 1964 * ===================== 1965 * = dfx_ctl_get_stats = 1966 * ===================== 1967 * 1968 * Overview: 1969 * Get statistics for FDDI adapter 1970 * 1971 * Returns: 1972 * Pointer to FDDI statistics structure 1973 * 1974 * Arguments: 1975 * dev - pointer to device information 1976 * 1977 * Functional Description: 1978 * Gets current MIB objects from adapter, then 1979 * returns FDDI statistics structure as defined 1980 * in if_fddi.h. 1981 * 1982 * Note: Since the FDDI statistics structure is 1983 * still new and the device structure doesn't 1984 * have an FDDI-specific get statistics handler, 1985 * we'll return the FDDI statistics structure as 1986 * a pointer to an Ethernet statistics structure. 1987 * That way, at least the first part of the statistics 1988 * structure can be decoded properly, and it allows 1989 * "smart" applications to perform a second cast to 1990 * decode the FDDI-specific statistics. 1991 * 1992 * We'll have to pay attention to this routine as the 1993 * device structure becomes more mature and LAN media 1994 * independent. 1995 * 1996 * Return Codes: 1997 * None 1998 * 1999 * Assumptions: 2000 * None 2001 * 2002 * Side Effects: 2003 * None 2004 */ 2005 2006 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev) 2007 { 2008 DFX_board_t *bp = netdev_priv(dev); 2009 2010 /* Fill the bp->stats structure with driver-maintained counters */ 2011 2012 bp->stats.gen.rx_packets = bp->rcv_total_frames; 2013 bp->stats.gen.tx_packets = bp->xmt_total_frames; 2014 bp->stats.gen.rx_bytes = bp->rcv_total_bytes; 2015 bp->stats.gen.tx_bytes = bp->xmt_total_bytes; 2016 bp->stats.gen.rx_errors = bp->rcv_crc_errors + 2017 bp->rcv_frame_status_errors + 2018 bp->rcv_length_errors; 2019 bp->stats.gen.tx_errors = bp->xmt_length_errors; 2020 bp->stats.gen.rx_dropped = bp->rcv_discards; 2021 bp->stats.gen.tx_dropped = bp->xmt_discards; 2022 bp->stats.gen.multicast = bp->rcv_multicast_frames; 2023 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */ 2024 2025 /* Get FDDI SMT MIB objects */ 2026 2027 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET; 2028 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2029 return (struct net_device_stats *)&bp->stats; 2030 2031 /* Fill the bp->stats structure with the SMT MIB object values */ 2032 2033 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id)); 2034 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id; 2035 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id; 2036 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id; 2037 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data)); 2038 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id; 2039 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct; 2040 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct; 2041 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct; 2042 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths; 2043 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities; 2044 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy; 2045 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy; 2046 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify; 2047 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy; 2048 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration; 2049 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present; 2050 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state; 2051 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state; 2052 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag; 2053 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status; 2054 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag; 2055 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls; 2056 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls; 2057 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions; 2058 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability; 2059 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability; 2060 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths; 2061 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path; 2062 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN); 2063 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN); 2064 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN); 2065 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN); 2066 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test; 2067 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths; 2068 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type; 2069 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN); 2070 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req; 2071 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg; 2072 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max; 2073 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value; 2074 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold; 2075 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio; 2076 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state; 2077 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag; 2078 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag; 2079 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag; 2080 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available; 2081 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present; 2082 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable; 2083 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound; 2084 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound; 2085 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req; 2086 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration)); 2087 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0]; 2088 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1]; 2089 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0]; 2090 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1]; 2091 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0]; 2092 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1]; 2093 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0]; 2094 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1]; 2095 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0]; 2096 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1]; 2097 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3); 2098 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3); 2099 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0]; 2100 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1]; 2101 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0]; 2102 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1]; 2103 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0]; 2104 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1]; 2105 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0]; 2106 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1]; 2107 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0]; 2108 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1]; 2109 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0]; 2110 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1]; 2111 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0]; 2112 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1]; 2113 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0]; 2114 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1]; 2115 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0]; 2116 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1]; 2117 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0]; 2118 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1]; 2119 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0]; 2120 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1]; 2121 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0]; 2122 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1]; 2123 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0]; 2124 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1]; 2125 2126 /* Get FDDI counters */ 2127 2128 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET; 2129 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2130 return (struct net_device_stats *)&bp->stats; 2131 2132 /* Fill the bp->stats structure with the FDDI counter values */ 2133 2134 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls; 2135 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls; 2136 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls; 2137 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls; 2138 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls; 2139 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls; 2140 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls; 2141 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls; 2142 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls; 2143 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls; 2144 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls; 2145 2146 return (struct net_device_stats *)&bp->stats; 2147 } 2148 2149 2150 /* 2151 * ============================== 2152 * = dfx_ctl_set_multicast_list = 2153 * ============================== 2154 * 2155 * Overview: 2156 * Enable/Disable LLC frame promiscuous mode reception 2157 * on the adapter and/or update multicast address table. 2158 * 2159 * Returns: 2160 * None 2161 * 2162 * Arguments: 2163 * dev - pointer to device information 2164 * 2165 * Functional Description: 2166 * This routine follows a fairly simple algorithm for setting the 2167 * adapter filters and CAM: 2168 * 2169 * if IFF_PROMISC flag is set 2170 * enable LLC individual/group promiscuous mode 2171 * else 2172 * disable LLC individual/group promiscuous mode 2173 * if number of incoming multicast addresses > 2174 * (CAM max size - number of unicast addresses in CAM) 2175 * enable LLC group promiscuous mode 2176 * set driver-maintained multicast address count to zero 2177 * else 2178 * disable LLC group promiscuous mode 2179 * set driver-maintained multicast address count to incoming count 2180 * update adapter CAM 2181 * update adapter filters 2182 * 2183 * Return Codes: 2184 * None 2185 * 2186 * Assumptions: 2187 * Multicast addresses are presented in canonical (LSB) format. 2188 * 2189 * Side Effects: 2190 * On-board adapter CAM and filters are updated. 2191 */ 2192 2193 static void dfx_ctl_set_multicast_list(struct net_device *dev) 2194 { 2195 DFX_board_t *bp = netdev_priv(dev); 2196 int i; /* used as index in for loop */ 2197 struct netdev_hw_addr *ha; 2198 2199 /* Enable LLC frame promiscuous mode, if necessary */ 2200 2201 if (dev->flags & IFF_PROMISC) 2202 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */ 2203 2204 /* Else, update multicast address table */ 2205 2206 else 2207 { 2208 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */ 2209 /* 2210 * Check whether incoming multicast address count exceeds table size 2211 * 2212 * Note: The adapters utilize an on-board 64 entry CAM for 2213 * supporting perfect filtering of multicast packets 2214 * and bridge functions when adding unicast addresses. 2215 * There is no hash function available. To support 2216 * additional multicast addresses, the all multicast 2217 * filter (LLC group promiscuous mode) must be enabled. 2218 * 2219 * The firmware reserves two CAM entries for SMT-related 2220 * multicast addresses, which leaves 62 entries available. 2221 * The following code ensures that we're not being asked 2222 * to add more than 62 addresses to the CAM. If we are, 2223 * the driver will enable the all multicast filter. 2224 * Should the number of multicast addresses drop below 2225 * the high water mark, the filter will be disabled and 2226 * perfect filtering will be used. 2227 */ 2228 2229 if (netdev_mc_count(dev) > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count)) 2230 { 2231 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2232 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2233 } 2234 else 2235 { 2236 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */ 2237 bp->mc_count = netdev_mc_count(dev); /* Add mc addrs to CAM */ 2238 } 2239 2240 /* Copy addresses to multicast address table, then update adapter CAM */ 2241 2242 i = 0; 2243 netdev_for_each_mc_addr(ha, dev) 2244 memcpy(&bp->mc_table[i++ * FDDI_K_ALEN], 2245 ha->addr, FDDI_K_ALEN); 2246 2247 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2248 { 2249 DBG_printk("%s: Could not update multicast address table!\n", dev->name); 2250 } 2251 else 2252 { 2253 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count); 2254 } 2255 } 2256 2257 /* Update adapter filters */ 2258 2259 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2260 { 2261 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2262 } 2263 else 2264 { 2265 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2266 } 2267 } 2268 2269 2270 /* 2271 * =========================== 2272 * = dfx_ctl_set_mac_address = 2273 * =========================== 2274 * 2275 * Overview: 2276 * Add node address override (unicast address) to adapter 2277 * CAM and update dev_addr field in device table. 2278 * 2279 * Returns: 2280 * None 2281 * 2282 * Arguments: 2283 * dev - pointer to device information 2284 * addr - pointer to sockaddr structure containing unicast address to add 2285 * 2286 * Functional Description: 2287 * The adapter supports node address overrides by adding one or more 2288 * unicast addresses to the adapter CAM. This is similar to adding 2289 * multicast addresses. In this routine we'll update the driver and 2290 * device structures with the new address, then update the adapter CAM 2291 * to ensure that the adapter will copy and strip frames destined and 2292 * sourced by that address. 2293 * 2294 * Return Codes: 2295 * Always returns zero. 2296 * 2297 * Assumptions: 2298 * The address pointed to by addr->sa_data is a valid unicast 2299 * address and is presented in canonical (LSB) format. 2300 * 2301 * Side Effects: 2302 * On-board adapter CAM is updated. On-board adapter filters 2303 * may be updated. 2304 */ 2305 2306 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr) 2307 { 2308 struct sockaddr *p_sockaddr = (struct sockaddr *)addr; 2309 DFX_board_t *bp = netdev_priv(dev); 2310 2311 /* Copy unicast address to driver-maintained structs and update count */ 2312 2313 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */ 2314 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */ 2315 bp->uc_count = 1; 2316 2317 /* 2318 * Verify we're not exceeding the CAM size by adding unicast address 2319 * 2320 * Note: It's possible that before entering this routine we've 2321 * already filled the CAM with 62 multicast addresses. 2322 * Since we need to place the node address override into 2323 * the CAM, we have to check to see that we're not 2324 * exceeding the CAM size. If we are, we have to enable 2325 * the LLC group (multicast) promiscuous mode filter as 2326 * in dfx_ctl_set_multicast_list. 2327 */ 2328 2329 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE) 2330 { 2331 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2332 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2333 2334 /* Update adapter filters */ 2335 2336 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2337 { 2338 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2339 } 2340 else 2341 { 2342 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2343 } 2344 } 2345 2346 /* Update adapter CAM with new unicast address */ 2347 2348 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2349 { 2350 DBG_printk("%s: Could not set new MAC address!\n", dev->name); 2351 } 2352 else 2353 { 2354 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name); 2355 } 2356 return 0; /* always return zero */ 2357 } 2358 2359 2360 /* 2361 * ====================== 2362 * = dfx_ctl_update_cam = 2363 * ====================== 2364 * 2365 * Overview: 2366 * Procedure to update adapter CAM (Content Addressable Memory) 2367 * with desired unicast and multicast address entries. 2368 * 2369 * Returns: 2370 * Condition code 2371 * 2372 * Arguments: 2373 * bp - pointer to board information 2374 * 2375 * Functional Description: 2376 * Updates adapter CAM with current contents of board structure 2377 * unicast and multicast address tables. Since there are only 62 2378 * free entries in CAM, this routine ensures that the command 2379 * request buffer is not overrun. 2380 * 2381 * Return Codes: 2382 * DFX_K_SUCCESS - Request succeeded 2383 * DFX_K_FAILURE - Request failed 2384 * 2385 * Assumptions: 2386 * All addresses being added (unicast and multicast) are in canonical 2387 * order. 2388 * 2389 * Side Effects: 2390 * On-board adapter CAM is updated. 2391 */ 2392 2393 static int dfx_ctl_update_cam(DFX_board_t *bp) 2394 { 2395 int i; /* used as index */ 2396 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */ 2397 2398 /* 2399 * Fill in command request information 2400 * 2401 * Note: Even though both the unicast and multicast address 2402 * table entries are stored as contiguous 6 byte entries, 2403 * the firmware address filter set command expects each 2404 * entry to be two longwords (8 bytes total). We must be 2405 * careful to only copy the six bytes of each unicast and 2406 * multicast table entry into each command entry. This 2407 * is also why we must first clear the entire command 2408 * request buffer. 2409 */ 2410 2411 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */ 2412 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET; 2413 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0]; 2414 2415 /* Now add unicast addresses to command request buffer, if any */ 2416 2417 for (i=0; i < (int)bp->uc_count; i++) 2418 { 2419 if (i < PI_CMD_ADDR_FILTER_K_SIZE) 2420 { 2421 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2422 p_addr++; /* point to next command entry */ 2423 } 2424 } 2425 2426 /* Now add multicast addresses to command request buffer, if any */ 2427 2428 for (i=0; i < (int)bp->mc_count; i++) 2429 { 2430 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE) 2431 { 2432 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2433 p_addr++; /* point to next command entry */ 2434 } 2435 } 2436 2437 /* Issue command to update adapter CAM, then return */ 2438 2439 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2440 return DFX_K_FAILURE; 2441 return DFX_K_SUCCESS; 2442 } 2443 2444 2445 /* 2446 * ========================== 2447 * = dfx_ctl_update_filters = 2448 * ========================== 2449 * 2450 * Overview: 2451 * Procedure to update adapter filters with desired 2452 * filter settings. 2453 * 2454 * Returns: 2455 * Condition code 2456 * 2457 * Arguments: 2458 * bp - pointer to board information 2459 * 2460 * Functional Description: 2461 * Enables or disables filter using current filter settings. 2462 * 2463 * Return Codes: 2464 * DFX_K_SUCCESS - Request succeeded. 2465 * DFX_K_FAILURE - Request failed. 2466 * 2467 * Assumptions: 2468 * We must always pass up packets destined to the broadcast 2469 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the 2470 * broadcast filter enabled. 2471 * 2472 * Side Effects: 2473 * On-board adapter filters are updated. 2474 */ 2475 2476 static int dfx_ctl_update_filters(DFX_board_t *bp) 2477 { 2478 int i = 0; /* used as index */ 2479 2480 /* Fill in command request information */ 2481 2482 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET; 2483 2484 /* Initialize Broadcast filter - * ALWAYS ENABLED * */ 2485 2486 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST; 2487 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS; 2488 2489 /* Initialize LLC Individual/Group Promiscuous filter */ 2490 2491 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM; 2492 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom; 2493 2494 /* Initialize LLC Group Promiscuous filter */ 2495 2496 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM; 2497 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom; 2498 2499 /* Terminate the item code list */ 2500 2501 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL; 2502 2503 /* Issue command to update adapter filters, then return */ 2504 2505 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2506 return DFX_K_FAILURE; 2507 return DFX_K_SUCCESS; 2508 } 2509 2510 2511 /* 2512 * ====================== 2513 * = dfx_hw_dma_cmd_req = 2514 * ====================== 2515 * 2516 * Overview: 2517 * Sends PDQ DMA command to adapter firmware 2518 * 2519 * Returns: 2520 * Condition code 2521 * 2522 * Arguments: 2523 * bp - pointer to board information 2524 * 2525 * Functional Description: 2526 * The command request and response buffers are posted to the adapter in the manner 2527 * described in the PDQ Port Specification: 2528 * 2529 * 1. Command Response Buffer is posted to adapter. 2530 * 2. Command Request Buffer is posted to adapter. 2531 * 3. Command Request consumer index is polled until it indicates that request 2532 * buffer has been DMA'd to adapter. 2533 * 4. Command Response consumer index is polled until it indicates that response 2534 * buffer has been DMA'd from adapter. 2535 * 2536 * This ordering ensures that a response buffer is already available for the firmware 2537 * to use once it's done processing the request buffer. 2538 * 2539 * Return Codes: 2540 * DFX_K_SUCCESS - DMA command succeeded 2541 * DFX_K_OUTSTATE - Adapter is NOT in proper state 2542 * DFX_K_HW_TIMEOUT - DMA command timed out 2543 * 2544 * Assumptions: 2545 * Command request buffer has already been filled with desired DMA command. 2546 * 2547 * Side Effects: 2548 * None 2549 */ 2550 2551 static int dfx_hw_dma_cmd_req(DFX_board_t *bp) 2552 { 2553 int status; /* adapter status */ 2554 int timeout_cnt; /* used in for loops */ 2555 2556 /* Make sure the adapter is in a state that we can issue the DMA command in */ 2557 2558 status = dfx_hw_adap_state_rd(bp); 2559 if ((status == PI_STATE_K_RESET) || 2560 (status == PI_STATE_K_HALTED) || 2561 (status == PI_STATE_K_DMA_UNAVAIL) || 2562 (status == PI_STATE_K_UPGRADE)) 2563 return DFX_K_OUTSTATE; 2564 2565 /* Put response buffer on the command response queue */ 2566 2567 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2568 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2569 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys; 2570 2571 /* Bump (and wrap) the producer index and write out to register */ 2572 2573 bp->cmd_rsp_reg.index.prod += 1; 2574 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2575 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2576 2577 /* Put request buffer on the command request queue */ 2578 2579 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP | 2580 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN)); 2581 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys; 2582 2583 /* Bump (and wrap) the producer index and write out to register */ 2584 2585 bp->cmd_req_reg.index.prod += 1; 2586 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2587 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2588 2589 /* 2590 * Here we wait for the command request consumer index to be equal 2591 * to the producer, indicating that the adapter has DMAed the request. 2592 */ 2593 2594 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2595 { 2596 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req)) 2597 break; 2598 udelay(100); /* wait for 100 microseconds */ 2599 } 2600 if (timeout_cnt == 0) 2601 return DFX_K_HW_TIMEOUT; 2602 2603 /* Bump (and wrap) the completion index and write out to register */ 2604 2605 bp->cmd_req_reg.index.comp += 1; 2606 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2607 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2608 2609 /* 2610 * Here we wait for the command response consumer index to be equal 2611 * to the producer, indicating that the adapter has DMAed the response. 2612 */ 2613 2614 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2615 { 2616 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp)) 2617 break; 2618 udelay(100); /* wait for 100 microseconds */ 2619 } 2620 if (timeout_cnt == 0) 2621 return DFX_K_HW_TIMEOUT; 2622 2623 /* Bump (and wrap) the completion index and write out to register */ 2624 2625 bp->cmd_rsp_reg.index.comp += 1; 2626 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2627 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2628 return DFX_K_SUCCESS; 2629 } 2630 2631 2632 /* 2633 * ======================== 2634 * = dfx_hw_port_ctrl_req = 2635 * ======================== 2636 * 2637 * Overview: 2638 * Sends PDQ port control command to adapter firmware 2639 * 2640 * Returns: 2641 * Host data register value in host_data if ptr is not NULL 2642 * 2643 * Arguments: 2644 * bp - pointer to board information 2645 * command - port control command 2646 * data_a - port data A register value 2647 * data_b - port data B register value 2648 * host_data - ptr to host data register value 2649 * 2650 * Functional Description: 2651 * Send generic port control command to adapter by writing 2652 * to various PDQ port registers, then polling for completion. 2653 * 2654 * Return Codes: 2655 * DFX_K_SUCCESS - port control command succeeded 2656 * DFX_K_HW_TIMEOUT - port control command timed out 2657 * 2658 * Assumptions: 2659 * None 2660 * 2661 * Side Effects: 2662 * None 2663 */ 2664 2665 static int dfx_hw_port_ctrl_req( 2666 DFX_board_t *bp, 2667 PI_UINT32 command, 2668 PI_UINT32 data_a, 2669 PI_UINT32 data_b, 2670 PI_UINT32 *host_data 2671 ) 2672 2673 { 2674 PI_UINT32 port_cmd; /* Port Control command register value */ 2675 int timeout_cnt; /* used in for loops */ 2676 2677 /* Set Command Error bit in command longword */ 2678 2679 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR); 2680 2681 /* Issue port command to the adapter */ 2682 2683 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a); 2684 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b); 2685 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd); 2686 2687 /* Now wait for command to complete */ 2688 2689 if (command == PI_PCTRL_M_BLAST_FLASH) 2690 timeout_cnt = 600000; /* set command timeout count to 60 seconds */ 2691 else 2692 timeout_cnt = 20000; /* set command timeout count to 2 seconds */ 2693 2694 for (; timeout_cnt > 0; timeout_cnt--) 2695 { 2696 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd); 2697 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR)) 2698 break; 2699 udelay(100); /* wait for 100 microseconds */ 2700 } 2701 if (timeout_cnt == 0) 2702 return DFX_K_HW_TIMEOUT; 2703 2704 /* 2705 * If the address of host_data is non-zero, assume caller has supplied a 2706 * non NULL pointer, and return the contents of the HOST_DATA register in 2707 * it. 2708 */ 2709 2710 if (host_data != NULL) 2711 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data); 2712 return DFX_K_SUCCESS; 2713 } 2714 2715 2716 /* 2717 * ===================== 2718 * = dfx_hw_adap_reset = 2719 * ===================== 2720 * 2721 * Overview: 2722 * Resets adapter 2723 * 2724 * Returns: 2725 * None 2726 * 2727 * Arguments: 2728 * bp - pointer to board information 2729 * type - type of reset to perform 2730 * 2731 * Functional Description: 2732 * Issue soft reset to adapter by writing to PDQ Port Reset 2733 * register. Use incoming reset type to tell adapter what 2734 * kind of reset operation to perform. 2735 * 2736 * Return Codes: 2737 * None 2738 * 2739 * Assumptions: 2740 * This routine merely issues a soft reset to the adapter. 2741 * It is expected that after this routine returns, the caller 2742 * will appropriately poll the Port Status register for the 2743 * adapter to enter the proper state. 2744 * 2745 * Side Effects: 2746 * Internal adapter registers are cleared. 2747 */ 2748 2749 static void dfx_hw_adap_reset( 2750 DFX_board_t *bp, 2751 PI_UINT32 type 2752 ) 2753 2754 { 2755 /* Set Reset type and assert reset */ 2756 2757 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */ 2758 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET); 2759 2760 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */ 2761 2762 udelay(20); 2763 2764 /* Deassert reset */ 2765 2766 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0); 2767 } 2768 2769 2770 /* 2771 * ======================== 2772 * = dfx_hw_adap_state_rd = 2773 * ======================== 2774 * 2775 * Overview: 2776 * Returns current adapter state 2777 * 2778 * Returns: 2779 * Adapter state per PDQ Port Specification 2780 * 2781 * Arguments: 2782 * bp - pointer to board information 2783 * 2784 * Functional Description: 2785 * Reads PDQ Port Status register and returns adapter state. 2786 * 2787 * Return Codes: 2788 * None 2789 * 2790 * Assumptions: 2791 * None 2792 * 2793 * Side Effects: 2794 * None 2795 */ 2796 2797 static int dfx_hw_adap_state_rd(DFX_board_t *bp) 2798 { 2799 PI_UINT32 port_status; /* Port Status register value */ 2800 2801 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 2802 return (port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE; 2803 } 2804 2805 2806 /* 2807 * ===================== 2808 * = dfx_hw_dma_uninit = 2809 * ===================== 2810 * 2811 * Overview: 2812 * Brings adapter to DMA_UNAVAILABLE state 2813 * 2814 * Returns: 2815 * Condition code 2816 * 2817 * Arguments: 2818 * bp - pointer to board information 2819 * type - type of reset to perform 2820 * 2821 * Functional Description: 2822 * Bring adapter to DMA_UNAVAILABLE state by performing the following: 2823 * 1. Set reset type bit in Port Data A Register then reset adapter. 2824 * 2. Check that adapter is in DMA_UNAVAILABLE state. 2825 * 2826 * Return Codes: 2827 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state 2828 * DFX_K_HW_TIMEOUT - adapter did not reset properly 2829 * 2830 * Assumptions: 2831 * None 2832 * 2833 * Side Effects: 2834 * Internal adapter registers are cleared. 2835 */ 2836 2837 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type) 2838 { 2839 int timeout_cnt; /* used in for loops */ 2840 2841 /* Set reset type bit and reset adapter */ 2842 2843 dfx_hw_adap_reset(bp, type); 2844 2845 /* Now wait for adapter to enter DMA_UNAVAILABLE state */ 2846 2847 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--) 2848 { 2849 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL) 2850 break; 2851 udelay(100); /* wait for 100 microseconds */ 2852 } 2853 if (timeout_cnt == 0) 2854 return DFX_K_HW_TIMEOUT; 2855 return DFX_K_SUCCESS; 2856 } 2857 2858 /* 2859 * Align an sk_buff to a boundary power of 2 2860 * 2861 */ 2862 2863 static void my_skb_align(struct sk_buff *skb, int n) 2864 { 2865 unsigned long x = (unsigned long)skb->data; 2866 unsigned long v; 2867 2868 v = ALIGN(x, n); /* Where we want to be */ 2869 2870 skb_reserve(skb, v - x); 2871 } 2872 2873 2874 /* 2875 * ================ 2876 * = dfx_rcv_init = 2877 * ================ 2878 * 2879 * Overview: 2880 * Produces buffers to adapter LLC Host receive descriptor block 2881 * 2882 * Returns: 2883 * None 2884 * 2885 * Arguments: 2886 * bp - pointer to board information 2887 * get_buffers - non-zero if buffers to be allocated 2888 * 2889 * Functional Description: 2890 * This routine can be called during dfx_adap_init() or during an adapter 2891 * reset. It initializes the descriptor block and produces all allocated 2892 * LLC Host queue receive buffers. 2893 * 2894 * Return Codes: 2895 * Return 0 on success or -ENOMEM if buffer allocation failed (when using 2896 * dynamic buffer allocation). If the buffer allocation failed, the 2897 * already allocated buffers will not be released and the caller should do 2898 * this. 2899 * 2900 * Assumptions: 2901 * The PDQ has been reset and the adapter and driver maintained Type 2 2902 * register indices are cleared. 2903 * 2904 * Side Effects: 2905 * Receive buffers are posted to the adapter LLC queue and the adapter 2906 * is notified. 2907 */ 2908 2909 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers) 2910 { 2911 int i, j; /* used in for loop */ 2912 2913 /* 2914 * Since each receive buffer is a single fragment of same length, initialize 2915 * first longword in each receive descriptor for entire LLC Host descriptor 2916 * block. Also initialize second longword in each receive descriptor with 2917 * physical address of receive buffer. We'll always allocate receive 2918 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor 2919 * block and produce new receive buffers by simply updating the receive 2920 * producer index. 2921 * 2922 * Assumptions: 2923 * To support all shipping versions of PDQ, the receive buffer size 2924 * must be mod 128 in length and the physical address must be 128 byte 2925 * aligned. In other words, bits 0-6 of the length and address must 2926 * be zero for the following descriptor field entries to be correct on 2927 * all PDQ-based boards. We guaranteed both requirements during 2928 * driver initialization when we allocated memory for the receive buffers. 2929 */ 2930 2931 if (get_buffers) { 2932 #ifdef DYNAMIC_BUFFERS 2933 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 2934 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2935 { 2936 struct sk_buff *newskb = __netdev_alloc_skb(bp->dev, NEW_SKB_SIZE, GFP_NOIO); 2937 if (!newskb) 2938 return -ENOMEM; 2939 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2940 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2941 /* 2942 * align to 128 bytes for compatibility with 2943 * the old EISA boards. 2944 */ 2945 2946 my_skb_align(newskb, 128); 2947 bp->descr_block_virt->rcv_data[i + j].long_1 = 2948 (u32)dma_map_single(bp->bus_dev, newskb->data, 2949 NEW_SKB_SIZE, 2950 DMA_FROM_DEVICE); 2951 /* 2952 * p_rcv_buff_va is only used inside the 2953 * kernel so we put the skb pointer here. 2954 */ 2955 bp->p_rcv_buff_va[i+j] = (char *) newskb; 2956 } 2957 #else 2958 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++) 2959 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2960 { 2961 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2962 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2963 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX)); 2964 bp->p_rcv_buff_va[i+j] = (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX)); 2965 } 2966 #endif 2967 } 2968 2969 /* Update receive producer and Type 2 register */ 2970 2971 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post; 2972 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 2973 return 0; 2974 } 2975 2976 2977 /* 2978 * ========================= 2979 * = dfx_rcv_queue_process = 2980 * ========================= 2981 * 2982 * Overview: 2983 * Process received LLC frames. 2984 * 2985 * Returns: 2986 * None 2987 * 2988 * Arguments: 2989 * bp - pointer to board information 2990 * 2991 * Functional Description: 2992 * Received LLC frames are processed until there are no more consumed frames. 2993 * Once all frames are processed, the receive buffers are returned to the 2994 * adapter. Note that this algorithm fixes the length of time that can be spent 2995 * in this routine, because there are a fixed number of receive buffers to 2996 * process and buffers are not produced until this routine exits and returns 2997 * to the ISR. 2998 * 2999 * Return Codes: 3000 * None 3001 * 3002 * Assumptions: 3003 * None 3004 * 3005 * Side Effects: 3006 * None 3007 */ 3008 3009 static void dfx_rcv_queue_process( 3010 DFX_board_t *bp 3011 ) 3012 3013 { 3014 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3015 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */ 3016 u32 descr, pkt_len; /* FMC descriptor field and packet length */ 3017 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */ 3018 3019 /* Service all consumed LLC receive frames */ 3020 3021 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3022 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons) 3023 { 3024 /* Process any errors */ 3025 3026 int entry; 3027 3028 entry = bp->rcv_xmt_reg.index.rcv_comp; 3029 #ifdef DYNAMIC_BUFFERS 3030 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data); 3031 #else 3032 p_buff = bp->p_rcv_buff_va[entry]; 3033 #endif 3034 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32)); 3035 3036 if (descr & PI_FMC_DESCR_M_RCC_FLUSH) 3037 { 3038 if (descr & PI_FMC_DESCR_M_RCC_CRC) 3039 bp->rcv_crc_errors++; 3040 else 3041 bp->rcv_frame_status_errors++; 3042 } 3043 else 3044 { 3045 int rx_in_place = 0; 3046 3047 /* The frame was received without errors - verify packet length */ 3048 3049 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN); 3050 pkt_len -= 4; /* subtract 4 byte CRC */ 3051 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3052 bp->rcv_length_errors++; 3053 else{ 3054 #ifdef DYNAMIC_BUFFERS 3055 if (pkt_len > SKBUFF_RX_COPYBREAK) { 3056 struct sk_buff *newskb; 3057 3058 newskb = dev_alloc_skb(NEW_SKB_SIZE); 3059 if (newskb){ 3060 rx_in_place = 1; 3061 3062 my_skb_align(newskb, 128); 3063 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; 3064 dma_unmap_single(bp->bus_dev, 3065 bp->descr_block_virt->rcv_data[entry].long_1, 3066 NEW_SKB_SIZE, 3067 DMA_FROM_DEVICE); 3068 skb_reserve(skb, RCV_BUFF_K_PADDING); 3069 bp->p_rcv_buff_va[entry] = (char *)newskb; 3070 bp->descr_block_virt->rcv_data[entry].long_1 = 3071 (u32)dma_map_single(bp->bus_dev, 3072 newskb->data, 3073 NEW_SKB_SIZE, 3074 DMA_FROM_DEVICE); 3075 } else 3076 skb = NULL; 3077 } else 3078 #endif 3079 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */ 3080 if (skb == NULL) 3081 { 3082 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name); 3083 bp->rcv_discards++; 3084 break; 3085 } 3086 else { 3087 #ifndef DYNAMIC_BUFFERS 3088 if (! rx_in_place) 3089 #endif 3090 { 3091 /* Receive buffer allocated, pass receive packet up */ 3092 3093 skb_copy_to_linear_data(skb, 3094 p_buff + RCV_BUFF_K_PADDING, 3095 pkt_len + 3); 3096 } 3097 3098 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */ 3099 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */ 3100 skb->protocol = fddi_type_trans(skb, bp->dev); 3101 bp->rcv_total_bytes += skb->len; 3102 netif_rx(skb); 3103 3104 /* Update the rcv counters */ 3105 bp->rcv_total_frames++; 3106 if (*(p_buff + RCV_BUFF_K_DA) & 0x01) 3107 bp->rcv_multicast_frames++; 3108 } 3109 } 3110 } 3111 3112 /* 3113 * Advance the producer (for recycling) and advance the completion 3114 * (for servicing received frames). Note that it is okay to 3115 * advance the producer without checking that it passes the 3116 * completion index because they are both advanced at the same 3117 * rate. 3118 */ 3119 3120 bp->rcv_xmt_reg.index.rcv_prod += 1; 3121 bp->rcv_xmt_reg.index.rcv_comp += 1; 3122 } 3123 } 3124 3125 3126 /* 3127 * ===================== 3128 * = dfx_xmt_queue_pkt = 3129 * ===================== 3130 * 3131 * Overview: 3132 * Queues packets for transmission 3133 * 3134 * Returns: 3135 * Condition code 3136 * 3137 * Arguments: 3138 * skb - pointer to sk_buff to queue for transmission 3139 * dev - pointer to device information 3140 * 3141 * Functional Description: 3142 * Here we assume that an incoming skb transmit request 3143 * is contained in a single physically contiguous buffer 3144 * in which the virtual address of the start of packet 3145 * (skb->data) can be converted to a physical address 3146 * by using pci_map_single(). 3147 * 3148 * Since the adapter architecture requires a three byte 3149 * packet request header to prepend the start of packet, 3150 * we'll write the three byte field immediately prior to 3151 * the FC byte. This assumption is valid because we've 3152 * ensured that dev->hard_header_len includes three pad 3153 * bytes. By posting a single fragment to the adapter, 3154 * we'll reduce the number of descriptor fetches and 3155 * bus traffic needed to send the request. 3156 * 3157 * Also, we can't free the skb until after it's been DMA'd 3158 * out by the adapter, so we'll queue it in the driver and 3159 * return it in dfx_xmt_done. 3160 * 3161 * Return Codes: 3162 * 0 - driver queued packet, link is unavailable, or skbuff was bad 3163 * 1 - caller should requeue the sk_buff for later transmission 3164 * 3165 * Assumptions: 3166 * First and foremost, we assume the incoming skb pointer 3167 * is NOT NULL and is pointing to a valid sk_buff structure. 3168 * 3169 * The outgoing packet is complete, starting with the 3170 * frame control byte including the last byte of data, 3171 * but NOT including the 4 byte CRC. We'll let the 3172 * adapter hardware generate and append the CRC. 3173 * 3174 * The entire packet is stored in one physically 3175 * contiguous buffer which is not cached and whose 3176 * 32-bit physical address can be determined. 3177 * 3178 * It's vital that this routine is NOT reentered for the 3179 * same board and that the OS is not in another section of 3180 * code (eg. dfx_int_common) for the same board on a 3181 * different thread. 3182 * 3183 * Side Effects: 3184 * None 3185 */ 3186 3187 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 3188 struct net_device *dev) 3189 { 3190 DFX_board_t *bp = netdev_priv(dev); 3191 u8 prod; /* local transmit producer index */ 3192 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */ 3193 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3194 unsigned long flags; 3195 3196 netif_stop_queue(dev); 3197 3198 /* 3199 * Verify that incoming transmit request is OK 3200 * 3201 * Note: The packet size check is consistent with other 3202 * Linux device drivers, although the correct packet 3203 * size should be verified before calling the 3204 * transmit routine. 3205 */ 3206 3207 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3208 { 3209 printk("%s: Invalid packet length - %u bytes\n", 3210 dev->name, skb->len); 3211 bp->xmt_length_errors++; /* bump error counter */ 3212 netif_wake_queue(dev); 3213 dev_kfree_skb(skb); 3214 return NETDEV_TX_OK; /* return "success" */ 3215 } 3216 /* 3217 * See if adapter link is available, if not, free buffer 3218 * 3219 * Note: If the link isn't available, free buffer and return 0 3220 * rather than tell the upper layer to requeue the packet. 3221 * The methodology here is that by the time the link 3222 * becomes available, the packet to be sent will be 3223 * fairly stale. By simply dropping the packet, the 3224 * higher layer protocols will eventually time out 3225 * waiting for response packets which it won't receive. 3226 */ 3227 3228 if (bp->link_available == PI_K_FALSE) 3229 { 3230 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */ 3231 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */ 3232 else 3233 { 3234 bp->xmt_discards++; /* bump error counter */ 3235 dev_kfree_skb(skb); /* free sk_buff now */ 3236 netif_wake_queue(dev); 3237 return NETDEV_TX_OK; /* return "success" */ 3238 } 3239 } 3240 3241 spin_lock_irqsave(&bp->lock, flags); 3242 3243 /* Get the current producer and the next free xmt data descriptor */ 3244 3245 prod = bp->rcv_xmt_reg.index.xmt_prod; 3246 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]); 3247 3248 /* 3249 * Get pointer to auxiliary queue entry to contain information 3250 * for this packet. 3251 * 3252 * Note: The current xmt producer index will become the 3253 * current xmt completion index when we complete this 3254 * packet later on. So, we'll get the pointer to the 3255 * next auxiliary queue entry now before we bump the 3256 * producer index. 3257 */ 3258 3259 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */ 3260 3261 /* Write the three PRH bytes immediately before the FC byte */ 3262 3263 skb_push(skb,3); 3264 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */ 3265 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */ 3266 skb->data[2] = DFX_PRH2_BYTE; /* specification */ 3267 3268 /* 3269 * Write the descriptor with buffer info and bump producer 3270 * 3271 * Note: Since we need to start DMA from the packet request 3272 * header, we'll add 3 bytes to the DMA buffer length, 3273 * and we'll determine the physical address of the 3274 * buffer from the PRH, not skb->data. 3275 * 3276 * Assumptions: 3277 * 1. Packet starts with the frame control (FC) byte 3278 * at skb->data. 3279 * 2. The 4-byte CRC is not appended to the buffer or 3280 * included in the length. 3281 * 3. Packet length (skb->len) is from FC to end of 3282 * data, inclusive. 3283 * 4. The packet length does not exceed the maximum 3284 * FDDI LLC frame length of 4491 bytes. 3285 * 5. The entire packet is contained in a physically 3286 * contiguous, non-cached, locked memory space 3287 * comprised of a single buffer pointed to by 3288 * skb->data. 3289 * 6. The physical address of the start of packet 3290 * can be determined from the virtual address 3291 * by using pci_map_single() and is only 32-bits 3292 * wide. 3293 */ 3294 3295 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); 3296 p_xmt_descr->long_1 = (u32)dma_map_single(bp->bus_dev, skb->data, 3297 skb->len, DMA_TO_DEVICE); 3298 3299 /* 3300 * Verify that descriptor is actually available 3301 * 3302 * Note: If descriptor isn't available, return 1 which tells 3303 * the upper layer to requeue the packet for later 3304 * transmission. 3305 * 3306 * We need to ensure that the producer never reaches the 3307 * completion, except to indicate that the queue is empty. 3308 */ 3309 3310 if (prod == bp->rcv_xmt_reg.index.xmt_comp) 3311 { 3312 skb_pull(skb,3); 3313 spin_unlock_irqrestore(&bp->lock, flags); 3314 return NETDEV_TX_BUSY; /* requeue packet for later */ 3315 } 3316 3317 /* 3318 * Save info for this packet for xmt done indication routine 3319 * 3320 * Normally, we'd save the producer index in the p_xmt_drv_descr 3321 * structure so that we'd have it handy when we complete this 3322 * packet later (in dfx_xmt_done). However, since the current 3323 * transmit architecture guarantees a single fragment for the 3324 * entire packet, we can simply bump the completion index by 3325 * one (1) for each completed packet. 3326 * 3327 * Note: If this assumption changes and we're presented with 3328 * an inconsistent number of transmit fragments for packet 3329 * data, we'll need to modify this code to save the current 3330 * transmit producer index. 3331 */ 3332 3333 p_xmt_drv_descr->p_skb = skb; 3334 3335 /* Update Type 2 register */ 3336 3337 bp->rcv_xmt_reg.index.xmt_prod = prod; 3338 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 3339 spin_unlock_irqrestore(&bp->lock, flags); 3340 netif_wake_queue(dev); 3341 return NETDEV_TX_OK; /* packet queued to adapter */ 3342 } 3343 3344 3345 /* 3346 * ================ 3347 * = dfx_xmt_done = 3348 * ================ 3349 * 3350 * Overview: 3351 * Processes all frames that have been transmitted. 3352 * 3353 * Returns: 3354 * None 3355 * 3356 * Arguments: 3357 * bp - pointer to board information 3358 * 3359 * Functional Description: 3360 * For all consumed transmit descriptors that have not 3361 * yet been completed, we'll free the skb we were holding 3362 * onto using dev_kfree_skb and bump the appropriate 3363 * counters. 3364 * 3365 * Return Codes: 3366 * None 3367 * 3368 * Assumptions: 3369 * The Type 2 register is not updated in this routine. It is 3370 * assumed that it will be updated in the ISR when dfx_xmt_done 3371 * returns. 3372 * 3373 * Side Effects: 3374 * None 3375 */ 3376 3377 static int dfx_xmt_done(DFX_board_t *bp) 3378 { 3379 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3380 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3381 u8 comp; /* local transmit completion index */ 3382 int freed = 0; /* buffers freed */ 3383 3384 /* Service all consumed transmit frames */ 3385 3386 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3387 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons) 3388 { 3389 /* Get pointer to the transmit driver descriptor block information */ 3390 3391 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3392 3393 /* Increment transmit counters */ 3394 3395 bp->xmt_total_frames++; 3396 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; 3397 3398 /* Return skb to operating system */ 3399 comp = bp->rcv_xmt_reg.index.xmt_comp; 3400 dma_unmap_single(bp->bus_dev, 3401 bp->descr_block_virt->xmt_data[comp].long_1, 3402 p_xmt_drv_descr->p_skb->len, 3403 DMA_TO_DEVICE); 3404 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); 3405 3406 /* 3407 * Move to start of next packet by updating completion index 3408 * 3409 * Here we assume that a transmit packet request is always 3410 * serviced by posting one fragment. We can therefore 3411 * simplify the completion code by incrementing the 3412 * completion index by one. This code will need to be 3413 * modified if this assumption changes. See comments 3414 * in dfx_xmt_queue_pkt for more details. 3415 */ 3416 3417 bp->rcv_xmt_reg.index.xmt_comp += 1; 3418 freed++; 3419 } 3420 return freed; 3421 } 3422 3423 3424 /* 3425 * ================= 3426 * = dfx_rcv_flush = 3427 * ================= 3428 * 3429 * Overview: 3430 * Remove all skb's in the receive ring. 3431 * 3432 * Returns: 3433 * None 3434 * 3435 * Arguments: 3436 * bp - pointer to board information 3437 * 3438 * Functional Description: 3439 * Free's all the dynamically allocated skb's that are 3440 * currently attached to the device receive ring. This 3441 * function is typically only used when the device is 3442 * initialized or reinitialized. 3443 * 3444 * Return Codes: 3445 * None 3446 * 3447 * Side Effects: 3448 * None 3449 */ 3450 #ifdef DYNAMIC_BUFFERS 3451 static void dfx_rcv_flush( DFX_board_t *bp ) 3452 { 3453 int i, j; 3454 3455 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 3456 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 3457 { 3458 struct sk_buff *skb; 3459 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j]; 3460 if (skb) 3461 dev_kfree_skb(skb); 3462 bp->p_rcv_buff_va[i+j] = NULL; 3463 } 3464 3465 } 3466 #else 3467 static inline void dfx_rcv_flush( DFX_board_t *bp ) 3468 { 3469 } 3470 #endif /* DYNAMIC_BUFFERS */ 3471 3472 /* 3473 * ================= 3474 * = dfx_xmt_flush = 3475 * ================= 3476 * 3477 * Overview: 3478 * Processes all frames whether they've been transmitted 3479 * or not. 3480 * 3481 * Returns: 3482 * None 3483 * 3484 * Arguments: 3485 * bp - pointer to board information 3486 * 3487 * Functional Description: 3488 * For all produced transmit descriptors that have not 3489 * yet been completed, we'll free the skb we were holding 3490 * onto using dev_kfree_skb and bump the appropriate 3491 * counters. Of course, it's possible that some of 3492 * these transmit requests actually did go out, but we 3493 * won't make that distinction here. Finally, we'll 3494 * update the consumer index to match the producer. 3495 * 3496 * Return Codes: 3497 * None 3498 * 3499 * Assumptions: 3500 * This routine does NOT update the Type 2 register. It 3501 * is assumed that this routine is being called during a 3502 * transmit flush interrupt, or a shutdown or close routine. 3503 * 3504 * Side Effects: 3505 * None 3506 */ 3507 3508 static void dfx_xmt_flush( DFX_board_t *bp ) 3509 { 3510 u32 prod_cons; /* rcv/xmt consumer block longword */ 3511 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3512 u8 comp; /* local transmit completion index */ 3513 3514 /* Flush all outstanding transmit frames */ 3515 3516 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod) 3517 { 3518 /* Get pointer to the transmit driver descriptor block information */ 3519 3520 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3521 3522 /* Return skb to operating system */ 3523 comp = bp->rcv_xmt_reg.index.xmt_comp; 3524 dma_unmap_single(bp->bus_dev, 3525 bp->descr_block_virt->xmt_data[comp].long_1, 3526 p_xmt_drv_descr->p_skb->len, 3527 DMA_TO_DEVICE); 3528 dev_kfree_skb(p_xmt_drv_descr->p_skb); 3529 3530 /* Increment transmit error counter */ 3531 3532 bp->xmt_discards++; 3533 3534 /* 3535 * Move to start of next packet by updating completion index 3536 * 3537 * Here we assume that a transmit packet request is always 3538 * serviced by posting one fragment. We can therefore 3539 * simplify the completion code by incrementing the 3540 * completion index by one. This code will need to be 3541 * modified if this assumption changes. See comments 3542 * in dfx_xmt_queue_pkt for more details. 3543 */ 3544 3545 bp->rcv_xmt_reg.index.xmt_comp += 1; 3546 } 3547 3548 /* Update the transmit consumer index in the consumer block */ 3549 3550 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX); 3551 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX); 3552 bp->cons_block_virt->xmt_rcv_data = prod_cons; 3553 } 3554 3555 /* 3556 * ================== 3557 * = dfx_unregister = 3558 * ================== 3559 * 3560 * Overview: 3561 * Shuts down an FDDI controller 3562 * 3563 * Returns: 3564 * Condition code 3565 * 3566 * Arguments: 3567 * bdev - pointer to device information 3568 * 3569 * Functional Description: 3570 * 3571 * Return Codes: 3572 * None 3573 * 3574 * Assumptions: 3575 * It compiles so it should work :-( (PCI cards do :-) 3576 * 3577 * Side Effects: 3578 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 3579 * freed. 3580 */ 3581 static void dfx_unregister(struct device *bdev) 3582 { 3583 struct net_device *dev = dev_get_drvdata(bdev); 3584 DFX_board_t *bp = netdev_priv(dev); 3585 int dfx_bus_pci = DFX_BUS_PCI(bdev); 3586 int dfx_bus_tc = DFX_BUS_TC(bdev); 3587 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 3588 resource_size_t bar_start = 0; /* pointer to port */ 3589 resource_size_t bar_len = 0; /* resource length */ 3590 int alloc_size; /* total buffer size used */ 3591 3592 unregister_netdev(dev); 3593 3594 alloc_size = sizeof(PI_DESCR_BLOCK) + 3595 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 3596 #ifndef DYNAMIC_BUFFERS 3597 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 3598 #endif 3599 sizeof(PI_CONSUMER_BLOCK) + 3600 (PI_ALIGN_K_DESC_BLK - 1); 3601 if (bp->kmalloced) 3602 dma_free_coherent(bdev, alloc_size, 3603 bp->kmalloced, bp->kmalloced_dma); 3604 3605 dfx_bus_uninit(dev); 3606 3607 dfx_get_bars(bdev, &bar_start, &bar_len); 3608 if (dfx_use_mmio) { 3609 iounmap(bp->base.mem); 3610 release_mem_region(bar_start, bar_len); 3611 } else 3612 release_region(bar_start, bar_len); 3613 3614 if (dfx_bus_pci) 3615 pci_disable_device(to_pci_dev(bdev)); 3616 3617 free_netdev(dev); 3618 } 3619 3620 3621 static int __maybe_unused dfx_dev_register(struct device *); 3622 static int __maybe_unused dfx_dev_unregister(struct device *); 3623 3624 #ifdef CONFIG_PCI 3625 static int dfx_pci_register(struct pci_dev *, const struct pci_device_id *); 3626 static void dfx_pci_unregister(struct pci_dev *); 3627 3628 static DEFINE_PCI_DEVICE_TABLE(dfx_pci_table) = { 3629 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) }, 3630 { } 3631 }; 3632 MODULE_DEVICE_TABLE(pci, dfx_pci_table); 3633 3634 static struct pci_driver dfx_pci_driver = { 3635 .name = "defxx", 3636 .id_table = dfx_pci_table, 3637 .probe = dfx_pci_register, 3638 .remove = dfx_pci_unregister, 3639 }; 3640 3641 static int dfx_pci_register(struct pci_dev *pdev, 3642 const struct pci_device_id *ent) 3643 { 3644 return dfx_register(&pdev->dev); 3645 } 3646 3647 static void dfx_pci_unregister(struct pci_dev *pdev) 3648 { 3649 dfx_unregister(&pdev->dev); 3650 } 3651 #endif /* CONFIG_PCI */ 3652 3653 #ifdef CONFIG_EISA 3654 static struct eisa_device_id dfx_eisa_table[] = { 3655 { "DEC3001", DEFEA_PROD_ID_1 }, 3656 { "DEC3002", DEFEA_PROD_ID_2 }, 3657 { "DEC3003", DEFEA_PROD_ID_3 }, 3658 { "DEC3004", DEFEA_PROD_ID_4 }, 3659 { } 3660 }; 3661 MODULE_DEVICE_TABLE(eisa, dfx_eisa_table); 3662 3663 static struct eisa_driver dfx_eisa_driver = { 3664 .id_table = dfx_eisa_table, 3665 .driver = { 3666 .name = "defxx", 3667 .bus = &eisa_bus_type, 3668 .probe = dfx_dev_register, 3669 .remove = dfx_dev_unregister, 3670 }, 3671 }; 3672 #endif /* CONFIG_EISA */ 3673 3674 #ifdef CONFIG_TC 3675 static struct tc_device_id const dfx_tc_table[] = { 3676 { "DEC ", "PMAF-FA " }, 3677 { "DEC ", "PMAF-FD " }, 3678 { "DEC ", "PMAF-FS " }, 3679 { "DEC ", "PMAF-FU " }, 3680 { } 3681 }; 3682 MODULE_DEVICE_TABLE(tc, dfx_tc_table); 3683 3684 static struct tc_driver dfx_tc_driver = { 3685 .id_table = dfx_tc_table, 3686 .driver = { 3687 .name = "defxx", 3688 .bus = &tc_bus_type, 3689 .probe = dfx_dev_register, 3690 .remove = dfx_dev_unregister, 3691 }, 3692 }; 3693 #endif /* CONFIG_TC */ 3694 3695 static int __maybe_unused dfx_dev_register(struct device *dev) 3696 { 3697 int status; 3698 3699 status = dfx_register(dev); 3700 if (!status) 3701 get_device(dev); 3702 return status; 3703 } 3704 3705 static int __maybe_unused dfx_dev_unregister(struct device *dev) 3706 { 3707 put_device(dev); 3708 dfx_unregister(dev); 3709 return 0; 3710 } 3711 3712 3713 static int dfx_init(void) 3714 { 3715 int status; 3716 3717 status = pci_register_driver(&dfx_pci_driver); 3718 if (!status) 3719 status = eisa_driver_register(&dfx_eisa_driver); 3720 if (!status) 3721 status = tc_register_driver(&dfx_tc_driver); 3722 return status; 3723 } 3724 3725 static void dfx_cleanup(void) 3726 { 3727 tc_unregister_driver(&dfx_tc_driver); 3728 eisa_driver_unregister(&dfx_eisa_driver); 3729 pci_unregister_driver(&dfx_pci_driver); 3730 } 3731 3732 module_init(dfx_init); 3733 module_exit(dfx_cleanup); 3734 MODULE_AUTHOR("Lawrence V. Stefani"); 3735 MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver " 3736 DRV_VERSION " " DRV_RELDATE); 3737 MODULE_LICENSE("GPL"); 3738