1 /* 2 * File Name: 3 * defxx.c 4 * 5 * Copyright Information: 6 * Copyright Digital Equipment Corporation 1996. 7 * 8 * This software may be used and distributed according to the terms of 9 * the GNU General Public License, incorporated herein by reference. 10 * 11 * Abstract: 12 * A Linux device driver supporting the Digital Equipment Corporation 13 * FDDI TURBOchannel, EISA and PCI controller families. Supported 14 * adapters include: 15 * 16 * DEC FDDIcontroller/TURBOchannel (DEFTA) 17 * DEC FDDIcontroller/EISA (DEFEA) 18 * DEC FDDIcontroller/PCI (DEFPA) 19 * 20 * The original author: 21 * LVS Lawrence V. Stefani <lstefani@yahoo.com> 22 * 23 * Maintainers: 24 * macro Maciej W. Rozycki <macro@linux-mips.org> 25 * 26 * Credits: 27 * I'd like to thank Patricia Cross for helping me get started with 28 * Linux, David Davies for a lot of help upgrading and configuring 29 * my development system and for answering many OS and driver 30 * development questions, and Alan Cox for recommendations and 31 * integration help on getting FDDI support into Linux. LVS 32 * 33 * Driver Architecture: 34 * The driver architecture is largely based on previous driver work 35 * for other operating systems. The upper edge interface and 36 * functions were largely taken from existing Linux device drivers 37 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C 38 * driver. 39 * 40 * Adapter Probe - 41 * The driver scans for supported EISA adapters by reading the 42 * SLOT ID register for each EISA slot and making a match 43 * against the expected value. 44 * 45 * Bus-Specific Initialization - 46 * This driver currently supports both EISA and PCI controller 47 * families. While the custom DMA chip and FDDI logic is similar 48 * or identical, the bus logic is very different. After 49 * initialization, the only bus-specific differences is in how the 50 * driver enables and disables interrupts. Other than that, the 51 * run-time critical code behaves the same on both families. 52 * It's important to note that both adapter families are configured 53 * to I/O map, rather than memory map, the adapter registers. 54 * 55 * Driver Open/Close - 56 * In the driver open routine, the driver ISR (interrupt service 57 * routine) is registered and the adapter is brought to an 58 * operational state. In the driver close routine, the opposite 59 * occurs; the driver ISR is deregistered and the adapter is 60 * brought to a safe, but closed state. Users may use consecutive 61 * commands to bring the adapter up and down as in the following 62 * example: 63 * ifconfig fddi0 up 64 * ifconfig fddi0 down 65 * ifconfig fddi0 up 66 * 67 * Driver Shutdown - 68 * Apparently, there is no shutdown or halt routine support under 69 * Linux. This routine would be called during "reboot" or 70 * "shutdown" to allow the driver to place the adapter in a safe 71 * state before a warm reboot occurs. To be really safe, the user 72 * should close the adapter before shutdown (eg. ifconfig fddi0 down) 73 * to ensure that the adapter DMA engine is taken off-line. However, 74 * the current driver code anticipates this problem and always issues 75 * a soft reset of the adapter at the beginning of driver initialization. 76 * A future driver enhancement in this area may occur in 2.1.X where 77 * Alan indicated that a shutdown handler may be implemented. 78 * 79 * Interrupt Service Routine - 80 * The driver supports shared interrupts, so the ISR is registered for 81 * each board with the appropriate flag and the pointer to that board's 82 * device structure. This provides the context during interrupt 83 * processing to support shared interrupts and multiple boards. 84 * 85 * Interrupt enabling/disabling can occur at many levels. At the host 86 * end, you can disable system interrupts, or disable interrupts at the 87 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters 88 * have a bus-logic chip interrupt enable/disable as well as a DMA 89 * controller interrupt enable/disable. 90 * 91 * The driver currently enables and disables adapter interrupts at the 92 * bus-logic chip and assumes that Linux will take care of clearing or 93 * acknowledging any host-based interrupt chips. 94 * 95 * Control Functions - 96 * Control functions are those used to support functions such as adding 97 * or deleting multicast addresses, enabling or disabling packet 98 * reception filters, or other custom/proprietary commands. Presently, 99 * the driver supports the "get statistics", "set multicast list", and 100 * "set mac address" functions defined by Linux. A list of possible 101 * enhancements include: 102 * 103 * - Custom ioctl interface for executing port interface commands 104 * - Custom ioctl interface for adding unicast addresses to 105 * adapter CAM (to support bridge functions). 106 * - Custom ioctl interface for supporting firmware upgrades. 107 * 108 * Hardware (port interface) Support Routines - 109 * The driver function names that start with "dfx_hw_" represent 110 * low-level port interface routines that are called frequently. They 111 * include issuing a DMA or port control command to the adapter, 112 * resetting the adapter, or reading the adapter state. Since the 113 * driver initialization and run-time code must make calls into the 114 * port interface, these routines were written to be as generic and 115 * usable as possible. 116 * 117 * Receive Path - 118 * The adapter DMA engine supports a 256 entry receive descriptor block 119 * of which up to 255 entries can be used at any given time. The 120 * architecture is a standard producer, consumer, completion model in 121 * which the driver "produces" receive buffers to the adapter, the 122 * adapter "consumes" the receive buffers by DMAing incoming packet data, 123 * and the driver "completes" the receive buffers by servicing the 124 * incoming packet, then "produces" a new buffer and starts the cycle 125 * again. Receive buffers can be fragmented in up to 16 fragments 126 * (descriptor entries). For simplicity, this driver posts 127 * single-fragment receive buffers of 4608 bytes, then allocates a 128 * sk_buff, copies the data, then reposts the buffer. To reduce CPU 129 * utilization, a better approach would be to pass up the receive 130 * buffer (no extra copy) then allocate and post a replacement buffer. 131 * This is a performance enhancement that should be looked into at 132 * some point. 133 * 134 * Transmit Path - 135 * Like the receive path, the adapter DMA engine supports a 256 entry 136 * transmit descriptor block of which up to 255 entries can be used at 137 * any given time. Transmit buffers can be fragmented in up to 255 138 * fragments (descriptor entries). This driver always posts one 139 * fragment per transmit packet request. 140 * 141 * The fragment contains the entire packet from FC to end of data. 142 * Before posting the buffer to the adapter, the driver sets a three-byte 143 * packet request header (PRH) which is required by the Motorola MAC chip 144 * used on the adapters. The PRH tells the MAC the type of token to 145 * receive/send, whether or not to generate and append the CRC, whether 146 * synchronous or asynchronous framing is used, etc. Since the PRH 147 * definition is not necessarily consistent across all FDDI chipsets, 148 * the driver, rather than the common FDDI packet handler routines, 149 * sets these bytes. 150 * 151 * To reduce the amount of descriptor fetches needed per transmit request, 152 * the driver takes advantage of the fact that there are at least three 153 * bytes available before the skb->data field on the outgoing transmit 154 * request. This is guaranteed by having fddi_setup() in net_init.c set 155 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest 156 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad" 157 * bytes which we'll use to store the PRH. 158 * 159 * There's a subtle advantage to adding these pad bytes to the 160 * hard_header_len, it ensures that the data portion of the packet for 161 * an 802.2 SNAP frame is longword aligned. Other FDDI driver 162 * implementations may not need the extra padding and can start copying 163 * or DMAing directly from the FC byte which starts at skb->data. Should 164 * another driver implementation need ADDITIONAL padding, the net_init.c 165 * module should be updated and dev->hard_header_len should be increased. 166 * NOTE: To maintain the alignment on the data portion of the packet, 167 * dev->hard_header_len should always be evenly divisible by 4 and at 168 * least 24 bytes in size. 169 * 170 * Modification History: 171 * Date Name Description 172 * 16-Aug-96 LVS Created. 173 * 20-Aug-96 LVS Updated dfx_probe so that version information 174 * string is only displayed if 1 or more cards are 175 * found. Changed dfx_rcv_queue_process to copy 176 * 3 NULL bytes before FC to ensure that data is 177 * longword aligned in receive buffer. 178 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable 179 * LLC group promiscuous mode if multicast list 180 * is too large. LLC individual/group promiscuous 181 * mode is now disabled if IFF_PROMISC flag not set. 182 * dfx_xmt_queue_pkt no longer checks for NULL skb 183 * on Alan Cox recommendation. Added node address 184 * override support. 185 * 12-Sep-96 LVS Reset current address to factory address during 186 * device open. Updated transmit path to post a 187 * single fragment which includes PRH->end of data. 188 * Mar 2000 AC Did various cleanups for 2.3.x 189 * Jun 2000 jgarzik PCI and resource alloc cleanups 190 * Jul 2000 tjeerd Much cleanup and some bug fixes 191 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup 192 * Feb 2001 Skb allocation fixes 193 * Feb 2001 davej PCI enable cleanups. 194 * 04 Aug 2003 macro Converted to the DMA API. 195 * 14 Aug 2004 macro Fix device names reported. 196 * 14 Jun 2005 macro Use irqreturn_t. 197 * 23 Oct 2006 macro Big-endian host support. 198 * 14 Dec 2006 macro TURBOchannel support. 199 */ 200 201 /* Include files */ 202 #include <linux/bitops.h> 203 #include <linux/compiler.h> 204 #include <linux/delay.h> 205 #include <linux/dma-mapping.h> 206 #include <linux/eisa.h> 207 #include <linux/errno.h> 208 #include <linux/fddidevice.h> 209 #include <linux/init.h> 210 #include <linux/interrupt.h> 211 #include <linux/ioport.h> 212 #include <linux/kernel.h> 213 #include <linux/module.h> 214 #include <linux/netdevice.h> 215 #include <linux/pci.h> 216 #include <linux/skbuff.h> 217 #include <linux/slab.h> 218 #include <linux/string.h> 219 #include <linux/tc.h> 220 221 #include <asm/byteorder.h> 222 #include <asm/io.h> 223 224 #include "defxx.h" 225 226 /* Version information string should be updated prior to each new release! */ 227 #define DRV_NAME "defxx" 228 #define DRV_VERSION "v1.10" 229 #define DRV_RELDATE "2006/12/14" 230 231 static char version[] = 232 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE 233 " Lawrence V. Stefani and others\n"; 234 235 #define DYNAMIC_BUFFERS 1 236 237 #define SKBUFF_RX_COPYBREAK 200 238 /* 239 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte 240 * alignment for compatibility with old EISA boards. 241 */ 242 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128) 243 244 #ifdef CONFIG_EISA 245 #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type) 246 #else 247 #define DFX_BUS_EISA(dev) 0 248 #endif 249 250 #ifdef CONFIG_TC 251 #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type) 252 #else 253 #define DFX_BUS_TC(dev) 0 254 #endif 255 256 #ifdef CONFIG_DEFXX_MMIO 257 #define DFX_MMIO 1 258 #else 259 #define DFX_MMIO 0 260 #endif 261 262 /* Define module-wide (static) routines */ 263 264 static void dfx_bus_init(struct net_device *dev); 265 static void dfx_bus_uninit(struct net_device *dev); 266 static void dfx_bus_config_check(DFX_board_t *bp); 267 268 static int dfx_driver_init(struct net_device *dev, 269 const char *print_name, 270 resource_size_t bar_start); 271 static int dfx_adap_init(DFX_board_t *bp, int get_buffers); 272 273 static int dfx_open(struct net_device *dev); 274 static int dfx_close(struct net_device *dev); 275 276 static void dfx_int_pr_halt_id(DFX_board_t *bp); 277 static void dfx_int_type_0_process(DFX_board_t *bp); 278 static void dfx_int_common(struct net_device *dev); 279 static irqreturn_t dfx_interrupt(int irq, void *dev_id); 280 281 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev); 282 static void dfx_ctl_set_multicast_list(struct net_device *dev); 283 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr); 284 static int dfx_ctl_update_cam(DFX_board_t *bp); 285 static int dfx_ctl_update_filters(DFX_board_t *bp); 286 287 static int dfx_hw_dma_cmd_req(DFX_board_t *bp); 288 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data); 289 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type); 290 static int dfx_hw_adap_state_rd(DFX_board_t *bp); 291 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type); 292 293 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers); 294 static void dfx_rcv_queue_process(DFX_board_t *bp); 295 static void dfx_rcv_flush(DFX_board_t *bp); 296 297 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 298 struct net_device *dev); 299 static int dfx_xmt_done(DFX_board_t *bp); 300 static void dfx_xmt_flush(DFX_board_t *bp); 301 302 /* Define module-wide (static) variables */ 303 304 static struct pci_driver dfx_pci_driver; 305 static struct eisa_driver dfx_eisa_driver; 306 static struct tc_driver dfx_tc_driver; 307 308 309 /* 310 * ======================= 311 * = dfx_port_write_long = 312 * = dfx_port_read_long = 313 * ======================= 314 * 315 * Overview: 316 * Routines for reading and writing values from/to adapter 317 * 318 * Returns: 319 * None 320 * 321 * Arguments: 322 * bp - pointer to board information 323 * offset - register offset from base I/O address 324 * data - for dfx_port_write_long, this is a value to write; 325 * for dfx_port_read_long, this is a pointer to store 326 * the read value 327 * 328 * Functional Description: 329 * These routines perform the correct operation to read or write 330 * the adapter register. 331 * 332 * EISA port block base addresses are based on the slot number in which the 333 * controller is installed. For example, if the EISA controller is installed 334 * in slot 4, the port block base address is 0x4000. If the controller is 335 * installed in slot 2, the port block base address is 0x2000, and so on. 336 * This port block can be used to access PDQ, ESIC, and DEFEA on-board 337 * registers using the register offsets defined in DEFXX.H. 338 * 339 * PCI port block base addresses are assigned by the PCI BIOS or system 340 * firmware. There is one 128 byte port block which can be accessed. It 341 * allows for I/O mapping of both PDQ and PFI registers using the register 342 * offsets defined in DEFXX.H. 343 * 344 * Return Codes: 345 * None 346 * 347 * Assumptions: 348 * bp->base is a valid base I/O address for this adapter. 349 * offset is a valid register offset for this adapter. 350 * 351 * Side Effects: 352 * Rather than produce macros for these functions, these routines 353 * are defined using "inline" to ensure that the compiler will 354 * generate inline code and not waste a procedure call and return. 355 * This provides all the benefits of macros, but with the 356 * advantage of strict data type checking. 357 */ 358 359 static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data) 360 { 361 writel(data, bp->base.mem + offset); 362 mb(); 363 } 364 365 static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data) 366 { 367 outl(data, bp->base.port + offset); 368 } 369 370 static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data) 371 { 372 struct device __maybe_unused *bdev = bp->bus_dev; 373 int dfx_bus_tc = DFX_BUS_TC(bdev); 374 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 375 376 if (dfx_use_mmio) 377 dfx_writel(bp, offset, data); 378 else 379 dfx_outl(bp, offset, data); 380 } 381 382 383 static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data) 384 { 385 mb(); 386 *data = readl(bp->base.mem + offset); 387 } 388 389 static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data) 390 { 391 *data = inl(bp->base.port + offset); 392 } 393 394 static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data) 395 { 396 struct device __maybe_unused *bdev = bp->bus_dev; 397 int dfx_bus_tc = DFX_BUS_TC(bdev); 398 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 399 400 if (dfx_use_mmio) 401 dfx_readl(bp, offset, data); 402 else 403 dfx_inl(bp, offset, data); 404 } 405 406 407 /* 408 * ================ 409 * = dfx_get_bars = 410 * ================ 411 * 412 * Overview: 413 * Retrieves the address range used to access control and status 414 * registers. 415 * 416 * Returns: 417 * None 418 * 419 * Arguments: 420 * bdev - pointer to device information 421 * bar_start - pointer to store the start address 422 * bar_len - pointer to store the length of the area 423 * 424 * Assumptions: 425 * I am sure there are some. 426 * 427 * Side Effects: 428 * None 429 */ 430 static void dfx_get_bars(struct device *bdev, 431 resource_size_t *bar_start, resource_size_t *bar_len) 432 { 433 int dfx_bus_pci = dev_is_pci(bdev); 434 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 435 int dfx_bus_tc = DFX_BUS_TC(bdev); 436 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 437 438 if (dfx_bus_pci) { 439 int num = dfx_use_mmio ? 0 : 1; 440 441 *bar_start = pci_resource_start(to_pci_dev(bdev), num); 442 *bar_len = pci_resource_len(to_pci_dev(bdev), num); 443 } 444 if (dfx_bus_eisa) { 445 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 446 resource_size_t bar; 447 448 if (dfx_use_mmio) { 449 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2); 450 bar <<= 8; 451 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1); 452 bar <<= 8; 453 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0); 454 bar <<= 16; 455 *bar_start = bar; 456 bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2); 457 bar <<= 8; 458 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1); 459 bar <<= 8; 460 bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0); 461 bar <<= 16; 462 *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1; 463 } else { 464 *bar_start = base_addr; 465 *bar_len = PI_ESIC_K_CSR_IO_LEN; 466 } 467 } 468 if (dfx_bus_tc) { 469 *bar_start = to_tc_dev(bdev)->resource.start + 470 PI_TC_K_CSR_OFFSET; 471 *bar_len = PI_TC_K_CSR_LEN; 472 } 473 } 474 475 static const struct net_device_ops dfx_netdev_ops = { 476 .ndo_open = dfx_open, 477 .ndo_stop = dfx_close, 478 .ndo_start_xmit = dfx_xmt_queue_pkt, 479 .ndo_get_stats = dfx_ctl_get_stats, 480 .ndo_set_rx_mode = dfx_ctl_set_multicast_list, 481 .ndo_set_mac_address = dfx_ctl_set_mac_address, 482 }; 483 484 /* 485 * ================ 486 * = dfx_register = 487 * ================ 488 * 489 * Overview: 490 * Initializes a supported FDDI controller 491 * 492 * Returns: 493 * Condition code 494 * 495 * Arguments: 496 * bdev - pointer to device information 497 * 498 * Functional Description: 499 * 500 * Return Codes: 501 * 0 - This device (fddi0, fddi1, etc) configured successfully 502 * -EBUSY - Failed to get resources, or dfx_driver_init failed. 503 * 504 * Assumptions: 505 * It compiles so it should work :-( (PCI cards do :-) 506 * 507 * Side Effects: 508 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 509 * initialized and the board resources are read and stored in 510 * the device structure. 511 */ 512 static int dfx_register(struct device *bdev) 513 { 514 static int version_disp; 515 int dfx_bus_pci = dev_is_pci(bdev); 516 int dfx_bus_tc = DFX_BUS_TC(bdev); 517 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 518 const char *print_name = dev_name(bdev); 519 struct net_device *dev; 520 DFX_board_t *bp; /* board pointer */ 521 resource_size_t bar_start = 0; /* pointer to port */ 522 resource_size_t bar_len = 0; /* resource length */ 523 int alloc_size; /* total buffer size used */ 524 struct resource *region; 525 int err = 0; 526 527 if (!version_disp) { /* display version info if adapter is found */ 528 version_disp = 1; /* set display flag to TRUE so that */ 529 printk(version); /* we only display this string ONCE */ 530 } 531 532 dev = alloc_fddidev(sizeof(*bp)); 533 if (!dev) { 534 printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n", 535 print_name); 536 return -ENOMEM; 537 } 538 539 /* Enable PCI device. */ 540 if (dfx_bus_pci && pci_enable_device(to_pci_dev(bdev))) { 541 printk(KERN_ERR "%s: Cannot enable PCI device, aborting\n", 542 print_name); 543 goto err_out; 544 } 545 546 SET_NETDEV_DEV(dev, bdev); 547 548 bp = netdev_priv(dev); 549 bp->bus_dev = bdev; 550 dev_set_drvdata(bdev, dev); 551 552 dfx_get_bars(bdev, &bar_start, &bar_len); 553 554 if (dfx_use_mmio) 555 region = request_mem_region(bar_start, bar_len, print_name); 556 else 557 region = request_region(bar_start, bar_len, print_name); 558 if (!region) { 559 printk(KERN_ERR "%s: Cannot reserve I/O resource " 560 "0x%lx @ 0x%lx, aborting\n", 561 print_name, (long)bar_len, (long)bar_start); 562 err = -EBUSY; 563 goto err_out_disable; 564 } 565 566 /* Set up I/O base address. */ 567 if (dfx_use_mmio) { 568 bp->base.mem = ioremap_nocache(bar_start, bar_len); 569 if (!bp->base.mem) { 570 printk(KERN_ERR "%s: Cannot map MMIO\n", print_name); 571 err = -ENOMEM; 572 goto err_out_region; 573 } 574 } else { 575 bp->base.port = bar_start; 576 dev->base_addr = bar_start; 577 } 578 579 /* Initialize new device structure */ 580 dev->netdev_ops = &dfx_netdev_ops; 581 582 if (dfx_bus_pci) 583 pci_set_master(to_pci_dev(bdev)); 584 585 if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) { 586 err = -ENODEV; 587 goto err_out_unmap; 588 } 589 590 err = register_netdev(dev); 591 if (err) 592 goto err_out_kfree; 593 594 printk("%s: registered as %s\n", print_name, dev->name); 595 return 0; 596 597 err_out_kfree: 598 alloc_size = sizeof(PI_DESCR_BLOCK) + 599 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 600 #ifndef DYNAMIC_BUFFERS 601 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 602 #endif 603 sizeof(PI_CONSUMER_BLOCK) + 604 (PI_ALIGN_K_DESC_BLK - 1); 605 if (bp->kmalloced) 606 dma_free_coherent(bdev, alloc_size, 607 bp->kmalloced, bp->kmalloced_dma); 608 609 err_out_unmap: 610 if (dfx_use_mmio) 611 iounmap(bp->base.mem); 612 613 err_out_region: 614 if (dfx_use_mmio) 615 release_mem_region(bar_start, bar_len); 616 else 617 release_region(bar_start, bar_len); 618 619 err_out_disable: 620 if (dfx_bus_pci) 621 pci_disable_device(to_pci_dev(bdev)); 622 623 err_out: 624 free_netdev(dev); 625 return err; 626 } 627 628 629 /* 630 * ================ 631 * = dfx_bus_init = 632 * ================ 633 * 634 * Overview: 635 * Initializes the bus-specific controller logic. 636 * 637 * Returns: 638 * None 639 * 640 * Arguments: 641 * dev - pointer to device information 642 * 643 * Functional Description: 644 * Determine and save adapter IRQ in device table, 645 * then perform bus-specific logic initialization. 646 * 647 * Return Codes: 648 * None 649 * 650 * Assumptions: 651 * bp->base has already been set with the proper 652 * base I/O address for this device. 653 * 654 * Side Effects: 655 * Interrupts are enabled at the adapter bus-specific logic. 656 * Note: Interrupts at the DMA engine (PDQ chip) are not 657 * enabled yet. 658 */ 659 660 static void dfx_bus_init(struct net_device *dev) 661 { 662 DFX_board_t *bp = netdev_priv(dev); 663 struct device *bdev = bp->bus_dev; 664 int dfx_bus_pci = dev_is_pci(bdev); 665 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 666 int dfx_bus_tc = DFX_BUS_TC(bdev); 667 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 668 u8 val; 669 670 DBG_printk("In dfx_bus_init...\n"); 671 672 /* Initialize a pointer back to the net_device struct */ 673 bp->dev = dev; 674 675 /* Initialize adapter based on bus type */ 676 677 if (dfx_bus_tc) 678 dev->irq = to_tc_dev(bdev)->interrupt; 679 if (dfx_bus_eisa) { 680 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 681 682 /* Get the interrupt level from the ESIC chip. */ 683 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 684 val &= PI_CONFIG_STAT_0_M_IRQ; 685 val >>= PI_CONFIG_STAT_0_V_IRQ; 686 687 switch (val) { 688 case PI_CONFIG_STAT_0_IRQ_K_9: 689 dev->irq = 9; 690 break; 691 692 case PI_CONFIG_STAT_0_IRQ_K_10: 693 dev->irq = 10; 694 break; 695 696 case PI_CONFIG_STAT_0_IRQ_K_11: 697 dev->irq = 11; 698 break; 699 700 case PI_CONFIG_STAT_0_IRQ_K_15: 701 dev->irq = 15; 702 break; 703 } 704 705 /* 706 * Enable memory decoding (MEMCS0) and/or port decoding 707 * (IOCS1/IOCS0) as appropriate in Function Control 708 * Register. One of the port chip selects seems to be 709 * used for the Burst Holdoff register, but this bit of 710 * documentation is missing and as yet it has not been 711 * determined which of the two. This is also the reason 712 * the size of the decoded port range is twice as large 713 * as one required by the PDQ. 714 */ 715 716 /* Set the decode range of the board. */ 717 val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT); 718 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val); 719 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0); 720 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val); 721 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0); 722 val = PI_ESIC_K_CSR_IO_LEN - 1; 723 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff); 724 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff); 725 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff); 726 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff); 727 728 /* Enable the decoders. */ 729 val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0; 730 if (dfx_use_mmio) 731 val |= PI_FUNCTION_CNTRL_M_MEMCS0; 732 outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val); 733 734 /* 735 * Enable access to the rest of the module 736 * (including PDQ and packet memory). 737 */ 738 val = PI_SLOT_CNTRL_M_ENB; 739 outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val); 740 741 /* 742 * Map PDQ registers into memory or port space. This is 743 * done with a bit in the Burst Holdoff register. 744 */ 745 val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF); 746 if (dfx_use_mmio) 747 val |= PI_BURST_HOLDOFF_V_MEM_MAP; 748 else 749 val &= ~PI_BURST_HOLDOFF_V_MEM_MAP; 750 outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val); 751 752 /* Enable interrupts at EISA bus interface chip (ESIC) */ 753 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 754 val |= PI_CONFIG_STAT_0_M_INT_ENB; 755 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 756 } 757 if (dfx_bus_pci) { 758 struct pci_dev *pdev = to_pci_dev(bdev); 759 760 /* Get the interrupt level from the PCI Configuration Table */ 761 762 dev->irq = pdev->irq; 763 764 /* Check Latency Timer and set if less than minimal */ 765 766 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); 767 if (val < PFI_K_LAT_TIMER_MIN) { 768 val = PFI_K_LAT_TIMER_DEF; 769 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val); 770 } 771 772 /* Enable interrupts at PCI bus interface chip (PFI) */ 773 val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB; 774 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val); 775 } 776 } 777 778 /* 779 * ================== 780 * = dfx_bus_uninit = 781 * ================== 782 * 783 * Overview: 784 * Uninitializes the bus-specific controller logic. 785 * 786 * Returns: 787 * None 788 * 789 * Arguments: 790 * dev - pointer to device information 791 * 792 * Functional Description: 793 * Perform bus-specific logic uninitialization. 794 * 795 * Return Codes: 796 * None 797 * 798 * Assumptions: 799 * bp->base has already been set with the proper 800 * base I/O address for this device. 801 * 802 * Side Effects: 803 * Interrupts are disabled at the adapter bus-specific logic. 804 */ 805 806 static void dfx_bus_uninit(struct net_device *dev) 807 { 808 DFX_board_t *bp = netdev_priv(dev); 809 struct device *bdev = bp->bus_dev; 810 int dfx_bus_pci = dev_is_pci(bdev); 811 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 812 u8 val; 813 814 DBG_printk("In dfx_bus_uninit...\n"); 815 816 /* Uninitialize adapter based on bus type */ 817 818 if (dfx_bus_eisa) { 819 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 820 821 /* Disable interrupts at EISA bus interface chip (ESIC) */ 822 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 823 val &= ~PI_CONFIG_STAT_0_M_INT_ENB; 824 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val); 825 } 826 if (dfx_bus_pci) { 827 /* Disable interrupts at PCI bus interface chip (PFI) */ 828 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0); 829 } 830 } 831 832 833 /* 834 * ======================== 835 * = dfx_bus_config_check = 836 * ======================== 837 * 838 * Overview: 839 * Checks the configuration (burst size, full-duplex, etc.) If any parameters 840 * are illegal, then this routine will set new defaults. 841 * 842 * Returns: 843 * None 844 * 845 * Arguments: 846 * bp - pointer to board information 847 * 848 * Functional Description: 849 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later 850 * PDQ, and all FDDI PCI controllers, all values are legal. 851 * 852 * Return Codes: 853 * None 854 * 855 * Assumptions: 856 * dfx_adap_init has NOT been called yet so burst size and other items have 857 * not been set. 858 * 859 * Side Effects: 860 * None 861 */ 862 863 static void dfx_bus_config_check(DFX_board_t *bp) 864 { 865 struct device __maybe_unused *bdev = bp->bus_dev; 866 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 867 int status; /* return code from adapter port control call */ 868 u32 host_data; /* LW data returned from port control call */ 869 870 DBG_printk("In dfx_bus_config_check...\n"); 871 872 /* Configuration check only valid for EISA adapter */ 873 874 if (dfx_bus_eisa) { 875 /* 876 * First check if revision 2 EISA controller. Rev. 1 cards used 877 * PDQ revision B, so no workaround needed in this case. Rev. 3 878 * cards used PDQ revision E, so no workaround needed in this 879 * case, either. Only Rev. 2 cards used either Rev. D or E 880 * chips, so we must verify the chip revision on Rev. 2 cards. 881 */ 882 if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) { 883 /* 884 * Revision 2 FDDI EISA controller found, 885 * so let's check PDQ revision of adapter. 886 */ 887 status = dfx_hw_port_ctrl_req(bp, 888 PI_PCTRL_M_SUB_CMD, 889 PI_SUB_CMD_K_PDQ_REV_GET, 890 0, 891 &host_data); 892 if ((status != DFX_K_SUCCESS) || (host_data == 2)) 893 { 894 /* 895 * Either we couldn't determine the PDQ revision, or 896 * we determined that it is at revision D. In either case, 897 * we need to implement the workaround. 898 */ 899 900 /* Ensure that the burst size is set to 8 longwords or less */ 901 902 switch (bp->burst_size) 903 { 904 case PI_PDATA_B_DMA_BURST_SIZE_32: 905 case PI_PDATA_B_DMA_BURST_SIZE_16: 906 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8; 907 break; 908 909 default: 910 break; 911 } 912 913 /* Ensure that full-duplex mode is not enabled */ 914 915 bp->full_duplex_enb = PI_SNMP_K_FALSE; 916 } 917 } 918 } 919 } 920 921 922 /* 923 * =================== 924 * = dfx_driver_init = 925 * =================== 926 * 927 * Overview: 928 * Initializes remaining adapter board structure information 929 * and makes sure adapter is in a safe state prior to dfx_open(). 930 * 931 * Returns: 932 * Condition code 933 * 934 * Arguments: 935 * dev - pointer to device information 936 * print_name - printable device name 937 * 938 * Functional Description: 939 * This function allocates additional resources such as the host memory 940 * blocks needed by the adapter (eg. descriptor and consumer blocks). 941 * Remaining bus initialization steps are also completed. The adapter 942 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS 943 * must call dfx_open() to open the adapter and bring it on-line. 944 * 945 * Return Codes: 946 * DFX_K_SUCCESS - initialization succeeded 947 * DFX_K_FAILURE - initialization failed - could not allocate memory 948 * or read adapter MAC address 949 * 950 * Assumptions: 951 * Memory allocated from pci_alloc_consistent() call is physically 952 * contiguous, locked memory. 953 * 954 * Side Effects: 955 * Adapter is reset and should be in DMA_UNAVAILABLE state before 956 * returning from this routine. 957 */ 958 959 static int dfx_driver_init(struct net_device *dev, const char *print_name, 960 resource_size_t bar_start) 961 { 962 DFX_board_t *bp = netdev_priv(dev); 963 struct device *bdev = bp->bus_dev; 964 int dfx_bus_pci = dev_is_pci(bdev); 965 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 966 int dfx_bus_tc = DFX_BUS_TC(bdev); 967 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 968 int alloc_size; /* total buffer size needed */ 969 char *top_v, *curr_v; /* virtual addrs into memory block */ 970 dma_addr_t top_p, curr_p; /* physical addrs into memory block */ 971 u32 data; /* host data register value */ 972 __le32 le32; 973 char *board_name = NULL; 974 975 DBG_printk("In dfx_driver_init...\n"); 976 977 /* Initialize bus-specific hardware registers */ 978 979 dfx_bus_init(dev); 980 981 /* 982 * Initialize default values for configurable parameters 983 * 984 * Note: All of these parameters are ones that a user may 985 * want to customize. It'd be nice to break these 986 * out into Space.c or someplace else that's more 987 * accessible/understandable than this file. 988 */ 989 990 bp->full_duplex_enb = PI_SNMP_K_FALSE; 991 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */ 992 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF; 993 bp->rcv_bufs_to_post = RCV_BUFS_DEF; 994 995 /* 996 * Ensure that HW configuration is OK 997 * 998 * Note: Depending on the hardware revision, we may need to modify 999 * some of the configurable parameters to workaround hardware 1000 * limitations. We'll perform this configuration check AFTER 1001 * setting the parameters to their default values. 1002 */ 1003 1004 dfx_bus_config_check(bp); 1005 1006 /* Disable PDQ interrupts first */ 1007 1008 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1009 1010 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1011 1012 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1013 1014 /* Read the factory MAC address from the adapter then save it */ 1015 1016 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0, 1017 &data) != DFX_K_SUCCESS) { 1018 printk("%s: Could not read adapter factory MAC address!\n", 1019 print_name); 1020 return DFX_K_FAILURE; 1021 } 1022 le32 = cpu_to_le32(data); 1023 memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32)); 1024 1025 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0, 1026 &data) != DFX_K_SUCCESS) { 1027 printk("%s: Could not read adapter factory MAC address!\n", 1028 print_name); 1029 return DFX_K_FAILURE; 1030 } 1031 le32 = cpu_to_le32(data); 1032 memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16)); 1033 1034 /* 1035 * Set current address to factory address 1036 * 1037 * Note: Node address override support is handled through 1038 * dfx_ctl_set_mac_address. 1039 */ 1040 1041 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1042 if (dfx_bus_tc) 1043 board_name = "DEFTA"; 1044 if (dfx_bus_eisa) 1045 board_name = "DEFEA"; 1046 if (dfx_bus_pci) 1047 board_name = "DEFPA"; 1048 pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, Hardware addr = %pMF\n", 1049 print_name, board_name, dfx_use_mmio ? "" : "I/O ", 1050 (long long)bar_start, dev->irq, dev->dev_addr); 1051 1052 /* 1053 * Get memory for descriptor block, consumer block, and other buffers 1054 * that need to be DMA read or written to by the adapter. 1055 */ 1056 1057 alloc_size = sizeof(PI_DESCR_BLOCK) + 1058 PI_CMD_REQ_K_SIZE_MAX + 1059 PI_CMD_RSP_K_SIZE_MAX + 1060 #ifndef DYNAMIC_BUFFERS 1061 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 1062 #endif 1063 sizeof(PI_CONSUMER_BLOCK) + 1064 (PI_ALIGN_K_DESC_BLK - 1); 1065 bp->kmalloced = top_v = dma_zalloc_coherent(bp->bus_dev, alloc_size, 1066 &bp->kmalloced_dma, 1067 GFP_ATOMIC); 1068 if (top_v == NULL) 1069 return DFX_K_FAILURE; 1070 1071 top_p = bp->kmalloced_dma; /* get physical address of buffer */ 1072 1073 /* 1074 * To guarantee the 8K alignment required for the descriptor block, 8K - 1 1075 * plus the amount of memory needed was allocated. The physical address 1076 * is now 8K aligned. By carving up the memory in a specific order, 1077 * we'll guarantee the alignment requirements for all other structures. 1078 * 1079 * Note: If the assumptions change regarding the non-paged, non-cached, 1080 * physically contiguous nature of the memory block or the address 1081 * alignments, then we'll need to implement a different algorithm 1082 * for allocating the needed memory. 1083 */ 1084 1085 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK); 1086 curr_v = top_v + (curr_p - top_p); 1087 1088 /* Reserve space for descriptor block */ 1089 1090 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v; 1091 bp->descr_block_phys = curr_p; 1092 curr_v += sizeof(PI_DESCR_BLOCK); 1093 curr_p += sizeof(PI_DESCR_BLOCK); 1094 1095 /* Reserve space for command request buffer */ 1096 1097 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v; 1098 bp->cmd_req_phys = curr_p; 1099 curr_v += PI_CMD_REQ_K_SIZE_MAX; 1100 curr_p += PI_CMD_REQ_K_SIZE_MAX; 1101 1102 /* Reserve space for command response buffer */ 1103 1104 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v; 1105 bp->cmd_rsp_phys = curr_p; 1106 curr_v += PI_CMD_RSP_K_SIZE_MAX; 1107 curr_p += PI_CMD_RSP_K_SIZE_MAX; 1108 1109 /* Reserve space for the LLC host receive queue buffers */ 1110 1111 bp->rcv_block_virt = curr_v; 1112 bp->rcv_block_phys = curr_p; 1113 1114 #ifndef DYNAMIC_BUFFERS 1115 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1116 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX); 1117 #endif 1118 1119 /* Reserve space for the consumer block */ 1120 1121 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v; 1122 bp->cons_block_phys = curr_p; 1123 1124 /* Display virtual and physical addresses if debug driver */ 1125 1126 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n", 1127 print_name, 1128 (long)bp->descr_block_virt, bp->descr_block_phys); 1129 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n", 1130 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys); 1131 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n", 1132 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys); 1133 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n", 1134 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys); 1135 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n", 1136 print_name, (long)bp->cons_block_virt, bp->cons_block_phys); 1137 1138 return DFX_K_SUCCESS; 1139 } 1140 1141 1142 /* 1143 * ================= 1144 * = dfx_adap_init = 1145 * ================= 1146 * 1147 * Overview: 1148 * Brings the adapter to the link avail/link unavailable state. 1149 * 1150 * Returns: 1151 * Condition code 1152 * 1153 * Arguments: 1154 * bp - pointer to board information 1155 * get_buffers - non-zero if buffers to be allocated 1156 * 1157 * Functional Description: 1158 * Issues the low-level firmware/hardware calls necessary to bring 1159 * the adapter up, or to properly reset and restore adapter during 1160 * run-time. 1161 * 1162 * Return Codes: 1163 * DFX_K_SUCCESS - Adapter brought up successfully 1164 * DFX_K_FAILURE - Adapter initialization failed 1165 * 1166 * Assumptions: 1167 * bp->reset_type should be set to a valid reset type value before 1168 * calling this routine. 1169 * 1170 * Side Effects: 1171 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1172 * upon a successful return of this routine. 1173 */ 1174 1175 static int dfx_adap_init(DFX_board_t *bp, int get_buffers) 1176 { 1177 DBG_printk("In dfx_adap_init...\n"); 1178 1179 /* Disable PDQ interrupts first */ 1180 1181 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1182 1183 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1184 1185 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS) 1186 { 1187 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name); 1188 return DFX_K_FAILURE; 1189 } 1190 1191 /* 1192 * When the PDQ is reset, some false Type 0 interrupts may be pending, 1193 * so we'll acknowledge all Type 0 interrupts now before continuing. 1194 */ 1195 1196 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0); 1197 1198 /* 1199 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state 1200 * 1201 * Note: We only need to clear host copies of these registers. The PDQ reset 1202 * takes care of the on-board register values. 1203 */ 1204 1205 bp->cmd_req_reg.lword = 0; 1206 bp->cmd_rsp_reg.lword = 0; 1207 bp->rcv_xmt_reg.lword = 0; 1208 1209 /* Clear consumer block before going to DMA_AVAILABLE state */ 1210 1211 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1212 1213 /* Initialize the DMA Burst Size */ 1214 1215 if (dfx_hw_port_ctrl_req(bp, 1216 PI_PCTRL_M_SUB_CMD, 1217 PI_SUB_CMD_K_BURST_SIZE_SET, 1218 bp->burst_size, 1219 NULL) != DFX_K_SUCCESS) 1220 { 1221 printk("%s: Could not set adapter burst size!\n", bp->dev->name); 1222 return DFX_K_FAILURE; 1223 } 1224 1225 /* 1226 * Set base address of Consumer Block 1227 * 1228 * Assumption: 32-bit physical address of consumer block is 64 byte 1229 * aligned. That is, bits 0-5 of the address must be zero. 1230 */ 1231 1232 if (dfx_hw_port_ctrl_req(bp, 1233 PI_PCTRL_M_CONS_BLOCK, 1234 bp->cons_block_phys, 1235 0, 1236 NULL) != DFX_K_SUCCESS) 1237 { 1238 printk("%s: Could not set consumer block address!\n", bp->dev->name); 1239 return DFX_K_FAILURE; 1240 } 1241 1242 /* 1243 * Set the base address of Descriptor Block and bring adapter 1244 * to DMA_AVAILABLE state. 1245 * 1246 * Note: We also set the literal and data swapping requirements 1247 * in this command. 1248 * 1249 * Assumption: 32-bit physical address of descriptor block 1250 * is 8Kbyte aligned. 1251 */ 1252 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT, 1253 (u32)(bp->descr_block_phys | 1254 PI_PDATA_A_INIT_M_BSWAP_INIT), 1255 0, NULL) != DFX_K_SUCCESS) { 1256 printk("%s: Could not set descriptor block address!\n", 1257 bp->dev->name); 1258 return DFX_K_FAILURE; 1259 } 1260 1261 /* Set transmit flush timeout value */ 1262 1263 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET; 1264 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME; 1265 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */ 1266 bp->cmd_req_virt->char_set.item[0].item_index = 0; 1267 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL; 1268 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1269 { 1270 printk("%s: DMA command request failed!\n", bp->dev->name); 1271 return DFX_K_FAILURE; 1272 } 1273 1274 /* Set the initial values for eFDXEnable and MACTReq MIB objects */ 1275 1276 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET; 1277 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS; 1278 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb; 1279 bp->cmd_req_virt->snmp_set.item[0].item_index = 0; 1280 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ; 1281 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt; 1282 bp->cmd_req_virt->snmp_set.item[1].item_index = 0; 1283 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL; 1284 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1285 { 1286 printk("%s: DMA command request failed!\n", bp->dev->name); 1287 return DFX_K_FAILURE; 1288 } 1289 1290 /* Initialize adapter CAM */ 1291 1292 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 1293 { 1294 printk("%s: Adapter CAM update failed!\n", bp->dev->name); 1295 return DFX_K_FAILURE; 1296 } 1297 1298 /* Initialize adapter filters */ 1299 1300 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 1301 { 1302 printk("%s: Adapter filters update failed!\n", bp->dev->name); 1303 return DFX_K_FAILURE; 1304 } 1305 1306 /* 1307 * Remove any existing dynamic buffers (i.e. if the adapter is being 1308 * reinitialized) 1309 */ 1310 1311 if (get_buffers) 1312 dfx_rcv_flush(bp); 1313 1314 /* Initialize receive descriptor block and produce buffers */ 1315 1316 if (dfx_rcv_init(bp, get_buffers)) 1317 { 1318 printk("%s: Receive buffer allocation failed\n", bp->dev->name); 1319 if (get_buffers) 1320 dfx_rcv_flush(bp); 1321 return DFX_K_FAILURE; 1322 } 1323 1324 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */ 1325 1326 bp->cmd_req_virt->cmd_type = PI_CMD_K_START; 1327 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 1328 { 1329 printk("%s: Start command failed\n", bp->dev->name); 1330 if (get_buffers) 1331 dfx_rcv_flush(bp); 1332 return DFX_K_FAILURE; 1333 } 1334 1335 /* Initialization succeeded, reenable PDQ interrupts */ 1336 1337 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS); 1338 return DFX_K_SUCCESS; 1339 } 1340 1341 1342 /* 1343 * ============ 1344 * = dfx_open = 1345 * ============ 1346 * 1347 * Overview: 1348 * Opens the adapter 1349 * 1350 * Returns: 1351 * Condition code 1352 * 1353 * Arguments: 1354 * dev - pointer to device information 1355 * 1356 * Functional Description: 1357 * This function brings the adapter to an operational state. 1358 * 1359 * Return Codes: 1360 * 0 - Adapter was successfully opened 1361 * -EAGAIN - Could not register IRQ or adapter initialization failed 1362 * 1363 * Assumptions: 1364 * This routine should only be called for a device that was 1365 * initialized successfully. 1366 * 1367 * Side Effects: 1368 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state 1369 * if the open is successful. 1370 */ 1371 1372 static int dfx_open(struct net_device *dev) 1373 { 1374 DFX_board_t *bp = netdev_priv(dev); 1375 int ret; 1376 1377 DBG_printk("In dfx_open...\n"); 1378 1379 /* Register IRQ - support shared interrupts by passing device ptr */ 1380 1381 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, 1382 dev); 1383 if (ret) { 1384 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq); 1385 return ret; 1386 } 1387 1388 /* 1389 * Set current address to factory MAC address 1390 * 1391 * Note: We've already done this step in dfx_driver_init. 1392 * However, it's possible that a user has set a node 1393 * address override, then closed and reopened the 1394 * adapter. Unless we reset the device address field 1395 * now, we'll continue to use the existing modified 1396 * address. 1397 */ 1398 1399 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN); 1400 1401 /* Clear local unicast/multicast address tables and counts */ 1402 1403 memset(bp->uc_table, 0, sizeof(bp->uc_table)); 1404 memset(bp->mc_table, 0, sizeof(bp->mc_table)); 1405 bp->uc_count = 0; 1406 bp->mc_count = 0; 1407 1408 /* Disable promiscuous filter settings */ 1409 1410 bp->ind_group_prom = PI_FSTATE_K_BLOCK; 1411 bp->group_prom = PI_FSTATE_K_BLOCK; 1412 1413 spin_lock_init(&bp->lock); 1414 1415 /* Reset and initialize adapter */ 1416 1417 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */ 1418 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS) 1419 { 1420 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name); 1421 free_irq(dev->irq, dev); 1422 return -EAGAIN; 1423 } 1424 1425 /* Set device structure info */ 1426 netif_start_queue(dev); 1427 return 0; 1428 } 1429 1430 1431 /* 1432 * ============= 1433 * = dfx_close = 1434 * ============= 1435 * 1436 * Overview: 1437 * Closes the device/module. 1438 * 1439 * Returns: 1440 * Condition code 1441 * 1442 * Arguments: 1443 * dev - pointer to device information 1444 * 1445 * Functional Description: 1446 * This routine closes the adapter and brings it to a safe state. 1447 * The interrupt service routine is deregistered with the OS. 1448 * The adapter can be opened again with another call to dfx_open(). 1449 * 1450 * Return Codes: 1451 * Always return 0. 1452 * 1453 * Assumptions: 1454 * No further requests for this adapter are made after this routine is 1455 * called. dfx_open() can be called to reset and reinitialize the 1456 * adapter. 1457 * 1458 * Side Effects: 1459 * Adapter should be in DMA_UNAVAILABLE state upon completion of this 1460 * routine. 1461 */ 1462 1463 static int dfx_close(struct net_device *dev) 1464 { 1465 DFX_board_t *bp = netdev_priv(dev); 1466 1467 DBG_printk("In dfx_close...\n"); 1468 1469 /* Disable PDQ interrupts first */ 1470 1471 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1472 1473 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */ 1474 1475 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST); 1476 1477 /* 1478 * Flush any pending transmit buffers 1479 * 1480 * Note: It's important that we flush the transmit buffers 1481 * BEFORE we clear our copy of the Type 2 register. 1482 * Otherwise, we'll have no idea how many buffers 1483 * we need to free. 1484 */ 1485 1486 dfx_xmt_flush(bp); 1487 1488 /* 1489 * Clear Type 1 and Type 2 registers after adapter reset 1490 * 1491 * Note: Even though we're closing the adapter, it's 1492 * possible that an interrupt will occur after 1493 * dfx_close is called. Without some assurance to 1494 * the contrary we want to make sure that we don't 1495 * process receive and transmit LLC frames and update 1496 * the Type 2 register with bad information. 1497 */ 1498 1499 bp->cmd_req_reg.lword = 0; 1500 bp->cmd_rsp_reg.lword = 0; 1501 bp->rcv_xmt_reg.lword = 0; 1502 1503 /* Clear consumer block for the same reason given above */ 1504 1505 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK)); 1506 1507 /* Release all dynamically allocate skb in the receive ring. */ 1508 1509 dfx_rcv_flush(bp); 1510 1511 /* Clear device structure flags */ 1512 1513 netif_stop_queue(dev); 1514 1515 /* Deregister (free) IRQ */ 1516 1517 free_irq(dev->irq, dev); 1518 1519 return 0; 1520 } 1521 1522 1523 /* 1524 * ====================== 1525 * = dfx_int_pr_halt_id = 1526 * ====================== 1527 * 1528 * Overview: 1529 * Displays halt id's in string form. 1530 * 1531 * Returns: 1532 * None 1533 * 1534 * Arguments: 1535 * bp - pointer to board information 1536 * 1537 * Functional Description: 1538 * Determine current halt id and display appropriate string. 1539 * 1540 * Return Codes: 1541 * None 1542 * 1543 * Assumptions: 1544 * None 1545 * 1546 * Side Effects: 1547 * None 1548 */ 1549 1550 static void dfx_int_pr_halt_id(DFX_board_t *bp) 1551 { 1552 PI_UINT32 port_status; /* PDQ port status register value */ 1553 PI_UINT32 halt_id; /* PDQ port status halt ID */ 1554 1555 /* Read the latest port status */ 1556 1557 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1558 1559 /* Display halt state transition information */ 1560 1561 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID; 1562 switch (halt_id) 1563 { 1564 case PI_HALT_ID_K_SELFTEST_TIMEOUT: 1565 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name); 1566 break; 1567 1568 case PI_HALT_ID_K_PARITY_ERROR: 1569 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name); 1570 break; 1571 1572 case PI_HALT_ID_K_HOST_DIR_HALT: 1573 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name); 1574 break; 1575 1576 case PI_HALT_ID_K_SW_FAULT: 1577 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name); 1578 break; 1579 1580 case PI_HALT_ID_K_HW_FAULT: 1581 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name); 1582 break; 1583 1584 case PI_HALT_ID_K_PC_TRACE: 1585 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name); 1586 break; 1587 1588 case PI_HALT_ID_K_DMA_ERROR: 1589 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name); 1590 break; 1591 1592 case PI_HALT_ID_K_IMAGE_CRC_ERROR: 1593 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name); 1594 break; 1595 1596 case PI_HALT_ID_K_BUS_EXCEPTION: 1597 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name); 1598 break; 1599 1600 default: 1601 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id); 1602 break; 1603 } 1604 } 1605 1606 1607 /* 1608 * ========================== 1609 * = dfx_int_type_0_process = 1610 * ========================== 1611 * 1612 * Overview: 1613 * Processes Type 0 interrupts. 1614 * 1615 * Returns: 1616 * None 1617 * 1618 * Arguments: 1619 * bp - pointer to board information 1620 * 1621 * Functional Description: 1622 * Processes all enabled Type 0 interrupts. If the reason for the interrupt 1623 * is a serious fault on the adapter, then an error message is displayed 1624 * and the adapter is reset. 1625 * 1626 * One tricky potential timing window is the rapid succession of "link avail" 1627 * "link unavail" state change interrupts. The acknowledgement of the Type 0 1628 * interrupt must be done before reading the state from the Port Status 1629 * register. This is true because a state change could occur after reading 1630 * the data, but before acknowledging the interrupt. If this state change 1631 * does happen, it would be lost because the driver is using the old state, 1632 * and it will never know about the new state because it subsequently 1633 * acknowledges the state change interrupt. 1634 * 1635 * INCORRECT CORRECT 1636 * read type 0 int reasons read type 0 int reasons 1637 * read adapter state ack type 0 interrupts 1638 * ack type 0 interrupts read adapter state 1639 * ... process interrupt ... ... process interrupt ... 1640 * 1641 * Return Codes: 1642 * None 1643 * 1644 * Assumptions: 1645 * None 1646 * 1647 * Side Effects: 1648 * An adapter reset may occur if the adapter has any Type 0 error interrupts 1649 * or if the port status indicates that the adapter is halted. The driver 1650 * is responsible for reinitializing the adapter with the current CAM 1651 * contents and adapter filter settings. 1652 */ 1653 1654 static void dfx_int_type_0_process(DFX_board_t *bp) 1655 1656 { 1657 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */ 1658 PI_UINT32 state; /* current adap state (from port status) */ 1659 1660 /* 1661 * Read host interrupt Type 0 register to determine which Type 0 1662 * interrupts are pending. Immediately write it back out to clear 1663 * those interrupts. 1664 */ 1665 1666 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status); 1667 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status); 1668 1669 /* Check for Type 0 error interrupts */ 1670 1671 if (type_0_status & (PI_TYPE_0_STAT_M_NXM | 1672 PI_TYPE_0_STAT_M_PM_PAR_ERR | 1673 PI_TYPE_0_STAT_M_BUS_PAR_ERR)) 1674 { 1675 /* Check for Non-Existent Memory error */ 1676 1677 if (type_0_status & PI_TYPE_0_STAT_M_NXM) 1678 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name); 1679 1680 /* Check for Packet Memory Parity error */ 1681 1682 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR) 1683 printk("%s: Packet Memory Parity Error\n", bp->dev->name); 1684 1685 /* Check for Host Bus Parity error */ 1686 1687 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR) 1688 printk("%s: Host Bus Parity Error\n", bp->dev->name); 1689 1690 /* Reset adapter and bring it back on-line */ 1691 1692 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1693 bp->reset_type = 0; /* rerun on-board diagnostics */ 1694 printk("%s: Resetting adapter...\n", bp->dev->name); 1695 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1696 { 1697 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1698 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1699 return; 1700 } 1701 printk("%s: Adapter reset successful!\n", bp->dev->name); 1702 return; 1703 } 1704 1705 /* Check for transmit flush interrupt */ 1706 1707 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH) 1708 { 1709 /* Flush any pending xmt's and acknowledge the flush interrupt */ 1710 1711 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1712 dfx_xmt_flush(bp); /* flush any outstanding packets */ 1713 (void) dfx_hw_port_ctrl_req(bp, 1714 PI_PCTRL_M_XMT_DATA_FLUSH_DONE, 1715 0, 1716 0, 1717 NULL); 1718 } 1719 1720 /* Check for adapter state change */ 1721 1722 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE) 1723 { 1724 /* Get latest adapter state */ 1725 1726 state = dfx_hw_adap_state_rd(bp); /* get adapter state */ 1727 if (state == PI_STATE_K_HALTED) 1728 { 1729 /* 1730 * Adapter has transitioned to HALTED state, try to reset 1731 * adapter to bring it back on-line. If reset fails, 1732 * leave the adapter in the broken state. 1733 */ 1734 1735 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name); 1736 dfx_int_pr_halt_id(bp); /* display halt id as string */ 1737 1738 /* Reset adapter and bring it back on-line */ 1739 1740 bp->link_available = PI_K_FALSE; /* link is no longer available */ 1741 bp->reset_type = 0; /* rerun on-board diagnostics */ 1742 printk("%s: Resetting adapter...\n", bp->dev->name); 1743 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS) 1744 { 1745 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name); 1746 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS); 1747 return; 1748 } 1749 printk("%s: Adapter reset successful!\n", bp->dev->name); 1750 } 1751 else if (state == PI_STATE_K_LINK_AVAIL) 1752 { 1753 bp->link_available = PI_K_TRUE; /* set link available flag */ 1754 } 1755 } 1756 } 1757 1758 1759 /* 1760 * ================== 1761 * = dfx_int_common = 1762 * ================== 1763 * 1764 * Overview: 1765 * Interrupt service routine (ISR) 1766 * 1767 * Returns: 1768 * None 1769 * 1770 * Arguments: 1771 * bp - pointer to board information 1772 * 1773 * Functional Description: 1774 * This is the ISR which processes incoming adapter interrupts. 1775 * 1776 * Return Codes: 1777 * None 1778 * 1779 * Assumptions: 1780 * This routine assumes PDQ interrupts have not been disabled. 1781 * When interrupts are disabled at the PDQ, the Port Status register 1782 * is automatically cleared. This routine uses the Port Status 1783 * register value to determine whether a Type 0 interrupt occurred, 1784 * so it's important that adapter interrupts are not normally 1785 * enabled/disabled at the PDQ. 1786 * 1787 * It's vital that this routine is NOT reentered for the 1788 * same board and that the OS is not in another section of 1789 * code (eg. dfx_xmt_queue_pkt) for the same board on a 1790 * different thread. 1791 * 1792 * Side Effects: 1793 * Pending interrupts are serviced. Depending on the type of 1794 * interrupt, acknowledging and clearing the interrupt at the 1795 * PDQ involves writing a register to clear the interrupt bit 1796 * or updating completion indices. 1797 */ 1798 1799 static void dfx_int_common(struct net_device *dev) 1800 { 1801 DFX_board_t *bp = netdev_priv(dev); 1802 PI_UINT32 port_status; /* Port Status register */ 1803 1804 /* Process xmt interrupts - frequent case, so always call this routine */ 1805 1806 if(dfx_xmt_done(bp)) /* free consumed xmt packets */ 1807 netif_wake_queue(dev); 1808 1809 /* Process rcv interrupts - frequent case, so always call this routine */ 1810 1811 dfx_rcv_queue_process(bp); /* service received LLC frames */ 1812 1813 /* 1814 * Transmit and receive producer and completion indices are updated on the 1815 * adapter by writing to the Type 2 Producer register. Since the frequent 1816 * case is that we'll be processing either LLC transmit or receive buffers, 1817 * we'll optimize I/O writes by doing a single register write here. 1818 */ 1819 1820 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 1821 1822 /* Read PDQ Port Status register to find out which interrupts need processing */ 1823 1824 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 1825 1826 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */ 1827 1828 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING) 1829 dfx_int_type_0_process(bp); /* process Type 0 interrupts */ 1830 } 1831 1832 1833 /* 1834 * ================= 1835 * = dfx_interrupt = 1836 * ================= 1837 * 1838 * Overview: 1839 * Interrupt processing routine 1840 * 1841 * Returns: 1842 * Whether a valid interrupt was seen. 1843 * 1844 * Arguments: 1845 * irq - interrupt vector 1846 * dev_id - pointer to device information 1847 * 1848 * Functional Description: 1849 * This routine calls the interrupt processing routine for this adapter. It 1850 * disables and reenables adapter interrupts, as appropriate. We can support 1851 * shared interrupts since the incoming dev_id pointer provides our device 1852 * structure context. 1853 * 1854 * Return Codes: 1855 * IRQ_HANDLED - an IRQ was handled. 1856 * IRQ_NONE - no IRQ was handled. 1857 * 1858 * Assumptions: 1859 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC 1860 * on Intel-based systems) is done by the operating system outside this 1861 * routine. 1862 * 1863 * System interrupts are enabled through this call. 1864 * 1865 * Side Effects: 1866 * Interrupts are disabled, then reenabled at the adapter. 1867 */ 1868 1869 static irqreturn_t dfx_interrupt(int irq, void *dev_id) 1870 { 1871 struct net_device *dev = dev_id; 1872 DFX_board_t *bp = netdev_priv(dev); 1873 struct device *bdev = bp->bus_dev; 1874 int dfx_bus_pci = dev_is_pci(bdev); 1875 int dfx_bus_eisa = DFX_BUS_EISA(bdev); 1876 int dfx_bus_tc = DFX_BUS_TC(bdev); 1877 1878 /* Service adapter interrupts */ 1879 1880 if (dfx_bus_pci) { 1881 u32 status; 1882 1883 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status); 1884 if (!(status & PFI_STATUS_M_PDQ_INT)) 1885 return IRQ_NONE; 1886 1887 spin_lock(&bp->lock); 1888 1889 /* Disable PDQ-PFI interrupts at PFI */ 1890 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1891 PFI_MODE_M_DMA_ENB); 1892 1893 /* Call interrupt service routine for this adapter */ 1894 dfx_int_common(dev); 1895 1896 /* Clear PDQ interrupt status bit and reenable interrupts */ 1897 dfx_port_write_long(bp, PFI_K_REG_STATUS, 1898 PFI_STATUS_M_PDQ_INT); 1899 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 1900 (PFI_MODE_M_PDQ_INT_ENB | 1901 PFI_MODE_M_DMA_ENB)); 1902 1903 spin_unlock(&bp->lock); 1904 } 1905 if (dfx_bus_eisa) { 1906 unsigned long base_addr = to_eisa_device(bdev)->base_addr; 1907 u8 status; 1908 1909 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1910 if (!(status & PI_CONFIG_STAT_0_M_PEND)) 1911 return IRQ_NONE; 1912 1913 spin_lock(&bp->lock); 1914 1915 /* Disable interrupts at the ESIC */ 1916 status &= ~PI_CONFIG_STAT_0_M_INT_ENB; 1917 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1918 1919 /* Call interrupt service routine for this adapter */ 1920 dfx_int_common(dev); 1921 1922 /* Reenable interrupts at the ESIC */ 1923 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0); 1924 status |= PI_CONFIG_STAT_0_M_INT_ENB; 1925 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status); 1926 1927 spin_unlock(&bp->lock); 1928 } 1929 if (dfx_bus_tc) { 1930 u32 status; 1931 1932 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status); 1933 if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING | 1934 PI_PSTATUS_M_XMT_DATA_PENDING | 1935 PI_PSTATUS_M_SMT_HOST_PENDING | 1936 PI_PSTATUS_M_UNSOL_PENDING | 1937 PI_PSTATUS_M_CMD_RSP_PENDING | 1938 PI_PSTATUS_M_CMD_REQ_PENDING | 1939 PI_PSTATUS_M_TYPE_0_PENDING))) 1940 return IRQ_NONE; 1941 1942 spin_lock(&bp->lock); 1943 1944 /* Call interrupt service routine for this adapter */ 1945 dfx_int_common(dev); 1946 1947 spin_unlock(&bp->lock); 1948 } 1949 1950 return IRQ_HANDLED; 1951 } 1952 1953 1954 /* 1955 * ===================== 1956 * = dfx_ctl_get_stats = 1957 * ===================== 1958 * 1959 * Overview: 1960 * Get statistics for FDDI adapter 1961 * 1962 * Returns: 1963 * Pointer to FDDI statistics structure 1964 * 1965 * Arguments: 1966 * dev - pointer to device information 1967 * 1968 * Functional Description: 1969 * Gets current MIB objects from adapter, then 1970 * returns FDDI statistics structure as defined 1971 * in if_fddi.h. 1972 * 1973 * Note: Since the FDDI statistics structure is 1974 * still new and the device structure doesn't 1975 * have an FDDI-specific get statistics handler, 1976 * we'll return the FDDI statistics structure as 1977 * a pointer to an Ethernet statistics structure. 1978 * That way, at least the first part of the statistics 1979 * structure can be decoded properly, and it allows 1980 * "smart" applications to perform a second cast to 1981 * decode the FDDI-specific statistics. 1982 * 1983 * We'll have to pay attention to this routine as the 1984 * device structure becomes more mature and LAN media 1985 * independent. 1986 * 1987 * Return Codes: 1988 * None 1989 * 1990 * Assumptions: 1991 * None 1992 * 1993 * Side Effects: 1994 * None 1995 */ 1996 1997 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev) 1998 { 1999 DFX_board_t *bp = netdev_priv(dev); 2000 2001 /* Fill the bp->stats structure with driver-maintained counters */ 2002 2003 bp->stats.gen.rx_packets = bp->rcv_total_frames; 2004 bp->stats.gen.tx_packets = bp->xmt_total_frames; 2005 bp->stats.gen.rx_bytes = bp->rcv_total_bytes; 2006 bp->stats.gen.tx_bytes = bp->xmt_total_bytes; 2007 bp->stats.gen.rx_errors = bp->rcv_crc_errors + 2008 bp->rcv_frame_status_errors + 2009 bp->rcv_length_errors; 2010 bp->stats.gen.tx_errors = bp->xmt_length_errors; 2011 bp->stats.gen.rx_dropped = bp->rcv_discards; 2012 bp->stats.gen.tx_dropped = bp->xmt_discards; 2013 bp->stats.gen.multicast = bp->rcv_multicast_frames; 2014 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */ 2015 2016 /* Get FDDI SMT MIB objects */ 2017 2018 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET; 2019 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2020 return (struct net_device_stats *)&bp->stats; 2021 2022 /* Fill the bp->stats structure with the SMT MIB object values */ 2023 2024 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id)); 2025 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id; 2026 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id; 2027 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id; 2028 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data)); 2029 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id; 2030 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct; 2031 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct; 2032 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct; 2033 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths; 2034 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities; 2035 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy; 2036 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy; 2037 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify; 2038 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy; 2039 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration; 2040 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present; 2041 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state; 2042 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state; 2043 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag; 2044 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status; 2045 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag; 2046 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls; 2047 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls; 2048 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions; 2049 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability; 2050 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability; 2051 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths; 2052 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path; 2053 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN); 2054 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN); 2055 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN); 2056 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN); 2057 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test; 2058 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths; 2059 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type; 2060 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN); 2061 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req; 2062 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg; 2063 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max; 2064 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value; 2065 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold; 2066 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio; 2067 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state; 2068 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag; 2069 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag; 2070 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag; 2071 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available; 2072 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present; 2073 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable; 2074 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound; 2075 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound; 2076 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req; 2077 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration)); 2078 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0]; 2079 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1]; 2080 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0]; 2081 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1]; 2082 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0]; 2083 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1]; 2084 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0]; 2085 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1]; 2086 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0]; 2087 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1]; 2088 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3); 2089 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3); 2090 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0]; 2091 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1]; 2092 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0]; 2093 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1]; 2094 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0]; 2095 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1]; 2096 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0]; 2097 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1]; 2098 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0]; 2099 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1]; 2100 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0]; 2101 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1]; 2102 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0]; 2103 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1]; 2104 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0]; 2105 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1]; 2106 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0]; 2107 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1]; 2108 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0]; 2109 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1]; 2110 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0]; 2111 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1]; 2112 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0]; 2113 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1]; 2114 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0]; 2115 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1]; 2116 2117 /* Get FDDI counters */ 2118 2119 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET; 2120 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2121 return (struct net_device_stats *)&bp->stats; 2122 2123 /* Fill the bp->stats structure with the FDDI counter values */ 2124 2125 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls; 2126 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls; 2127 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls; 2128 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls; 2129 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls; 2130 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls; 2131 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls; 2132 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls; 2133 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls; 2134 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls; 2135 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls; 2136 2137 return (struct net_device_stats *)&bp->stats; 2138 } 2139 2140 2141 /* 2142 * ============================== 2143 * = dfx_ctl_set_multicast_list = 2144 * ============================== 2145 * 2146 * Overview: 2147 * Enable/Disable LLC frame promiscuous mode reception 2148 * on the adapter and/or update multicast address table. 2149 * 2150 * Returns: 2151 * None 2152 * 2153 * Arguments: 2154 * dev - pointer to device information 2155 * 2156 * Functional Description: 2157 * This routine follows a fairly simple algorithm for setting the 2158 * adapter filters and CAM: 2159 * 2160 * if IFF_PROMISC flag is set 2161 * enable LLC individual/group promiscuous mode 2162 * else 2163 * disable LLC individual/group promiscuous mode 2164 * if number of incoming multicast addresses > 2165 * (CAM max size - number of unicast addresses in CAM) 2166 * enable LLC group promiscuous mode 2167 * set driver-maintained multicast address count to zero 2168 * else 2169 * disable LLC group promiscuous mode 2170 * set driver-maintained multicast address count to incoming count 2171 * update adapter CAM 2172 * update adapter filters 2173 * 2174 * Return Codes: 2175 * None 2176 * 2177 * Assumptions: 2178 * Multicast addresses are presented in canonical (LSB) format. 2179 * 2180 * Side Effects: 2181 * On-board adapter CAM and filters are updated. 2182 */ 2183 2184 static void dfx_ctl_set_multicast_list(struct net_device *dev) 2185 { 2186 DFX_board_t *bp = netdev_priv(dev); 2187 int i; /* used as index in for loop */ 2188 struct netdev_hw_addr *ha; 2189 2190 /* Enable LLC frame promiscuous mode, if necessary */ 2191 2192 if (dev->flags & IFF_PROMISC) 2193 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */ 2194 2195 /* Else, update multicast address table */ 2196 2197 else 2198 { 2199 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */ 2200 /* 2201 * Check whether incoming multicast address count exceeds table size 2202 * 2203 * Note: The adapters utilize an on-board 64 entry CAM for 2204 * supporting perfect filtering of multicast packets 2205 * and bridge functions when adding unicast addresses. 2206 * There is no hash function available. To support 2207 * additional multicast addresses, the all multicast 2208 * filter (LLC group promiscuous mode) must be enabled. 2209 * 2210 * The firmware reserves two CAM entries for SMT-related 2211 * multicast addresses, which leaves 62 entries available. 2212 * The following code ensures that we're not being asked 2213 * to add more than 62 addresses to the CAM. If we are, 2214 * the driver will enable the all multicast filter. 2215 * Should the number of multicast addresses drop below 2216 * the high water mark, the filter will be disabled and 2217 * perfect filtering will be used. 2218 */ 2219 2220 if (netdev_mc_count(dev) > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count)) 2221 { 2222 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2223 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2224 } 2225 else 2226 { 2227 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */ 2228 bp->mc_count = netdev_mc_count(dev); /* Add mc addrs to CAM */ 2229 } 2230 2231 /* Copy addresses to multicast address table, then update adapter CAM */ 2232 2233 i = 0; 2234 netdev_for_each_mc_addr(ha, dev) 2235 memcpy(&bp->mc_table[i++ * FDDI_K_ALEN], 2236 ha->addr, FDDI_K_ALEN); 2237 2238 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2239 { 2240 DBG_printk("%s: Could not update multicast address table!\n", dev->name); 2241 } 2242 else 2243 { 2244 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count); 2245 } 2246 } 2247 2248 /* Update adapter filters */ 2249 2250 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2251 { 2252 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2253 } 2254 else 2255 { 2256 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2257 } 2258 } 2259 2260 2261 /* 2262 * =========================== 2263 * = dfx_ctl_set_mac_address = 2264 * =========================== 2265 * 2266 * Overview: 2267 * Add node address override (unicast address) to adapter 2268 * CAM and update dev_addr field in device table. 2269 * 2270 * Returns: 2271 * None 2272 * 2273 * Arguments: 2274 * dev - pointer to device information 2275 * addr - pointer to sockaddr structure containing unicast address to add 2276 * 2277 * Functional Description: 2278 * The adapter supports node address overrides by adding one or more 2279 * unicast addresses to the adapter CAM. This is similar to adding 2280 * multicast addresses. In this routine we'll update the driver and 2281 * device structures with the new address, then update the adapter CAM 2282 * to ensure that the adapter will copy and strip frames destined and 2283 * sourced by that address. 2284 * 2285 * Return Codes: 2286 * Always returns zero. 2287 * 2288 * Assumptions: 2289 * The address pointed to by addr->sa_data is a valid unicast 2290 * address and is presented in canonical (LSB) format. 2291 * 2292 * Side Effects: 2293 * On-board adapter CAM is updated. On-board adapter filters 2294 * may be updated. 2295 */ 2296 2297 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr) 2298 { 2299 struct sockaddr *p_sockaddr = (struct sockaddr *)addr; 2300 DFX_board_t *bp = netdev_priv(dev); 2301 2302 /* Copy unicast address to driver-maintained structs and update count */ 2303 2304 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */ 2305 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */ 2306 bp->uc_count = 1; 2307 2308 /* 2309 * Verify we're not exceeding the CAM size by adding unicast address 2310 * 2311 * Note: It's possible that before entering this routine we've 2312 * already filled the CAM with 62 multicast addresses. 2313 * Since we need to place the node address override into 2314 * the CAM, we have to check to see that we're not 2315 * exceeding the CAM size. If we are, we have to enable 2316 * the LLC group (multicast) promiscuous mode filter as 2317 * in dfx_ctl_set_multicast_list. 2318 */ 2319 2320 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE) 2321 { 2322 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */ 2323 bp->mc_count = 0; /* Don't add mc addrs to CAM */ 2324 2325 /* Update adapter filters */ 2326 2327 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS) 2328 { 2329 DBG_printk("%s: Could not update adapter filters!\n", dev->name); 2330 } 2331 else 2332 { 2333 DBG_printk("%s: Adapter filters updated!\n", dev->name); 2334 } 2335 } 2336 2337 /* Update adapter CAM with new unicast address */ 2338 2339 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS) 2340 { 2341 DBG_printk("%s: Could not set new MAC address!\n", dev->name); 2342 } 2343 else 2344 { 2345 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name); 2346 } 2347 return 0; /* always return zero */ 2348 } 2349 2350 2351 /* 2352 * ====================== 2353 * = dfx_ctl_update_cam = 2354 * ====================== 2355 * 2356 * Overview: 2357 * Procedure to update adapter CAM (Content Addressable Memory) 2358 * with desired unicast and multicast address entries. 2359 * 2360 * Returns: 2361 * Condition code 2362 * 2363 * Arguments: 2364 * bp - pointer to board information 2365 * 2366 * Functional Description: 2367 * Updates adapter CAM with current contents of board structure 2368 * unicast and multicast address tables. Since there are only 62 2369 * free entries in CAM, this routine ensures that the command 2370 * request buffer is not overrun. 2371 * 2372 * Return Codes: 2373 * DFX_K_SUCCESS - Request succeeded 2374 * DFX_K_FAILURE - Request failed 2375 * 2376 * Assumptions: 2377 * All addresses being added (unicast and multicast) are in canonical 2378 * order. 2379 * 2380 * Side Effects: 2381 * On-board adapter CAM is updated. 2382 */ 2383 2384 static int dfx_ctl_update_cam(DFX_board_t *bp) 2385 { 2386 int i; /* used as index */ 2387 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */ 2388 2389 /* 2390 * Fill in command request information 2391 * 2392 * Note: Even though both the unicast and multicast address 2393 * table entries are stored as contiguous 6 byte entries, 2394 * the firmware address filter set command expects each 2395 * entry to be two longwords (8 bytes total). We must be 2396 * careful to only copy the six bytes of each unicast and 2397 * multicast table entry into each command entry. This 2398 * is also why we must first clear the entire command 2399 * request buffer. 2400 */ 2401 2402 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */ 2403 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET; 2404 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0]; 2405 2406 /* Now add unicast addresses to command request buffer, if any */ 2407 2408 for (i=0; i < (int)bp->uc_count; i++) 2409 { 2410 if (i < PI_CMD_ADDR_FILTER_K_SIZE) 2411 { 2412 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2413 p_addr++; /* point to next command entry */ 2414 } 2415 } 2416 2417 /* Now add multicast addresses to command request buffer, if any */ 2418 2419 for (i=0; i < (int)bp->mc_count; i++) 2420 { 2421 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE) 2422 { 2423 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN); 2424 p_addr++; /* point to next command entry */ 2425 } 2426 } 2427 2428 /* Issue command to update adapter CAM, then return */ 2429 2430 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2431 return DFX_K_FAILURE; 2432 return DFX_K_SUCCESS; 2433 } 2434 2435 2436 /* 2437 * ========================== 2438 * = dfx_ctl_update_filters = 2439 * ========================== 2440 * 2441 * Overview: 2442 * Procedure to update adapter filters with desired 2443 * filter settings. 2444 * 2445 * Returns: 2446 * Condition code 2447 * 2448 * Arguments: 2449 * bp - pointer to board information 2450 * 2451 * Functional Description: 2452 * Enables or disables filter using current filter settings. 2453 * 2454 * Return Codes: 2455 * DFX_K_SUCCESS - Request succeeded. 2456 * DFX_K_FAILURE - Request failed. 2457 * 2458 * Assumptions: 2459 * We must always pass up packets destined to the broadcast 2460 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the 2461 * broadcast filter enabled. 2462 * 2463 * Side Effects: 2464 * On-board adapter filters are updated. 2465 */ 2466 2467 static int dfx_ctl_update_filters(DFX_board_t *bp) 2468 { 2469 int i = 0; /* used as index */ 2470 2471 /* Fill in command request information */ 2472 2473 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET; 2474 2475 /* Initialize Broadcast filter - * ALWAYS ENABLED * */ 2476 2477 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST; 2478 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS; 2479 2480 /* Initialize LLC Individual/Group Promiscuous filter */ 2481 2482 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM; 2483 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom; 2484 2485 /* Initialize LLC Group Promiscuous filter */ 2486 2487 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM; 2488 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom; 2489 2490 /* Terminate the item code list */ 2491 2492 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL; 2493 2494 /* Issue command to update adapter filters, then return */ 2495 2496 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS) 2497 return DFX_K_FAILURE; 2498 return DFX_K_SUCCESS; 2499 } 2500 2501 2502 /* 2503 * ====================== 2504 * = dfx_hw_dma_cmd_req = 2505 * ====================== 2506 * 2507 * Overview: 2508 * Sends PDQ DMA command to adapter firmware 2509 * 2510 * Returns: 2511 * Condition code 2512 * 2513 * Arguments: 2514 * bp - pointer to board information 2515 * 2516 * Functional Description: 2517 * The command request and response buffers are posted to the adapter in the manner 2518 * described in the PDQ Port Specification: 2519 * 2520 * 1. Command Response Buffer is posted to adapter. 2521 * 2. Command Request Buffer is posted to adapter. 2522 * 3. Command Request consumer index is polled until it indicates that request 2523 * buffer has been DMA'd to adapter. 2524 * 4. Command Response consumer index is polled until it indicates that response 2525 * buffer has been DMA'd from adapter. 2526 * 2527 * This ordering ensures that a response buffer is already available for the firmware 2528 * to use once it's done processing the request buffer. 2529 * 2530 * Return Codes: 2531 * DFX_K_SUCCESS - DMA command succeeded 2532 * DFX_K_OUTSTATE - Adapter is NOT in proper state 2533 * DFX_K_HW_TIMEOUT - DMA command timed out 2534 * 2535 * Assumptions: 2536 * Command request buffer has already been filled with desired DMA command. 2537 * 2538 * Side Effects: 2539 * None 2540 */ 2541 2542 static int dfx_hw_dma_cmd_req(DFX_board_t *bp) 2543 { 2544 int status; /* adapter status */ 2545 int timeout_cnt; /* used in for loops */ 2546 2547 /* Make sure the adapter is in a state that we can issue the DMA command in */ 2548 2549 status = dfx_hw_adap_state_rd(bp); 2550 if ((status == PI_STATE_K_RESET) || 2551 (status == PI_STATE_K_HALTED) || 2552 (status == PI_STATE_K_DMA_UNAVAIL) || 2553 (status == PI_STATE_K_UPGRADE)) 2554 return DFX_K_OUTSTATE; 2555 2556 /* Put response buffer on the command response queue */ 2557 2558 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2559 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2560 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys; 2561 2562 /* Bump (and wrap) the producer index and write out to register */ 2563 2564 bp->cmd_rsp_reg.index.prod += 1; 2565 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2566 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2567 2568 /* Put request buffer on the command request queue */ 2569 2570 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP | 2571 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN)); 2572 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys; 2573 2574 /* Bump (and wrap) the producer index and write out to register */ 2575 2576 bp->cmd_req_reg.index.prod += 1; 2577 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2578 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2579 2580 /* 2581 * Here we wait for the command request consumer index to be equal 2582 * to the producer, indicating that the adapter has DMAed the request. 2583 */ 2584 2585 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2586 { 2587 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req)) 2588 break; 2589 udelay(100); /* wait for 100 microseconds */ 2590 } 2591 if (timeout_cnt == 0) 2592 return DFX_K_HW_TIMEOUT; 2593 2594 /* Bump (and wrap) the completion index and write out to register */ 2595 2596 bp->cmd_req_reg.index.comp += 1; 2597 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1; 2598 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword); 2599 2600 /* 2601 * Here we wait for the command response consumer index to be equal 2602 * to the producer, indicating that the adapter has DMAed the response. 2603 */ 2604 2605 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--) 2606 { 2607 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp)) 2608 break; 2609 udelay(100); /* wait for 100 microseconds */ 2610 } 2611 if (timeout_cnt == 0) 2612 return DFX_K_HW_TIMEOUT; 2613 2614 /* Bump (and wrap) the completion index and write out to register */ 2615 2616 bp->cmd_rsp_reg.index.comp += 1; 2617 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1; 2618 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword); 2619 return DFX_K_SUCCESS; 2620 } 2621 2622 2623 /* 2624 * ======================== 2625 * = dfx_hw_port_ctrl_req = 2626 * ======================== 2627 * 2628 * Overview: 2629 * Sends PDQ port control command to adapter firmware 2630 * 2631 * Returns: 2632 * Host data register value in host_data if ptr is not NULL 2633 * 2634 * Arguments: 2635 * bp - pointer to board information 2636 * command - port control command 2637 * data_a - port data A register value 2638 * data_b - port data B register value 2639 * host_data - ptr to host data register value 2640 * 2641 * Functional Description: 2642 * Send generic port control command to adapter by writing 2643 * to various PDQ port registers, then polling for completion. 2644 * 2645 * Return Codes: 2646 * DFX_K_SUCCESS - port control command succeeded 2647 * DFX_K_HW_TIMEOUT - port control command timed out 2648 * 2649 * Assumptions: 2650 * None 2651 * 2652 * Side Effects: 2653 * None 2654 */ 2655 2656 static int dfx_hw_port_ctrl_req( 2657 DFX_board_t *bp, 2658 PI_UINT32 command, 2659 PI_UINT32 data_a, 2660 PI_UINT32 data_b, 2661 PI_UINT32 *host_data 2662 ) 2663 2664 { 2665 PI_UINT32 port_cmd; /* Port Control command register value */ 2666 int timeout_cnt; /* used in for loops */ 2667 2668 /* Set Command Error bit in command longword */ 2669 2670 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR); 2671 2672 /* Issue port command to the adapter */ 2673 2674 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a); 2675 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b); 2676 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd); 2677 2678 /* Now wait for command to complete */ 2679 2680 if (command == PI_PCTRL_M_BLAST_FLASH) 2681 timeout_cnt = 600000; /* set command timeout count to 60 seconds */ 2682 else 2683 timeout_cnt = 20000; /* set command timeout count to 2 seconds */ 2684 2685 for (; timeout_cnt > 0; timeout_cnt--) 2686 { 2687 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd); 2688 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR)) 2689 break; 2690 udelay(100); /* wait for 100 microseconds */ 2691 } 2692 if (timeout_cnt == 0) 2693 return DFX_K_HW_TIMEOUT; 2694 2695 /* 2696 * If the address of host_data is non-zero, assume caller has supplied a 2697 * non NULL pointer, and return the contents of the HOST_DATA register in 2698 * it. 2699 */ 2700 2701 if (host_data != NULL) 2702 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data); 2703 return DFX_K_SUCCESS; 2704 } 2705 2706 2707 /* 2708 * ===================== 2709 * = dfx_hw_adap_reset = 2710 * ===================== 2711 * 2712 * Overview: 2713 * Resets adapter 2714 * 2715 * Returns: 2716 * None 2717 * 2718 * Arguments: 2719 * bp - pointer to board information 2720 * type - type of reset to perform 2721 * 2722 * Functional Description: 2723 * Issue soft reset to adapter by writing to PDQ Port Reset 2724 * register. Use incoming reset type to tell adapter what 2725 * kind of reset operation to perform. 2726 * 2727 * Return Codes: 2728 * None 2729 * 2730 * Assumptions: 2731 * This routine merely issues a soft reset to the adapter. 2732 * It is expected that after this routine returns, the caller 2733 * will appropriately poll the Port Status register for the 2734 * adapter to enter the proper state. 2735 * 2736 * Side Effects: 2737 * Internal adapter registers are cleared. 2738 */ 2739 2740 static void dfx_hw_adap_reset( 2741 DFX_board_t *bp, 2742 PI_UINT32 type 2743 ) 2744 2745 { 2746 /* Set Reset type and assert reset */ 2747 2748 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */ 2749 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET); 2750 2751 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */ 2752 2753 udelay(20); 2754 2755 /* Deassert reset */ 2756 2757 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0); 2758 } 2759 2760 2761 /* 2762 * ======================== 2763 * = dfx_hw_adap_state_rd = 2764 * ======================== 2765 * 2766 * Overview: 2767 * Returns current adapter state 2768 * 2769 * Returns: 2770 * Adapter state per PDQ Port Specification 2771 * 2772 * Arguments: 2773 * bp - pointer to board information 2774 * 2775 * Functional Description: 2776 * Reads PDQ Port Status register and returns adapter state. 2777 * 2778 * Return Codes: 2779 * None 2780 * 2781 * Assumptions: 2782 * None 2783 * 2784 * Side Effects: 2785 * None 2786 */ 2787 2788 static int dfx_hw_adap_state_rd(DFX_board_t *bp) 2789 { 2790 PI_UINT32 port_status; /* Port Status register value */ 2791 2792 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status); 2793 return (port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE; 2794 } 2795 2796 2797 /* 2798 * ===================== 2799 * = dfx_hw_dma_uninit = 2800 * ===================== 2801 * 2802 * Overview: 2803 * Brings adapter to DMA_UNAVAILABLE state 2804 * 2805 * Returns: 2806 * Condition code 2807 * 2808 * Arguments: 2809 * bp - pointer to board information 2810 * type - type of reset to perform 2811 * 2812 * Functional Description: 2813 * Bring adapter to DMA_UNAVAILABLE state by performing the following: 2814 * 1. Set reset type bit in Port Data A Register then reset adapter. 2815 * 2. Check that adapter is in DMA_UNAVAILABLE state. 2816 * 2817 * Return Codes: 2818 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state 2819 * DFX_K_HW_TIMEOUT - adapter did not reset properly 2820 * 2821 * Assumptions: 2822 * None 2823 * 2824 * Side Effects: 2825 * Internal adapter registers are cleared. 2826 */ 2827 2828 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type) 2829 { 2830 int timeout_cnt; /* used in for loops */ 2831 2832 /* Set reset type bit and reset adapter */ 2833 2834 dfx_hw_adap_reset(bp, type); 2835 2836 /* Now wait for adapter to enter DMA_UNAVAILABLE state */ 2837 2838 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--) 2839 { 2840 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL) 2841 break; 2842 udelay(100); /* wait for 100 microseconds */ 2843 } 2844 if (timeout_cnt == 0) 2845 return DFX_K_HW_TIMEOUT; 2846 return DFX_K_SUCCESS; 2847 } 2848 2849 /* 2850 * Align an sk_buff to a boundary power of 2 2851 * 2852 */ 2853 2854 static void my_skb_align(struct sk_buff *skb, int n) 2855 { 2856 unsigned long x = (unsigned long)skb->data; 2857 unsigned long v; 2858 2859 v = ALIGN(x, n); /* Where we want to be */ 2860 2861 skb_reserve(skb, v - x); 2862 } 2863 2864 2865 /* 2866 * ================ 2867 * = dfx_rcv_init = 2868 * ================ 2869 * 2870 * Overview: 2871 * Produces buffers to adapter LLC Host receive descriptor block 2872 * 2873 * Returns: 2874 * None 2875 * 2876 * Arguments: 2877 * bp - pointer to board information 2878 * get_buffers - non-zero if buffers to be allocated 2879 * 2880 * Functional Description: 2881 * This routine can be called during dfx_adap_init() or during an adapter 2882 * reset. It initializes the descriptor block and produces all allocated 2883 * LLC Host queue receive buffers. 2884 * 2885 * Return Codes: 2886 * Return 0 on success or -ENOMEM if buffer allocation failed (when using 2887 * dynamic buffer allocation). If the buffer allocation failed, the 2888 * already allocated buffers will not be released and the caller should do 2889 * this. 2890 * 2891 * Assumptions: 2892 * The PDQ has been reset and the adapter and driver maintained Type 2 2893 * register indices are cleared. 2894 * 2895 * Side Effects: 2896 * Receive buffers are posted to the adapter LLC queue and the adapter 2897 * is notified. 2898 */ 2899 2900 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers) 2901 { 2902 int i, j; /* used in for loop */ 2903 2904 /* 2905 * Since each receive buffer is a single fragment of same length, initialize 2906 * first longword in each receive descriptor for entire LLC Host descriptor 2907 * block. Also initialize second longword in each receive descriptor with 2908 * physical address of receive buffer. We'll always allocate receive 2909 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor 2910 * block and produce new receive buffers by simply updating the receive 2911 * producer index. 2912 * 2913 * Assumptions: 2914 * To support all shipping versions of PDQ, the receive buffer size 2915 * must be mod 128 in length and the physical address must be 128 byte 2916 * aligned. In other words, bits 0-6 of the length and address must 2917 * be zero for the following descriptor field entries to be correct on 2918 * all PDQ-based boards. We guaranteed both requirements during 2919 * driver initialization when we allocated memory for the receive buffers. 2920 */ 2921 2922 if (get_buffers) { 2923 #ifdef DYNAMIC_BUFFERS 2924 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 2925 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2926 { 2927 struct sk_buff *newskb = __netdev_alloc_skb(bp->dev, NEW_SKB_SIZE, GFP_NOIO); 2928 if (!newskb) 2929 return -ENOMEM; 2930 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2931 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2932 /* 2933 * align to 128 bytes for compatibility with 2934 * the old EISA boards. 2935 */ 2936 2937 my_skb_align(newskb, 128); 2938 bp->descr_block_virt->rcv_data[i + j].long_1 = 2939 (u32)dma_map_single(bp->bus_dev, newskb->data, 2940 NEW_SKB_SIZE, 2941 DMA_FROM_DEVICE); 2942 /* 2943 * p_rcv_buff_va is only used inside the 2944 * kernel so we put the skb pointer here. 2945 */ 2946 bp->p_rcv_buff_va[i+j] = (char *) newskb; 2947 } 2948 #else 2949 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++) 2950 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 2951 { 2952 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP | 2953 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN)); 2954 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX)); 2955 bp->p_rcv_buff_va[i+j] = (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX)); 2956 } 2957 #endif 2958 } 2959 2960 /* Update receive producer and Type 2 register */ 2961 2962 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post; 2963 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 2964 return 0; 2965 } 2966 2967 2968 /* 2969 * ========================= 2970 * = dfx_rcv_queue_process = 2971 * ========================= 2972 * 2973 * Overview: 2974 * Process received LLC frames. 2975 * 2976 * Returns: 2977 * None 2978 * 2979 * Arguments: 2980 * bp - pointer to board information 2981 * 2982 * Functional Description: 2983 * Received LLC frames are processed until there are no more consumed frames. 2984 * Once all frames are processed, the receive buffers are returned to the 2985 * adapter. Note that this algorithm fixes the length of time that can be spent 2986 * in this routine, because there are a fixed number of receive buffers to 2987 * process and buffers are not produced until this routine exits and returns 2988 * to the ISR. 2989 * 2990 * Return Codes: 2991 * None 2992 * 2993 * Assumptions: 2994 * None 2995 * 2996 * Side Effects: 2997 * None 2998 */ 2999 3000 static void dfx_rcv_queue_process( 3001 DFX_board_t *bp 3002 ) 3003 3004 { 3005 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3006 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */ 3007 u32 descr, pkt_len; /* FMC descriptor field and packet length */ 3008 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */ 3009 3010 /* Service all consumed LLC receive frames */ 3011 3012 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3013 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons) 3014 { 3015 /* Process any errors */ 3016 3017 int entry; 3018 3019 entry = bp->rcv_xmt_reg.index.rcv_comp; 3020 #ifdef DYNAMIC_BUFFERS 3021 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data); 3022 #else 3023 p_buff = bp->p_rcv_buff_va[entry]; 3024 #endif 3025 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32)); 3026 3027 if (descr & PI_FMC_DESCR_M_RCC_FLUSH) 3028 { 3029 if (descr & PI_FMC_DESCR_M_RCC_CRC) 3030 bp->rcv_crc_errors++; 3031 else 3032 bp->rcv_frame_status_errors++; 3033 } 3034 else 3035 { 3036 int rx_in_place = 0; 3037 3038 /* The frame was received without errors - verify packet length */ 3039 3040 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN); 3041 pkt_len -= 4; /* subtract 4 byte CRC */ 3042 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3043 bp->rcv_length_errors++; 3044 else{ 3045 #ifdef DYNAMIC_BUFFERS 3046 if (pkt_len > SKBUFF_RX_COPYBREAK) { 3047 struct sk_buff *newskb; 3048 3049 newskb = dev_alloc_skb(NEW_SKB_SIZE); 3050 if (newskb){ 3051 rx_in_place = 1; 3052 3053 my_skb_align(newskb, 128); 3054 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry]; 3055 dma_unmap_single(bp->bus_dev, 3056 bp->descr_block_virt->rcv_data[entry].long_1, 3057 NEW_SKB_SIZE, 3058 DMA_FROM_DEVICE); 3059 skb_reserve(skb, RCV_BUFF_K_PADDING); 3060 bp->p_rcv_buff_va[entry] = (char *)newskb; 3061 bp->descr_block_virt->rcv_data[entry].long_1 = 3062 (u32)dma_map_single(bp->bus_dev, 3063 newskb->data, 3064 NEW_SKB_SIZE, 3065 DMA_FROM_DEVICE); 3066 } else 3067 skb = NULL; 3068 } else 3069 #endif 3070 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */ 3071 if (skb == NULL) 3072 { 3073 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name); 3074 bp->rcv_discards++; 3075 break; 3076 } 3077 else { 3078 #ifndef DYNAMIC_BUFFERS 3079 if (! rx_in_place) 3080 #endif 3081 { 3082 /* Receive buffer allocated, pass receive packet up */ 3083 3084 skb_copy_to_linear_data(skb, 3085 p_buff + RCV_BUFF_K_PADDING, 3086 pkt_len + 3); 3087 } 3088 3089 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */ 3090 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */ 3091 skb->protocol = fddi_type_trans(skb, bp->dev); 3092 bp->rcv_total_bytes += skb->len; 3093 netif_rx(skb); 3094 3095 /* Update the rcv counters */ 3096 bp->rcv_total_frames++; 3097 if (*(p_buff + RCV_BUFF_K_DA) & 0x01) 3098 bp->rcv_multicast_frames++; 3099 } 3100 } 3101 } 3102 3103 /* 3104 * Advance the producer (for recycling) and advance the completion 3105 * (for servicing received frames). Note that it is okay to 3106 * advance the producer without checking that it passes the 3107 * completion index because they are both advanced at the same 3108 * rate. 3109 */ 3110 3111 bp->rcv_xmt_reg.index.rcv_prod += 1; 3112 bp->rcv_xmt_reg.index.rcv_comp += 1; 3113 } 3114 } 3115 3116 3117 /* 3118 * ===================== 3119 * = dfx_xmt_queue_pkt = 3120 * ===================== 3121 * 3122 * Overview: 3123 * Queues packets for transmission 3124 * 3125 * Returns: 3126 * Condition code 3127 * 3128 * Arguments: 3129 * skb - pointer to sk_buff to queue for transmission 3130 * dev - pointer to device information 3131 * 3132 * Functional Description: 3133 * Here we assume that an incoming skb transmit request 3134 * is contained in a single physically contiguous buffer 3135 * in which the virtual address of the start of packet 3136 * (skb->data) can be converted to a physical address 3137 * by using pci_map_single(). 3138 * 3139 * Since the adapter architecture requires a three byte 3140 * packet request header to prepend the start of packet, 3141 * we'll write the three byte field immediately prior to 3142 * the FC byte. This assumption is valid because we've 3143 * ensured that dev->hard_header_len includes three pad 3144 * bytes. By posting a single fragment to the adapter, 3145 * we'll reduce the number of descriptor fetches and 3146 * bus traffic needed to send the request. 3147 * 3148 * Also, we can't free the skb until after it's been DMA'd 3149 * out by the adapter, so we'll queue it in the driver and 3150 * return it in dfx_xmt_done. 3151 * 3152 * Return Codes: 3153 * 0 - driver queued packet, link is unavailable, or skbuff was bad 3154 * 1 - caller should requeue the sk_buff for later transmission 3155 * 3156 * Assumptions: 3157 * First and foremost, we assume the incoming skb pointer 3158 * is NOT NULL and is pointing to a valid sk_buff structure. 3159 * 3160 * The outgoing packet is complete, starting with the 3161 * frame control byte including the last byte of data, 3162 * but NOT including the 4 byte CRC. We'll let the 3163 * adapter hardware generate and append the CRC. 3164 * 3165 * The entire packet is stored in one physically 3166 * contiguous buffer which is not cached and whose 3167 * 32-bit physical address can be determined. 3168 * 3169 * It's vital that this routine is NOT reentered for the 3170 * same board and that the OS is not in another section of 3171 * code (eg. dfx_int_common) for the same board on a 3172 * different thread. 3173 * 3174 * Side Effects: 3175 * None 3176 */ 3177 3178 static netdev_tx_t dfx_xmt_queue_pkt(struct sk_buff *skb, 3179 struct net_device *dev) 3180 { 3181 DFX_board_t *bp = netdev_priv(dev); 3182 u8 prod; /* local transmit producer index */ 3183 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */ 3184 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3185 unsigned long flags; 3186 3187 netif_stop_queue(dev); 3188 3189 /* 3190 * Verify that incoming transmit request is OK 3191 * 3192 * Note: The packet size check is consistent with other 3193 * Linux device drivers, although the correct packet 3194 * size should be verified before calling the 3195 * transmit routine. 3196 */ 3197 3198 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN)) 3199 { 3200 printk("%s: Invalid packet length - %u bytes\n", 3201 dev->name, skb->len); 3202 bp->xmt_length_errors++; /* bump error counter */ 3203 netif_wake_queue(dev); 3204 dev_kfree_skb(skb); 3205 return NETDEV_TX_OK; /* return "success" */ 3206 } 3207 /* 3208 * See if adapter link is available, if not, free buffer 3209 * 3210 * Note: If the link isn't available, free buffer and return 0 3211 * rather than tell the upper layer to requeue the packet. 3212 * The methodology here is that by the time the link 3213 * becomes available, the packet to be sent will be 3214 * fairly stale. By simply dropping the packet, the 3215 * higher layer protocols will eventually time out 3216 * waiting for response packets which it won't receive. 3217 */ 3218 3219 if (bp->link_available == PI_K_FALSE) 3220 { 3221 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */ 3222 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */ 3223 else 3224 { 3225 bp->xmt_discards++; /* bump error counter */ 3226 dev_kfree_skb(skb); /* free sk_buff now */ 3227 netif_wake_queue(dev); 3228 return NETDEV_TX_OK; /* return "success" */ 3229 } 3230 } 3231 3232 spin_lock_irqsave(&bp->lock, flags); 3233 3234 /* Get the current producer and the next free xmt data descriptor */ 3235 3236 prod = bp->rcv_xmt_reg.index.xmt_prod; 3237 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]); 3238 3239 /* 3240 * Get pointer to auxiliary queue entry to contain information 3241 * for this packet. 3242 * 3243 * Note: The current xmt producer index will become the 3244 * current xmt completion index when we complete this 3245 * packet later on. So, we'll get the pointer to the 3246 * next auxiliary queue entry now before we bump the 3247 * producer index. 3248 */ 3249 3250 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */ 3251 3252 /* Write the three PRH bytes immediately before the FC byte */ 3253 3254 skb_push(skb,3); 3255 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */ 3256 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */ 3257 skb->data[2] = DFX_PRH2_BYTE; /* specification */ 3258 3259 /* 3260 * Write the descriptor with buffer info and bump producer 3261 * 3262 * Note: Since we need to start DMA from the packet request 3263 * header, we'll add 3 bytes to the DMA buffer length, 3264 * and we'll determine the physical address of the 3265 * buffer from the PRH, not skb->data. 3266 * 3267 * Assumptions: 3268 * 1. Packet starts with the frame control (FC) byte 3269 * at skb->data. 3270 * 2. The 4-byte CRC is not appended to the buffer or 3271 * included in the length. 3272 * 3. Packet length (skb->len) is from FC to end of 3273 * data, inclusive. 3274 * 4. The packet length does not exceed the maximum 3275 * FDDI LLC frame length of 4491 bytes. 3276 * 5. The entire packet is contained in a physically 3277 * contiguous, non-cached, locked memory space 3278 * comprised of a single buffer pointed to by 3279 * skb->data. 3280 * 6. The physical address of the start of packet 3281 * can be determined from the virtual address 3282 * by using pci_map_single() and is only 32-bits 3283 * wide. 3284 */ 3285 3286 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN)); 3287 p_xmt_descr->long_1 = (u32)dma_map_single(bp->bus_dev, skb->data, 3288 skb->len, DMA_TO_DEVICE); 3289 3290 /* 3291 * Verify that descriptor is actually available 3292 * 3293 * Note: If descriptor isn't available, return 1 which tells 3294 * the upper layer to requeue the packet for later 3295 * transmission. 3296 * 3297 * We need to ensure that the producer never reaches the 3298 * completion, except to indicate that the queue is empty. 3299 */ 3300 3301 if (prod == bp->rcv_xmt_reg.index.xmt_comp) 3302 { 3303 skb_pull(skb,3); 3304 spin_unlock_irqrestore(&bp->lock, flags); 3305 return NETDEV_TX_BUSY; /* requeue packet for later */ 3306 } 3307 3308 /* 3309 * Save info for this packet for xmt done indication routine 3310 * 3311 * Normally, we'd save the producer index in the p_xmt_drv_descr 3312 * structure so that we'd have it handy when we complete this 3313 * packet later (in dfx_xmt_done). However, since the current 3314 * transmit architecture guarantees a single fragment for the 3315 * entire packet, we can simply bump the completion index by 3316 * one (1) for each completed packet. 3317 * 3318 * Note: If this assumption changes and we're presented with 3319 * an inconsistent number of transmit fragments for packet 3320 * data, we'll need to modify this code to save the current 3321 * transmit producer index. 3322 */ 3323 3324 p_xmt_drv_descr->p_skb = skb; 3325 3326 /* Update Type 2 register */ 3327 3328 bp->rcv_xmt_reg.index.xmt_prod = prod; 3329 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword); 3330 spin_unlock_irqrestore(&bp->lock, flags); 3331 netif_wake_queue(dev); 3332 return NETDEV_TX_OK; /* packet queued to adapter */ 3333 } 3334 3335 3336 /* 3337 * ================ 3338 * = dfx_xmt_done = 3339 * ================ 3340 * 3341 * Overview: 3342 * Processes all frames that have been transmitted. 3343 * 3344 * Returns: 3345 * None 3346 * 3347 * Arguments: 3348 * bp - pointer to board information 3349 * 3350 * Functional Description: 3351 * For all consumed transmit descriptors that have not 3352 * yet been completed, we'll free the skb we were holding 3353 * onto using dev_kfree_skb and bump the appropriate 3354 * counters. 3355 * 3356 * Return Codes: 3357 * None 3358 * 3359 * Assumptions: 3360 * The Type 2 register is not updated in this routine. It is 3361 * assumed that it will be updated in the ISR when dfx_xmt_done 3362 * returns. 3363 * 3364 * Side Effects: 3365 * None 3366 */ 3367 3368 static int dfx_xmt_done(DFX_board_t *bp) 3369 { 3370 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3371 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */ 3372 u8 comp; /* local transmit completion index */ 3373 int freed = 0; /* buffers freed */ 3374 3375 /* Service all consumed transmit frames */ 3376 3377 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data); 3378 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons) 3379 { 3380 /* Get pointer to the transmit driver descriptor block information */ 3381 3382 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3383 3384 /* Increment transmit counters */ 3385 3386 bp->xmt_total_frames++; 3387 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len; 3388 3389 /* Return skb to operating system */ 3390 comp = bp->rcv_xmt_reg.index.xmt_comp; 3391 dma_unmap_single(bp->bus_dev, 3392 bp->descr_block_virt->xmt_data[comp].long_1, 3393 p_xmt_drv_descr->p_skb->len, 3394 DMA_TO_DEVICE); 3395 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb); 3396 3397 /* 3398 * Move to start of next packet by updating completion index 3399 * 3400 * Here we assume that a transmit packet request is always 3401 * serviced by posting one fragment. We can therefore 3402 * simplify the completion code by incrementing the 3403 * completion index by one. This code will need to be 3404 * modified if this assumption changes. See comments 3405 * in dfx_xmt_queue_pkt for more details. 3406 */ 3407 3408 bp->rcv_xmt_reg.index.xmt_comp += 1; 3409 freed++; 3410 } 3411 return freed; 3412 } 3413 3414 3415 /* 3416 * ================= 3417 * = dfx_rcv_flush = 3418 * ================= 3419 * 3420 * Overview: 3421 * Remove all skb's in the receive ring. 3422 * 3423 * Returns: 3424 * None 3425 * 3426 * Arguments: 3427 * bp - pointer to board information 3428 * 3429 * Functional Description: 3430 * Free's all the dynamically allocated skb's that are 3431 * currently attached to the device receive ring. This 3432 * function is typically only used when the device is 3433 * initialized or reinitialized. 3434 * 3435 * Return Codes: 3436 * None 3437 * 3438 * Side Effects: 3439 * None 3440 */ 3441 #ifdef DYNAMIC_BUFFERS 3442 static void dfx_rcv_flush( DFX_board_t *bp ) 3443 { 3444 int i, j; 3445 3446 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++) 3447 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post) 3448 { 3449 struct sk_buff *skb; 3450 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j]; 3451 if (skb) 3452 dev_kfree_skb(skb); 3453 bp->p_rcv_buff_va[i+j] = NULL; 3454 } 3455 3456 } 3457 #else 3458 static inline void dfx_rcv_flush( DFX_board_t *bp ) 3459 { 3460 } 3461 #endif /* DYNAMIC_BUFFERS */ 3462 3463 /* 3464 * ================= 3465 * = dfx_xmt_flush = 3466 * ================= 3467 * 3468 * Overview: 3469 * Processes all frames whether they've been transmitted 3470 * or not. 3471 * 3472 * Returns: 3473 * None 3474 * 3475 * Arguments: 3476 * bp - pointer to board information 3477 * 3478 * Functional Description: 3479 * For all produced transmit descriptors that have not 3480 * yet been completed, we'll free the skb we were holding 3481 * onto using dev_kfree_skb and bump the appropriate 3482 * counters. Of course, it's possible that some of 3483 * these transmit requests actually did go out, but we 3484 * won't make that distinction here. Finally, we'll 3485 * update the consumer index to match the producer. 3486 * 3487 * Return Codes: 3488 * None 3489 * 3490 * Assumptions: 3491 * This routine does NOT update the Type 2 register. It 3492 * is assumed that this routine is being called during a 3493 * transmit flush interrupt, or a shutdown or close routine. 3494 * 3495 * Side Effects: 3496 * None 3497 */ 3498 3499 static void dfx_xmt_flush( DFX_board_t *bp ) 3500 { 3501 u32 prod_cons; /* rcv/xmt consumer block longword */ 3502 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */ 3503 u8 comp; /* local transmit completion index */ 3504 3505 /* Flush all outstanding transmit frames */ 3506 3507 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod) 3508 { 3509 /* Get pointer to the transmit driver descriptor block information */ 3510 3511 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]); 3512 3513 /* Return skb to operating system */ 3514 comp = bp->rcv_xmt_reg.index.xmt_comp; 3515 dma_unmap_single(bp->bus_dev, 3516 bp->descr_block_virt->xmt_data[comp].long_1, 3517 p_xmt_drv_descr->p_skb->len, 3518 DMA_TO_DEVICE); 3519 dev_kfree_skb(p_xmt_drv_descr->p_skb); 3520 3521 /* Increment transmit error counter */ 3522 3523 bp->xmt_discards++; 3524 3525 /* 3526 * Move to start of next packet by updating completion index 3527 * 3528 * Here we assume that a transmit packet request is always 3529 * serviced by posting one fragment. We can therefore 3530 * simplify the completion code by incrementing the 3531 * completion index by one. This code will need to be 3532 * modified if this assumption changes. See comments 3533 * in dfx_xmt_queue_pkt for more details. 3534 */ 3535 3536 bp->rcv_xmt_reg.index.xmt_comp += 1; 3537 } 3538 3539 /* Update the transmit consumer index in the consumer block */ 3540 3541 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX); 3542 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX); 3543 bp->cons_block_virt->xmt_rcv_data = prod_cons; 3544 } 3545 3546 /* 3547 * ================== 3548 * = dfx_unregister = 3549 * ================== 3550 * 3551 * Overview: 3552 * Shuts down an FDDI controller 3553 * 3554 * Returns: 3555 * Condition code 3556 * 3557 * Arguments: 3558 * bdev - pointer to device information 3559 * 3560 * Functional Description: 3561 * 3562 * Return Codes: 3563 * None 3564 * 3565 * Assumptions: 3566 * It compiles so it should work :-( (PCI cards do :-) 3567 * 3568 * Side Effects: 3569 * Device structures for FDDI adapters (fddi0, fddi1, etc) are 3570 * freed. 3571 */ 3572 static void dfx_unregister(struct device *bdev) 3573 { 3574 struct net_device *dev = dev_get_drvdata(bdev); 3575 DFX_board_t *bp = netdev_priv(dev); 3576 int dfx_bus_pci = dev_is_pci(bdev); 3577 int dfx_bus_tc = DFX_BUS_TC(bdev); 3578 int dfx_use_mmio = DFX_MMIO || dfx_bus_tc; 3579 resource_size_t bar_start = 0; /* pointer to port */ 3580 resource_size_t bar_len = 0; /* resource length */ 3581 int alloc_size; /* total buffer size used */ 3582 3583 unregister_netdev(dev); 3584 3585 alloc_size = sizeof(PI_DESCR_BLOCK) + 3586 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX + 3587 #ifndef DYNAMIC_BUFFERS 3588 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) + 3589 #endif 3590 sizeof(PI_CONSUMER_BLOCK) + 3591 (PI_ALIGN_K_DESC_BLK - 1); 3592 if (bp->kmalloced) 3593 dma_free_coherent(bdev, alloc_size, 3594 bp->kmalloced, bp->kmalloced_dma); 3595 3596 dfx_bus_uninit(dev); 3597 3598 dfx_get_bars(bdev, &bar_start, &bar_len); 3599 if (dfx_use_mmio) { 3600 iounmap(bp->base.mem); 3601 release_mem_region(bar_start, bar_len); 3602 } else 3603 release_region(bar_start, bar_len); 3604 3605 if (dfx_bus_pci) 3606 pci_disable_device(to_pci_dev(bdev)); 3607 3608 free_netdev(dev); 3609 } 3610 3611 3612 static int __maybe_unused dfx_dev_register(struct device *); 3613 static int __maybe_unused dfx_dev_unregister(struct device *); 3614 3615 #ifdef CONFIG_PCI 3616 static int dfx_pci_register(struct pci_dev *, const struct pci_device_id *); 3617 static void dfx_pci_unregister(struct pci_dev *); 3618 3619 static DEFINE_PCI_DEVICE_TABLE(dfx_pci_table) = { 3620 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) }, 3621 { } 3622 }; 3623 MODULE_DEVICE_TABLE(pci, dfx_pci_table); 3624 3625 static struct pci_driver dfx_pci_driver = { 3626 .name = "defxx", 3627 .id_table = dfx_pci_table, 3628 .probe = dfx_pci_register, 3629 .remove = dfx_pci_unregister, 3630 }; 3631 3632 static int dfx_pci_register(struct pci_dev *pdev, 3633 const struct pci_device_id *ent) 3634 { 3635 return dfx_register(&pdev->dev); 3636 } 3637 3638 static void dfx_pci_unregister(struct pci_dev *pdev) 3639 { 3640 dfx_unregister(&pdev->dev); 3641 } 3642 #endif /* CONFIG_PCI */ 3643 3644 #ifdef CONFIG_EISA 3645 static struct eisa_device_id dfx_eisa_table[] = { 3646 { "DEC3001", DEFEA_PROD_ID_1 }, 3647 { "DEC3002", DEFEA_PROD_ID_2 }, 3648 { "DEC3003", DEFEA_PROD_ID_3 }, 3649 { "DEC3004", DEFEA_PROD_ID_4 }, 3650 { } 3651 }; 3652 MODULE_DEVICE_TABLE(eisa, dfx_eisa_table); 3653 3654 static struct eisa_driver dfx_eisa_driver = { 3655 .id_table = dfx_eisa_table, 3656 .driver = { 3657 .name = "defxx", 3658 .bus = &eisa_bus_type, 3659 .probe = dfx_dev_register, 3660 .remove = dfx_dev_unregister, 3661 }, 3662 }; 3663 #endif /* CONFIG_EISA */ 3664 3665 #ifdef CONFIG_TC 3666 static struct tc_device_id const dfx_tc_table[] = { 3667 { "DEC ", "PMAF-FA " }, 3668 { "DEC ", "PMAF-FD " }, 3669 { "DEC ", "PMAF-FS " }, 3670 { "DEC ", "PMAF-FU " }, 3671 { } 3672 }; 3673 MODULE_DEVICE_TABLE(tc, dfx_tc_table); 3674 3675 static struct tc_driver dfx_tc_driver = { 3676 .id_table = dfx_tc_table, 3677 .driver = { 3678 .name = "defxx", 3679 .bus = &tc_bus_type, 3680 .probe = dfx_dev_register, 3681 .remove = dfx_dev_unregister, 3682 }, 3683 }; 3684 #endif /* CONFIG_TC */ 3685 3686 static int __maybe_unused dfx_dev_register(struct device *dev) 3687 { 3688 int status; 3689 3690 status = dfx_register(dev); 3691 if (!status) 3692 get_device(dev); 3693 return status; 3694 } 3695 3696 static int __maybe_unused dfx_dev_unregister(struct device *dev) 3697 { 3698 put_device(dev); 3699 dfx_unregister(dev); 3700 return 0; 3701 } 3702 3703 3704 static int dfx_init(void) 3705 { 3706 int status; 3707 3708 status = pci_register_driver(&dfx_pci_driver); 3709 if (!status) 3710 status = eisa_driver_register(&dfx_eisa_driver); 3711 if (!status) 3712 status = tc_register_driver(&dfx_tc_driver); 3713 return status; 3714 } 3715 3716 static void dfx_cleanup(void) 3717 { 3718 tc_unregister_driver(&dfx_tc_driver); 3719 eisa_driver_unregister(&dfx_eisa_driver); 3720 pci_unregister_driver(&dfx_pci_driver); 3721 } 3722 3723 module_init(dfx_init); 3724 module_exit(dfx_cleanup); 3725 MODULE_AUTHOR("Lawrence V. Stefani"); 3726 MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver " 3727 DRV_VERSION " " DRV_RELDATE); 3728 MODULE_LICENSE("GPL"); 3729