1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel IXP4xx Ethernet driver for Linux 4 * 5 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * Ethernet port config (0x00 is not present on IXP42X): 8 * 9 * logical port 0x00 0x10 0x20 10 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) 11 * physical PortId 2 0 1 12 * TX queue 23 24 25 13 * RX-free queue 26 27 28 14 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable 15 * 16 * Queue entries: 17 * bits 0 -> 1 - NPE ID (RX and TX-done) 18 * bits 0 -> 2 - priority (TX, per 802.1D) 19 * bits 3 -> 4 - port ID (user-set?) 20 * bits 5 -> 31 - physical descriptor address 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmapool.h> 26 #include <linux/etherdevice.h> 27 #include <linux/if_vlan.h> 28 #include <linux/io.h> 29 #include <linux/kernel.h> 30 #include <linux/net_tstamp.h> 31 #include <linux/of.h> 32 #include <linux/of_mdio.h> 33 #include <linux/of_net.h> 34 #include <linux/phy.h> 35 #include <linux/platform_device.h> 36 #include <linux/ptp_classify.h> 37 #include <linux/slab.h> 38 #include <linux/module.h> 39 #include <linux/soc/ixp4xx/npe.h> 40 #include <linux/soc/ixp4xx/qmgr.h> 41 #include <linux/soc/ixp4xx/cpu.h> 42 #include <linux/types.h> 43 44 #define IXP4XX_ETH_NPEA 0x00 45 #define IXP4XX_ETH_NPEB 0x10 46 #define IXP4XX_ETH_NPEC 0x20 47 48 #include "ixp46x_ts.h" 49 50 #define DEBUG_DESC 0 51 #define DEBUG_RX 0 52 #define DEBUG_TX 0 53 #define DEBUG_PKT_BYTES 0 54 #define DEBUG_MDIO 0 55 #define DEBUG_CLOSE 0 56 57 #define DRV_NAME "ixp4xx_eth" 58 59 #define MAX_NPES 3 60 61 #define RX_DESCS 64 /* also length of all RX queues */ 62 #define TX_DESCS 16 /* also length of all TX queues */ 63 #define TXDONE_QUEUE_LEN 64 /* dwords */ 64 65 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 66 #define REGS_SIZE 0x1000 67 #define MAX_MRU 1536 /* 0x600 */ 68 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) 69 70 #define NAPI_WEIGHT 16 71 #define MDIO_INTERVAL (3 * HZ) 72 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ 73 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ 74 75 #define NPE_ID(port_id) ((port_id) >> 4) 76 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) 77 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) 78 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) 79 #define TXDONE_QUEUE 31 80 81 #define PTP_SLAVE_MODE 1 82 #define PTP_MASTER_MODE 2 83 #define PORT2CHANNEL(p) NPE_ID(p->id) 84 85 /* TX Control Registers */ 86 #define TX_CNTRL0_TX_EN 0x01 87 #define TX_CNTRL0_HALFDUPLEX 0x02 88 #define TX_CNTRL0_RETRY 0x04 89 #define TX_CNTRL0_PAD_EN 0x08 90 #define TX_CNTRL0_APPEND_FCS 0x10 91 #define TX_CNTRL0_2DEFER 0x20 92 #define TX_CNTRL0_RMII 0x40 /* reduced MII */ 93 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ 94 95 /* RX Control Registers */ 96 #define RX_CNTRL0_RX_EN 0x01 97 #define RX_CNTRL0_PADSTRIP_EN 0x02 98 #define RX_CNTRL0_SEND_FCS 0x04 99 #define RX_CNTRL0_PAUSE_EN 0x08 100 #define RX_CNTRL0_LOOP_EN 0x10 101 #define RX_CNTRL0_ADDR_FLTR_EN 0x20 102 #define RX_CNTRL0_RX_RUNT_EN 0x40 103 #define RX_CNTRL0_BCAST_DIS 0x80 104 #define RX_CNTRL1_DEFER_EN 0x01 105 106 /* Core Control Register */ 107 #define CORE_RESET 0x01 108 #define CORE_RX_FIFO_FLUSH 0x02 109 #define CORE_TX_FIFO_FLUSH 0x04 110 #define CORE_SEND_JAM 0x08 111 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ 112 113 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ 114 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ 115 TX_CNTRL0_2DEFER) 116 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN 117 #define DEFAULT_CORE_CNTRL CORE_MDC_EN 118 119 120 /* NPE message codes */ 121 #define NPE_GETSTATUS 0x00 122 #define NPE_EDB_SETPORTADDRESS 0x01 123 #define NPE_EDB_GETMACADDRESSDATABASE 0x02 124 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 125 #define NPE_GETSTATS 0x04 126 #define NPE_RESETSTATS 0x05 127 #define NPE_SETMAXFRAMELENGTHS 0x06 128 #define NPE_VLAN_SETRXTAGMODE 0x07 129 #define NPE_VLAN_SETDEFAULTRXVID 0x08 130 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 131 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A 132 #define NPE_VLAN_SETRXQOSENTRY 0x0B 133 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C 134 #define NPE_STP_SETBLOCKINGSTATE 0x0D 135 #define NPE_FW_SETFIREWALLMODE 0x0E 136 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F 137 #define NPE_PC_SETAPMACTABLE 0x11 138 #define NPE_SETLOOPBACK_MODE 0x12 139 #define NPE_PC_SETBSSIDTABLE 0x13 140 #define NPE_ADDRESS_FILTER_CONFIG 0x14 141 #define NPE_APPENDFCSCONFIG 0x15 142 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 143 #define NPE_MAC_RECOVERY_START 0x17 144 145 146 #ifdef __ARMEB__ 147 typedef struct sk_buff buffer_t; 148 #define free_buffer dev_kfree_skb 149 #define free_buffer_irq dev_consume_skb_irq 150 #else 151 typedef void buffer_t; 152 #define free_buffer kfree 153 #define free_buffer_irq kfree 154 #endif 155 156 /* Information about built-in Ethernet MAC interfaces */ 157 struct eth_plat_info { 158 u8 phy; /* MII PHY ID, 0 - 31 */ 159 u8 rxq; /* configurable, currently 0 - 31 only */ 160 u8 txreadyq; 161 u8 hwaddr[ETH_ALEN]; 162 u8 npe; /* NPE instance used by this interface */ 163 bool has_mdio; /* If this instance has an MDIO bus */ 164 }; 165 166 struct eth_regs { 167 u32 tx_control[2], __res1[2]; /* 000 */ 168 u32 rx_control[2], __res2[2]; /* 010 */ 169 u32 random_seed, __res3[3]; /* 020 */ 170 u32 partial_empty_threshold, __res4; /* 030 */ 171 u32 partial_full_threshold, __res5; /* 038 */ 172 u32 tx_start_bytes, __res6[3]; /* 040 */ 173 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ 174 u32 tx_2part_deferral[2], __res8[2]; /* 060 */ 175 u32 slot_time, __res9[3]; /* 070 */ 176 u32 mdio_command[4]; /* 080 */ 177 u32 mdio_status[4]; /* 090 */ 178 u32 mcast_mask[6], __res10[2]; /* 0A0 */ 179 u32 mcast_addr[6], __res11[2]; /* 0C0 */ 180 u32 int_clock_threshold, __res12[3]; /* 0E0 */ 181 u32 hw_addr[6], __res13[61]; /* 0F0 */ 182 u32 core_control; /* 1FC */ 183 }; 184 185 struct port { 186 struct eth_regs __iomem *regs; 187 struct ixp46x_ts_regs __iomem *timesync_regs; 188 int phc_index; 189 struct npe *npe; 190 struct net_device *netdev; 191 struct napi_struct napi; 192 struct eth_plat_info *plat; 193 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 194 struct desc *desc_tab; /* coherent */ 195 dma_addr_t desc_tab_phys; 196 int id; /* logical port ID */ 197 int speed, duplex; 198 u8 firmware[4]; 199 int hwts_tx_en; 200 int hwts_rx_en; 201 }; 202 203 /* NPE message structure */ 204 struct msg { 205 #ifdef __ARMEB__ 206 u8 cmd, eth_id, byte2, byte3; 207 u8 byte4, byte5, byte6, byte7; 208 #else 209 u8 byte3, byte2, eth_id, cmd; 210 u8 byte7, byte6, byte5, byte4; 211 #endif 212 }; 213 214 /* Ethernet packet descriptor */ 215 struct desc { 216 u32 next; /* pointer to next buffer, unused */ 217 218 #ifdef __ARMEB__ 219 u16 buf_len; /* buffer length */ 220 u16 pkt_len; /* packet length */ 221 u32 data; /* pointer to data buffer in RAM */ 222 u8 dest_id; 223 u8 src_id; 224 u16 flags; 225 u8 qos; 226 u8 padlen; 227 u16 vlan_tci; 228 #else 229 u16 pkt_len; /* packet length */ 230 u16 buf_len; /* buffer length */ 231 u32 data; /* pointer to data buffer in RAM */ 232 u16 flags; 233 u8 src_id; 234 u8 dest_id; 235 u16 vlan_tci; 236 u8 padlen; 237 u8 qos; 238 #endif 239 240 #ifdef __ARMEB__ 241 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; 242 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; 243 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; 244 #else 245 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; 246 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; 247 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; 248 #endif 249 }; 250 251 252 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 253 (n) * sizeof(struct desc)) 254 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 255 256 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 257 ((n) + RX_DESCS) * sizeof(struct desc)) 258 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 259 260 #ifndef __ARMEB__ 261 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 262 { 263 int i; 264 for (i = 0; i < cnt; i++) 265 dest[i] = swab32(src[i]); 266 } 267 #endif 268 269 static DEFINE_SPINLOCK(mdio_lock); 270 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ 271 static struct mii_bus *mdio_bus; 272 static struct device_node *mdio_bus_np; 273 static int ports_open; 274 static struct port *npe_port_tab[MAX_NPES]; 275 static struct dma_pool *dma_pool; 276 277 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 278 { 279 u8 *data = skb->data; 280 unsigned int offset; 281 u16 *hi, *id; 282 u32 lo; 283 284 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4) 285 return 0; 286 287 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 288 289 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 290 return 0; 291 292 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID); 293 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 294 295 memcpy(&lo, &hi[1], sizeof(lo)); 296 297 return (uid_hi == ntohs(*hi) && 298 uid_lo == ntohl(lo) && 299 seqid == ntohs(*id)); 300 } 301 302 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb) 303 { 304 struct skb_shared_hwtstamps *shhwtstamps; 305 struct ixp46x_ts_regs *regs; 306 u64 ns; 307 u32 ch, hi, lo, val; 308 u16 uid, seq; 309 310 if (!port->hwts_rx_en) 311 return; 312 313 ch = PORT2CHANNEL(port); 314 315 regs = port->timesync_regs; 316 317 val = __raw_readl(®s->channel[ch].ch_event); 318 319 if (!(val & RX_SNAPSHOT_LOCKED)) 320 return; 321 322 lo = __raw_readl(®s->channel[ch].src_uuid_lo); 323 hi = __raw_readl(®s->channel[ch].src_uuid_hi); 324 325 uid = hi & 0xffff; 326 seq = (hi >> 16) & 0xffff; 327 328 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq))) 329 goto out; 330 331 lo = __raw_readl(®s->channel[ch].rx_snap_lo); 332 hi = __raw_readl(®s->channel[ch].rx_snap_hi); 333 ns = ((u64) hi) << 32; 334 ns |= lo; 335 ns <<= TICKS_NS_SHIFT; 336 337 shhwtstamps = skb_hwtstamps(skb); 338 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 339 shhwtstamps->hwtstamp = ns_to_ktime(ns); 340 out: 341 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 342 } 343 344 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb) 345 { 346 struct skb_shared_hwtstamps shhwtstamps; 347 struct ixp46x_ts_regs *regs; 348 struct skb_shared_info *shtx; 349 u64 ns; 350 u32 ch, cnt, hi, lo, val; 351 352 shtx = skb_shinfo(skb); 353 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en)) 354 shtx->tx_flags |= SKBTX_IN_PROGRESS; 355 else 356 return; 357 358 ch = PORT2CHANNEL(port); 359 360 regs = port->timesync_regs; 361 362 /* 363 * This really stinks, but we have to poll for the Tx time stamp. 364 * Usually, the time stamp is ready after 4 to 6 microseconds. 365 */ 366 for (cnt = 0; cnt < 100; cnt++) { 367 val = __raw_readl(®s->channel[ch].ch_event); 368 if (val & TX_SNAPSHOT_LOCKED) 369 break; 370 udelay(1); 371 } 372 if (!(val & TX_SNAPSHOT_LOCKED)) { 373 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 374 return; 375 } 376 377 lo = __raw_readl(®s->channel[ch].tx_snap_lo); 378 hi = __raw_readl(®s->channel[ch].tx_snap_hi); 379 ns = ((u64) hi) << 32; 380 ns |= lo; 381 ns <<= TICKS_NS_SHIFT; 382 383 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 384 shhwtstamps.hwtstamp = ns_to_ktime(ns); 385 skb_tstamp_tx(skb, &shhwtstamps); 386 387 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 388 } 389 390 static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) 391 { 392 struct hwtstamp_config cfg; 393 struct ixp46x_ts_regs *regs; 394 struct port *port = netdev_priv(netdev); 395 int ret; 396 int ch; 397 398 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 399 return -EFAULT; 400 401 ret = ixp46x_ptp_find(&port->timesync_regs, &port->phc_index); 402 if (ret) 403 return ret; 404 405 ch = PORT2CHANNEL(port); 406 regs = port->timesync_regs; 407 408 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 409 return -ERANGE; 410 411 switch (cfg.rx_filter) { 412 case HWTSTAMP_FILTER_NONE: 413 port->hwts_rx_en = 0; 414 break; 415 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 416 port->hwts_rx_en = PTP_SLAVE_MODE; 417 __raw_writel(0, ®s->channel[ch].ch_control); 418 break; 419 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 420 port->hwts_rx_en = PTP_MASTER_MODE; 421 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control); 422 break; 423 default: 424 return -ERANGE; 425 } 426 427 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON; 428 429 /* Clear out any old time stamps. */ 430 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED, 431 ®s->channel[ch].ch_event); 432 433 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 434 } 435 436 static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) 437 { 438 struct hwtstamp_config cfg; 439 struct port *port = netdev_priv(netdev); 440 441 cfg.flags = 0; 442 cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 443 444 switch (port->hwts_rx_en) { 445 case 0: 446 cfg.rx_filter = HWTSTAMP_FILTER_NONE; 447 break; 448 case PTP_SLAVE_MODE: 449 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 450 break; 451 case PTP_MASTER_MODE: 452 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 453 break; 454 default: 455 WARN_ON_ONCE(1); 456 return -ERANGE; 457 } 458 459 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 460 } 461 462 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, 463 int write, u16 cmd) 464 { 465 int cycles = 0; 466 467 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { 468 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name); 469 return -1; 470 } 471 472 if (write) { 473 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); 474 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); 475 } 476 __raw_writel(((phy_id << 5) | location) & 0xFF, 477 &mdio_regs->mdio_command[2]); 478 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, 479 &mdio_regs->mdio_command[3]); 480 481 while ((cycles < MAX_MDIO_RETRIES) && 482 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { 483 udelay(1); 484 cycles++; 485 } 486 487 if (cycles == MAX_MDIO_RETRIES) { 488 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name, 489 phy_id); 490 return -1; 491 } 492 493 #if DEBUG_MDIO 494 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name, 495 phy_id, write ? "write" : "read", cycles); 496 #endif 497 498 if (write) 499 return 0; 500 501 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { 502 #if DEBUG_MDIO 503 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name, 504 phy_id); 505 #endif 506 return 0xFFFF; /* don't return error */ 507 } 508 509 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | 510 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); 511 } 512 513 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location) 514 { 515 unsigned long flags; 516 int ret; 517 518 spin_lock_irqsave(&mdio_lock, flags); 519 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0); 520 spin_unlock_irqrestore(&mdio_lock, flags); 521 #if DEBUG_MDIO 522 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name, 523 phy_id, location, ret); 524 #endif 525 return ret; 526 } 527 528 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, 529 u16 val) 530 { 531 unsigned long flags; 532 int ret; 533 534 spin_lock_irqsave(&mdio_lock, flags); 535 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); 536 spin_unlock_irqrestore(&mdio_lock, flags); 537 #if DEBUG_MDIO 538 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", 539 bus->name, phy_id, location, val, ret); 540 #endif 541 return ret; 542 } 543 544 static int ixp4xx_mdio_register(struct eth_regs __iomem *regs) 545 { 546 int err; 547 548 if (!(mdio_bus = mdiobus_alloc())) 549 return -ENOMEM; 550 551 mdio_regs = regs; 552 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); 553 mdio_bus->name = "IXP4xx MII Bus"; 554 mdio_bus->read = &ixp4xx_mdio_read; 555 mdio_bus->write = &ixp4xx_mdio_write; 556 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0"); 557 558 err = of_mdiobus_register(mdio_bus, mdio_bus_np); 559 if (err) 560 mdiobus_free(mdio_bus); 561 return err; 562 } 563 564 static void ixp4xx_mdio_remove(void) 565 { 566 mdiobus_unregister(mdio_bus); 567 mdiobus_free(mdio_bus); 568 } 569 570 571 static void ixp4xx_adjust_link(struct net_device *dev) 572 { 573 struct port *port = netdev_priv(dev); 574 struct phy_device *phydev = dev->phydev; 575 576 if (!phydev->link) { 577 if (port->speed) { 578 port->speed = 0; 579 printk(KERN_INFO "%s: link down\n", dev->name); 580 } 581 return; 582 } 583 584 if (port->speed == phydev->speed && port->duplex == phydev->duplex) 585 return; 586 587 port->speed = phydev->speed; 588 port->duplex = phydev->duplex; 589 590 if (port->duplex) 591 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, 592 &port->regs->tx_control[0]); 593 else 594 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, 595 &port->regs->tx_control[0]); 596 597 netdev_info(dev, "%s: link up, speed %u Mb/s, %s duplex\n", 598 dev->name, port->speed, port->duplex ? "full" : "half"); 599 } 600 601 602 static inline void debug_pkt(struct net_device *dev, const char *func, 603 u8 *data, int len) 604 { 605 #if DEBUG_PKT_BYTES 606 int i; 607 608 netdev_debug(dev, "%s(%i) ", func, len); 609 for (i = 0; i < len; i++) { 610 if (i >= DEBUG_PKT_BYTES) 611 break; 612 printk("%s%02X", 613 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", 614 data[i]); 615 } 616 printk("\n"); 617 #endif 618 } 619 620 621 static inline void debug_desc(u32 phys, struct desc *desc) 622 { 623 #if DEBUG_DESC 624 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" 625 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", 626 phys, desc->next, desc->buf_len, desc->pkt_len, 627 desc->data, desc->dest_id, desc->src_id, desc->flags, 628 desc->qos, desc->padlen, desc->vlan_tci, 629 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, 630 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, 631 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, 632 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); 633 #endif 634 } 635 636 static inline int queue_get_desc(unsigned int queue, struct port *port, 637 int is_tx) 638 { 639 u32 phys, tab_phys, n_desc; 640 struct desc *tab; 641 642 if (!(phys = qmgr_get_entry(queue))) 643 return -1; 644 645 phys &= ~0x1F; /* mask out non-address bits */ 646 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 647 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 648 n_desc = (phys - tab_phys) / sizeof(struct desc); 649 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 650 debug_desc(phys, &tab[n_desc]); 651 BUG_ON(tab[n_desc].next); 652 return n_desc; 653 } 654 655 static inline void queue_put_desc(unsigned int queue, u32 phys, 656 struct desc *desc) 657 { 658 debug_desc(phys, desc); 659 BUG_ON(phys & 0x1F); 660 qmgr_put_entry(queue, phys); 661 /* Don't check for queue overflow here, we've allocated sufficient 662 length and queues >= 32 don't support this check anyway. */ 663 } 664 665 666 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 667 { 668 #ifdef __ARMEB__ 669 dma_unmap_single(&port->netdev->dev, desc->data, 670 desc->buf_len, DMA_TO_DEVICE); 671 #else 672 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 673 ALIGN((desc->data & 3) + desc->buf_len, 4), 674 DMA_TO_DEVICE); 675 #endif 676 } 677 678 679 static void eth_rx_irq(void *pdev) 680 { 681 struct net_device *dev = pdev; 682 struct port *port = netdev_priv(dev); 683 684 #if DEBUG_RX 685 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); 686 #endif 687 qmgr_disable_irq(port->plat->rxq); 688 napi_schedule(&port->napi); 689 } 690 691 static int eth_poll(struct napi_struct *napi, int budget) 692 { 693 struct port *port = container_of(napi, struct port, napi); 694 struct net_device *dev = port->netdev; 695 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); 696 int received = 0; 697 698 #if DEBUG_RX 699 netdev_debug(dev, "eth_poll\n"); 700 #endif 701 702 while (received < budget) { 703 struct sk_buff *skb; 704 struct desc *desc; 705 int n; 706 #ifdef __ARMEB__ 707 struct sk_buff *temp; 708 u32 phys; 709 #endif 710 711 if ((n = queue_get_desc(rxq, port, 0)) < 0) { 712 #if DEBUG_RX 713 netdev_debug(dev, "eth_poll napi_complete\n"); 714 #endif 715 napi_complete(napi); 716 qmgr_enable_irq(rxq); 717 if (!qmgr_stat_below_low_watermark(rxq) && 718 napi_reschedule(napi)) { /* not empty again */ 719 #if DEBUG_RX 720 netdev_debug(dev, "eth_poll napi_reschedule succeeded\n"); 721 #endif 722 qmgr_disable_irq(rxq); 723 continue; 724 } 725 #if DEBUG_RX 726 netdev_debug(dev, "eth_poll all done\n"); 727 #endif 728 return received; /* all work done */ 729 } 730 731 desc = rx_desc_ptr(port, n); 732 733 #ifdef __ARMEB__ 734 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { 735 phys = dma_map_single(&dev->dev, skb->data, 736 RX_BUFF_SIZE, DMA_FROM_DEVICE); 737 if (dma_mapping_error(&dev->dev, phys)) { 738 dev_kfree_skb(skb); 739 skb = NULL; 740 } 741 } 742 #else 743 skb = netdev_alloc_skb(dev, 744 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); 745 #endif 746 747 if (!skb) { 748 dev->stats.rx_dropped++; 749 /* put the desc back on RX-ready queue */ 750 desc->buf_len = MAX_MRU; 751 desc->pkt_len = 0; 752 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 753 continue; 754 } 755 756 /* process received frame */ 757 #ifdef __ARMEB__ 758 temp = skb; 759 skb = port->rx_buff_tab[n]; 760 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, 761 RX_BUFF_SIZE, DMA_FROM_DEVICE); 762 #else 763 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, 764 RX_BUFF_SIZE, DMA_FROM_DEVICE); 765 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 766 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); 767 #endif 768 skb_reserve(skb, NET_IP_ALIGN); 769 skb_put(skb, desc->pkt_len); 770 771 debug_pkt(dev, "eth_poll", skb->data, skb->len); 772 773 ixp_rx_timestamp(port, skb); 774 skb->protocol = eth_type_trans(skb, dev); 775 dev->stats.rx_packets++; 776 dev->stats.rx_bytes += skb->len; 777 netif_receive_skb(skb); 778 779 /* put the new buffer on RX-free queue */ 780 #ifdef __ARMEB__ 781 port->rx_buff_tab[n] = temp; 782 desc->data = phys + NET_IP_ALIGN; 783 #endif 784 desc->buf_len = MAX_MRU; 785 desc->pkt_len = 0; 786 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 787 received++; 788 } 789 790 #if DEBUG_RX 791 netdev_debug(dev, "eth_poll(): end, not all work done\n"); 792 #endif 793 return received; /* not all work done */ 794 } 795 796 797 static void eth_txdone_irq(void *unused) 798 { 799 u32 phys; 800 801 #if DEBUG_TX 802 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); 803 #endif 804 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) { 805 u32 npe_id, n_desc; 806 struct port *port; 807 struct desc *desc; 808 int start; 809 810 npe_id = phys & 3; 811 BUG_ON(npe_id >= MAX_NPES); 812 port = npe_port_tab[npe_id]; 813 BUG_ON(!port); 814 phys &= ~0x1F; /* mask out non-address bits */ 815 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); 816 BUG_ON(n_desc >= TX_DESCS); 817 desc = tx_desc_ptr(port, n_desc); 818 debug_desc(phys, desc); 819 820 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ 821 port->netdev->stats.tx_packets++; 822 port->netdev->stats.tx_bytes += desc->pkt_len; 823 824 dma_unmap_tx(port, desc); 825 #if DEBUG_TX 826 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", 827 port->netdev->name, port->tx_buff_tab[n_desc]); 828 #endif 829 free_buffer_irq(port->tx_buff_tab[n_desc]); 830 port->tx_buff_tab[n_desc] = NULL; 831 } 832 833 start = qmgr_stat_below_low_watermark(port->plat->txreadyq); 834 queue_put_desc(port->plat->txreadyq, phys, desc); 835 if (start) { /* TX-ready queue was empty */ 836 #if DEBUG_TX 837 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", 838 port->netdev->name); 839 #endif 840 netif_wake_queue(port->netdev); 841 } 842 } 843 } 844 845 static netdev_tx_t eth_xmit(struct sk_buff *skb, struct net_device *dev) 846 { 847 struct port *port = netdev_priv(dev); 848 unsigned int txreadyq = port->plat->txreadyq; 849 int len, offset, bytes, n; 850 void *mem; 851 u32 phys; 852 struct desc *desc; 853 854 #if DEBUG_TX 855 netdev_debug(dev, "eth_xmit\n"); 856 #endif 857 858 if (unlikely(skb->len > MAX_MRU)) { 859 dev_kfree_skb(skb); 860 dev->stats.tx_errors++; 861 return NETDEV_TX_OK; 862 } 863 864 debug_pkt(dev, "eth_xmit", skb->data, skb->len); 865 866 len = skb->len; 867 #ifdef __ARMEB__ 868 offset = 0; /* no need to keep alignment */ 869 bytes = len; 870 mem = skb->data; 871 #else 872 offset = (uintptr_t)skb->data & 3; /* keep 32-bit alignment */ 873 bytes = ALIGN(offset + len, 4); 874 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { 875 dev_kfree_skb(skb); 876 dev->stats.tx_dropped++; 877 return NETDEV_TX_OK; 878 } 879 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4); 880 #endif 881 882 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 883 if (dma_mapping_error(&dev->dev, phys)) { 884 dev_kfree_skb(skb); 885 #ifndef __ARMEB__ 886 kfree(mem); 887 #endif 888 dev->stats.tx_dropped++; 889 return NETDEV_TX_OK; 890 } 891 892 n = queue_get_desc(txreadyq, port, 1); 893 BUG_ON(n < 0); 894 desc = tx_desc_ptr(port, n); 895 896 #ifdef __ARMEB__ 897 port->tx_buff_tab[n] = skb; 898 #else 899 port->tx_buff_tab[n] = mem; 900 #endif 901 desc->data = phys + offset; 902 desc->buf_len = desc->pkt_len = len; 903 904 /* NPE firmware pads short frames with zeros internally */ 905 wmb(); 906 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); 907 908 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 909 #if DEBUG_TX 910 netdev_debug(dev, "eth_xmit queue full\n"); 911 #endif 912 netif_stop_queue(dev); 913 /* we could miss TX ready interrupt */ 914 /* really empty in fact */ 915 if (!qmgr_stat_below_low_watermark(txreadyq)) { 916 #if DEBUG_TX 917 netdev_debug(dev, "eth_xmit ready again\n"); 918 #endif 919 netif_wake_queue(dev); 920 } 921 } 922 923 #if DEBUG_TX 924 netdev_debug(dev, "eth_xmit end\n"); 925 #endif 926 927 ixp_tx_timestamp(port, skb); 928 skb_tx_timestamp(skb); 929 930 #ifndef __ARMEB__ 931 dev_kfree_skb(skb); 932 #endif 933 return NETDEV_TX_OK; 934 } 935 936 937 static void eth_set_mcast_list(struct net_device *dev) 938 { 939 struct port *port = netdev_priv(dev); 940 struct netdev_hw_addr *ha; 941 u8 diffs[ETH_ALEN], *addr; 942 int i; 943 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 944 945 if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) { 946 for (i = 0; i < ETH_ALEN; i++) { 947 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]); 948 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]); 949 } 950 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 951 &port->regs->rx_control[0]); 952 return; 953 } 954 955 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) { 956 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, 957 &port->regs->rx_control[0]); 958 return; 959 } 960 961 eth_zero_addr(diffs); 962 963 addr = NULL; 964 netdev_for_each_mc_addr(ha, dev) { 965 if (!addr) 966 addr = ha->addr; /* first MAC address */ 967 for (i = 0; i < ETH_ALEN; i++) 968 diffs[i] |= addr[i] ^ ha->addr[i]; 969 } 970 971 for (i = 0; i < ETH_ALEN; i++) { 972 __raw_writel(addr[i], &port->regs->mcast_addr[i]); 973 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); 974 } 975 976 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 977 &port->regs->rx_control[0]); 978 } 979 980 981 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 982 { 983 if (!netif_running(dev)) 984 return -EINVAL; 985 986 if (cpu_is_ixp46x()) { 987 if (cmd == SIOCSHWTSTAMP) 988 return hwtstamp_set(dev, req); 989 if (cmd == SIOCGHWTSTAMP) 990 return hwtstamp_get(dev, req); 991 } 992 993 return phy_mii_ioctl(dev->phydev, req, cmd); 994 } 995 996 /* ethtool support */ 997 998 static void ixp4xx_get_drvinfo(struct net_device *dev, 999 struct ethtool_drvinfo *info) 1000 { 1001 struct port *port = netdev_priv(dev); 1002 1003 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 1004 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u", 1005 port->firmware[0], port->firmware[1], 1006 port->firmware[2], port->firmware[3]); 1007 strscpy(info->bus_info, "internal", sizeof(info->bus_info)); 1008 } 1009 1010 static int ixp4xx_get_ts_info(struct net_device *dev, 1011 struct ethtool_ts_info *info) 1012 { 1013 struct port *port = netdev_priv(dev); 1014 1015 if (port->phc_index < 0) 1016 ixp46x_ptp_find(&port->timesync_regs, &port->phc_index); 1017 1018 info->phc_index = port->phc_index; 1019 1020 if (info->phc_index < 0) { 1021 info->so_timestamping = 1022 SOF_TIMESTAMPING_TX_SOFTWARE | 1023 SOF_TIMESTAMPING_RX_SOFTWARE | 1024 SOF_TIMESTAMPING_SOFTWARE; 1025 return 0; 1026 } 1027 info->so_timestamping = 1028 SOF_TIMESTAMPING_TX_HARDWARE | 1029 SOF_TIMESTAMPING_RX_HARDWARE | 1030 SOF_TIMESTAMPING_RAW_HARDWARE; 1031 info->tx_types = 1032 (1 << HWTSTAMP_TX_OFF) | 1033 (1 << HWTSTAMP_TX_ON); 1034 info->rx_filters = 1035 (1 << HWTSTAMP_FILTER_NONE) | 1036 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1037 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1038 return 0; 1039 } 1040 1041 static const struct ethtool_ops ixp4xx_ethtool_ops = { 1042 .get_drvinfo = ixp4xx_get_drvinfo, 1043 .nway_reset = phy_ethtool_nway_reset, 1044 .get_link = ethtool_op_get_link, 1045 .get_ts_info = ixp4xx_get_ts_info, 1046 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1047 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1048 }; 1049 1050 1051 static int request_queues(struct port *port) 1052 { 1053 int err; 1054 1055 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0, 1056 "%s:RX-free", port->netdev->name); 1057 if (err) 1058 return err; 1059 1060 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0, 1061 "%s:RX", port->netdev->name); 1062 if (err) 1063 goto rel_rxfree; 1064 1065 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0, 1066 "%s:TX", port->netdev->name); 1067 if (err) 1068 goto rel_rx; 1069 1070 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, 1071 "%s:TX-ready", port->netdev->name); 1072 if (err) 1073 goto rel_tx; 1074 1075 /* TX-done queue handles skbs sent out by the NPEs */ 1076 if (!ports_open) { 1077 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0, 1078 "%s:TX-done", DRV_NAME); 1079 if (err) 1080 goto rel_txready; 1081 } 1082 return 0; 1083 1084 rel_txready: 1085 qmgr_release_queue(port->plat->txreadyq); 1086 rel_tx: 1087 qmgr_release_queue(TX_QUEUE(port->id)); 1088 rel_rx: 1089 qmgr_release_queue(port->plat->rxq); 1090 rel_rxfree: 1091 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1092 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 1093 port->netdev->name); 1094 return err; 1095 } 1096 1097 static void release_queues(struct port *port) 1098 { 1099 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1100 qmgr_release_queue(port->plat->rxq); 1101 qmgr_release_queue(TX_QUEUE(port->id)); 1102 qmgr_release_queue(port->plat->txreadyq); 1103 1104 if (!ports_open) 1105 qmgr_release_queue(TXDONE_QUEUE); 1106 } 1107 1108 static int init_queues(struct port *port) 1109 { 1110 int i; 1111 1112 if (!ports_open) { 1113 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, 1114 POOL_ALLOC_SIZE, 32, 0); 1115 if (!dma_pool) 1116 return -ENOMEM; 1117 } 1118 1119 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL, &port->desc_tab_phys); 1120 if (!port->desc_tab) 1121 return -ENOMEM; 1122 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 1123 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 1124 1125 /* Setup RX buffers */ 1126 for (i = 0; i < RX_DESCS; i++) { 1127 struct desc *desc = rx_desc_ptr(port, i); 1128 buffer_t *buff; /* skb or kmalloc()ated memory */ 1129 void *data; 1130 #ifdef __ARMEB__ 1131 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) 1132 return -ENOMEM; 1133 data = buff->data; 1134 #else 1135 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) 1136 return -ENOMEM; 1137 data = buff; 1138 #endif 1139 desc->buf_len = MAX_MRU; 1140 desc->data = dma_map_single(&port->netdev->dev, data, 1141 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1142 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1143 free_buffer(buff); 1144 return -EIO; 1145 } 1146 desc->data += NET_IP_ALIGN; 1147 port->rx_buff_tab[i] = buff; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void destroy_queues(struct port *port) 1154 { 1155 int i; 1156 1157 if (port->desc_tab) { 1158 for (i = 0; i < RX_DESCS; i++) { 1159 struct desc *desc = rx_desc_ptr(port, i); 1160 buffer_t *buff = port->rx_buff_tab[i]; 1161 if (buff) { 1162 dma_unmap_single(&port->netdev->dev, 1163 desc->data - NET_IP_ALIGN, 1164 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1165 free_buffer(buff); 1166 } 1167 } 1168 for (i = 0; i < TX_DESCS; i++) { 1169 struct desc *desc = tx_desc_ptr(port, i); 1170 buffer_t *buff = port->tx_buff_tab[i]; 1171 if (buff) { 1172 dma_unmap_tx(port, desc); 1173 free_buffer(buff); 1174 } 1175 } 1176 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1177 port->desc_tab = NULL; 1178 } 1179 1180 if (!ports_open && dma_pool) { 1181 dma_pool_destroy(dma_pool); 1182 dma_pool = NULL; 1183 } 1184 } 1185 1186 static int eth_open(struct net_device *dev) 1187 { 1188 struct port *port = netdev_priv(dev); 1189 struct npe *npe = port->npe; 1190 struct msg msg; 1191 int i, err; 1192 1193 if (!npe_running(npe)) { 1194 err = npe_load_firmware(npe, npe_name(npe), &dev->dev); 1195 if (err) 1196 return err; 1197 1198 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { 1199 netdev_err(dev, "%s not responding\n", npe_name(npe)); 1200 return -EIO; 1201 } 1202 port->firmware[0] = msg.byte4; 1203 port->firmware[1] = msg.byte5; 1204 port->firmware[2] = msg.byte6; 1205 port->firmware[3] = msg.byte7; 1206 } 1207 1208 memset(&msg, 0, sizeof(msg)); 1209 msg.cmd = NPE_VLAN_SETRXQOSENTRY; 1210 msg.eth_id = port->id; 1211 msg.byte5 = port->plat->rxq | 0x80; 1212 msg.byte7 = port->plat->rxq << 4; 1213 for (i = 0; i < 8; i++) { 1214 msg.byte3 = i; 1215 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) 1216 return -EIO; 1217 } 1218 1219 msg.cmd = NPE_EDB_SETPORTADDRESS; 1220 msg.eth_id = PHYSICAL_ID(port->id); 1221 msg.byte2 = dev->dev_addr[0]; 1222 msg.byte3 = dev->dev_addr[1]; 1223 msg.byte4 = dev->dev_addr[2]; 1224 msg.byte5 = dev->dev_addr[3]; 1225 msg.byte6 = dev->dev_addr[4]; 1226 msg.byte7 = dev->dev_addr[5]; 1227 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) 1228 return -EIO; 1229 1230 memset(&msg, 0, sizeof(msg)); 1231 msg.cmd = NPE_FW_SETFIREWALLMODE; 1232 msg.eth_id = port->id; 1233 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) 1234 return -EIO; 1235 1236 if ((err = request_queues(port)) != 0) 1237 return err; 1238 1239 if ((err = init_queues(port)) != 0) { 1240 destroy_queues(port); 1241 release_queues(port); 1242 return err; 1243 } 1244 1245 port->speed = 0; /* force "link up" message */ 1246 phy_start(dev->phydev); 1247 1248 for (i = 0; i < ETH_ALEN; i++) 1249 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); 1250 __raw_writel(0x08, &port->regs->random_seed); 1251 __raw_writel(0x12, &port->regs->partial_empty_threshold); 1252 __raw_writel(0x30, &port->regs->partial_full_threshold); 1253 __raw_writel(0x08, &port->regs->tx_start_bytes); 1254 __raw_writel(0x15, &port->regs->tx_deferral); 1255 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); 1256 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); 1257 __raw_writel(0x80, &port->regs->slot_time); 1258 __raw_writel(0x01, &port->regs->int_clock_threshold); 1259 1260 /* Populate queues with buffers, no failure after this point */ 1261 for (i = 0; i < TX_DESCS; i++) 1262 queue_put_desc(port->plat->txreadyq, 1263 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1264 1265 for (i = 0; i < RX_DESCS; i++) 1266 queue_put_desc(RXFREE_QUEUE(port->id), 1267 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1268 1269 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); 1270 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); 1271 __raw_writel(0, &port->regs->rx_control[1]); 1272 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); 1273 1274 napi_enable(&port->napi); 1275 eth_set_mcast_list(dev); 1276 netif_start_queue(dev); 1277 1278 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, 1279 eth_rx_irq, dev); 1280 if (!ports_open) { 1281 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, 1282 eth_txdone_irq, NULL); 1283 qmgr_enable_irq(TXDONE_QUEUE); 1284 } 1285 ports_open++; 1286 /* we may already have RX data, enables IRQ */ 1287 napi_schedule(&port->napi); 1288 return 0; 1289 } 1290 1291 static int eth_close(struct net_device *dev) 1292 { 1293 struct port *port = netdev_priv(dev); 1294 struct msg msg; 1295 int buffs = RX_DESCS; /* allocated RX buffers */ 1296 int i; 1297 1298 ports_open--; 1299 qmgr_disable_irq(port->plat->rxq); 1300 napi_disable(&port->napi); 1301 netif_stop_queue(dev); 1302 1303 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) 1304 buffs--; 1305 1306 memset(&msg, 0, sizeof(msg)); 1307 msg.cmd = NPE_SETLOOPBACK_MODE; 1308 msg.eth_id = port->id; 1309 msg.byte3 = 1; 1310 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) 1311 netdev_crit(dev, "unable to enable loopback\n"); 1312 1313 i = 0; 1314 do { /* drain RX buffers */ 1315 while (queue_get_desc(port->plat->rxq, port, 0) >= 0) 1316 buffs--; 1317 if (!buffs) 1318 break; 1319 if (qmgr_stat_empty(TX_QUEUE(port->id))) { 1320 /* we have to inject some packet */ 1321 struct desc *desc; 1322 u32 phys; 1323 int n = queue_get_desc(port->plat->txreadyq, port, 1); 1324 BUG_ON(n < 0); 1325 desc = tx_desc_ptr(port, n); 1326 phys = tx_desc_phys(port, n); 1327 desc->buf_len = desc->pkt_len = 1; 1328 wmb(); 1329 queue_put_desc(TX_QUEUE(port->id), phys, desc); 1330 } 1331 udelay(1); 1332 } while (++i < MAX_CLOSE_WAIT); 1333 1334 if (buffs) 1335 netdev_crit(dev, "unable to drain RX queue, %i buffer(s)" 1336 " left in NPE\n", buffs); 1337 #if DEBUG_CLOSE 1338 if (!buffs) 1339 netdev_debug(dev, "draining RX queue took %i cycles\n", i); 1340 #endif 1341 1342 buffs = TX_DESCS; 1343 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) 1344 buffs--; /* cancel TX */ 1345 1346 i = 0; 1347 do { 1348 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) 1349 buffs--; 1350 if (!buffs) 1351 break; 1352 } while (++i < MAX_CLOSE_WAIT); 1353 1354 if (buffs) 1355 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) " 1356 "left in NPE\n", buffs); 1357 #if DEBUG_CLOSE 1358 if (!buffs) 1359 netdev_debug(dev, "draining TX queues took %i cycles\n", i); 1360 #endif 1361 1362 msg.byte3 = 0; 1363 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) 1364 netdev_crit(dev, "unable to disable loopback\n"); 1365 1366 phy_stop(dev->phydev); 1367 1368 if (!ports_open) 1369 qmgr_disable_irq(TXDONE_QUEUE); 1370 destroy_queues(port); 1371 release_queues(port); 1372 return 0; 1373 } 1374 1375 static const struct net_device_ops ixp4xx_netdev_ops = { 1376 .ndo_open = eth_open, 1377 .ndo_stop = eth_close, 1378 .ndo_start_xmit = eth_xmit, 1379 .ndo_set_rx_mode = eth_set_mcast_list, 1380 .ndo_eth_ioctl = eth_ioctl, 1381 .ndo_set_mac_address = eth_mac_addr, 1382 .ndo_validate_addr = eth_validate_addr, 1383 }; 1384 1385 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) 1386 { 1387 struct device_node *np = dev->of_node; 1388 struct of_phandle_args queue_spec; 1389 struct of_phandle_args npe_spec; 1390 struct device_node *mdio_np; 1391 struct eth_plat_info *plat; 1392 u8 mac[ETH_ALEN]; 1393 int ret; 1394 1395 plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL); 1396 if (!plat) 1397 return NULL; 1398 1399 ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0, 1400 &npe_spec); 1401 if (ret) { 1402 dev_err(dev, "no NPE engine specified\n"); 1403 return NULL; 1404 } 1405 /* NPE ID 0x00, 0x10, 0x20... */ 1406 plat->npe = (npe_spec.args[0] << 4); 1407 1408 /* Check if this device has an MDIO bus */ 1409 mdio_np = of_get_child_by_name(np, "mdio"); 1410 if (mdio_np) { 1411 plat->has_mdio = true; 1412 mdio_bus_np = mdio_np; 1413 /* DO NOT put the mdio_np, it will be used */ 1414 } 1415 1416 /* Get the rx queue as a resource from queue manager */ 1417 ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0, 1418 &queue_spec); 1419 if (ret) { 1420 dev_err(dev, "no rx queue phandle\n"); 1421 return NULL; 1422 } 1423 plat->rxq = queue_spec.args[0]; 1424 1425 /* Get the txready queue as resource from queue manager */ 1426 ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0, 1427 &queue_spec); 1428 if (ret) { 1429 dev_err(dev, "no txready queue phandle\n"); 1430 return NULL; 1431 } 1432 plat->txreadyq = queue_spec.args[0]; 1433 1434 ret = of_get_mac_address(np, mac); 1435 if (!ret) { 1436 dev_info(dev, "Setting macaddr from DT %pM\n", mac); 1437 memcpy(plat->hwaddr, mac, ETH_ALEN); 1438 } 1439 1440 return plat; 1441 } 1442 1443 static int ixp4xx_eth_probe(struct platform_device *pdev) 1444 { 1445 struct phy_device *phydev = NULL; 1446 struct device *dev = &pdev->dev; 1447 struct device_node *np = dev->of_node; 1448 struct eth_plat_info *plat; 1449 struct net_device *ndev; 1450 struct port *port; 1451 int err; 1452 1453 plat = ixp4xx_of_get_platdata(dev); 1454 if (!plat) 1455 return -ENODEV; 1456 1457 if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port)))) 1458 return -ENOMEM; 1459 1460 SET_NETDEV_DEV(ndev, dev); 1461 port = netdev_priv(ndev); 1462 port->netdev = ndev; 1463 port->id = plat->npe; 1464 port->phc_index = -1; 1465 1466 /* Get the port resource and remap */ 1467 port->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1468 if (IS_ERR(port->regs)) 1469 return PTR_ERR(port->regs); 1470 1471 /* Register the MDIO bus if we have it */ 1472 if (plat->has_mdio) { 1473 err = ixp4xx_mdio_register(port->regs); 1474 if (err) { 1475 dev_err(dev, "failed to register MDIO bus\n"); 1476 return err; 1477 } 1478 } 1479 /* If the instance with the MDIO bus has not yet appeared, 1480 * defer probing until it gets probed. 1481 */ 1482 if (!mdio_bus) 1483 return -EPROBE_DEFER; 1484 1485 ndev->netdev_ops = &ixp4xx_netdev_ops; 1486 ndev->ethtool_ops = &ixp4xx_ethtool_ops; 1487 ndev->tx_queue_len = 100; 1488 /* Inherit the DMA masks from the platform device */ 1489 ndev->dev.dma_mask = dev->dma_mask; 1490 ndev->dev.coherent_dma_mask = dev->coherent_dma_mask; 1491 1492 /* Maximum frame size is 16320 bytes and includes VLAN and 1493 * ethernet headers. See "IXP400 Software Programmer's Guide" 1494 * section 10.3.2, page 161. 1495 */ 1496 ndev->min_mtu = ETH_MIN_MTU; 1497 ndev->max_mtu = 16320 - VLAN_ETH_HLEN; 1498 1499 netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT); 1500 1501 if (!(port->npe = npe_request(NPE_ID(port->id)))) 1502 return -EIO; 1503 1504 port->plat = plat; 1505 npe_port_tab[NPE_ID(port->id)] = port; 1506 if (is_valid_ether_addr(plat->hwaddr)) 1507 eth_hw_addr_set(ndev, plat->hwaddr); 1508 else 1509 eth_hw_addr_random(ndev); 1510 1511 platform_set_drvdata(pdev, ndev); 1512 1513 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, 1514 &port->regs->core_control); 1515 udelay(50); 1516 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); 1517 udelay(50); 1518 1519 phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link); 1520 if (!phydev) { 1521 err = -ENODEV; 1522 dev_err(dev, "no phydev\n"); 1523 goto err_free_mem; 1524 } 1525 1526 phydev->irq = PHY_POLL; 1527 1528 if ((err = register_netdev(ndev))) 1529 goto err_phy_dis; 1530 1531 netdev_info(ndev, "%s: MII PHY %i on %s\n", ndev->name, plat->phy, 1532 npe_name(port->npe)); 1533 1534 return 0; 1535 1536 err_phy_dis: 1537 phy_disconnect(phydev); 1538 err_free_mem: 1539 npe_port_tab[NPE_ID(port->id)] = NULL; 1540 npe_release(port->npe); 1541 return err; 1542 } 1543 1544 static void ixp4xx_eth_remove(struct platform_device *pdev) 1545 { 1546 struct net_device *ndev = platform_get_drvdata(pdev); 1547 struct phy_device *phydev = ndev->phydev; 1548 struct port *port = netdev_priv(ndev); 1549 1550 unregister_netdev(ndev); 1551 phy_disconnect(phydev); 1552 ixp4xx_mdio_remove(); 1553 npe_port_tab[NPE_ID(port->id)] = NULL; 1554 npe_release(port->npe); 1555 } 1556 1557 static const struct of_device_id ixp4xx_eth_of_match[] = { 1558 { 1559 .compatible = "intel,ixp4xx-ethernet", 1560 }, 1561 { }, 1562 }; 1563 1564 static struct platform_driver ixp4xx_eth_driver = { 1565 .driver = { 1566 .name = DRV_NAME, 1567 .of_match_table = of_match_ptr(ixp4xx_eth_of_match), 1568 }, 1569 .probe = ixp4xx_eth_probe, 1570 .remove_new = ixp4xx_eth_remove, 1571 }; 1572 module_platform_driver(ixp4xx_eth_driver); 1573 1574 MODULE_AUTHOR("Krzysztof Halasa"); 1575 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); 1576 MODULE_LICENSE("GPL v2"); 1577 MODULE_ALIAS("platform:ixp4xx_eth"); 1578