1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel IXP4xx Ethernet driver for Linux 4 * 5 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * Ethernet port config (0x00 is not present on IXP42X): 8 * 9 * logical port 0x00 0x10 0x20 10 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C) 11 * physical PortId 2 0 1 12 * TX queue 23 24 25 13 * RX-free queue 26 27 28 14 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable 15 * 16 * Queue entries: 17 * bits 0 -> 1 - NPE ID (RX and TX-done) 18 * bits 0 -> 2 - priority (TX, per 802.1D) 19 * bits 3 -> 4 - port ID (user-set?) 20 * bits 5 -> 31 - physical descriptor address 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/dmapool.h> 26 #include <linux/etherdevice.h> 27 #include <linux/if_vlan.h> 28 #include <linux/io.h> 29 #include <linux/kernel.h> 30 #include <linux/net_tstamp.h> 31 #include <linux/of.h> 32 #include <linux/of_mdio.h> 33 #include <linux/of_net.h> 34 #include <linux/phy.h> 35 #include <linux/platform_device.h> 36 #include <linux/ptp_classify.h> 37 #include <linux/slab.h> 38 #include <linux/module.h> 39 #include <linux/soc/ixp4xx/npe.h> 40 #include <linux/soc/ixp4xx/qmgr.h> 41 #include <linux/soc/ixp4xx/cpu.h> 42 #include <linux/types.h> 43 44 #define IXP4XX_ETH_NPEA 0x00 45 #define IXP4XX_ETH_NPEB 0x10 46 #define IXP4XX_ETH_NPEC 0x20 47 48 #include "ixp46x_ts.h" 49 50 #define DEBUG_DESC 0 51 #define DEBUG_RX 0 52 #define DEBUG_TX 0 53 #define DEBUG_PKT_BYTES 0 54 #define DEBUG_MDIO 0 55 #define DEBUG_CLOSE 0 56 57 #define DRV_NAME "ixp4xx_eth" 58 59 #define MAX_NPES 3 60 61 #define RX_DESCS 64 /* also length of all RX queues */ 62 #define TX_DESCS 16 /* also length of all TX queues */ 63 #define TXDONE_QUEUE_LEN 64 /* dwords */ 64 65 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS)) 66 #define REGS_SIZE 0x1000 67 68 /* MRU is said to be 14320 in a code dump, the SW manual says that 69 * MRU/MTU is 16320 and includes VLAN and ethernet headers. 70 * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161. 71 * 72 * FIXME: we have chosen the safe default (14320) but if you can test 73 * jumboframes, experiment with 16320 and see what happens! 74 */ 75 #define MAX_MRU (14320 - VLAN_ETH_HLEN) 76 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4) 77 78 #define NAPI_WEIGHT 16 79 #define MDIO_INTERVAL (3 * HZ) 80 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */ 81 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */ 82 83 #define NPE_ID(port_id) ((port_id) >> 4) 84 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3) 85 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23) 86 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26) 87 #define TXDONE_QUEUE 31 88 89 #define PTP_SLAVE_MODE 1 90 #define PTP_MASTER_MODE 2 91 #define PORT2CHANNEL(p) NPE_ID(p->id) 92 93 /* TX Control Registers */ 94 #define TX_CNTRL0_TX_EN 0x01 95 #define TX_CNTRL0_HALFDUPLEX 0x02 96 #define TX_CNTRL0_RETRY 0x04 97 #define TX_CNTRL0_PAD_EN 0x08 98 #define TX_CNTRL0_APPEND_FCS 0x10 99 #define TX_CNTRL0_2DEFER 0x20 100 #define TX_CNTRL0_RMII 0x40 /* reduced MII */ 101 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */ 102 103 /* RX Control Registers */ 104 #define RX_CNTRL0_RX_EN 0x01 105 #define RX_CNTRL0_PADSTRIP_EN 0x02 106 #define RX_CNTRL0_SEND_FCS 0x04 107 #define RX_CNTRL0_PAUSE_EN 0x08 108 #define RX_CNTRL0_LOOP_EN 0x10 109 #define RX_CNTRL0_ADDR_FLTR_EN 0x20 110 #define RX_CNTRL0_RX_RUNT_EN 0x40 111 #define RX_CNTRL0_BCAST_DIS 0x80 112 #define RX_CNTRL1_DEFER_EN 0x01 113 114 /* Core Control Register */ 115 #define CORE_RESET 0x01 116 #define CORE_RX_FIFO_FLUSH 0x02 117 #define CORE_TX_FIFO_FLUSH 0x04 118 #define CORE_SEND_JAM 0x08 119 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */ 120 121 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \ 122 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \ 123 TX_CNTRL0_2DEFER) 124 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN 125 #define DEFAULT_CORE_CNTRL CORE_MDC_EN 126 127 128 /* NPE message codes */ 129 #define NPE_GETSTATUS 0x00 130 #define NPE_EDB_SETPORTADDRESS 0x01 131 #define NPE_EDB_GETMACADDRESSDATABASE 0x02 132 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03 133 #define NPE_GETSTATS 0x04 134 #define NPE_RESETSTATS 0x05 135 #define NPE_SETMAXFRAMELENGTHS 0x06 136 #define NPE_VLAN_SETRXTAGMODE 0x07 137 #define NPE_VLAN_SETDEFAULTRXVID 0x08 138 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09 139 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A 140 #define NPE_VLAN_SETRXQOSENTRY 0x0B 141 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C 142 #define NPE_STP_SETBLOCKINGSTATE 0x0D 143 #define NPE_FW_SETFIREWALLMODE 0x0E 144 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F 145 #define NPE_PC_SETAPMACTABLE 0x11 146 #define NPE_SETLOOPBACK_MODE 0x12 147 #define NPE_PC_SETBSSIDTABLE 0x13 148 #define NPE_ADDRESS_FILTER_CONFIG 0x14 149 #define NPE_APPENDFCSCONFIG 0x15 150 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16 151 #define NPE_MAC_RECOVERY_START 0x17 152 153 154 #ifdef __ARMEB__ 155 typedef struct sk_buff buffer_t; 156 #define free_buffer dev_kfree_skb 157 #define free_buffer_irq dev_consume_skb_irq 158 #else 159 typedef void buffer_t; 160 #define free_buffer kfree 161 #define free_buffer_irq kfree 162 #endif 163 164 /* Information about built-in Ethernet MAC interfaces */ 165 struct eth_plat_info { 166 u8 rxq; /* configurable, currently 0 - 31 only */ 167 u8 txreadyq; 168 u8 hwaddr[ETH_ALEN]; 169 u8 npe; /* NPE instance used by this interface */ 170 bool has_mdio; /* If this instance has an MDIO bus */ 171 }; 172 173 struct eth_regs { 174 u32 tx_control[2], __res1[2]; /* 000 */ 175 u32 rx_control[2], __res2[2]; /* 010 */ 176 u32 random_seed, __res3[3]; /* 020 */ 177 u32 partial_empty_threshold, __res4; /* 030 */ 178 u32 partial_full_threshold, __res5; /* 038 */ 179 u32 tx_start_bytes, __res6[3]; /* 040 */ 180 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */ 181 u32 tx_2part_deferral[2], __res8[2]; /* 060 */ 182 u32 slot_time, __res9[3]; /* 070 */ 183 u32 mdio_command[4]; /* 080 */ 184 u32 mdio_status[4]; /* 090 */ 185 u32 mcast_mask[6], __res10[2]; /* 0A0 */ 186 u32 mcast_addr[6], __res11[2]; /* 0C0 */ 187 u32 int_clock_threshold, __res12[3]; /* 0E0 */ 188 u32 hw_addr[6], __res13[61]; /* 0F0 */ 189 u32 core_control; /* 1FC */ 190 }; 191 192 struct port { 193 struct eth_regs __iomem *regs; 194 struct ixp46x_ts_regs __iomem *timesync_regs; 195 int phc_index; 196 struct npe *npe; 197 struct net_device *netdev; 198 struct napi_struct napi; 199 struct eth_plat_info *plat; 200 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS]; 201 struct desc *desc_tab; /* coherent */ 202 dma_addr_t desc_tab_phys; 203 int id; /* logical port ID */ 204 int speed, duplex; 205 u8 firmware[4]; 206 int hwts_tx_en; 207 int hwts_rx_en; 208 }; 209 210 /* NPE message structure */ 211 struct msg { 212 #ifdef __ARMEB__ 213 u8 cmd, eth_id, byte2, byte3; 214 u8 byte4, byte5, byte6, byte7; 215 #else 216 u8 byte3, byte2, eth_id, cmd; 217 u8 byte7, byte6, byte5, byte4; 218 #endif 219 }; 220 221 /* Ethernet packet descriptor */ 222 struct desc { 223 u32 next; /* pointer to next buffer, unused */ 224 225 #ifdef __ARMEB__ 226 u16 buf_len; /* buffer length */ 227 u16 pkt_len; /* packet length */ 228 u32 data; /* pointer to data buffer in RAM */ 229 u8 dest_id; 230 u8 src_id; 231 u16 flags; 232 u8 qos; 233 u8 padlen; 234 u16 vlan_tci; 235 #else 236 u16 pkt_len; /* packet length */ 237 u16 buf_len; /* buffer length */ 238 u32 data; /* pointer to data buffer in RAM */ 239 u16 flags; 240 u8 src_id; 241 u8 dest_id; 242 u16 vlan_tci; 243 u8 padlen; 244 u8 qos; 245 #endif 246 247 #ifdef __ARMEB__ 248 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3; 249 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1; 250 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5; 251 #else 252 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0; 253 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4; 254 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2; 255 #endif 256 }; 257 258 259 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \ 260 (n) * sizeof(struct desc)) 261 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n]) 262 263 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \ 264 ((n) + RX_DESCS) * sizeof(struct desc)) 265 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS]) 266 267 #ifndef __ARMEB__ 268 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt) 269 { 270 int i; 271 for (i = 0; i < cnt; i++) 272 dest[i] = swab32(src[i]); 273 } 274 #endif 275 276 static DEFINE_SPINLOCK(mdio_lock); 277 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */ 278 static struct mii_bus *mdio_bus; 279 static struct device_node *mdio_bus_np; 280 static int ports_open; 281 static struct port *npe_port_tab[MAX_NPES]; 282 static struct dma_pool *dma_pool; 283 284 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 285 { 286 u8 *data = skb->data; 287 unsigned int offset; 288 u16 *hi, *id; 289 u32 lo; 290 291 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4) 292 return 0; 293 294 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 295 296 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 297 return 0; 298 299 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID); 300 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID); 301 302 memcpy(&lo, &hi[1], sizeof(lo)); 303 304 return (uid_hi == ntohs(*hi) && 305 uid_lo == ntohl(lo) && 306 seqid == ntohs(*id)); 307 } 308 309 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb) 310 { 311 struct skb_shared_hwtstamps *shhwtstamps; 312 struct ixp46x_ts_regs *regs; 313 u64 ns; 314 u32 ch, hi, lo, val; 315 u16 uid, seq; 316 317 if (!port->hwts_rx_en) 318 return; 319 320 ch = PORT2CHANNEL(port); 321 322 regs = port->timesync_regs; 323 324 val = __raw_readl(®s->channel[ch].ch_event); 325 326 if (!(val & RX_SNAPSHOT_LOCKED)) 327 return; 328 329 lo = __raw_readl(®s->channel[ch].src_uuid_lo); 330 hi = __raw_readl(®s->channel[ch].src_uuid_hi); 331 332 uid = hi & 0xffff; 333 seq = (hi >> 16) & 0xffff; 334 335 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq))) 336 goto out; 337 338 lo = __raw_readl(®s->channel[ch].rx_snap_lo); 339 hi = __raw_readl(®s->channel[ch].rx_snap_hi); 340 ns = ((u64) hi) << 32; 341 ns |= lo; 342 ns <<= TICKS_NS_SHIFT; 343 344 shhwtstamps = skb_hwtstamps(skb); 345 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 346 shhwtstamps->hwtstamp = ns_to_ktime(ns); 347 out: 348 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 349 } 350 351 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb) 352 { 353 struct skb_shared_hwtstamps shhwtstamps; 354 struct ixp46x_ts_regs *regs; 355 struct skb_shared_info *shtx; 356 u64 ns; 357 u32 ch, cnt, hi, lo, val; 358 359 shtx = skb_shinfo(skb); 360 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en)) 361 shtx->tx_flags |= SKBTX_IN_PROGRESS; 362 else 363 return; 364 365 ch = PORT2CHANNEL(port); 366 367 regs = port->timesync_regs; 368 369 /* 370 * This really stinks, but we have to poll for the Tx time stamp. 371 * Usually, the time stamp is ready after 4 to 6 microseconds. 372 */ 373 for (cnt = 0; cnt < 100; cnt++) { 374 val = __raw_readl(®s->channel[ch].ch_event); 375 if (val & TX_SNAPSHOT_LOCKED) 376 break; 377 udelay(1); 378 } 379 if (!(val & TX_SNAPSHOT_LOCKED)) { 380 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 381 return; 382 } 383 384 lo = __raw_readl(®s->channel[ch].tx_snap_lo); 385 hi = __raw_readl(®s->channel[ch].tx_snap_hi); 386 ns = ((u64) hi) << 32; 387 ns |= lo; 388 ns <<= TICKS_NS_SHIFT; 389 390 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 391 shhwtstamps.hwtstamp = ns_to_ktime(ns); 392 skb_tstamp_tx(skb, &shhwtstamps); 393 394 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event); 395 } 396 397 static int ixp4xx_hwtstamp_set(struct net_device *netdev, 398 struct kernel_hwtstamp_config *cfg, 399 struct netlink_ext_ack *extack) 400 { 401 struct ixp46x_ts_regs *regs; 402 struct port *port = netdev_priv(netdev); 403 int ret; 404 int ch; 405 406 if (!netif_running(netdev)) 407 return -EINVAL; 408 409 ret = ixp46x_ptp_find(&port->timesync_regs, &port->phc_index); 410 if (ret) 411 return -EOPNOTSUPP; 412 413 ch = PORT2CHANNEL(port); 414 regs = port->timesync_regs; 415 416 if (cfg->tx_type != HWTSTAMP_TX_OFF && cfg->tx_type != HWTSTAMP_TX_ON) 417 return -ERANGE; 418 419 switch (cfg->rx_filter) { 420 case HWTSTAMP_FILTER_NONE: 421 port->hwts_rx_en = 0; 422 break; 423 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 424 port->hwts_rx_en = PTP_SLAVE_MODE; 425 __raw_writel(0, ®s->channel[ch].ch_control); 426 break; 427 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 428 port->hwts_rx_en = PTP_MASTER_MODE; 429 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control); 430 break; 431 default: 432 return -ERANGE; 433 } 434 435 port->hwts_tx_en = cfg->tx_type == HWTSTAMP_TX_ON; 436 437 /* Clear out any old time stamps. */ 438 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED, 439 ®s->channel[ch].ch_event); 440 441 return 0; 442 } 443 444 static int ixp4xx_hwtstamp_get(struct net_device *netdev, 445 struct kernel_hwtstamp_config *cfg) 446 { 447 struct port *port = netdev_priv(netdev); 448 449 if (!cpu_is_ixp46x()) 450 return -EOPNOTSUPP; 451 452 if (!netif_running(netdev)) 453 return -EINVAL; 454 455 cfg->flags = 0; 456 cfg->tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 457 458 switch (port->hwts_rx_en) { 459 case 0: 460 cfg->rx_filter = HWTSTAMP_FILTER_NONE; 461 break; 462 case PTP_SLAVE_MODE: 463 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 464 break; 465 case PTP_MASTER_MODE: 466 cfg->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 467 break; 468 default: 469 WARN_ON_ONCE(1); 470 return -ERANGE; 471 } 472 473 return 0; 474 } 475 476 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location, 477 int write, u16 cmd) 478 { 479 int cycles = 0; 480 481 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) { 482 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name); 483 return -1; 484 } 485 486 if (write) { 487 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); 488 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); 489 } 490 __raw_writel(((phy_id << 5) | location) & 0xFF, 491 &mdio_regs->mdio_command[2]); 492 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, 493 &mdio_regs->mdio_command[3]); 494 495 while ((cycles < MAX_MDIO_RETRIES) && 496 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) { 497 udelay(1); 498 cycles++; 499 } 500 501 if (cycles == MAX_MDIO_RETRIES) { 502 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name, 503 phy_id); 504 return -1; 505 } 506 507 #if DEBUG_MDIO 508 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name, 509 phy_id, write ? "write" : "read", cycles); 510 #endif 511 512 if (write) 513 return 0; 514 515 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) { 516 #if DEBUG_MDIO 517 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name, 518 phy_id); 519 #endif 520 return 0xFFFF; /* don't return error */ 521 } 522 523 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) | 524 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8); 525 } 526 527 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location) 528 { 529 unsigned long flags; 530 int ret; 531 532 spin_lock_irqsave(&mdio_lock, flags); 533 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0); 534 spin_unlock_irqrestore(&mdio_lock, flags); 535 #if DEBUG_MDIO 536 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name, 537 phy_id, location, ret); 538 #endif 539 return ret; 540 } 541 542 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location, 543 u16 val) 544 { 545 unsigned long flags; 546 int ret; 547 548 spin_lock_irqsave(&mdio_lock, flags); 549 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val); 550 spin_unlock_irqrestore(&mdio_lock, flags); 551 #if DEBUG_MDIO 552 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n", 553 bus->name, phy_id, location, val, ret); 554 #endif 555 return ret; 556 } 557 558 static int ixp4xx_mdio_register(struct eth_regs __iomem *regs) 559 { 560 int err; 561 562 if (!(mdio_bus = mdiobus_alloc())) 563 return -ENOMEM; 564 565 mdio_regs = regs; 566 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); 567 mdio_bus->name = "IXP4xx MII Bus"; 568 mdio_bus->read = &ixp4xx_mdio_read; 569 mdio_bus->write = &ixp4xx_mdio_write; 570 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0"); 571 572 err = of_mdiobus_register(mdio_bus, mdio_bus_np); 573 if (err) 574 mdiobus_free(mdio_bus); 575 return err; 576 } 577 578 static void ixp4xx_mdio_remove(void) 579 { 580 mdiobus_unregister(mdio_bus); 581 mdiobus_free(mdio_bus); 582 } 583 584 585 static void ixp4xx_adjust_link(struct net_device *dev) 586 { 587 struct port *port = netdev_priv(dev); 588 struct phy_device *phydev = dev->phydev; 589 590 if (!phydev->link) { 591 if (port->speed) { 592 port->speed = 0; 593 printk(KERN_INFO "%s: link down\n", dev->name); 594 } 595 return; 596 } 597 598 if (port->speed == phydev->speed && port->duplex == phydev->duplex) 599 return; 600 601 port->speed = phydev->speed; 602 port->duplex = phydev->duplex; 603 604 if (port->duplex) 605 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX, 606 &port->regs->tx_control[0]); 607 else 608 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX, 609 &port->regs->tx_control[0]); 610 611 netdev_info(dev, "%s: link up, speed %u Mb/s, %s duplex\n", 612 dev->name, port->speed, port->duplex ? "full" : "half"); 613 } 614 615 616 static inline void debug_pkt(struct net_device *dev, const char *func, 617 u8 *data, int len) 618 { 619 #if DEBUG_PKT_BYTES 620 int i; 621 622 netdev_debug(dev, "%s(%i) ", func, len); 623 for (i = 0; i < len; i++) { 624 if (i >= DEBUG_PKT_BYTES) 625 break; 626 printk("%s%02X", 627 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "", 628 data[i]); 629 } 630 printk("\n"); 631 #endif 632 } 633 634 635 static inline void debug_desc(u32 phys, struct desc *desc) 636 { 637 #if DEBUG_DESC 638 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X" 639 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n", 640 phys, desc->next, desc->buf_len, desc->pkt_len, 641 desc->data, desc->dest_id, desc->src_id, desc->flags, 642 desc->qos, desc->padlen, desc->vlan_tci, 643 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2, 644 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5, 645 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2, 646 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5); 647 #endif 648 } 649 650 static inline int queue_get_desc(unsigned int queue, struct port *port, 651 int is_tx) 652 { 653 u32 phys, tab_phys, n_desc; 654 struct desc *tab; 655 656 if (!(phys = qmgr_get_entry(queue))) 657 return -1; 658 659 phys &= ~0x1F; /* mask out non-address bits */ 660 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0); 661 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0); 662 n_desc = (phys - tab_phys) / sizeof(struct desc); 663 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS)); 664 debug_desc(phys, &tab[n_desc]); 665 BUG_ON(tab[n_desc].next); 666 return n_desc; 667 } 668 669 static inline void queue_put_desc(unsigned int queue, u32 phys, 670 struct desc *desc) 671 { 672 debug_desc(phys, desc); 673 BUG_ON(phys & 0x1F); 674 qmgr_put_entry(queue, phys); 675 /* Don't check for queue overflow here, we've allocated sufficient 676 length and queues >= 32 don't support this check anyway. */ 677 } 678 679 680 static inline void dma_unmap_tx(struct port *port, struct desc *desc) 681 { 682 #ifdef __ARMEB__ 683 dma_unmap_single(&port->netdev->dev, desc->data, 684 desc->buf_len, DMA_TO_DEVICE); 685 #else 686 dma_unmap_single(&port->netdev->dev, desc->data & ~3, 687 ALIGN((desc->data & 3) + desc->buf_len, 4), 688 DMA_TO_DEVICE); 689 #endif 690 } 691 692 693 static void eth_rx_irq(void *pdev) 694 { 695 struct net_device *dev = pdev; 696 struct port *port = netdev_priv(dev); 697 698 #if DEBUG_RX 699 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name); 700 #endif 701 qmgr_disable_irq(port->plat->rxq); 702 napi_schedule(&port->napi); 703 } 704 705 static int eth_poll(struct napi_struct *napi, int budget) 706 { 707 struct port *port = container_of(napi, struct port, napi); 708 struct net_device *dev = port->netdev; 709 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id); 710 int received = 0; 711 712 #if DEBUG_RX 713 netdev_debug(dev, "eth_poll\n"); 714 #endif 715 716 while (received < budget) { 717 struct sk_buff *skb; 718 struct desc *desc; 719 int n; 720 #ifdef __ARMEB__ 721 struct sk_buff *temp; 722 u32 phys; 723 #endif 724 725 if ((n = queue_get_desc(rxq, port, 0)) < 0) { 726 #if DEBUG_RX 727 netdev_debug(dev, "eth_poll napi_complete\n"); 728 #endif 729 napi_complete(napi); 730 qmgr_enable_irq(rxq); 731 if (!qmgr_stat_below_low_watermark(rxq) && 732 napi_schedule(napi)) { /* not empty again */ 733 #if DEBUG_RX 734 netdev_debug(dev, "eth_poll napi_schedule succeeded\n"); 735 #endif 736 qmgr_disable_irq(rxq); 737 continue; 738 } 739 #if DEBUG_RX 740 netdev_debug(dev, "eth_poll all done\n"); 741 #endif 742 return received; /* all work done */ 743 } 744 745 desc = rx_desc_ptr(port, n); 746 747 #ifdef __ARMEB__ 748 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) { 749 phys = dma_map_single(&dev->dev, skb->data, 750 RX_BUFF_SIZE, DMA_FROM_DEVICE); 751 if (dma_mapping_error(&dev->dev, phys)) { 752 dev_kfree_skb(skb); 753 skb = NULL; 754 } 755 } 756 #else 757 skb = netdev_alloc_skb(dev, 758 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4)); 759 #endif 760 761 if (!skb) { 762 dev->stats.rx_dropped++; 763 /* put the desc back on RX-ready queue */ 764 desc->buf_len = MAX_MRU; 765 desc->pkt_len = 0; 766 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 767 continue; 768 } 769 770 /* process received frame */ 771 #ifdef __ARMEB__ 772 temp = skb; 773 skb = port->rx_buff_tab[n]; 774 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN, 775 RX_BUFF_SIZE, DMA_FROM_DEVICE); 776 #else 777 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN, 778 RX_BUFF_SIZE, DMA_FROM_DEVICE); 779 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n], 780 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4); 781 #endif 782 skb_reserve(skb, NET_IP_ALIGN); 783 skb_put(skb, desc->pkt_len); 784 785 debug_pkt(dev, "eth_poll", skb->data, skb->len); 786 787 ixp_rx_timestamp(port, skb); 788 skb->protocol = eth_type_trans(skb, dev); 789 dev->stats.rx_packets++; 790 dev->stats.rx_bytes += skb->len; 791 netif_receive_skb(skb); 792 793 /* put the new buffer on RX-free queue */ 794 #ifdef __ARMEB__ 795 port->rx_buff_tab[n] = temp; 796 desc->data = phys + NET_IP_ALIGN; 797 #endif 798 desc->buf_len = MAX_MRU; 799 desc->pkt_len = 0; 800 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc); 801 received++; 802 } 803 804 #if DEBUG_RX 805 netdev_debug(dev, "eth_poll(): end, not all work done\n"); 806 #endif 807 return received; /* not all work done */ 808 } 809 810 811 static void eth_txdone_irq(void *unused) 812 { 813 u32 phys; 814 815 #if DEBUG_TX 816 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n"); 817 #endif 818 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) { 819 u32 npe_id, n_desc; 820 struct port *port; 821 struct desc *desc; 822 int start; 823 824 npe_id = phys & 3; 825 BUG_ON(npe_id >= MAX_NPES); 826 port = npe_port_tab[npe_id]; 827 BUG_ON(!port); 828 phys &= ~0x1F; /* mask out non-address bits */ 829 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc); 830 BUG_ON(n_desc >= TX_DESCS); 831 desc = tx_desc_ptr(port, n_desc); 832 debug_desc(phys, desc); 833 834 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */ 835 port->netdev->stats.tx_packets++; 836 port->netdev->stats.tx_bytes += desc->pkt_len; 837 838 dma_unmap_tx(port, desc); 839 #if DEBUG_TX 840 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n", 841 port->netdev->name, port->tx_buff_tab[n_desc]); 842 #endif 843 free_buffer_irq(port->tx_buff_tab[n_desc]); 844 port->tx_buff_tab[n_desc] = NULL; 845 } 846 847 start = qmgr_stat_below_low_watermark(port->plat->txreadyq); 848 queue_put_desc(port->plat->txreadyq, phys, desc); 849 if (start) { /* TX-ready queue was empty */ 850 #if DEBUG_TX 851 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n", 852 port->netdev->name); 853 #endif 854 netif_wake_queue(port->netdev); 855 } 856 } 857 } 858 859 static netdev_tx_t eth_xmit(struct sk_buff *skb, struct net_device *dev) 860 { 861 struct port *port = netdev_priv(dev); 862 unsigned int txreadyq = port->plat->txreadyq; 863 int len, offset, bytes, n; 864 void *mem; 865 u32 phys; 866 struct desc *desc; 867 868 #if DEBUG_TX 869 netdev_debug(dev, "eth_xmit\n"); 870 #endif 871 872 if (unlikely(skb->len > MAX_MRU)) { 873 dev_kfree_skb(skb); 874 dev->stats.tx_errors++; 875 return NETDEV_TX_OK; 876 } 877 878 debug_pkt(dev, "eth_xmit", skb->data, skb->len); 879 880 len = skb->len; 881 #ifdef __ARMEB__ 882 offset = 0; /* no need to keep alignment */ 883 bytes = len; 884 mem = skb->data; 885 #else 886 offset = (uintptr_t)skb->data & 3; /* keep 32-bit alignment */ 887 bytes = ALIGN(offset + len, 4); 888 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) { 889 dev_kfree_skb(skb); 890 dev->stats.tx_dropped++; 891 return NETDEV_TX_OK; 892 } 893 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4); 894 #endif 895 896 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE); 897 if (dma_mapping_error(&dev->dev, phys)) { 898 dev_kfree_skb(skb); 899 #ifndef __ARMEB__ 900 kfree(mem); 901 #endif 902 dev->stats.tx_dropped++; 903 return NETDEV_TX_OK; 904 } 905 906 n = queue_get_desc(txreadyq, port, 1); 907 BUG_ON(n < 0); 908 desc = tx_desc_ptr(port, n); 909 910 #ifdef __ARMEB__ 911 port->tx_buff_tab[n] = skb; 912 #else 913 port->tx_buff_tab[n] = mem; 914 #endif 915 desc->data = phys + offset; 916 desc->buf_len = desc->pkt_len = len; 917 918 /* NPE firmware pads short frames with zeros internally */ 919 wmb(); 920 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc); 921 922 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */ 923 #if DEBUG_TX 924 netdev_debug(dev, "eth_xmit queue full\n"); 925 #endif 926 netif_stop_queue(dev); 927 /* we could miss TX ready interrupt */ 928 /* really empty in fact */ 929 if (!qmgr_stat_below_low_watermark(txreadyq)) { 930 #if DEBUG_TX 931 netdev_debug(dev, "eth_xmit ready again\n"); 932 #endif 933 netif_wake_queue(dev); 934 } 935 } 936 937 #if DEBUG_TX 938 netdev_debug(dev, "eth_xmit end\n"); 939 #endif 940 941 ixp_tx_timestamp(port, skb); 942 skb_tx_timestamp(skb); 943 944 #ifndef __ARMEB__ 945 dev_kfree_skb(skb); 946 #endif 947 return NETDEV_TX_OK; 948 } 949 950 951 static void eth_set_mcast_list(struct net_device *dev) 952 { 953 struct port *port = netdev_priv(dev); 954 struct netdev_hw_addr *ha; 955 u8 diffs[ETH_ALEN], *addr; 956 int i; 957 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 958 959 if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) { 960 for (i = 0; i < ETH_ALEN; i++) { 961 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]); 962 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]); 963 } 964 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 965 &port->regs->rx_control[0]); 966 return; 967 } 968 969 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) { 970 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN, 971 &port->regs->rx_control[0]); 972 return; 973 } 974 975 eth_zero_addr(diffs); 976 977 addr = NULL; 978 netdev_for_each_mc_addr(ha, dev) { 979 if (!addr) 980 addr = ha->addr; /* first MAC address */ 981 for (i = 0; i < ETH_ALEN; i++) 982 diffs[i] |= addr[i] ^ ha->addr[i]; 983 } 984 985 for (i = 0; i < ETH_ALEN; i++) { 986 __raw_writel(addr[i], &port->regs->mcast_addr[i]); 987 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]); 988 } 989 990 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN, 991 &port->regs->rx_control[0]); 992 } 993 994 995 /* ethtool support */ 996 997 static void ixp4xx_get_drvinfo(struct net_device *dev, 998 struct ethtool_drvinfo *info) 999 { 1000 struct port *port = netdev_priv(dev); 1001 1002 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 1003 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u", 1004 port->firmware[0], port->firmware[1], 1005 port->firmware[2], port->firmware[3]); 1006 strscpy(info->bus_info, "internal", sizeof(info->bus_info)); 1007 } 1008 1009 static int ixp4xx_get_ts_info(struct net_device *dev, 1010 struct kernel_ethtool_ts_info *info) 1011 { 1012 struct port *port = netdev_priv(dev); 1013 1014 if (port->phc_index < 0) 1015 ixp46x_ptp_find(&port->timesync_regs, &port->phc_index); 1016 1017 info->phc_index = port->phc_index; 1018 1019 if (info->phc_index < 0) { 1020 info->so_timestamping = 1021 SOF_TIMESTAMPING_TX_SOFTWARE; 1022 return 0; 1023 } 1024 info->so_timestamping = 1025 SOF_TIMESTAMPING_TX_HARDWARE | 1026 SOF_TIMESTAMPING_RX_HARDWARE | 1027 SOF_TIMESTAMPING_RAW_HARDWARE; 1028 info->tx_types = 1029 (1 << HWTSTAMP_TX_OFF) | 1030 (1 << HWTSTAMP_TX_ON); 1031 info->rx_filters = 1032 (1 << HWTSTAMP_FILTER_NONE) | 1033 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 1034 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ); 1035 return 0; 1036 } 1037 1038 static const struct ethtool_ops ixp4xx_ethtool_ops = { 1039 .get_drvinfo = ixp4xx_get_drvinfo, 1040 .nway_reset = phy_ethtool_nway_reset, 1041 .get_link = ethtool_op_get_link, 1042 .get_ts_info = ixp4xx_get_ts_info, 1043 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1044 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1045 }; 1046 1047 1048 static int request_queues(struct port *port) 1049 { 1050 int err; 1051 1052 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0, 1053 "%s:RX-free", port->netdev->name); 1054 if (err) 1055 return err; 1056 1057 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0, 1058 "%s:RX", port->netdev->name); 1059 if (err) 1060 goto rel_rxfree; 1061 1062 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0, 1063 "%s:TX", port->netdev->name); 1064 if (err) 1065 goto rel_rx; 1066 1067 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0, 1068 "%s:TX-ready", port->netdev->name); 1069 if (err) 1070 goto rel_tx; 1071 1072 /* TX-done queue handles skbs sent out by the NPEs */ 1073 if (!ports_open) { 1074 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0, 1075 "%s:TX-done", DRV_NAME); 1076 if (err) 1077 goto rel_txready; 1078 } 1079 return 0; 1080 1081 rel_txready: 1082 qmgr_release_queue(port->plat->txreadyq); 1083 rel_tx: 1084 qmgr_release_queue(TX_QUEUE(port->id)); 1085 rel_rx: 1086 qmgr_release_queue(port->plat->rxq); 1087 rel_rxfree: 1088 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1089 printk(KERN_DEBUG "%s: unable to request hardware queues\n", 1090 port->netdev->name); 1091 return err; 1092 } 1093 1094 static void release_queues(struct port *port) 1095 { 1096 qmgr_release_queue(RXFREE_QUEUE(port->id)); 1097 qmgr_release_queue(port->plat->rxq); 1098 qmgr_release_queue(TX_QUEUE(port->id)); 1099 qmgr_release_queue(port->plat->txreadyq); 1100 1101 if (!ports_open) 1102 qmgr_release_queue(TXDONE_QUEUE); 1103 } 1104 1105 static int init_queues(struct port *port) 1106 { 1107 int i; 1108 1109 if (!ports_open) { 1110 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev, 1111 POOL_ALLOC_SIZE, 32, 0); 1112 if (!dma_pool) 1113 return -ENOMEM; 1114 } 1115 1116 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL, &port->desc_tab_phys); 1117 if (!port->desc_tab) 1118 return -ENOMEM; 1119 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */ 1120 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab)); 1121 1122 /* Setup RX buffers */ 1123 for (i = 0; i < RX_DESCS; i++) { 1124 struct desc *desc = rx_desc_ptr(port, i); 1125 buffer_t *buff; /* skb or kmalloc()ated memory */ 1126 void *data; 1127 #ifdef __ARMEB__ 1128 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE))) 1129 return -ENOMEM; 1130 data = buff->data; 1131 #else 1132 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL))) 1133 return -ENOMEM; 1134 data = buff; 1135 #endif 1136 desc->buf_len = MAX_MRU; 1137 desc->data = dma_map_single(&port->netdev->dev, data, 1138 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1139 if (dma_mapping_error(&port->netdev->dev, desc->data)) { 1140 free_buffer(buff); 1141 return -EIO; 1142 } 1143 desc->data += NET_IP_ALIGN; 1144 port->rx_buff_tab[i] = buff; 1145 } 1146 1147 return 0; 1148 } 1149 1150 static void destroy_queues(struct port *port) 1151 { 1152 int i; 1153 1154 if (port->desc_tab) { 1155 for (i = 0; i < RX_DESCS; i++) { 1156 struct desc *desc = rx_desc_ptr(port, i); 1157 buffer_t *buff = port->rx_buff_tab[i]; 1158 if (buff) { 1159 dma_unmap_single(&port->netdev->dev, 1160 desc->data - NET_IP_ALIGN, 1161 RX_BUFF_SIZE, DMA_FROM_DEVICE); 1162 free_buffer(buff); 1163 } 1164 } 1165 for (i = 0; i < TX_DESCS; i++) { 1166 struct desc *desc = tx_desc_ptr(port, i); 1167 buffer_t *buff = port->tx_buff_tab[i]; 1168 if (buff) { 1169 dma_unmap_tx(port, desc); 1170 free_buffer(buff); 1171 } 1172 } 1173 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys); 1174 port->desc_tab = NULL; 1175 } 1176 1177 if (!ports_open && dma_pool) { 1178 dma_pool_destroy(dma_pool); 1179 dma_pool = NULL; 1180 } 1181 } 1182 1183 static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu) 1184 { 1185 struct port *port = netdev_priv(dev); 1186 struct npe *npe = port->npe; 1187 int framesize, chunks; 1188 struct msg msg = {}; 1189 1190 /* adjust for ethernet headers */ 1191 framesize = new_mtu + VLAN_ETH_HLEN; 1192 /* max rx/tx 64 byte chunks */ 1193 chunks = DIV_ROUND_UP(framesize, 64); 1194 1195 msg.cmd = NPE_SETMAXFRAMELENGTHS; 1196 msg.eth_id = port->id; 1197 1198 /* Firmware wants to know buffer size in 64 byte chunks */ 1199 msg.byte2 = chunks << 8; 1200 msg.byte3 = chunks << 8; 1201 1202 msg.byte4 = msg.byte6 = framesize >> 8; 1203 msg.byte5 = msg.byte7 = framesize & 0xff; 1204 1205 if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH")) 1206 return -EIO; 1207 netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n", 1208 npe_name(npe), new_mtu); 1209 1210 return 0; 1211 } 1212 1213 static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu) 1214 { 1215 int ret; 1216 1217 /* MTU can only be changed when the interface is up. We also 1218 * set the MTU from dev->mtu when opening the device. 1219 */ 1220 if (dev->flags & IFF_UP) { 1221 ret = ixp4xx_do_change_mtu(dev, new_mtu); 1222 if (ret < 0) 1223 return ret; 1224 } 1225 1226 WRITE_ONCE(dev->mtu, new_mtu); 1227 1228 return 0; 1229 } 1230 1231 static int eth_open(struct net_device *dev) 1232 { 1233 struct port *port = netdev_priv(dev); 1234 struct npe *npe = port->npe; 1235 struct msg msg; 1236 int i, err; 1237 1238 if (!npe_running(npe)) { 1239 err = npe_load_firmware(npe, npe_name(npe), &dev->dev); 1240 if (err) 1241 return err; 1242 1243 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) { 1244 netdev_err(dev, "%s not responding\n", npe_name(npe)); 1245 return -EIO; 1246 } 1247 port->firmware[0] = msg.byte4; 1248 port->firmware[1] = msg.byte5; 1249 port->firmware[2] = msg.byte6; 1250 port->firmware[3] = msg.byte7; 1251 } 1252 1253 memset(&msg, 0, sizeof(msg)); 1254 msg.cmd = NPE_VLAN_SETRXQOSENTRY; 1255 msg.eth_id = port->id; 1256 msg.byte5 = port->plat->rxq | 0x80; 1257 msg.byte7 = port->plat->rxq << 4; 1258 for (i = 0; i < 8; i++) { 1259 msg.byte3 = i; 1260 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ")) 1261 return -EIO; 1262 } 1263 1264 msg.cmd = NPE_EDB_SETPORTADDRESS; 1265 msg.eth_id = PHYSICAL_ID(port->id); 1266 msg.byte2 = dev->dev_addr[0]; 1267 msg.byte3 = dev->dev_addr[1]; 1268 msg.byte4 = dev->dev_addr[2]; 1269 msg.byte5 = dev->dev_addr[3]; 1270 msg.byte6 = dev->dev_addr[4]; 1271 msg.byte7 = dev->dev_addr[5]; 1272 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC")) 1273 return -EIO; 1274 1275 memset(&msg, 0, sizeof(msg)); 1276 msg.cmd = NPE_FW_SETFIREWALLMODE; 1277 msg.eth_id = port->id; 1278 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE")) 1279 return -EIO; 1280 1281 ixp4xx_do_change_mtu(dev, dev->mtu); 1282 1283 if ((err = request_queues(port)) != 0) 1284 return err; 1285 1286 if ((err = init_queues(port)) != 0) { 1287 destroy_queues(port); 1288 release_queues(port); 1289 return err; 1290 } 1291 1292 port->speed = 0; /* force "link up" message */ 1293 phy_start(dev->phydev); 1294 1295 for (i = 0; i < ETH_ALEN; i++) 1296 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]); 1297 __raw_writel(0x08, &port->regs->random_seed); 1298 __raw_writel(0x12, &port->regs->partial_empty_threshold); 1299 __raw_writel(0x30, &port->regs->partial_full_threshold); 1300 __raw_writel(0x08, &port->regs->tx_start_bytes); 1301 __raw_writel(0x15, &port->regs->tx_deferral); 1302 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]); 1303 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]); 1304 __raw_writel(0x80, &port->regs->slot_time); 1305 __raw_writel(0x01, &port->regs->int_clock_threshold); 1306 1307 /* Populate queues with buffers, no failure after this point */ 1308 for (i = 0; i < TX_DESCS; i++) 1309 queue_put_desc(port->plat->txreadyq, 1310 tx_desc_phys(port, i), tx_desc_ptr(port, i)); 1311 1312 for (i = 0; i < RX_DESCS; i++) 1313 queue_put_desc(RXFREE_QUEUE(port->id), 1314 rx_desc_phys(port, i), rx_desc_ptr(port, i)); 1315 1316 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]); 1317 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]); 1318 __raw_writel(0, &port->regs->rx_control[1]); 1319 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]); 1320 1321 napi_enable(&port->napi); 1322 eth_set_mcast_list(dev); 1323 netif_start_queue(dev); 1324 1325 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY, 1326 eth_rx_irq, dev); 1327 if (!ports_open) { 1328 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY, 1329 eth_txdone_irq, NULL); 1330 qmgr_enable_irq(TXDONE_QUEUE); 1331 } 1332 ports_open++; 1333 /* we may already have RX data, enables IRQ */ 1334 napi_schedule(&port->napi); 1335 return 0; 1336 } 1337 1338 static int eth_close(struct net_device *dev) 1339 { 1340 struct port *port = netdev_priv(dev); 1341 struct msg msg; 1342 int buffs = RX_DESCS; /* allocated RX buffers */ 1343 int i; 1344 1345 ports_open--; 1346 qmgr_disable_irq(port->plat->rxq); 1347 napi_disable(&port->napi); 1348 netif_stop_queue(dev); 1349 1350 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0) 1351 buffs--; 1352 1353 memset(&msg, 0, sizeof(msg)); 1354 msg.cmd = NPE_SETLOOPBACK_MODE; 1355 msg.eth_id = port->id; 1356 msg.byte3 = 1; 1357 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK")) 1358 netdev_crit(dev, "unable to enable loopback\n"); 1359 1360 i = 0; 1361 do { /* drain RX buffers */ 1362 while (queue_get_desc(port->plat->rxq, port, 0) >= 0) 1363 buffs--; 1364 if (!buffs) 1365 break; 1366 if (qmgr_stat_empty(TX_QUEUE(port->id))) { 1367 /* we have to inject some packet */ 1368 struct desc *desc; 1369 u32 phys; 1370 int n = queue_get_desc(port->plat->txreadyq, port, 1); 1371 BUG_ON(n < 0); 1372 desc = tx_desc_ptr(port, n); 1373 phys = tx_desc_phys(port, n); 1374 desc->buf_len = desc->pkt_len = 1; 1375 wmb(); 1376 queue_put_desc(TX_QUEUE(port->id), phys, desc); 1377 } 1378 udelay(1); 1379 } while (++i < MAX_CLOSE_WAIT); 1380 1381 if (buffs) 1382 netdev_crit(dev, "unable to drain RX queue, %i buffer(s)" 1383 " left in NPE\n", buffs); 1384 #if DEBUG_CLOSE 1385 if (!buffs) 1386 netdev_debug(dev, "draining RX queue took %i cycles\n", i); 1387 #endif 1388 1389 buffs = TX_DESCS; 1390 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0) 1391 buffs--; /* cancel TX */ 1392 1393 i = 0; 1394 do { 1395 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0) 1396 buffs--; 1397 if (!buffs) 1398 break; 1399 } while (++i < MAX_CLOSE_WAIT); 1400 1401 if (buffs) 1402 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) " 1403 "left in NPE\n", buffs); 1404 #if DEBUG_CLOSE 1405 if (!buffs) 1406 netdev_debug(dev, "draining TX queues took %i cycles\n", i); 1407 #endif 1408 1409 msg.byte3 = 0; 1410 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK")) 1411 netdev_crit(dev, "unable to disable loopback\n"); 1412 1413 phy_stop(dev->phydev); 1414 1415 if (!ports_open) 1416 qmgr_disable_irq(TXDONE_QUEUE); 1417 destroy_queues(port); 1418 release_queues(port); 1419 return 0; 1420 } 1421 1422 static const struct net_device_ops ixp4xx_netdev_ops = { 1423 .ndo_open = eth_open, 1424 .ndo_stop = eth_close, 1425 .ndo_change_mtu = ixp4xx_eth_change_mtu, 1426 .ndo_start_xmit = eth_xmit, 1427 .ndo_set_rx_mode = eth_set_mcast_list, 1428 .ndo_eth_ioctl = phy_do_ioctl_running, 1429 .ndo_set_mac_address = eth_mac_addr, 1430 .ndo_validate_addr = eth_validate_addr, 1431 .ndo_hwtstamp_get = ixp4xx_hwtstamp_get, 1432 .ndo_hwtstamp_set = ixp4xx_hwtstamp_set, 1433 }; 1434 1435 static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) 1436 { 1437 struct device_node *np = dev->of_node; 1438 struct of_phandle_args queue_spec; 1439 struct of_phandle_args npe_spec; 1440 struct device_node *mdio_np; 1441 struct eth_plat_info *plat; 1442 u8 mac[ETH_ALEN]; 1443 int ret; 1444 1445 plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL); 1446 if (!plat) 1447 return NULL; 1448 1449 ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0, 1450 &npe_spec); 1451 if (ret) { 1452 dev_err(dev, "no NPE engine specified\n"); 1453 return NULL; 1454 } 1455 /* NPE ID 0x00, 0x10, 0x20... */ 1456 plat->npe = (npe_spec.args[0] << 4); 1457 1458 /* Check if this device has an MDIO bus */ 1459 mdio_np = of_get_child_by_name(np, "mdio"); 1460 if (mdio_np) { 1461 plat->has_mdio = true; 1462 mdio_bus_np = mdio_np; 1463 /* DO NOT put the mdio_np, it will be used */ 1464 } 1465 1466 /* Get the rx queue as a resource from queue manager */ 1467 ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0, 1468 &queue_spec); 1469 if (ret) { 1470 dev_err(dev, "no rx queue phandle\n"); 1471 return NULL; 1472 } 1473 plat->rxq = queue_spec.args[0]; 1474 1475 /* Get the txready queue as resource from queue manager */ 1476 ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0, 1477 &queue_spec); 1478 if (ret) { 1479 dev_err(dev, "no txready queue phandle\n"); 1480 return NULL; 1481 } 1482 plat->txreadyq = queue_spec.args[0]; 1483 1484 ret = of_get_mac_address(np, mac); 1485 if (!ret) { 1486 dev_info(dev, "Setting macaddr from DT %pM\n", mac); 1487 memcpy(plat->hwaddr, mac, ETH_ALEN); 1488 } 1489 1490 return plat; 1491 } 1492 1493 static int ixp4xx_eth_probe(struct platform_device *pdev) 1494 { 1495 struct phy_device *phydev = NULL; 1496 struct device *dev = &pdev->dev; 1497 struct device_node *np = dev->of_node; 1498 struct eth_plat_info *plat; 1499 struct net_device *ndev; 1500 struct port *port; 1501 int err; 1502 1503 plat = ixp4xx_of_get_platdata(dev); 1504 if (!plat) 1505 return -ENODEV; 1506 1507 if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port)))) 1508 return -ENOMEM; 1509 1510 SET_NETDEV_DEV(ndev, dev); 1511 port = netdev_priv(ndev); 1512 port->netdev = ndev; 1513 port->id = plat->npe; 1514 port->phc_index = -1; 1515 1516 /* Get the port resource and remap */ 1517 port->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1518 if (IS_ERR(port->regs)) 1519 return PTR_ERR(port->regs); 1520 1521 /* Register the MDIO bus if we have it */ 1522 if (plat->has_mdio) { 1523 err = ixp4xx_mdio_register(port->regs); 1524 if (err) { 1525 dev_err(dev, "failed to register MDIO bus\n"); 1526 return err; 1527 } 1528 } 1529 /* If the instance with the MDIO bus has not yet appeared, 1530 * defer probing until it gets probed. 1531 */ 1532 if (!mdio_bus) 1533 return -EPROBE_DEFER; 1534 1535 ndev->netdev_ops = &ixp4xx_netdev_ops; 1536 ndev->ethtool_ops = &ixp4xx_ethtool_ops; 1537 ndev->tx_queue_len = 100; 1538 /* Inherit the DMA masks from the platform device */ 1539 ndev->dev.dma_mask = dev->dma_mask; 1540 ndev->dev.coherent_dma_mask = dev->coherent_dma_mask; 1541 1542 ndev->min_mtu = ETH_MIN_MTU; 1543 ndev->max_mtu = MAX_MRU; 1544 1545 netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT); 1546 1547 if (!(port->npe = npe_request(NPE_ID(port->id)))) 1548 return -EIO; 1549 1550 port->plat = plat; 1551 npe_port_tab[NPE_ID(port->id)] = port; 1552 if (is_valid_ether_addr(plat->hwaddr)) 1553 eth_hw_addr_set(ndev, plat->hwaddr); 1554 else 1555 eth_hw_addr_random(ndev); 1556 1557 platform_set_drvdata(pdev, ndev); 1558 1559 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET, 1560 &port->regs->core_control); 1561 udelay(50); 1562 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); 1563 udelay(50); 1564 1565 phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link); 1566 if (!phydev) { 1567 err = -ENODEV; 1568 dev_err(dev, "no phydev\n"); 1569 goto err_free_mem; 1570 } 1571 1572 phydev->irq = PHY_POLL; 1573 1574 if ((err = register_netdev(ndev))) 1575 goto err_phy_dis; 1576 1577 netdev_info(ndev, "%s: MII PHY %s on %s\n", ndev->name, phydev_name(phydev), 1578 npe_name(port->npe)); 1579 1580 return 0; 1581 1582 err_phy_dis: 1583 phy_disconnect(phydev); 1584 err_free_mem: 1585 npe_port_tab[NPE_ID(port->id)] = NULL; 1586 npe_release(port->npe); 1587 return err; 1588 } 1589 1590 static void ixp4xx_eth_remove(struct platform_device *pdev) 1591 { 1592 struct net_device *ndev = platform_get_drvdata(pdev); 1593 struct phy_device *phydev = ndev->phydev; 1594 struct port *port = netdev_priv(ndev); 1595 1596 unregister_netdev(ndev); 1597 phy_disconnect(phydev); 1598 ixp4xx_mdio_remove(); 1599 npe_port_tab[NPE_ID(port->id)] = NULL; 1600 npe_release(port->npe); 1601 } 1602 1603 static const struct of_device_id ixp4xx_eth_of_match[] = { 1604 { 1605 .compatible = "intel,ixp4xx-ethernet", 1606 }, 1607 { }, 1608 }; 1609 1610 static struct platform_driver ixp4xx_eth_driver = { 1611 .driver = { 1612 .name = DRV_NAME, 1613 .of_match_table = of_match_ptr(ixp4xx_eth_of_match), 1614 }, 1615 .probe = ixp4xx_eth_probe, 1616 .remove = ixp4xx_eth_remove, 1617 }; 1618 module_platform_driver(ixp4xx_eth_driver); 1619 1620 MODULE_AUTHOR("Krzysztof Halasa"); 1621 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver"); 1622 MODULE_LICENSE("GPL v2"); 1623 MODULE_ALIAS("platform:ixp4xx_eth"); 1624