1 /* 2 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. 3 * 4 * This is a new flat driver which is based on the original emac_lite 5 * driver from John Williams <john.williams@xilinx.com>. 6 * 7 * 2007 - 2013 (c) Xilinx, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/uaccess.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/skbuff.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_platform.h> 25 #include <linux/of_mdio.h> 26 #include <linux/of_net.h> 27 #include <linux/phy.h> 28 #include <linux/interrupt.h> 29 30 #define DRIVER_NAME "xilinx_emaclite" 31 32 /* Register offsets for the EmacLite Core */ 33 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ 34 #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ 35 #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ 36 #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ 37 #define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ 38 #define XEL_GIER_OFFSET 0x07F8 /* GIE Register */ 39 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 40 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 41 42 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 43 #define XEL_RPLR_OFFSET 0x100C /* Rx packet length */ 44 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 45 46 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */ 47 48 /* MDIO Address Register Bit Masks */ 49 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 50 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 51 #define XEL_MDIOADDR_PHYADR_SHIFT 5 52 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 53 54 /* MDIO Write Data Register Bit Masks */ 55 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 56 57 /* MDIO Read Data Register Bit Masks */ 58 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 59 60 /* MDIO Control Register Bit Masks */ 61 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 62 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 63 64 /* Global Interrupt Enable Register (GIER) Bit Masks */ 65 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ 66 67 /* Transmit Status Register (TSR) Bit Masks */ 68 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ 69 #define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ 70 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ 71 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit 72 * only. This is not documented 73 * in the HW spec 74 */ 75 76 /* Define for programming the MAC address into the EmacLite */ 77 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 78 79 /* Receive Status Register (RSR) */ 80 #define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ 81 #define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ 82 83 /* Transmit Packet Length Register (TPLR) */ 84 #define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ 85 86 /* Receive Packet Length Register (RPLR) */ 87 #define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ 88 89 #define XEL_HEADER_OFFSET 12 /* Offset to length field */ 90 #define XEL_HEADER_SHIFT 16 /* Shift value for length */ 91 92 /* General Ethernet Definitions */ 93 #define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ 94 #define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ 95 96 97 98 #define TX_TIMEOUT (60 * HZ) /* Tx timeout is 60 seconds. */ 99 #define ALIGNMENT 4 100 101 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ 102 #define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32)adr)) % ALIGNMENT) 103 104 #ifdef __BIG_ENDIAN 105 #define xemaclite_readl ioread32be 106 #define xemaclite_writel iowrite32be 107 #else 108 #define xemaclite_readl ioread32 109 #define xemaclite_writel iowrite32 110 #endif 111 112 /** 113 * struct net_local - Our private per device data 114 * @ndev: instance of the network device 115 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW 116 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW 117 * @next_tx_buf_to_use: next Tx buffer to write to 118 * @next_rx_buf_to_use: next Rx buffer to read from 119 * @base_addr: base address of the Emaclite device 120 * @reset_lock: lock used for synchronization 121 * @deferred_skb: holds an skb (for transmission at a later time) when the 122 * Tx buffer is not free 123 * @phy_dev: pointer to the PHY device 124 * @phy_node: pointer to the PHY device node 125 * @mii_bus: pointer to the MII bus 126 * @last_link: last link status 127 */ 128 struct net_local { 129 130 struct net_device *ndev; 131 132 bool tx_ping_pong; 133 bool rx_ping_pong; 134 u32 next_tx_buf_to_use; 135 u32 next_rx_buf_to_use; 136 void __iomem *base_addr; 137 138 spinlock_t reset_lock; 139 struct sk_buff *deferred_skb; 140 141 struct phy_device *phy_dev; 142 struct device_node *phy_node; 143 144 struct mii_bus *mii_bus; 145 146 int last_link; 147 }; 148 149 150 /*************************/ 151 /* EmacLite driver calls */ 152 /*************************/ 153 154 /** 155 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device 156 * @drvdata: Pointer to the Emaclite device private data 157 * 158 * This function enables the Tx and Rx interrupts for the Emaclite device along 159 * with the Global Interrupt Enable. 160 */ 161 static void xemaclite_enable_interrupts(struct net_local *drvdata) 162 { 163 u32 reg_data; 164 165 /* Enable the Tx interrupts for the first Buffer */ 166 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 167 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 168 drvdata->base_addr + XEL_TSR_OFFSET); 169 170 /* Enable the Rx interrupts for the first buffer */ 171 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 172 173 /* Enable the Global Interrupt Enable */ 174 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 175 } 176 177 /** 178 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device 179 * @drvdata: Pointer to the Emaclite device private data 180 * 181 * This function disables the Tx and Rx interrupts for the Emaclite device, 182 * along with the Global Interrupt Enable. 183 */ 184 static void xemaclite_disable_interrupts(struct net_local *drvdata) 185 { 186 u32 reg_data; 187 188 /* Disable the Global Interrupt Enable */ 189 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 190 191 /* Disable the Tx interrupts for the first buffer */ 192 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 193 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 194 drvdata->base_addr + XEL_TSR_OFFSET); 195 196 /* Disable the Rx interrupts for the first buffer */ 197 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); 198 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 199 drvdata->base_addr + XEL_RSR_OFFSET); 200 } 201 202 /** 203 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address 204 * @src_ptr: Void pointer to the 16-bit aligned source address 205 * @dest_ptr: Pointer to the 32-bit aligned destination address 206 * @length: Number bytes to write from source to destination 207 * 208 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned 209 * address in the EmacLite device. 210 */ 211 static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr, 212 unsigned length) 213 { 214 u32 align_buffer; 215 u32 *to_u32_ptr; 216 u16 *from_u16_ptr, *to_u16_ptr; 217 218 to_u32_ptr = dest_ptr; 219 from_u16_ptr = src_ptr; 220 align_buffer = 0; 221 222 for (; length > 3; length -= 4) { 223 to_u16_ptr = (u16 *)&align_buffer; 224 *to_u16_ptr++ = *from_u16_ptr++; 225 *to_u16_ptr++ = *from_u16_ptr++; 226 227 /* This barrier resolves occasional issues seen around 228 * cases where the data is not properly flushed out 229 * from the processor store buffers to the destination 230 * memory locations. 231 */ 232 wmb(); 233 234 /* Output a word */ 235 *to_u32_ptr++ = align_buffer; 236 } 237 if (length) { 238 u8 *from_u8_ptr, *to_u8_ptr; 239 240 /* Set up to output the remaining data */ 241 align_buffer = 0; 242 to_u8_ptr = (u8 *)&align_buffer; 243 from_u8_ptr = (u8 *)from_u16_ptr; 244 245 /* Output the remaining data */ 246 for (; length > 0; length--) 247 *to_u8_ptr++ = *from_u8_ptr++; 248 249 /* This barrier resolves occasional issues seen around 250 * cases where the data is not properly flushed out 251 * from the processor store buffers to the destination 252 * memory locations. 253 */ 254 wmb(); 255 *to_u32_ptr = align_buffer; 256 } 257 } 258 259 /** 260 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer 261 * @src_ptr: Pointer to the 32-bit aligned source address 262 * @dest_ptr: Pointer to the 16-bit aligned destination address 263 * @length: Number bytes to read from source to destination 264 * 265 * This function reads data from a 32-bit aligned address in the EmacLite device 266 * to a 16-bit aligned buffer. 267 */ 268 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr, 269 unsigned length) 270 { 271 u16 *to_u16_ptr, *from_u16_ptr; 272 u32 *from_u32_ptr; 273 u32 align_buffer; 274 275 from_u32_ptr = src_ptr; 276 to_u16_ptr = (u16 *)dest_ptr; 277 278 for (; length > 3; length -= 4) { 279 /* Copy each word into the temporary buffer */ 280 align_buffer = *from_u32_ptr++; 281 from_u16_ptr = (u16 *)&align_buffer; 282 283 /* Read data from source */ 284 *to_u16_ptr++ = *from_u16_ptr++; 285 *to_u16_ptr++ = *from_u16_ptr++; 286 } 287 288 if (length) { 289 u8 *to_u8_ptr, *from_u8_ptr; 290 291 /* Set up to read the remaining data */ 292 to_u8_ptr = (u8 *)to_u16_ptr; 293 align_buffer = *from_u32_ptr++; 294 from_u8_ptr = (u8 *)&align_buffer; 295 296 /* Read the remaining data */ 297 for (; length > 0; length--) 298 *to_u8_ptr = *from_u8_ptr; 299 } 300 } 301 302 /** 303 * xemaclite_send_data - Send an Ethernet frame 304 * @drvdata: Pointer to the Emaclite device private data 305 * @data: Pointer to the data to be sent 306 * @byte_count: Total frame size, including header 307 * 308 * This function checks if the Tx buffer of the Emaclite device is free to send 309 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it 310 * returns an error. 311 * 312 * Return: 0 upon success or -1 if the buffer(s) are full. 313 * 314 * Note: The maximum Tx packet size can not be more than Ethernet header 315 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS. 316 */ 317 static int xemaclite_send_data(struct net_local *drvdata, u8 *data, 318 unsigned int byte_count) 319 { 320 u32 reg_data; 321 void __iomem *addr; 322 323 /* Determine the expected Tx buffer address */ 324 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 325 326 /* If the length is too large, truncate it */ 327 if (byte_count > ETH_FRAME_LEN) 328 byte_count = ETH_FRAME_LEN; 329 330 /* Check if the expected buffer is available */ 331 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 332 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 333 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) { 334 335 /* Switch to next buffer if configured */ 336 if (drvdata->tx_ping_pong != 0) 337 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET; 338 } else if (drvdata->tx_ping_pong != 0) { 339 /* If the expected buffer is full, try the other buffer, 340 * if it is configured in HW 341 */ 342 343 addr = (void __iomem __force *)((u32 __force)addr ^ 344 XEL_BUFFER_OFFSET); 345 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 346 347 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 348 XEL_TSR_XMIT_ACTIVE_MASK)) != 0) 349 return -1; /* Buffers were full, return failure */ 350 } else 351 return -1; /* Buffer was full, return failure */ 352 353 /* Write the frame to the buffer */ 354 xemaclite_aligned_write(data, (u32 __force *)addr, byte_count); 355 356 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK), 357 addr + XEL_TPLR_OFFSET); 358 359 /* Update the Tx Status Register to indicate that there is a 360 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which 361 * is used by the interrupt handler to check whether a frame 362 * has been transmitted 363 */ 364 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 365 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK); 366 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET); 367 368 return 0; 369 } 370 371 /** 372 * xemaclite_recv_data - Receive a frame 373 * @drvdata: Pointer to the Emaclite device private data 374 * @data: Address where the data is to be received 375 * @maxlen: Maximum supported ethernet packet length 376 * 377 * This function is intended to be called from the interrupt context or 378 * with a wrapper which waits for the receive frame to be available. 379 * 380 * Return: Total number of bytes received 381 */ 382 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen) 383 { 384 void __iomem *addr; 385 u16 length, proto_type; 386 u32 reg_data; 387 388 /* Determine the expected buffer address */ 389 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); 390 391 /* Verify which buffer has valid data */ 392 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 393 394 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 395 if (drvdata->rx_ping_pong != 0) 396 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET; 397 } else { 398 /* The instance is out of sync, try other buffer if other 399 * buffer is configured, return 0 otherwise. If the instance is 400 * out of sync, do not update the 'next_rx_buf_to_use' since it 401 * will correct on subsequent calls 402 */ 403 if (drvdata->rx_ping_pong != 0) 404 addr = (void __iomem __force *)((u32 __force)addr ^ 405 XEL_BUFFER_OFFSET); 406 else 407 return 0; /* No data was available */ 408 409 /* Verify that buffer has valid data */ 410 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 411 if ((reg_data & XEL_RSR_RECV_DONE_MASK) != 412 XEL_RSR_RECV_DONE_MASK) 413 return 0; /* No data was available */ 414 } 415 416 /* Get the protocol type of the ethernet frame that arrived 417 */ 418 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET + 419 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) & 420 XEL_RPLR_LENGTH_MASK); 421 422 /* Check if received ethernet frame is a raw ethernet frame 423 * or an IP packet or an ARP packet 424 */ 425 if (proto_type > ETH_DATA_LEN) { 426 427 if (proto_type == ETH_P_IP) { 428 length = ((ntohl(xemaclite_readl(addr + 429 XEL_HEADER_IP_LENGTH_OFFSET + 430 XEL_RXBUFF_OFFSET)) >> 431 XEL_HEADER_SHIFT) & 432 XEL_RPLR_LENGTH_MASK); 433 length = min_t(u16, length, ETH_DATA_LEN); 434 length += ETH_HLEN + ETH_FCS_LEN; 435 436 } else if (proto_type == ETH_P_ARP) 437 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN; 438 else 439 /* Field contains type other than IP or ARP, use max 440 * frame size and let user parse it 441 */ 442 length = ETH_FRAME_LEN + ETH_FCS_LEN; 443 } else 444 /* Use the length in the frame, plus the header and trailer */ 445 length = proto_type + ETH_HLEN + ETH_FCS_LEN; 446 447 if (WARN_ON(length > maxlen)) 448 length = maxlen; 449 450 /* Read from the EmacLite device */ 451 xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET), 452 data, length); 453 454 /* Acknowledge the frame */ 455 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 456 reg_data &= ~XEL_RSR_RECV_DONE_MASK; 457 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET); 458 459 return length; 460 } 461 462 /** 463 * xemaclite_update_address - Update the MAC address in the device 464 * @drvdata: Pointer to the Emaclite device private data 465 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) 466 * 467 * Tx must be idle and Rx should be idle for deterministic results. 468 * It is recommended that this function should be called after the 469 * initialization and before transmission of any packets from the device. 470 * The MAC address can be programmed using any of the two transmit 471 * buffers (if configured). 472 */ 473 static void xemaclite_update_address(struct net_local *drvdata, 474 u8 *address_ptr) 475 { 476 void __iomem *addr; 477 u32 reg_data; 478 479 /* Determine the expected Tx buffer address */ 480 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 481 482 xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN); 483 484 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); 485 486 /* Update the MAC address in the EmacLite */ 487 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 488 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); 489 490 /* Wait for EmacLite to finish with the MAC address update */ 491 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) & 492 XEL_TSR_PROG_MAC_ADDR) != 0) 493 ; 494 } 495 496 /** 497 * xemaclite_set_mac_address - Set the MAC address for this device 498 * @dev: Pointer to the network device instance 499 * @address: Void pointer to the sockaddr structure 500 * 501 * This function copies the HW address from the sockaddr strucutre to the 502 * net_device structure and updates the address in HW. 503 * 504 * Return: Error if the net device is busy or 0 if the addr is set 505 * successfully 506 */ 507 static int xemaclite_set_mac_address(struct net_device *dev, void *address) 508 { 509 struct net_local *lp = netdev_priv(dev); 510 struct sockaddr *addr = address; 511 512 if (netif_running(dev)) 513 return -EBUSY; 514 515 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 516 xemaclite_update_address(lp, dev->dev_addr); 517 return 0; 518 } 519 520 /** 521 * xemaclite_tx_timeout - Callback for Tx Timeout 522 * @dev: Pointer to the network device 523 * 524 * This function is called when Tx time out occurs for Emaclite device. 525 */ 526 static void xemaclite_tx_timeout(struct net_device *dev) 527 { 528 struct net_local *lp = netdev_priv(dev); 529 unsigned long flags; 530 531 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n", 532 TX_TIMEOUT * 1000UL / HZ); 533 534 dev->stats.tx_errors++; 535 536 /* Reset the device */ 537 spin_lock_irqsave(&lp->reset_lock, flags); 538 539 /* Shouldn't really be necessary, but shouldn't hurt */ 540 netif_stop_queue(dev); 541 542 xemaclite_disable_interrupts(lp); 543 xemaclite_enable_interrupts(lp); 544 545 if (lp->deferred_skb) { 546 dev_kfree_skb(lp->deferred_skb); 547 lp->deferred_skb = NULL; 548 dev->stats.tx_errors++; 549 } 550 551 /* To exclude tx timeout */ 552 netif_trans_update(dev); /* prevent tx timeout */ 553 554 /* We're all ready to go. Start the queue */ 555 netif_wake_queue(dev); 556 spin_unlock_irqrestore(&lp->reset_lock, flags); 557 } 558 559 /**********************/ 560 /* Interrupt Handlers */ 561 /**********************/ 562 563 /** 564 * xemaclite_tx_handler - Interrupt handler for frames sent 565 * @dev: Pointer to the network device 566 * 567 * This function updates the number of packets transmitted and handles the 568 * deferred skb, if there is one. 569 */ 570 static void xemaclite_tx_handler(struct net_device *dev) 571 { 572 struct net_local *lp = netdev_priv(dev); 573 574 dev->stats.tx_packets++; 575 576 if (!lp->deferred_skb) 577 return; 578 579 if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data, 580 lp->deferred_skb->len)) 581 return; 582 583 dev->stats.tx_bytes += lp->deferred_skb->len; 584 dev_kfree_skb_irq(lp->deferred_skb); 585 lp->deferred_skb = NULL; 586 netif_trans_update(dev); /* prevent tx timeout */ 587 netif_wake_queue(dev); 588 } 589 590 /** 591 * xemaclite_rx_handler- Interrupt handler for frames received 592 * @dev: Pointer to the network device 593 * 594 * This function allocates memory for a socket buffer, fills it with data 595 * received and hands it over to the TCP/IP stack. 596 */ 597 static void xemaclite_rx_handler(struct net_device *dev) 598 { 599 struct net_local *lp = netdev_priv(dev); 600 struct sk_buff *skb; 601 unsigned int align; 602 u32 len; 603 604 len = ETH_FRAME_LEN + ETH_FCS_LEN; 605 skb = netdev_alloc_skb(dev, len + ALIGNMENT); 606 if (!skb) { 607 /* Couldn't get memory. */ 608 dev->stats.rx_dropped++; 609 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n"); 610 return; 611 } 612 613 /* A new skb should have the data halfword aligned, but this code is 614 * here just in case that isn't true. Calculate how many 615 * bytes we should reserve to get the data to start on a word 616 * boundary 617 */ 618 align = BUFFER_ALIGN(skb->data); 619 if (align) 620 skb_reserve(skb, align); 621 622 skb_reserve(skb, 2); 623 624 len = xemaclite_recv_data(lp, (u8 *)skb->data, len); 625 626 if (!len) { 627 dev->stats.rx_errors++; 628 dev_kfree_skb_irq(skb); 629 return; 630 } 631 632 skb_put(skb, len); /* Tell the skb how much data we got */ 633 634 skb->protocol = eth_type_trans(skb, dev); 635 skb_checksum_none_assert(skb); 636 637 dev->stats.rx_packets++; 638 dev->stats.rx_bytes += len; 639 640 if (!skb_defer_rx_timestamp(skb)) 641 netif_rx(skb); /* Send the packet upstream */ 642 } 643 644 /** 645 * xemaclite_interrupt - Interrupt handler for this driver 646 * @irq: Irq of the Emaclite device 647 * @dev_id: Void pointer to the network device instance used as callback 648 * reference 649 * 650 * Return: IRQ_HANDLED 651 * 652 * This function handles the Tx and Rx interrupts of the EmacLite device. 653 */ 654 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id) 655 { 656 bool tx_complete = false; 657 struct net_device *dev = dev_id; 658 struct net_local *lp = netdev_priv(dev); 659 void __iomem *base_addr = lp->base_addr; 660 u32 tx_status; 661 662 /* Check if there is Rx Data available */ 663 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) & 664 XEL_RSR_RECV_DONE_MASK) || 665 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) 666 & XEL_RSR_RECV_DONE_MASK)) 667 668 xemaclite_rx_handler(dev); 669 670 /* Check if the Transmission for the first buffer is completed */ 671 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET); 672 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 673 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 674 675 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 676 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET); 677 678 tx_complete = true; 679 } 680 681 /* Check if the Transmission for the second buffer is completed */ 682 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 683 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 684 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 685 686 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 687 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + 688 XEL_TSR_OFFSET); 689 690 tx_complete = true; 691 } 692 693 /* If there was a Tx interrupt, call the Tx Handler */ 694 if (tx_complete != 0) 695 xemaclite_tx_handler(dev); 696 697 return IRQ_HANDLED; 698 } 699 700 /**********************/ 701 /* MDIO Bus functions */ 702 /**********************/ 703 704 /** 705 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use 706 * @lp: Pointer to the Emaclite device private data 707 * 708 * This function waits till the device is ready to accept a new MDIO 709 * request. 710 * 711 * Return: 0 for success or ETIMEDOUT for a timeout 712 */ 713 714 static int xemaclite_mdio_wait(struct net_local *lp) 715 { 716 unsigned long end = jiffies + 2; 717 718 /* wait for the MDIO interface to not be busy or timeout 719 * after some time. 720 */ 721 while (xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET) & 722 XEL_MDIOCTRL_MDIOSTS_MASK) { 723 if (time_before_eq(end, jiffies)) { 724 WARN_ON(1); 725 return -ETIMEDOUT; 726 } 727 msleep(1); 728 } 729 return 0; 730 } 731 732 /** 733 * xemaclite_mdio_read - Read from a given MII management register 734 * @bus: the mii_bus struct 735 * @phy_id: the phy address 736 * @reg: register number to read from 737 * 738 * This function waits till the device is ready to accept a new MDIO 739 * request and then writes the phy address to the MDIO Address register 740 * and reads data from MDIO Read Data register, when its available. 741 * 742 * Return: Value read from the MII management register 743 */ 744 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) 745 { 746 struct net_local *lp = bus->priv; 747 u32 ctrl_reg; 748 u32 rc; 749 750 if (xemaclite_mdio_wait(lp)) 751 return -ETIMEDOUT; 752 753 /* Write the PHY address, register number and set the OP bit in the 754 * MDIO Address register. Set the Status bit in the MDIO Control 755 * register to start a MDIO read transaction. 756 */ 757 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 758 xemaclite_writel(XEL_MDIOADDR_OP_MASK | 759 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 760 lp->base_addr + XEL_MDIOADDR_OFFSET); 761 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 762 lp->base_addr + XEL_MDIOCTRL_OFFSET); 763 764 if (xemaclite_mdio_wait(lp)) 765 return -ETIMEDOUT; 766 767 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET); 768 769 dev_dbg(&lp->ndev->dev, 770 "%s(phy_id=%i, reg=%x) == %x\n", __func__, 771 phy_id, reg, rc); 772 773 return rc; 774 } 775 776 /** 777 * xemaclite_mdio_write - Write to a given MII management register 778 * @bus: the mii_bus struct 779 * @phy_id: the phy address 780 * @reg: register number to write to 781 * @val: value to write to the register number specified by reg 782 * 783 * This function waits till the device is ready to accept a new MDIO 784 * request and then writes the val to the MDIO Write Data register. 785 * 786 * Return: 0 upon success or a negative error upon failure 787 */ 788 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, 789 u16 val) 790 { 791 struct net_local *lp = bus->priv; 792 u32 ctrl_reg; 793 794 dev_dbg(&lp->ndev->dev, 795 "%s(phy_id=%i, reg=%x, val=%x)\n", __func__, 796 phy_id, reg, val); 797 798 if (xemaclite_mdio_wait(lp)) 799 return -ETIMEDOUT; 800 801 /* Write the PHY address, register number and clear the OP bit in the 802 * MDIO Address register and then write the value into the MDIO Write 803 * Data register. Finally, set the Status bit in the MDIO Control 804 * register to start a MDIO write transaction. 805 */ 806 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 807 xemaclite_writel(~XEL_MDIOADDR_OP_MASK & 808 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 809 lp->base_addr + XEL_MDIOADDR_OFFSET); 810 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); 811 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 812 lp->base_addr + XEL_MDIOCTRL_OFFSET); 813 814 return 0; 815 } 816 817 /** 818 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device 819 * @lp: Pointer to the Emaclite device private data 820 * @dev: Pointer to OF device structure 821 * 822 * This function enables MDIO bus in the Emaclite device and registers a 823 * mii_bus. 824 * 825 * Return: 0 upon success or a negative error upon failure 826 */ 827 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev) 828 { 829 struct mii_bus *bus; 830 int rc; 831 struct resource res; 832 struct device_node *np = of_get_parent(lp->phy_node); 833 struct device_node *npp; 834 835 /* Don't register the MDIO bus if the phy_node or its parent node 836 * can't be found. 837 */ 838 if (!np) { 839 dev_err(dev, "Failed to register mdio bus.\n"); 840 return -ENODEV; 841 } 842 npp = of_get_parent(np); 843 844 of_address_to_resource(npp, 0, &res); 845 if (lp->ndev->mem_start != res.start) { 846 struct phy_device *phydev; 847 phydev = of_phy_find_device(lp->phy_node); 848 if (!phydev) 849 dev_info(dev, 850 "MDIO of the phy is not registered yet\n"); 851 else 852 put_device(&phydev->mdio.dev); 853 return 0; 854 } 855 856 /* Enable the MDIO bus by asserting the enable bit in MDIO Control 857 * register. 858 */ 859 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK, 860 lp->base_addr + XEL_MDIOCTRL_OFFSET); 861 862 bus = mdiobus_alloc(); 863 if (!bus) { 864 dev_err(dev, "Failed to allocate mdiobus\n"); 865 return -ENOMEM; 866 } 867 868 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 869 (unsigned long long)res.start); 870 bus->priv = lp; 871 bus->name = "Xilinx Emaclite MDIO"; 872 bus->read = xemaclite_mdio_read; 873 bus->write = xemaclite_mdio_write; 874 bus->parent = dev; 875 876 rc = of_mdiobus_register(bus, np); 877 if (rc) { 878 dev_err(dev, "Failed to register mdio bus.\n"); 879 goto err_register; 880 } 881 882 lp->mii_bus = bus; 883 884 return 0; 885 886 err_register: 887 mdiobus_free(bus); 888 return rc; 889 } 890 891 /** 892 * xemaclite_adjust_link - Link state callback for the Emaclite device 893 * @ndev: pointer to net_device struct 894 * 895 * There's nothing in the Emaclite device to be configured when the link 896 * state changes. We just print the status. 897 */ 898 static void xemaclite_adjust_link(struct net_device *ndev) 899 { 900 struct net_local *lp = netdev_priv(ndev); 901 struct phy_device *phy = lp->phy_dev; 902 int link_state; 903 904 /* hash together the state values to decide if something has changed */ 905 link_state = phy->speed | (phy->duplex << 1) | phy->link; 906 907 if (lp->last_link != link_state) { 908 lp->last_link = link_state; 909 phy_print_status(phy); 910 } 911 } 912 913 /** 914 * xemaclite_open - Open the network device 915 * @dev: Pointer to the network device 916 * 917 * This function sets the MAC address, requests an IRQ and enables interrupts 918 * for the Emaclite device and starts the Tx queue. 919 * It also connects to the phy device, if MDIO is included in Emaclite device. 920 * 921 * Return: 0 on success. -ENODEV, if PHY cannot be connected. 922 * Non-zero error value on failure. 923 */ 924 static int xemaclite_open(struct net_device *dev) 925 { 926 struct net_local *lp = netdev_priv(dev); 927 int retval; 928 929 /* Just to be safe, stop the device first */ 930 xemaclite_disable_interrupts(lp); 931 932 if (lp->phy_node) { 933 u32 bmcr; 934 935 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 936 xemaclite_adjust_link, 0, 937 PHY_INTERFACE_MODE_MII); 938 if (!lp->phy_dev) { 939 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n"); 940 return -ENODEV; 941 } 942 943 /* EmacLite doesn't support giga-bit speeds */ 944 lp->phy_dev->supported &= (PHY_BASIC_FEATURES); 945 lp->phy_dev->advertising = lp->phy_dev->supported; 946 947 /* Don't advertise 1000BASE-T Full/Half duplex speeds */ 948 phy_write(lp->phy_dev, MII_CTRL1000, 0); 949 950 /* Advertise only 10 and 100mbps full/half duplex speeds */ 951 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | 952 ADVERTISE_CSMA); 953 954 /* Restart auto negotiation */ 955 bmcr = phy_read(lp->phy_dev, MII_BMCR); 956 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 957 phy_write(lp->phy_dev, MII_BMCR, bmcr); 958 959 phy_start(lp->phy_dev); 960 } 961 962 /* Set the MAC address each time opened */ 963 xemaclite_update_address(lp, dev->dev_addr); 964 965 /* Grab the IRQ */ 966 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev); 967 if (retval) { 968 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n", 969 dev->irq); 970 if (lp->phy_dev) 971 phy_disconnect(lp->phy_dev); 972 lp->phy_dev = NULL; 973 974 return retval; 975 } 976 977 /* Enable Interrupts */ 978 xemaclite_enable_interrupts(lp); 979 980 /* We're ready to go */ 981 netif_start_queue(dev); 982 983 return 0; 984 } 985 986 /** 987 * xemaclite_close - Close the network device 988 * @dev: Pointer to the network device 989 * 990 * This function stops the Tx queue, disables interrupts and frees the IRQ for 991 * the Emaclite device. 992 * It also disconnects the phy device associated with the Emaclite device. 993 * 994 * Return: 0, always. 995 */ 996 static int xemaclite_close(struct net_device *dev) 997 { 998 struct net_local *lp = netdev_priv(dev); 999 1000 netif_stop_queue(dev); 1001 xemaclite_disable_interrupts(lp); 1002 free_irq(dev->irq, dev); 1003 1004 if (lp->phy_dev) 1005 phy_disconnect(lp->phy_dev); 1006 lp->phy_dev = NULL; 1007 1008 return 0; 1009 } 1010 1011 /** 1012 * xemaclite_send - Transmit a frame 1013 * @orig_skb: Pointer to the socket buffer to be transmitted 1014 * @dev: Pointer to the network device 1015 * 1016 * This function checks if the Tx buffer of the Emaclite device is free to send 1017 * data. If so, it fills the Tx buffer with data from socket buffer data, 1018 * updates the stats and frees the socket buffer. The Tx completion is signaled 1019 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is 1020 * deferred and the Tx queue is stopped so that the deferred socket buffer can 1021 * be transmitted when the Emaclite device is free to transmit data. 1022 * 1023 * Return: 0, always. 1024 */ 1025 static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev) 1026 { 1027 struct net_local *lp = netdev_priv(dev); 1028 struct sk_buff *new_skb; 1029 unsigned int len; 1030 unsigned long flags; 1031 1032 len = orig_skb->len; 1033 1034 new_skb = orig_skb; 1035 1036 spin_lock_irqsave(&lp->reset_lock, flags); 1037 if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) { 1038 /* If the Emaclite Tx buffer is busy, stop the Tx queue and 1039 * defer the skb for transmission during the ISR, after the 1040 * current transmission is complete 1041 */ 1042 netif_stop_queue(dev); 1043 lp->deferred_skb = new_skb; 1044 /* Take the time stamp now, since we can't do this in an ISR. */ 1045 skb_tx_timestamp(new_skb); 1046 spin_unlock_irqrestore(&lp->reset_lock, flags); 1047 return 0; 1048 } 1049 spin_unlock_irqrestore(&lp->reset_lock, flags); 1050 1051 skb_tx_timestamp(new_skb); 1052 1053 dev->stats.tx_bytes += len; 1054 dev_consume_skb_any(new_skb); 1055 1056 return 0; 1057 } 1058 1059 /** 1060 * get_bool - Get a parameter from the OF device 1061 * @ofdev: Pointer to OF device structure 1062 * @s: Property to be retrieved 1063 * 1064 * This function looks for a property in the device node and returns the value 1065 * of the property if its found or 0 if the property is not found. 1066 * 1067 * Return: Value of the parameter if the parameter is found, or 0 otherwise 1068 */ 1069 static bool get_bool(struct platform_device *ofdev, const char *s) 1070 { 1071 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL); 1072 1073 if (!p) { 1074 dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s); 1075 return false; 1076 } 1077 1078 return (bool)*p; 1079 } 1080 1081 static const struct net_device_ops xemaclite_netdev_ops; 1082 1083 /** 1084 * xemaclite_of_probe - Probe method for the Emaclite device. 1085 * @ofdev: Pointer to OF device structure 1086 * 1087 * This function probes for the Emaclite device in the device tree. 1088 * It initializes the driver data structure and the hardware, sets the MAC 1089 * address and registers the network device. 1090 * It also registers a mii_bus for the Emaclite device, if MDIO is included 1091 * in the device. 1092 * 1093 * Return: 0, if the driver is bound to the Emaclite device, or 1094 * a negative error if there is failure. 1095 */ 1096 static int xemaclite_of_probe(struct platform_device *ofdev) 1097 { 1098 struct resource *res; 1099 struct net_device *ndev = NULL; 1100 struct net_local *lp = NULL; 1101 struct device *dev = &ofdev->dev; 1102 const void *mac_address; 1103 1104 int rc = 0; 1105 1106 dev_info(dev, "Device Tree Probing\n"); 1107 1108 /* Create an ethernet device instance */ 1109 ndev = alloc_etherdev(sizeof(struct net_local)); 1110 if (!ndev) 1111 return -ENOMEM; 1112 1113 dev_set_drvdata(dev, ndev); 1114 SET_NETDEV_DEV(ndev, &ofdev->dev); 1115 1116 lp = netdev_priv(ndev); 1117 lp->ndev = ndev; 1118 1119 /* Get IRQ for the device */ 1120 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0); 1121 if (!res) { 1122 dev_err(dev, "no IRQ found\n"); 1123 rc = -ENXIO; 1124 goto error; 1125 } 1126 1127 ndev->irq = res->start; 1128 1129 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); 1130 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); 1131 if (IS_ERR(lp->base_addr)) { 1132 rc = PTR_ERR(lp->base_addr); 1133 goto error; 1134 } 1135 1136 ndev->mem_start = res->start; 1137 ndev->mem_end = res->end; 1138 1139 spin_lock_init(&lp->reset_lock); 1140 lp->next_tx_buf_to_use = 0x0; 1141 lp->next_rx_buf_to_use = 0x0; 1142 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); 1143 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); 1144 mac_address = of_get_mac_address(ofdev->dev.of_node); 1145 1146 if (mac_address) { 1147 /* Set the MAC address. */ 1148 memcpy(ndev->dev_addr, mac_address, ETH_ALEN); 1149 } else { 1150 dev_warn(dev, "No MAC address found, using random\n"); 1151 eth_hw_addr_random(ndev); 1152 } 1153 1154 /* Clear the Tx CSR's in case this is a restart */ 1155 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET); 1156 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 1157 1158 /* Set the MAC address in the EmacLite device */ 1159 xemaclite_update_address(lp, ndev->dev_addr); 1160 1161 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0); 1162 xemaclite_mdio_setup(lp, &ofdev->dev); 1163 1164 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr); 1165 1166 ndev->netdev_ops = &xemaclite_netdev_ops; 1167 ndev->flags &= ~IFF_MULTICAST; 1168 ndev->watchdog_timeo = TX_TIMEOUT; 1169 1170 /* Finally, register the device */ 1171 rc = register_netdev(ndev); 1172 if (rc) { 1173 dev_err(dev, 1174 "Cannot register network device, aborting\n"); 1175 goto error; 1176 } 1177 1178 dev_info(dev, 1179 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n", 1180 (unsigned int __force)ndev->mem_start, 1181 (unsigned int __force)lp->base_addr, ndev->irq); 1182 return 0; 1183 1184 error: 1185 free_netdev(ndev); 1186 return rc; 1187 } 1188 1189 /** 1190 * xemaclite_of_remove - Unbind the driver from the Emaclite device. 1191 * @of_dev: Pointer to OF device structure 1192 * 1193 * This function is called if a device is physically removed from the system or 1194 * if the driver module is being unloaded. It frees any resources allocated to 1195 * the device. 1196 * 1197 * Return: 0, always. 1198 */ 1199 static int xemaclite_of_remove(struct platform_device *of_dev) 1200 { 1201 struct net_device *ndev = platform_get_drvdata(of_dev); 1202 1203 struct net_local *lp = netdev_priv(ndev); 1204 1205 /* Un-register the mii_bus, if configured */ 1206 if (lp->mii_bus) { 1207 mdiobus_unregister(lp->mii_bus); 1208 mdiobus_free(lp->mii_bus); 1209 lp->mii_bus = NULL; 1210 } 1211 1212 unregister_netdev(ndev); 1213 1214 of_node_put(lp->phy_node); 1215 lp->phy_node = NULL; 1216 1217 free_netdev(ndev); 1218 1219 return 0; 1220 } 1221 1222 #ifdef CONFIG_NET_POLL_CONTROLLER 1223 static void 1224 xemaclite_poll_controller(struct net_device *ndev) 1225 { 1226 disable_irq(ndev->irq); 1227 xemaclite_interrupt(ndev->irq, ndev); 1228 enable_irq(ndev->irq); 1229 } 1230 #endif 1231 1232 static const struct net_device_ops xemaclite_netdev_ops = { 1233 .ndo_open = xemaclite_open, 1234 .ndo_stop = xemaclite_close, 1235 .ndo_start_xmit = xemaclite_send, 1236 .ndo_set_mac_address = xemaclite_set_mac_address, 1237 .ndo_tx_timeout = xemaclite_tx_timeout, 1238 #ifdef CONFIG_NET_POLL_CONTROLLER 1239 .ndo_poll_controller = xemaclite_poll_controller, 1240 #endif 1241 }; 1242 1243 /* Match table for OF platform binding */ 1244 static const struct of_device_id xemaclite_of_match[] = { 1245 { .compatible = "xlnx,opb-ethernetlite-1.01.a", }, 1246 { .compatible = "xlnx,opb-ethernetlite-1.01.b", }, 1247 { .compatible = "xlnx,xps-ethernetlite-1.00.a", }, 1248 { .compatible = "xlnx,xps-ethernetlite-2.00.a", }, 1249 { .compatible = "xlnx,xps-ethernetlite-2.01.a", }, 1250 { .compatible = "xlnx,xps-ethernetlite-3.00.a", }, 1251 { /* end of list */ }, 1252 }; 1253 MODULE_DEVICE_TABLE(of, xemaclite_of_match); 1254 1255 static struct platform_driver xemaclite_of_driver = { 1256 .driver = { 1257 .name = DRIVER_NAME, 1258 .of_match_table = xemaclite_of_match, 1259 }, 1260 .probe = xemaclite_of_probe, 1261 .remove = xemaclite_of_remove, 1262 }; 1263 1264 module_platform_driver(xemaclite_of_driver); 1265 1266 MODULE_AUTHOR("Xilinx, Inc."); 1267 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver"); 1268 MODULE_LICENSE("GPL"); 1269