1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. 3 * 4 * This is a new flat driver which is based on the original emac_lite 5 * driver from John Williams <john.williams@xilinx.com>. 6 * 7 * 2007 - 2013 (c) Xilinx, Inc. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/uaccess.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/skbuff.h> 15 #include <linux/ethtool.h> 16 #include <linux/io.h> 17 #include <linux/slab.h> 18 #include <linux/of_address.h> 19 #include <linux/of_device.h> 20 #include <linux/of_platform.h> 21 #include <linux/of_mdio.h> 22 #include <linux/of_net.h> 23 #include <linux/phy.h> 24 #include <linux/interrupt.h> 25 #include <linux/iopoll.h> 26 27 #define DRIVER_NAME "xilinx_emaclite" 28 29 /* Register offsets for the EmacLite Core */ 30 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ 31 #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ 32 #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ 33 #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ 34 #define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ 35 #define XEL_GIER_OFFSET 0x07F8 /* GIE Register */ 36 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 37 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 38 39 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 40 #define XEL_RPLR_OFFSET 0x100C /* Rx packet length */ 41 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 42 43 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */ 44 45 /* MDIO Address Register Bit Masks */ 46 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 47 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 48 #define XEL_MDIOADDR_PHYADR_SHIFT 5 49 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 50 51 /* MDIO Write Data Register Bit Masks */ 52 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 53 54 /* MDIO Read Data Register Bit Masks */ 55 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 56 57 /* MDIO Control Register Bit Masks */ 58 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 59 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 60 61 /* Global Interrupt Enable Register (GIER) Bit Masks */ 62 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ 63 64 /* Transmit Status Register (TSR) Bit Masks */ 65 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ 66 #define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ 67 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ 68 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit 69 * only. This is not documented 70 * in the HW spec 71 */ 72 73 /* Define for programming the MAC address into the EmacLite */ 74 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 75 76 /* Receive Status Register (RSR) */ 77 #define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ 78 #define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ 79 80 /* Transmit Packet Length Register (TPLR) */ 81 #define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ 82 83 /* Receive Packet Length Register (RPLR) */ 84 #define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ 85 86 #define XEL_HEADER_OFFSET 12 /* Offset to length field */ 87 #define XEL_HEADER_SHIFT 16 /* Shift value for length */ 88 89 /* General Ethernet Definitions */ 90 #define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ 91 #define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ 92 93 #define TX_TIMEOUT (60 * HZ) /* Tx timeout is 60 seconds. */ 94 #define ALIGNMENT 4 95 96 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ 97 #define BUFFER_ALIGN(adr) ((ALIGNMENT - ((uintptr_t)adr)) % ALIGNMENT) 98 99 #ifdef __BIG_ENDIAN 100 #define xemaclite_readl ioread32be 101 #define xemaclite_writel iowrite32be 102 #else 103 #define xemaclite_readl ioread32 104 #define xemaclite_writel iowrite32 105 #endif 106 107 /** 108 * struct net_local - Our private per device data 109 * @ndev: instance of the network device 110 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW 111 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW 112 * @next_tx_buf_to_use: next Tx buffer to write to 113 * @next_rx_buf_to_use: next Rx buffer to read from 114 * @base_addr: base address of the Emaclite device 115 * @reset_lock: lock used for synchronization 116 * @deferred_skb: holds an skb (for transmission at a later time) when the 117 * Tx buffer is not free 118 * @phy_dev: pointer to the PHY device 119 * @phy_node: pointer to the PHY device node 120 * @mii_bus: pointer to the MII bus 121 * @last_link: last link status 122 */ 123 struct net_local { 124 struct net_device *ndev; 125 126 bool tx_ping_pong; 127 bool rx_ping_pong; 128 u32 next_tx_buf_to_use; 129 u32 next_rx_buf_to_use; 130 void __iomem *base_addr; 131 132 spinlock_t reset_lock; /* serialize xmit and tx_timeout execution */ 133 struct sk_buff *deferred_skb; 134 135 struct phy_device *phy_dev; 136 struct device_node *phy_node; 137 138 struct mii_bus *mii_bus; 139 140 int last_link; 141 }; 142 143 /*************************/ 144 /* EmacLite driver calls */ 145 /*************************/ 146 147 /** 148 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device 149 * @drvdata: Pointer to the Emaclite device private data 150 * 151 * This function enables the Tx and Rx interrupts for the Emaclite device along 152 * with the Global Interrupt Enable. 153 */ 154 static void xemaclite_enable_interrupts(struct net_local *drvdata) 155 { 156 u32 reg_data; 157 158 /* Enable the Tx interrupts for the first Buffer */ 159 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 160 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 161 drvdata->base_addr + XEL_TSR_OFFSET); 162 163 /* Enable the Rx interrupts for the first buffer */ 164 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 165 166 /* Enable the Global Interrupt Enable */ 167 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 168 } 169 170 /** 171 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device 172 * @drvdata: Pointer to the Emaclite device private data 173 * 174 * This function disables the Tx and Rx interrupts for the Emaclite device, 175 * along with the Global Interrupt Enable. 176 */ 177 static void xemaclite_disable_interrupts(struct net_local *drvdata) 178 { 179 u32 reg_data; 180 181 /* Disable the Global Interrupt Enable */ 182 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 183 184 /* Disable the Tx interrupts for the first buffer */ 185 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 186 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 187 drvdata->base_addr + XEL_TSR_OFFSET); 188 189 /* Disable the Rx interrupts for the first buffer */ 190 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); 191 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 192 drvdata->base_addr + XEL_RSR_OFFSET); 193 } 194 195 /** 196 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address 197 * @src_ptr: Void pointer to the 16-bit aligned source address 198 * @dest_ptr: Pointer to the 32-bit aligned destination address 199 * @length: Number bytes to write from source to destination 200 * 201 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned 202 * address in the EmacLite device. 203 */ 204 static void xemaclite_aligned_write(const void *src_ptr, u32 *dest_ptr, 205 unsigned int length) 206 { 207 const u16 *from_u16_ptr; 208 u32 align_buffer; 209 u32 *to_u32_ptr; 210 u16 *to_u16_ptr; 211 212 to_u32_ptr = dest_ptr; 213 from_u16_ptr = src_ptr; 214 align_buffer = 0; 215 216 for (; length > 3; length -= 4) { 217 to_u16_ptr = (u16 *)&align_buffer; 218 *to_u16_ptr++ = *from_u16_ptr++; 219 *to_u16_ptr++ = *from_u16_ptr++; 220 221 /* This barrier resolves occasional issues seen around 222 * cases where the data is not properly flushed out 223 * from the processor store buffers to the destination 224 * memory locations. 225 */ 226 wmb(); 227 228 /* Output a word */ 229 *to_u32_ptr++ = align_buffer; 230 } 231 if (length) { 232 u8 *from_u8_ptr, *to_u8_ptr; 233 234 /* Set up to output the remaining data */ 235 align_buffer = 0; 236 to_u8_ptr = (u8 *)&align_buffer; 237 from_u8_ptr = (u8 *)from_u16_ptr; 238 239 /* Output the remaining data */ 240 for (; length > 0; length--) 241 *to_u8_ptr++ = *from_u8_ptr++; 242 243 /* This barrier resolves occasional issues seen around 244 * cases where the data is not properly flushed out 245 * from the processor store buffers to the destination 246 * memory locations. 247 */ 248 wmb(); 249 *to_u32_ptr = align_buffer; 250 } 251 } 252 253 /** 254 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer 255 * @src_ptr: Pointer to the 32-bit aligned source address 256 * @dest_ptr: Pointer to the 16-bit aligned destination address 257 * @length: Number bytes to read from source to destination 258 * 259 * This function reads data from a 32-bit aligned address in the EmacLite device 260 * to a 16-bit aligned buffer. 261 */ 262 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr, 263 unsigned int length) 264 { 265 u16 *to_u16_ptr, *from_u16_ptr; 266 u32 *from_u32_ptr; 267 u32 align_buffer; 268 269 from_u32_ptr = src_ptr; 270 to_u16_ptr = (u16 *)dest_ptr; 271 272 for (; length > 3; length -= 4) { 273 /* Copy each word into the temporary buffer */ 274 align_buffer = *from_u32_ptr++; 275 from_u16_ptr = (u16 *)&align_buffer; 276 277 /* Read data from source */ 278 *to_u16_ptr++ = *from_u16_ptr++; 279 *to_u16_ptr++ = *from_u16_ptr++; 280 } 281 282 if (length) { 283 u8 *to_u8_ptr, *from_u8_ptr; 284 285 /* Set up to read the remaining data */ 286 to_u8_ptr = (u8 *)to_u16_ptr; 287 align_buffer = *from_u32_ptr++; 288 from_u8_ptr = (u8 *)&align_buffer; 289 290 /* Read the remaining data */ 291 for (; length > 0; length--) 292 *to_u8_ptr = *from_u8_ptr; 293 } 294 } 295 296 /** 297 * xemaclite_send_data - Send an Ethernet frame 298 * @drvdata: Pointer to the Emaclite device private data 299 * @data: Pointer to the data to be sent 300 * @byte_count: Total frame size, including header 301 * 302 * This function checks if the Tx buffer of the Emaclite device is free to send 303 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it 304 * returns an error. 305 * 306 * Return: 0 upon success or -1 if the buffer(s) are full. 307 * 308 * Note: The maximum Tx packet size can not be more than Ethernet header 309 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS. 310 */ 311 static int xemaclite_send_data(struct net_local *drvdata, u8 *data, 312 unsigned int byte_count) 313 { 314 u32 reg_data; 315 void __iomem *addr; 316 317 /* Determine the expected Tx buffer address */ 318 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 319 320 /* If the length is too large, truncate it */ 321 if (byte_count > ETH_FRAME_LEN) 322 byte_count = ETH_FRAME_LEN; 323 324 /* Check if the expected buffer is available */ 325 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 326 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 327 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) { 328 /* Switch to next buffer if configured */ 329 if (drvdata->tx_ping_pong != 0) 330 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET; 331 } else if (drvdata->tx_ping_pong != 0) { 332 /* If the expected buffer is full, try the other buffer, 333 * if it is configured in HW 334 */ 335 336 addr = (void __iomem __force *)((uintptr_t __force)addr ^ 337 XEL_BUFFER_OFFSET); 338 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 339 340 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 341 XEL_TSR_XMIT_ACTIVE_MASK)) != 0) 342 return -1; /* Buffers were full, return failure */ 343 } else { 344 return -1; /* Buffer was full, return failure */ 345 } 346 347 /* Write the frame to the buffer */ 348 xemaclite_aligned_write(data, (u32 __force *)addr, byte_count); 349 350 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK), 351 addr + XEL_TPLR_OFFSET); 352 353 /* Update the Tx Status Register to indicate that there is a 354 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which 355 * is used by the interrupt handler to check whether a frame 356 * has been transmitted 357 */ 358 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 359 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK); 360 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET); 361 362 return 0; 363 } 364 365 /** 366 * xemaclite_recv_data - Receive a frame 367 * @drvdata: Pointer to the Emaclite device private data 368 * @data: Address where the data is to be received 369 * @maxlen: Maximum supported ethernet packet length 370 * 371 * This function is intended to be called from the interrupt context or 372 * with a wrapper which waits for the receive frame to be available. 373 * 374 * Return: Total number of bytes received 375 */ 376 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen) 377 { 378 void __iomem *addr; 379 u16 length, proto_type; 380 u32 reg_data; 381 382 /* Determine the expected buffer address */ 383 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); 384 385 /* Verify which buffer has valid data */ 386 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 387 388 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 389 if (drvdata->rx_ping_pong != 0) 390 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET; 391 } else { 392 /* The instance is out of sync, try other buffer if other 393 * buffer is configured, return 0 otherwise. If the instance is 394 * out of sync, do not update the 'next_rx_buf_to_use' since it 395 * will correct on subsequent calls 396 */ 397 if (drvdata->rx_ping_pong != 0) 398 addr = (void __iomem __force *) 399 ((uintptr_t __force)addr ^ 400 XEL_BUFFER_OFFSET); 401 else 402 return 0; /* No data was available */ 403 404 /* Verify that buffer has valid data */ 405 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 406 if ((reg_data & XEL_RSR_RECV_DONE_MASK) != 407 XEL_RSR_RECV_DONE_MASK) 408 return 0; /* No data was available */ 409 } 410 411 /* Get the protocol type of the ethernet frame that arrived 412 */ 413 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET + 414 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) & 415 XEL_RPLR_LENGTH_MASK); 416 417 /* Check if received ethernet frame is a raw ethernet frame 418 * or an IP packet or an ARP packet 419 */ 420 if (proto_type > ETH_DATA_LEN) { 421 if (proto_type == ETH_P_IP) { 422 length = ((ntohl(xemaclite_readl(addr + 423 XEL_HEADER_IP_LENGTH_OFFSET + 424 XEL_RXBUFF_OFFSET)) >> 425 XEL_HEADER_SHIFT) & 426 XEL_RPLR_LENGTH_MASK); 427 length = min_t(u16, length, ETH_DATA_LEN); 428 length += ETH_HLEN + ETH_FCS_LEN; 429 430 } else if (proto_type == ETH_P_ARP) { 431 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN; 432 } else { 433 /* Field contains type other than IP or ARP, use max 434 * frame size and let user parse it 435 */ 436 length = ETH_FRAME_LEN + ETH_FCS_LEN; 437 } 438 } else { 439 /* Use the length in the frame, plus the header and trailer */ 440 length = proto_type + ETH_HLEN + ETH_FCS_LEN; 441 } 442 443 if (WARN_ON(length > maxlen)) 444 length = maxlen; 445 446 /* Read from the EmacLite device */ 447 xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET), 448 data, length); 449 450 /* Acknowledge the frame */ 451 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 452 reg_data &= ~XEL_RSR_RECV_DONE_MASK; 453 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET); 454 455 return length; 456 } 457 458 /** 459 * xemaclite_update_address - Update the MAC address in the device 460 * @drvdata: Pointer to the Emaclite device private data 461 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) 462 * 463 * Tx must be idle and Rx should be idle for deterministic results. 464 * It is recommended that this function should be called after the 465 * initialization and before transmission of any packets from the device. 466 * The MAC address can be programmed using any of the two transmit 467 * buffers (if configured). 468 */ 469 static void xemaclite_update_address(struct net_local *drvdata, 470 const u8 *address_ptr) 471 { 472 void __iomem *addr; 473 u32 reg_data; 474 475 /* Determine the expected Tx buffer address */ 476 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 477 478 xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN); 479 480 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); 481 482 /* Update the MAC address in the EmacLite */ 483 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 484 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); 485 486 /* Wait for EmacLite to finish with the MAC address update */ 487 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) & 488 XEL_TSR_PROG_MAC_ADDR) != 0) 489 ; 490 } 491 492 /** 493 * xemaclite_set_mac_address - Set the MAC address for this device 494 * @dev: Pointer to the network device instance 495 * @address: Void pointer to the sockaddr structure 496 * 497 * This function copies the HW address from the sockaddr structure to the 498 * net_device structure and updates the address in HW. 499 * 500 * Return: Error if the net device is busy or 0 if the addr is set 501 * successfully 502 */ 503 static int xemaclite_set_mac_address(struct net_device *dev, void *address) 504 { 505 struct net_local *lp = netdev_priv(dev); 506 struct sockaddr *addr = address; 507 508 if (netif_running(dev)) 509 return -EBUSY; 510 511 eth_hw_addr_set(dev, addr->sa_data); 512 xemaclite_update_address(lp, dev->dev_addr); 513 return 0; 514 } 515 516 /** 517 * xemaclite_tx_timeout - Callback for Tx Timeout 518 * @dev: Pointer to the network device 519 * @txqueue: Unused 520 * 521 * This function is called when Tx time out occurs for Emaclite device. 522 */ 523 static void xemaclite_tx_timeout(struct net_device *dev, unsigned int txqueue) 524 { 525 struct net_local *lp = netdev_priv(dev); 526 unsigned long flags; 527 528 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n", 529 TX_TIMEOUT * 1000UL / HZ); 530 531 dev->stats.tx_errors++; 532 533 /* Reset the device */ 534 spin_lock_irqsave(&lp->reset_lock, flags); 535 536 /* Shouldn't really be necessary, but shouldn't hurt */ 537 netif_stop_queue(dev); 538 539 xemaclite_disable_interrupts(lp); 540 xemaclite_enable_interrupts(lp); 541 542 if (lp->deferred_skb) { 543 dev_kfree_skb(lp->deferred_skb); 544 lp->deferred_skb = NULL; 545 dev->stats.tx_errors++; 546 } 547 548 /* To exclude tx timeout */ 549 netif_trans_update(dev); /* prevent tx timeout */ 550 551 /* We're all ready to go. Start the queue */ 552 netif_wake_queue(dev); 553 spin_unlock_irqrestore(&lp->reset_lock, flags); 554 } 555 556 /**********************/ 557 /* Interrupt Handlers */ 558 /**********************/ 559 560 /** 561 * xemaclite_tx_handler - Interrupt handler for frames sent 562 * @dev: Pointer to the network device 563 * 564 * This function updates the number of packets transmitted and handles the 565 * deferred skb, if there is one. 566 */ 567 static void xemaclite_tx_handler(struct net_device *dev) 568 { 569 struct net_local *lp = netdev_priv(dev); 570 571 dev->stats.tx_packets++; 572 573 if (!lp->deferred_skb) 574 return; 575 576 if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data, 577 lp->deferred_skb->len)) 578 return; 579 580 dev->stats.tx_bytes += lp->deferred_skb->len; 581 dev_consume_skb_irq(lp->deferred_skb); 582 lp->deferred_skb = NULL; 583 netif_trans_update(dev); /* prevent tx timeout */ 584 netif_wake_queue(dev); 585 } 586 587 /** 588 * xemaclite_rx_handler- Interrupt handler for frames received 589 * @dev: Pointer to the network device 590 * 591 * This function allocates memory for a socket buffer, fills it with data 592 * received and hands it over to the TCP/IP stack. 593 */ 594 static void xemaclite_rx_handler(struct net_device *dev) 595 { 596 struct net_local *lp = netdev_priv(dev); 597 struct sk_buff *skb; 598 unsigned int align; 599 u32 len; 600 601 len = ETH_FRAME_LEN + ETH_FCS_LEN; 602 skb = netdev_alloc_skb(dev, len + ALIGNMENT); 603 if (!skb) { 604 /* Couldn't get memory. */ 605 dev->stats.rx_dropped++; 606 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n"); 607 return; 608 } 609 610 /* A new skb should have the data halfword aligned, but this code is 611 * here just in case that isn't true. Calculate how many 612 * bytes we should reserve to get the data to start on a word 613 * boundary 614 */ 615 align = BUFFER_ALIGN(skb->data); 616 if (align) 617 skb_reserve(skb, align); 618 619 skb_reserve(skb, 2); 620 621 len = xemaclite_recv_data(lp, (u8 *)skb->data, len); 622 623 if (!len) { 624 dev->stats.rx_errors++; 625 dev_kfree_skb_irq(skb); 626 return; 627 } 628 629 skb_put(skb, len); /* Tell the skb how much data we got */ 630 631 skb->protocol = eth_type_trans(skb, dev); 632 skb_checksum_none_assert(skb); 633 634 dev->stats.rx_packets++; 635 dev->stats.rx_bytes += len; 636 637 if (!skb_defer_rx_timestamp(skb)) 638 netif_rx(skb); /* Send the packet upstream */ 639 } 640 641 /** 642 * xemaclite_interrupt - Interrupt handler for this driver 643 * @irq: Irq of the Emaclite device 644 * @dev_id: Void pointer to the network device instance used as callback 645 * reference 646 * 647 * Return: IRQ_HANDLED 648 * 649 * This function handles the Tx and Rx interrupts of the EmacLite device. 650 */ 651 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id) 652 { 653 bool tx_complete = false; 654 struct net_device *dev = dev_id; 655 struct net_local *lp = netdev_priv(dev); 656 void __iomem *base_addr = lp->base_addr; 657 u32 tx_status; 658 659 /* Check if there is Rx Data available */ 660 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) & 661 XEL_RSR_RECV_DONE_MASK) || 662 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) 663 & XEL_RSR_RECV_DONE_MASK)) 664 665 xemaclite_rx_handler(dev); 666 667 /* Check if the Transmission for the first buffer is completed */ 668 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET); 669 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 670 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 671 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 672 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET); 673 674 tx_complete = true; 675 } 676 677 /* Check if the Transmission for the second buffer is completed */ 678 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 679 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 680 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 681 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 682 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + 683 XEL_TSR_OFFSET); 684 685 tx_complete = true; 686 } 687 688 /* If there was a Tx interrupt, call the Tx Handler */ 689 if (tx_complete != 0) 690 xemaclite_tx_handler(dev); 691 692 return IRQ_HANDLED; 693 } 694 695 /**********************/ 696 /* MDIO Bus functions */ 697 /**********************/ 698 699 /** 700 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use 701 * @lp: Pointer to the Emaclite device private data 702 * 703 * This function waits till the device is ready to accept a new MDIO 704 * request. 705 * 706 * Return: 0 for success or ETIMEDOUT for a timeout 707 */ 708 709 static int xemaclite_mdio_wait(struct net_local *lp) 710 { 711 u32 val; 712 713 /* wait for the MDIO interface to not be busy or timeout 714 * after some time. 715 */ 716 return readx_poll_timeout(xemaclite_readl, 717 lp->base_addr + XEL_MDIOCTRL_OFFSET, 718 val, !(val & XEL_MDIOCTRL_MDIOSTS_MASK), 719 1000, 20000); 720 } 721 722 /** 723 * xemaclite_mdio_read - Read from a given MII management register 724 * @bus: the mii_bus struct 725 * @phy_id: the phy address 726 * @reg: register number to read from 727 * 728 * This function waits till the device is ready to accept a new MDIO 729 * request and then writes the phy address to the MDIO Address register 730 * and reads data from MDIO Read Data register, when its available. 731 * 732 * Return: Value read from the MII management register 733 */ 734 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) 735 { 736 struct net_local *lp = bus->priv; 737 u32 ctrl_reg; 738 u32 rc; 739 740 if (xemaclite_mdio_wait(lp)) 741 return -ETIMEDOUT; 742 743 /* Write the PHY address, register number and set the OP bit in the 744 * MDIO Address register. Set the Status bit in the MDIO Control 745 * register to start a MDIO read transaction. 746 */ 747 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 748 xemaclite_writel(XEL_MDIOADDR_OP_MASK | 749 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 750 lp->base_addr + XEL_MDIOADDR_OFFSET); 751 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 752 lp->base_addr + XEL_MDIOCTRL_OFFSET); 753 754 if (xemaclite_mdio_wait(lp)) 755 return -ETIMEDOUT; 756 757 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET); 758 759 dev_dbg(&lp->ndev->dev, 760 "%s(phy_id=%i, reg=%x) == %x\n", __func__, 761 phy_id, reg, rc); 762 763 return rc; 764 } 765 766 /** 767 * xemaclite_mdio_write - Write to a given MII management register 768 * @bus: the mii_bus struct 769 * @phy_id: the phy address 770 * @reg: register number to write to 771 * @val: value to write to the register number specified by reg 772 * 773 * This function waits till the device is ready to accept a new MDIO 774 * request and then writes the val to the MDIO Write Data register. 775 * 776 * Return: 0 upon success or a negative error upon failure 777 */ 778 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, 779 u16 val) 780 { 781 struct net_local *lp = bus->priv; 782 u32 ctrl_reg; 783 784 dev_dbg(&lp->ndev->dev, 785 "%s(phy_id=%i, reg=%x, val=%x)\n", __func__, 786 phy_id, reg, val); 787 788 if (xemaclite_mdio_wait(lp)) 789 return -ETIMEDOUT; 790 791 /* Write the PHY address, register number and clear the OP bit in the 792 * MDIO Address register and then write the value into the MDIO Write 793 * Data register. Finally, set the Status bit in the MDIO Control 794 * register to start a MDIO write transaction. 795 */ 796 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 797 xemaclite_writel(~XEL_MDIOADDR_OP_MASK & 798 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 799 lp->base_addr + XEL_MDIOADDR_OFFSET); 800 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); 801 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 802 lp->base_addr + XEL_MDIOCTRL_OFFSET); 803 804 return 0; 805 } 806 807 /** 808 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device 809 * @lp: Pointer to the Emaclite device private data 810 * @dev: Pointer to OF device structure 811 * 812 * This function enables MDIO bus in the Emaclite device and registers a 813 * mii_bus. 814 * 815 * Return: 0 upon success or a negative error upon failure 816 */ 817 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev) 818 { 819 struct mii_bus *bus; 820 int rc; 821 struct resource res; 822 struct device_node *np = of_get_parent(lp->phy_node); 823 struct device_node *npp; 824 825 /* Don't register the MDIO bus if the phy_node or its parent node 826 * can't be found. 827 */ 828 if (!np) { 829 dev_err(dev, "Failed to register mdio bus.\n"); 830 return -ENODEV; 831 } 832 npp = of_get_parent(np); 833 834 of_address_to_resource(npp, 0, &res); 835 if (lp->ndev->mem_start != res.start) { 836 struct phy_device *phydev; 837 838 phydev = of_phy_find_device(lp->phy_node); 839 if (!phydev) 840 dev_info(dev, 841 "MDIO of the phy is not registered yet\n"); 842 else 843 put_device(&phydev->mdio.dev); 844 return 0; 845 } 846 847 /* Enable the MDIO bus by asserting the enable bit in MDIO Control 848 * register. 849 */ 850 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK, 851 lp->base_addr + XEL_MDIOCTRL_OFFSET); 852 853 bus = mdiobus_alloc(); 854 if (!bus) { 855 dev_err(dev, "Failed to allocate mdiobus\n"); 856 return -ENOMEM; 857 } 858 859 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 860 (unsigned long long)res.start); 861 bus->priv = lp; 862 bus->name = "Xilinx Emaclite MDIO"; 863 bus->read = xemaclite_mdio_read; 864 bus->write = xemaclite_mdio_write; 865 bus->parent = dev; 866 867 rc = of_mdiobus_register(bus, np); 868 if (rc) { 869 dev_err(dev, "Failed to register mdio bus.\n"); 870 goto err_register; 871 } 872 873 lp->mii_bus = bus; 874 875 return 0; 876 877 err_register: 878 mdiobus_free(bus); 879 return rc; 880 } 881 882 /** 883 * xemaclite_adjust_link - Link state callback for the Emaclite device 884 * @ndev: pointer to net_device struct 885 * 886 * There's nothing in the Emaclite device to be configured when the link 887 * state changes. We just print the status. 888 */ 889 static void xemaclite_adjust_link(struct net_device *ndev) 890 { 891 struct net_local *lp = netdev_priv(ndev); 892 struct phy_device *phy = lp->phy_dev; 893 int link_state; 894 895 /* hash together the state values to decide if something has changed */ 896 link_state = phy->speed | (phy->duplex << 1) | phy->link; 897 898 if (lp->last_link != link_state) { 899 lp->last_link = link_state; 900 phy_print_status(phy); 901 } 902 } 903 904 /** 905 * xemaclite_open - Open the network device 906 * @dev: Pointer to the network device 907 * 908 * This function sets the MAC address, requests an IRQ and enables interrupts 909 * for the Emaclite device and starts the Tx queue. 910 * It also connects to the phy device, if MDIO is included in Emaclite device. 911 * 912 * Return: 0 on success. -ENODEV, if PHY cannot be connected. 913 * Non-zero error value on failure. 914 */ 915 static int xemaclite_open(struct net_device *dev) 916 { 917 struct net_local *lp = netdev_priv(dev); 918 int retval; 919 920 /* Just to be safe, stop the device first */ 921 xemaclite_disable_interrupts(lp); 922 923 if (lp->phy_node) { 924 u32 bmcr; 925 926 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 927 xemaclite_adjust_link, 0, 928 PHY_INTERFACE_MODE_MII); 929 if (!lp->phy_dev) { 930 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n"); 931 return -ENODEV; 932 } 933 934 /* EmacLite doesn't support giga-bit speeds */ 935 phy_set_max_speed(lp->phy_dev, SPEED_100); 936 937 /* Don't advertise 1000BASE-T Full/Half duplex speeds */ 938 phy_write(lp->phy_dev, MII_CTRL1000, 0); 939 940 /* Advertise only 10 and 100mbps full/half duplex speeds */ 941 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | 942 ADVERTISE_CSMA); 943 944 /* Restart auto negotiation */ 945 bmcr = phy_read(lp->phy_dev, MII_BMCR); 946 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 947 phy_write(lp->phy_dev, MII_BMCR, bmcr); 948 949 phy_start(lp->phy_dev); 950 } 951 952 /* Set the MAC address each time opened */ 953 xemaclite_update_address(lp, dev->dev_addr); 954 955 /* Grab the IRQ */ 956 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev); 957 if (retval) { 958 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n", 959 dev->irq); 960 if (lp->phy_dev) 961 phy_disconnect(lp->phy_dev); 962 lp->phy_dev = NULL; 963 964 return retval; 965 } 966 967 /* Enable Interrupts */ 968 xemaclite_enable_interrupts(lp); 969 970 /* We're ready to go */ 971 netif_start_queue(dev); 972 973 return 0; 974 } 975 976 /** 977 * xemaclite_close - Close the network device 978 * @dev: Pointer to the network device 979 * 980 * This function stops the Tx queue, disables interrupts and frees the IRQ for 981 * the Emaclite device. 982 * It also disconnects the phy device associated with the Emaclite device. 983 * 984 * Return: 0, always. 985 */ 986 static int xemaclite_close(struct net_device *dev) 987 { 988 struct net_local *lp = netdev_priv(dev); 989 990 netif_stop_queue(dev); 991 xemaclite_disable_interrupts(lp); 992 free_irq(dev->irq, dev); 993 994 if (lp->phy_dev) 995 phy_disconnect(lp->phy_dev); 996 lp->phy_dev = NULL; 997 998 return 0; 999 } 1000 1001 /** 1002 * xemaclite_send - Transmit a frame 1003 * @orig_skb: Pointer to the socket buffer to be transmitted 1004 * @dev: Pointer to the network device 1005 * 1006 * This function checks if the Tx buffer of the Emaclite device is free to send 1007 * data. If so, it fills the Tx buffer with data from socket buffer data, 1008 * updates the stats and frees the socket buffer. The Tx completion is signaled 1009 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is 1010 * deferred and the Tx queue is stopped so that the deferred socket buffer can 1011 * be transmitted when the Emaclite device is free to transmit data. 1012 * 1013 * Return: NETDEV_TX_OK, always. 1014 */ 1015 static netdev_tx_t 1016 xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev) 1017 { 1018 struct net_local *lp = netdev_priv(dev); 1019 struct sk_buff *new_skb; 1020 unsigned int len; 1021 unsigned long flags; 1022 1023 len = orig_skb->len; 1024 1025 new_skb = orig_skb; 1026 1027 spin_lock_irqsave(&lp->reset_lock, flags); 1028 if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) { 1029 /* If the Emaclite Tx buffer is busy, stop the Tx queue and 1030 * defer the skb for transmission during the ISR, after the 1031 * current transmission is complete 1032 */ 1033 netif_stop_queue(dev); 1034 lp->deferred_skb = new_skb; 1035 /* Take the time stamp now, since we can't do this in an ISR. */ 1036 skb_tx_timestamp(new_skb); 1037 spin_unlock_irqrestore(&lp->reset_lock, flags); 1038 return NETDEV_TX_OK; 1039 } 1040 spin_unlock_irqrestore(&lp->reset_lock, flags); 1041 1042 skb_tx_timestamp(new_skb); 1043 1044 dev->stats.tx_bytes += len; 1045 dev_consume_skb_any(new_skb); 1046 1047 return NETDEV_TX_OK; 1048 } 1049 1050 /** 1051 * get_bool - Get a parameter from the OF device 1052 * @ofdev: Pointer to OF device structure 1053 * @s: Property to be retrieved 1054 * 1055 * This function looks for a property in the device node and returns the value 1056 * of the property if its found or 0 if the property is not found. 1057 * 1058 * Return: Value of the parameter if the parameter is found, or 0 otherwise 1059 */ 1060 static bool get_bool(struct platform_device *ofdev, const char *s) 1061 { 1062 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL); 1063 1064 if (!p) { 1065 dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s); 1066 return false; 1067 } 1068 1069 return (bool)*p; 1070 } 1071 1072 /** 1073 * xemaclite_ethtools_get_drvinfo - Get various Axi Emac Lite driver info 1074 * @ndev: Pointer to net_device structure 1075 * @ed: Pointer to ethtool_drvinfo structure 1076 * 1077 * This implements ethtool command for getting the driver information. 1078 * Issue "ethtool -i ethX" under linux prompt to execute this function. 1079 */ 1080 static void xemaclite_ethtools_get_drvinfo(struct net_device *ndev, 1081 struct ethtool_drvinfo *ed) 1082 { 1083 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); 1084 } 1085 1086 static const struct ethtool_ops xemaclite_ethtool_ops = { 1087 .get_drvinfo = xemaclite_ethtools_get_drvinfo, 1088 .get_link = ethtool_op_get_link, 1089 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1090 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1091 }; 1092 1093 static const struct net_device_ops xemaclite_netdev_ops; 1094 1095 /** 1096 * xemaclite_of_probe - Probe method for the Emaclite device. 1097 * @ofdev: Pointer to OF device structure 1098 * 1099 * This function probes for the Emaclite device in the device tree. 1100 * It initializes the driver data structure and the hardware, sets the MAC 1101 * address and registers the network device. 1102 * It also registers a mii_bus for the Emaclite device, if MDIO is included 1103 * in the device. 1104 * 1105 * Return: 0, if the driver is bound to the Emaclite device, or 1106 * a negative error if there is failure. 1107 */ 1108 static int xemaclite_of_probe(struct platform_device *ofdev) 1109 { 1110 struct resource *res; 1111 struct net_device *ndev = NULL; 1112 struct net_local *lp = NULL; 1113 struct device *dev = &ofdev->dev; 1114 1115 int rc = 0; 1116 1117 dev_info(dev, "Device Tree Probing\n"); 1118 1119 /* Create an ethernet device instance */ 1120 ndev = alloc_etherdev(sizeof(struct net_local)); 1121 if (!ndev) 1122 return -ENOMEM; 1123 1124 dev_set_drvdata(dev, ndev); 1125 SET_NETDEV_DEV(ndev, &ofdev->dev); 1126 1127 lp = netdev_priv(ndev); 1128 lp->ndev = ndev; 1129 1130 /* Get IRQ for the device */ 1131 rc = platform_get_irq(ofdev, 0); 1132 if (rc < 0) 1133 goto error; 1134 1135 ndev->irq = rc; 1136 1137 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); 1138 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); 1139 if (IS_ERR(lp->base_addr)) { 1140 rc = PTR_ERR(lp->base_addr); 1141 goto error; 1142 } 1143 1144 ndev->mem_start = res->start; 1145 ndev->mem_end = res->end; 1146 1147 spin_lock_init(&lp->reset_lock); 1148 lp->next_tx_buf_to_use = 0x0; 1149 lp->next_rx_buf_to_use = 0x0; 1150 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); 1151 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); 1152 1153 rc = of_get_ethdev_address(ofdev->dev.of_node, ndev); 1154 if (rc) { 1155 dev_warn(dev, "No MAC address found, using random\n"); 1156 eth_hw_addr_random(ndev); 1157 } 1158 1159 /* Clear the Tx CSR's in case this is a restart */ 1160 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET); 1161 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 1162 1163 /* Set the MAC address in the EmacLite device */ 1164 xemaclite_update_address(lp, ndev->dev_addr); 1165 1166 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0); 1167 xemaclite_mdio_setup(lp, &ofdev->dev); 1168 1169 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr); 1170 1171 ndev->netdev_ops = &xemaclite_netdev_ops; 1172 ndev->ethtool_ops = &xemaclite_ethtool_ops; 1173 ndev->flags &= ~IFF_MULTICAST; 1174 ndev->watchdog_timeo = TX_TIMEOUT; 1175 1176 /* Finally, register the device */ 1177 rc = register_netdev(ndev); 1178 if (rc) { 1179 dev_err(dev, 1180 "Cannot register network device, aborting\n"); 1181 goto put_node; 1182 } 1183 1184 dev_info(dev, 1185 "Xilinx EmacLite at 0x%08lX mapped to 0x%p, irq=%d\n", 1186 (unsigned long __force)ndev->mem_start, lp->base_addr, ndev->irq); 1187 return 0; 1188 1189 put_node: 1190 of_node_put(lp->phy_node); 1191 error: 1192 free_netdev(ndev); 1193 return rc; 1194 } 1195 1196 /** 1197 * xemaclite_of_remove - Unbind the driver from the Emaclite device. 1198 * @of_dev: Pointer to OF device structure 1199 * 1200 * This function is called if a device is physically removed from the system or 1201 * if the driver module is being unloaded. It frees any resources allocated to 1202 * the device. 1203 * 1204 * Return: 0, always. 1205 */ 1206 static int xemaclite_of_remove(struct platform_device *of_dev) 1207 { 1208 struct net_device *ndev = platform_get_drvdata(of_dev); 1209 1210 struct net_local *lp = netdev_priv(ndev); 1211 1212 /* Un-register the mii_bus, if configured */ 1213 if (lp->mii_bus) { 1214 mdiobus_unregister(lp->mii_bus); 1215 mdiobus_free(lp->mii_bus); 1216 lp->mii_bus = NULL; 1217 } 1218 1219 unregister_netdev(ndev); 1220 1221 of_node_put(lp->phy_node); 1222 lp->phy_node = NULL; 1223 1224 free_netdev(ndev); 1225 1226 return 0; 1227 } 1228 1229 #ifdef CONFIG_NET_POLL_CONTROLLER 1230 static void 1231 xemaclite_poll_controller(struct net_device *ndev) 1232 { 1233 disable_irq(ndev->irq); 1234 xemaclite_interrupt(ndev->irq, ndev); 1235 enable_irq(ndev->irq); 1236 } 1237 #endif 1238 1239 /* Ioctl MII Interface */ 1240 static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1241 { 1242 if (!dev->phydev || !netif_running(dev)) 1243 return -EINVAL; 1244 1245 switch (cmd) { 1246 case SIOCGMIIPHY: 1247 case SIOCGMIIREG: 1248 case SIOCSMIIREG: 1249 return phy_mii_ioctl(dev->phydev, rq, cmd); 1250 default: 1251 return -EOPNOTSUPP; 1252 } 1253 } 1254 1255 static const struct net_device_ops xemaclite_netdev_ops = { 1256 .ndo_open = xemaclite_open, 1257 .ndo_stop = xemaclite_close, 1258 .ndo_start_xmit = xemaclite_send, 1259 .ndo_set_mac_address = xemaclite_set_mac_address, 1260 .ndo_tx_timeout = xemaclite_tx_timeout, 1261 .ndo_eth_ioctl = xemaclite_ioctl, 1262 #ifdef CONFIG_NET_POLL_CONTROLLER 1263 .ndo_poll_controller = xemaclite_poll_controller, 1264 #endif 1265 }; 1266 1267 /* Match table for OF platform binding */ 1268 static const struct of_device_id xemaclite_of_match[] = { 1269 { .compatible = "xlnx,opb-ethernetlite-1.01.a", }, 1270 { .compatible = "xlnx,opb-ethernetlite-1.01.b", }, 1271 { .compatible = "xlnx,xps-ethernetlite-1.00.a", }, 1272 { .compatible = "xlnx,xps-ethernetlite-2.00.a", }, 1273 { .compatible = "xlnx,xps-ethernetlite-2.01.a", }, 1274 { .compatible = "xlnx,xps-ethernetlite-3.00.a", }, 1275 { /* end of list */ }, 1276 }; 1277 MODULE_DEVICE_TABLE(of, xemaclite_of_match); 1278 1279 static struct platform_driver xemaclite_of_driver = { 1280 .driver = { 1281 .name = DRIVER_NAME, 1282 .of_match_table = xemaclite_of_match, 1283 }, 1284 .probe = xemaclite_of_probe, 1285 .remove = xemaclite_of_remove, 1286 }; 1287 1288 module_platform_driver(xemaclite_of_driver); 1289 1290 MODULE_AUTHOR("Xilinx, Inc."); 1291 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver"); 1292 MODULE_LICENSE("GPL"); 1293