1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. 4 * 5 * This is a new flat driver which is based on the original emac_lite 6 * driver from John Williams <john.williams@xilinx.com>. 7 * 8 * 2007 - 2013 (c) Xilinx, Inc. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/uaccess.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/skbuff.h> 16 #include <linux/ethtool.h> 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/of_address.h> 20 #include <linux/of_device.h> 21 #include <linux/of_platform.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/phy.h> 25 #include <linux/interrupt.h> 26 #include <linux/iopoll.h> 27 28 #define DRIVER_NAME "xilinx_emaclite" 29 30 /* Register offsets for the EmacLite Core */ 31 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ 32 #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ 33 #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ 34 #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ 35 #define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ 36 #define XEL_GIER_OFFSET 0x07F8 /* GIE Register */ 37 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 38 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 39 40 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 41 #define XEL_RPLR_OFFSET 0x100C /* Rx packet length */ 42 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 43 44 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */ 45 46 /* MDIO Address Register Bit Masks */ 47 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 48 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 49 #define XEL_MDIOADDR_PHYADR_SHIFT 5 50 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 51 52 /* MDIO Write Data Register Bit Masks */ 53 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 54 55 /* MDIO Read Data Register Bit Masks */ 56 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 57 58 /* MDIO Control Register Bit Masks */ 59 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 60 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 61 62 /* Global Interrupt Enable Register (GIER) Bit Masks */ 63 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ 64 65 /* Transmit Status Register (TSR) Bit Masks */ 66 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ 67 #define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ 68 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ 69 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit 70 * only. This is not documented 71 * in the HW spec 72 */ 73 74 /* Define for programming the MAC address into the EmacLite */ 75 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 76 77 /* Receive Status Register (RSR) */ 78 #define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ 79 #define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ 80 81 /* Transmit Packet Length Register (TPLR) */ 82 #define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ 83 84 /* Receive Packet Length Register (RPLR) */ 85 #define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ 86 87 #define XEL_HEADER_OFFSET 12 /* Offset to length field */ 88 #define XEL_HEADER_SHIFT 16 /* Shift value for length */ 89 90 /* General Ethernet Definitions */ 91 #define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ 92 #define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ 93 94 95 96 #define TX_TIMEOUT (60 * HZ) /* Tx timeout is 60 seconds. */ 97 #define ALIGNMENT 4 98 99 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ 100 #define BUFFER_ALIGN(adr) ((ALIGNMENT - ((uintptr_t)adr)) % ALIGNMENT) 101 102 #ifdef __BIG_ENDIAN 103 #define xemaclite_readl ioread32be 104 #define xemaclite_writel iowrite32be 105 #else 106 #define xemaclite_readl ioread32 107 #define xemaclite_writel iowrite32 108 #endif 109 110 /** 111 * struct net_local - Our private per device data 112 * @ndev: instance of the network device 113 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW 114 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW 115 * @next_tx_buf_to_use: next Tx buffer to write to 116 * @next_rx_buf_to_use: next Rx buffer to read from 117 * @base_addr: base address of the Emaclite device 118 * @reset_lock: lock used for synchronization 119 * @deferred_skb: holds an skb (for transmission at a later time) when the 120 * Tx buffer is not free 121 * @phy_dev: pointer to the PHY device 122 * @phy_node: pointer to the PHY device node 123 * @mii_bus: pointer to the MII bus 124 * @last_link: last link status 125 */ 126 struct net_local { 127 128 struct net_device *ndev; 129 130 bool tx_ping_pong; 131 bool rx_ping_pong; 132 u32 next_tx_buf_to_use; 133 u32 next_rx_buf_to_use; 134 void __iomem *base_addr; 135 136 spinlock_t reset_lock; 137 struct sk_buff *deferred_skb; 138 139 struct phy_device *phy_dev; 140 struct device_node *phy_node; 141 142 struct mii_bus *mii_bus; 143 144 int last_link; 145 }; 146 147 148 /*************************/ 149 /* EmacLite driver calls */ 150 /*************************/ 151 152 /** 153 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device 154 * @drvdata: Pointer to the Emaclite device private data 155 * 156 * This function enables the Tx and Rx interrupts for the Emaclite device along 157 * with the Global Interrupt Enable. 158 */ 159 static void xemaclite_enable_interrupts(struct net_local *drvdata) 160 { 161 u32 reg_data; 162 163 /* Enable the Tx interrupts for the first Buffer */ 164 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 165 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 166 drvdata->base_addr + XEL_TSR_OFFSET); 167 168 /* Enable the Rx interrupts for the first buffer */ 169 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 170 171 /* Enable the Global Interrupt Enable */ 172 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 173 } 174 175 /** 176 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device 177 * @drvdata: Pointer to the Emaclite device private data 178 * 179 * This function disables the Tx and Rx interrupts for the Emaclite device, 180 * along with the Global Interrupt Enable. 181 */ 182 static void xemaclite_disable_interrupts(struct net_local *drvdata) 183 { 184 u32 reg_data; 185 186 /* Disable the Global Interrupt Enable */ 187 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 188 189 /* Disable the Tx interrupts for the first buffer */ 190 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 191 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 192 drvdata->base_addr + XEL_TSR_OFFSET); 193 194 /* Disable the Rx interrupts for the first buffer */ 195 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); 196 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 197 drvdata->base_addr + XEL_RSR_OFFSET); 198 } 199 200 /** 201 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address 202 * @src_ptr: Void pointer to the 16-bit aligned source address 203 * @dest_ptr: Pointer to the 32-bit aligned destination address 204 * @length: Number bytes to write from source to destination 205 * 206 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned 207 * address in the EmacLite device. 208 */ 209 static void xemaclite_aligned_write(const void *src_ptr, u32 *dest_ptr, 210 unsigned length) 211 { 212 const u16 *from_u16_ptr; 213 u32 align_buffer; 214 u32 *to_u32_ptr; 215 u16 *to_u16_ptr; 216 217 to_u32_ptr = dest_ptr; 218 from_u16_ptr = src_ptr; 219 align_buffer = 0; 220 221 for (; length > 3; length -= 4) { 222 to_u16_ptr = (u16 *)&align_buffer; 223 *to_u16_ptr++ = *from_u16_ptr++; 224 *to_u16_ptr++ = *from_u16_ptr++; 225 226 /* This barrier resolves occasional issues seen around 227 * cases where the data is not properly flushed out 228 * from the processor store buffers to the destination 229 * memory locations. 230 */ 231 wmb(); 232 233 /* Output a word */ 234 *to_u32_ptr++ = align_buffer; 235 } 236 if (length) { 237 u8 *from_u8_ptr, *to_u8_ptr; 238 239 /* Set up to output the remaining data */ 240 align_buffer = 0; 241 to_u8_ptr = (u8 *)&align_buffer; 242 from_u8_ptr = (u8 *)from_u16_ptr; 243 244 /* Output the remaining data */ 245 for (; length > 0; length--) 246 *to_u8_ptr++ = *from_u8_ptr++; 247 248 /* This barrier resolves occasional issues seen around 249 * cases where the data is not properly flushed out 250 * from the processor store buffers to the destination 251 * memory locations. 252 */ 253 wmb(); 254 *to_u32_ptr = align_buffer; 255 } 256 } 257 258 /** 259 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer 260 * @src_ptr: Pointer to the 32-bit aligned source address 261 * @dest_ptr: Pointer to the 16-bit aligned destination address 262 * @length: Number bytes to read from source to destination 263 * 264 * This function reads data from a 32-bit aligned address in the EmacLite device 265 * to a 16-bit aligned buffer. 266 */ 267 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr, 268 unsigned length) 269 { 270 u16 *to_u16_ptr, *from_u16_ptr; 271 u32 *from_u32_ptr; 272 u32 align_buffer; 273 274 from_u32_ptr = src_ptr; 275 to_u16_ptr = (u16 *)dest_ptr; 276 277 for (; length > 3; length -= 4) { 278 /* Copy each word into the temporary buffer */ 279 align_buffer = *from_u32_ptr++; 280 from_u16_ptr = (u16 *)&align_buffer; 281 282 /* Read data from source */ 283 *to_u16_ptr++ = *from_u16_ptr++; 284 *to_u16_ptr++ = *from_u16_ptr++; 285 } 286 287 if (length) { 288 u8 *to_u8_ptr, *from_u8_ptr; 289 290 /* Set up to read the remaining data */ 291 to_u8_ptr = (u8 *)to_u16_ptr; 292 align_buffer = *from_u32_ptr++; 293 from_u8_ptr = (u8 *)&align_buffer; 294 295 /* Read the remaining data */ 296 for (; length > 0; length--) 297 *to_u8_ptr = *from_u8_ptr; 298 } 299 } 300 301 /** 302 * xemaclite_send_data - Send an Ethernet frame 303 * @drvdata: Pointer to the Emaclite device private data 304 * @data: Pointer to the data to be sent 305 * @byte_count: Total frame size, including header 306 * 307 * This function checks if the Tx buffer of the Emaclite device is free to send 308 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it 309 * returns an error. 310 * 311 * Return: 0 upon success or -1 if the buffer(s) are full. 312 * 313 * Note: The maximum Tx packet size can not be more than Ethernet header 314 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS. 315 */ 316 static int xemaclite_send_data(struct net_local *drvdata, u8 *data, 317 unsigned int byte_count) 318 { 319 u32 reg_data; 320 void __iomem *addr; 321 322 /* Determine the expected Tx buffer address */ 323 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 324 325 /* If the length is too large, truncate it */ 326 if (byte_count > ETH_FRAME_LEN) 327 byte_count = ETH_FRAME_LEN; 328 329 /* Check if the expected buffer is available */ 330 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 331 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 332 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) { 333 334 /* Switch to next buffer if configured */ 335 if (drvdata->tx_ping_pong != 0) 336 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET; 337 } else if (drvdata->tx_ping_pong != 0) { 338 /* If the expected buffer is full, try the other buffer, 339 * if it is configured in HW 340 */ 341 342 addr = (void __iomem __force *)((uintptr_t __force)addr ^ 343 XEL_BUFFER_OFFSET); 344 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 345 346 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 347 XEL_TSR_XMIT_ACTIVE_MASK)) != 0) 348 return -1; /* Buffers were full, return failure */ 349 } else 350 return -1; /* Buffer was full, return failure */ 351 352 /* Write the frame to the buffer */ 353 xemaclite_aligned_write(data, (u32 __force *)addr, byte_count); 354 355 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK), 356 addr + XEL_TPLR_OFFSET); 357 358 /* Update the Tx Status Register to indicate that there is a 359 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which 360 * is used by the interrupt handler to check whether a frame 361 * has been transmitted 362 */ 363 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 364 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK); 365 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET); 366 367 return 0; 368 } 369 370 /** 371 * xemaclite_recv_data - Receive a frame 372 * @drvdata: Pointer to the Emaclite device private data 373 * @data: Address where the data is to be received 374 * @maxlen: Maximum supported ethernet packet length 375 * 376 * This function is intended to be called from the interrupt context or 377 * with a wrapper which waits for the receive frame to be available. 378 * 379 * Return: Total number of bytes received 380 */ 381 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen) 382 { 383 void __iomem *addr; 384 u16 length, proto_type; 385 u32 reg_data; 386 387 /* Determine the expected buffer address */ 388 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); 389 390 /* Verify which buffer has valid data */ 391 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 392 393 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 394 if (drvdata->rx_ping_pong != 0) 395 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET; 396 } else { 397 /* The instance is out of sync, try other buffer if other 398 * buffer is configured, return 0 otherwise. If the instance is 399 * out of sync, do not update the 'next_rx_buf_to_use' since it 400 * will correct on subsequent calls 401 */ 402 if (drvdata->rx_ping_pong != 0) 403 addr = (void __iomem __force *) 404 ((uintptr_t __force)addr ^ 405 XEL_BUFFER_OFFSET); 406 else 407 return 0; /* No data was available */ 408 409 /* Verify that buffer has valid data */ 410 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 411 if ((reg_data & XEL_RSR_RECV_DONE_MASK) != 412 XEL_RSR_RECV_DONE_MASK) 413 return 0; /* No data was available */ 414 } 415 416 /* Get the protocol type of the ethernet frame that arrived 417 */ 418 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET + 419 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) & 420 XEL_RPLR_LENGTH_MASK); 421 422 /* Check if received ethernet frame is a raw ethernet frame 423 * or an IP packet or an ARP packet 424 */ 425 if (proto_type > ETH_DATA_LEN) { 426 427 if (proto_type == ETH_P_IP) { 428 length = ((ntohl(xemaclite_readl(addr + 429 XEL_HEADER_IP_LENGTH_OFFSET + 430 XEL_RXBUFF_OFFSET)) >> 431 XEL_HEADER_SHIFT) & 432 XEL_RPLR_LENGTH_MASK); 433 length = min_t(u16, length, ETH_DATA_LEN); 434 length += ETH_HLEN + ETH_FCS_LEN; 435 436 } else if (proto_type == ETH_P_ARP) 437 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN; 438 else 439 /* Field contains type other than IP or ARP, use max 440 * frame size and let user parse it 441 */ 442 length = ETH_FRAME_LEN + ETH_FCS_LEN; 443 } else 444 /* Use the length in the frame, plus the header and trailer */ 445 length = proto_type + ETH_HLEN + ETH_FCS_LEN; 446 447 if (WARN_ON(length > maxlen)) 448 length = maxlen; 449 450 /* Read from the EmacLite device */ 451 xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET), 452 data, length); 453 454 /* Acknowledge the frame */ 455 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 456 reg_data &= ~XEL_RSR_RECV_DONE_MASK; 457 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET); 458 459 return length; 460 } 461 462 /** 463 * xemaclite_update_address - Update the MAC address in the device 464 * @drvdata: Pointer to the Emaclite device private data 465 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) 466 * 467 * Tx must be idle and Rx should be idle for deterministic results. 468 * It is recommended that this function should be called after the 469 * initialization and before transmission of any packets from the device. 470 * The MAC address can be programmed using any of the two transmit 471 * buffers (if configured). 472 */ 473 static void xemaclite_update_address(struct net_local *drvdata, 474 const u8 *address_ptr) 475 { 476 void __iomem *addr; 477 u32 reg_data; 478 479 /* Determine the expected Tx buffer address */ 480 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 481 482 xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN); 483 484 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); 485 486 /* Update the MAC address in the EmacLite */ 487 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 488 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); 489 490 /* Wait for EmacLite to finish with the MAC address update */ 491 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) & 492 XEL_TSR_PROG_MAC_ADDR) != 0) 493 ; 494 } 495 496 /** 497 * xemaclite_set_mac_address - Set the MAC address for this device 498 * @dev: Pointer to the network device instance 499 * @address: Void pointer to the sockaddr structure 500 * 501 * This function copies the HW address from the sockaddr structure to the 502 * net_device structure and updates the address in HW. 503 * 504 * Return: Error if the net device is busy or 0 if the addr is set 505 * successfully 506 */ 507 static int xemaclite_set_mac_address(struct net_device *dev, void *address) 508 { 509 struct net_local *lp = netdev_priv(dev); 510 struct sockaddr *addr = address; 511 512 if (netif_running(dev)) 513 return -EBUSY; 514 515 eth_hw_addr_set(dev, addr->sa_data); 516 xemaclite_update_address(lp, dev->dev_addr); 517 return 0; 518 } 519 520 /** 521 * xemaclite_tx_timeout - Callback for Tx Timeout 522 * @dev: Pointer to the network device 523 * @txqueue: Unused 524 * 525 * This function is called when Tx time out occurs for Emaclite device. 526 */ 527 static void xemaclite_tx_timeout(struct net_device *dev, unsigned int txqueue) 528 { 529 struct net_local *lp = netdev_priv(dev); 530 unsigned long flags; 531 532 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n", 533 TX_TIMEOUT * 1000UL / HZ); 534 535 dev->stats.tx_errors++; 536 537 /* Reset the device */ 538 spin_lock_irqsave(&lp->reset_lock, flags); 539 540 /* Shouldn't really be necessary, but shouldn't hurt */ 541 netif_stop_queue(dev); 542 543 xemaclite_disable_interrupts(lp); 544 xemaclite_enable_interrupts(lp); 545 546 if (lp->deferred_skb) { 547 dev_kfree_skb(lp->deferred_skb); 548 lp->deferred_skb = NULL; 549 dev->stats.tx_errors++; 550 } 551 552 /* To exclude tx timeout */ 553 netif_trans_update(dev); /* prevent tx timeout */ 554 555 /* We're all ready to go. Start the queue */ 556 netif_wake_queue(dev); 557 spin_unlock_irqrestore(&lp->reset_lock, flags); 558 } 559 560 /**********************/ 561 /* Interrupt Handlers */ 562 /**********************/ 563 564 /** 565 * xemaclite_tx_handler - Interrupt handler for frames sent 566 * @dev: Pointer to the network device 567 * 568 * This function updates the number of packets transmitted and handles the 569 * deferred skb, if there is one. 570 */ 571 static void xemaclite_tx_handler(struct net_device *dev) 572 { 573 struct net_local *lp = netdev_priv(dev); 574 575 dev->stats.tx_packets++; 576 577 if (!lp->deferred_skb) 578 return; 579 580 if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data, 581 lp->deferred_skb->len)) 582 return; 583 584 dev->stats.tx_bytes += lp->deferred_skb->len; 585 dev_consume_skb_irq(lp->deferred_skb); 586 lp->deferred_skb = NULL; 587 netif_trans_update(dev); /* prevent tx timeout */ 588 netif_wake_queue(dev); 589 } 590 591 /** 592 * xemaclite_rx_handler- Interrupt handler for frames received 593 * @dev: Pointer to the network device 594 * 595 * This function allocates memory for a socket buffer, fills it with data 596 * received and hands it over to the TCP/IP stack. 597 */ 598 static void xemaclite_rx_handler(struct net_device *dev) 599 { 600 struct net_local *lp = netdev_priv(dev); 601 struct sk_buff *skb; 602 unsigned int align; 603 u32 len; 604 605 len = ETH_FRAME_LEN + ETH_FCS_LEN; 606 skb = netdev_alloc_skb(dev, len + ALIGNMENT); 607 if (!skb) { 608 /* Couldn't get memory. */ 609 dev->stats.rx_dropped++; 610 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n"); 611 return; 612 } 613 614 /* A new skb should have the data halfword aligned, but this code is 615 * here just in case that isn't true. Calculate how many 616 * bytes we should reserve to get the data to start on a word 617 * boundary 618 */ 619 align = BUFFER_ALIGN(skb->data); 620 if (align) 621 skb_reserve(skb, align); 622 623 skb_reserve(skb, 2); 624 625 len = xemaclite_recv_data(lp, (u8 *)skb->data, len); 626 627 if (!len) { 628 dev->stats.rx_errors++; 629 dev_kfree_skb_irq(skb); 630 return; 631 } 632 633 skb_put(skb, len); /* Tell the skb how much data we got */ 634 635 skb->protocol = eth_type_trans(skb, dev); 636 skb_checksum_none_assert(skb); 637 638 dev->stats.rx_packets++; 639 dev->stats.rx_bytes += len; 640 641 if (!skb_defer_rx_timestamp(skb)) 642 netif_rx(skb); /* Send the packet upstream */ 643 } 644 645 /** 646 * xemaclite_interrupt - Interrupt handler for this driver 647 * @irq: Irq of the Emaclite device 648 * @dev_id: Void pointer to the network device instance used as callback 649 * reference 650 * 651 * Return: IRQ_HANDLED 652 * 653 * This function handles the Tx and Rx interrupts of the EmacLite device. 654 */ 655 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id) 656 { 657 bool tx_complete = false; 658 struct net_device *dev = dev_id; 659 struct net_local *lp = netdev_priv(dev); 660 void __iomem *base_addr = lp->base_addr; 661 u32 tx_status; 662 663 /* Check if there is Rx Data available */ 664 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) & 665 XEL_RSR_RECV_DONE_MASK) || 666 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) 667 & XEL_RSR_RECV_DONE_MASK)) 668 669 xemaclite_rx_handler(dev); 670 671 /* Check if the Transmission for the first buffer is completed */ 672 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET); 673 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 674 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 675 676 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 677 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET); 678 679 tx_complete = true; 680 } 681 682 /* Check if the Transmission for the second buffer is completed */ 683 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 684 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 685 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 686 687 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 688 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + 689 XEL_TSR_OFFSET); 690 691 tx_complete = true; 692 } 693 694 /* If there was a Tx interrupt, call the Tx Handler */ 695 if (tx_complete != 0) 696 xemaclite_tx_handler(dev); 697 698 return IRQ_HANDLED; 699 } 700 701 /**********************/ 702 /* MDIO Bus functions */ 703 /**********************/ 704 705 /** 706 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use 707 * @lp: Pointer to the Emaclite device private data 708 * 709 * This function waits till the device is ready to accept a new MDIO 710 * request. 711 * 712 * Return: 0 for success or ETIMEDOUT for a timeout 713 */ 714 715 static int xemaclite_mdio_wait(struct net_local *lp) 716 { 717 u32 val; 718 719 /* wait for the MDIO interface to not be busy or timeout 720 * after some time. 721 */ 722 return readx_poll_timeout(xemaclite_readl, 723 lp->base_addr + XEL_MDIOCTRL_OFFSET, 724 val, !(val & XEL_MDIOCTRL_MDIOSTS_MASK), 725 1000, 20000); 726 } 727 728 /** 729 * xemaclite_mdio_read - Read from a given MII management register 730 * @bus: the mii_bus struct 731 * @phy_id: the phy address 732 * @reg: register number to read from 733 * 734 * This function waits till the device is ready to accept a new MDIO 735 * request and then writes the phy address to the MDIO Address register 736 * and reads data from MDIO Read Data register, when its available. 737 * 738 * Return: Value read from the MII management register 739 */ 740 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) 741 { 742 struct net_local *lp = bus->priv; 743 u32 ctrl_reg; 744 u32 rc; 745 746 if (xemaclite_mdio_wait(lp)) 747 return -ETIMEDOUT; 748 749 /* Write the PHY address, register number and set the OP bit in the 750 * MDIO Address register. Set the Status bit in the MDIO Control 751 * register to start a MDIO read transaction. 752 */ 753 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 754 xemaclite_writel(XEL_MDIOADDR_OP_MASK | 755 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 756 lp->base_addr + XEL_MDIOADDR_OFFSET); 757 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 758 lp->base_addr + XEL_MDIOCTRL_OFFSET); 759 760 if (xemaclite_mdio_wait(lp)) 761 return -ETIMEDOUT; 762 763 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET); 764 765 dev_dbg(&lp->ndev->dev, 766 "%s(phy_id=%i, reg=%x) == %x\n", __func__, 767 phy_id, reg, rc); 768 769 return rc; 770 } 771 772 /** 773 * xemaclite_mdio_write - Write to a given MII management register 774 * @bus: the mii_bus struct 775 * @phy_id: the phy address 776 * @reg: register number to write to 777 * @val: value to write to the register number specified by reg 778 * 779 * This function waits till the device is ready to accept a new MDIO 780 * request and then writes the val to the MDIO Write Data register. 781 * 782 * Return: 0 upon success or a negative error upon failure 783 */ 784 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, 785 u16 val) 786 { 787 struct net_local *lp = bus->priv; 788 u32 ctrl_reg; 789 790 dev_dbg(&lp->ndev->dev, 791 "%s(phy_id=%i, reg=%x, val=%x)\n", __func__, 792 phy_id, reg, val); 793 794 if (xemaclite_mdio_wait(lp)) 795 return -ETIMEDOUT; 796 797 /* Write the PHY address, register number and clear the OP bit in the 798 * MDIO Address register and then write the value into the MDIO Write 799 * Data register. Finally, set the Status bit in the MDIO Control 800 * register to start a MDIO write transaction. 801 */ 802 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 803 xemaclite_writel(~XEL_MDIOADDR_OP_MASK & 804 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 805 lp->base_addr + XEL_MDIOADDR_OFFSET); 806 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); 807 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 808 lp->base_addr + XEL_MDIOCTRL_OFFSET); 809 810 return 0; 811 } 812 813 /** 814 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device 815 * @lp: Pointer to the Emaclite device private data 816 * @dev: Pointer to OF device structure 817 * 818 * This function enables MDIO bus in the Emaclite device and registers a 819 * mii_bus. 820 * 821 * Return: 0 upon success or a negative error upon failure 822 */ 823 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev) 824 { 825 struct mii_bus *bus; 826 struct resource res; 827 struct device_node *np = of_get_parent(lp->phy_node); 828 struct device_node *npp; 829 int rc, ret; 830 831 /* Don't register the MDIO bus if the phy_node or its parent node 832 * can't be found. 833 */ 834 if (!np) { 835 dev_err(dev, "Failed to register mdio bus.\n"); 836 return -ENODEV; 837 } 838 npp = of_get_parent(np); 839 ret = of_address_to_resource(npp, 0, &res); 840 of_node_put(npp); 841 if (ret) { 842 dev_err(dev, "%s resource error!\n", 843 dev->of_node->full_name); 844 of_node_put(np); 845 return ret; 846 } 847 if (lp->ndev->mem_start != res.start) { 848 struct phy_device *phydev; 849 phydev = of_phy_find_device(lp->phy_node); 850 if (!phydev) 851 dev_info(dev, 852 "MDIO of the phy is not registered yet\n"); 853 else 854 put_device(&phydev->mdio.dev); 855 of_node_put(np); 856 return 0; 857 } 858 859 /* Enable the MDIO bus by asserting the enable bit in MDIO Control 860 * register. 861 */ 862 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK, 863 lp->base_addr + XEL_MDIOCTRL_OFFSET); 864 865 bus = mdiobus_alloc(); 866 if (!bus) { 867 dev_err(dev, "Failed to allocate mdiobus\n"); 868 of_node_put(np); 869 return -ENOMEM; 870 } 871 872 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 873 (unsigned long long)res.start); 874 bus->priv = lp; 875 bus->name = "Xilinx Emaclite MDIO"; 876 bus->read = xemaclite_mdio_read; 877 bus->write = xemaclite_mdio_write; 878 bus->parent = dev; 879 880 rc = of_mdiobus_register(bus, np); 881 of_node_put(np); 882 if (rc) { 883 dev_err(dev, "Failed to register mdio bus.\n"); 884 goto err_register; 885 } 886 887 lp->mii_bus = bus; 888 889 return 0; 890 891 err_register: 892 mdiobus_free(bus); 893 return rc; 894 } 895 896 /** 897 * xemaclite_adjust_link - Link state callback for the Emaclite device 898 * @ndev: pointer to net_device struct 899 * 900 * There's nothing in the Emaclite device to be configured when the link 901 * state changes. We just print the status. 902 */ 903 static void xemaclite_adjust_link(struct net_device *ndev) 904 { 905 struct net_local *lp = netdev_priv(ndev); 906 struct phy_device *phy = lp->phy_dev; 907 int link_state; 908 909 /* hash together the state values to decide if something has changed */ 910 link_state = phy->speed | (phy->duplex << 1) | phy->link; 911 912 if (lp->last_link != link_state) { 913 lp->last_link = link_state; 914 phy_print_status(phy); 915 } 916 } 917 918 /** 919 * xemaclite_open - Open the network device 920 * @dev: Pointer to the network device 921 * 922 * This function sets the MAC address, requests an IRQ and enables interrupts 923 * for the Emaclite device and starts the Tx queue. 924 * It also connects to the phy device, if MDIO is included in Emaclite device. 925 * 926 * Return: 0 on success. -ENODEV, if PHY cannot be connected. 927 * Non-zero error value on failure. 928 */ 929 static int xemaclite_open(struct net_device *dev) 930 { 931 struct net_local *lp = netdev_priv(dev); 932 int retval; 933 934 /* Just to be safe, stop the device first */ 935 xemaclite_disable_interrupts(lp); 936 937 if (lp->phy_node) { 938 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 939 xemaclite_adjust_link, 0, 940 PHY_INTERFACE_MODE_MII); 941 if (!lp->phy_dev) { 942 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n"); 943 return -ENODEV; 944 } 945 946 /* EmacLite doesn't support giga-bit speeds */ 947 phy_set_max_speed(lp->phy_dev, SPEED_100); 948 phy_start(lp->phy_dev); 949 } 950 951 /* Set the MAC address each time opened */ 952 xemaclite_update_address(lp, dev->dev_addr); 953 954 /* Grab the IRQ */ 955 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev); 956 if (retval) { 957 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n", 958 dev->irq); 959 if (lp->phy_dev) 960 phy_disconnect(lp->phy_dev); 961 lp->phy_dev = NULL; 962 963 return retval; 964 } 965 966 /* Enable Interrupts */ 967 xemaclite_enable_interrupts(lp); 968 969 /* We're ready to go */ 970 netif_start_queue(dev); 971 972 return 0; 973 } 974 975 /** 976 * xemaclite_close - Close the network device 977 * @dev: Pointer to the network device 978 * 979 * This function stops the Tx queue, disables interrupts and frees the IRQ for 980 * the Emaclite device. 981 * It also disconnects the phy device associated with the Emaclite device. 982 * 983 * Return: 0, always. 984 */ 985 static int xemaclite_close(struct net_device *dev) 986 { 987 struct net_local *lp = netdev_priv(dev); 988 989 netif_stop_queue(dev); 990 xemaclite_disable_interrupts(lp); 991 free_irq(dev->irq, dev); 992 993 if (lp->phy_dev) 994 phy_disconnect(lp->phy_dev); 995 lp->phy_dev = NULL; 996 997 return 0; 998 } 999 1000 /** 1001 * xemaclite_send - Transmit a frame 1002 * @orig_skb: Pointer to the socket buffer to be transmitted 1003 * @dev: Pointer to the network device 1004 * 1005 * This function checks if the Tx buffer of the Emaclite device is free to send 1006 * data. If so, it fills the Tx buffer with data from socket buffer data, 1007 * updates the stats and frees the socket buffer. The Tx completion is signaled 1008 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is 1009 * deferred and the Tx queue is stopped so that the deferred socket buffer can 1010 * be transmitted when the Emaclite device is free to transmit data. 1011 * 1012 * Return: NETDEV_TX_OK, always. 1013 */ 1014 static netdev_tx_t 1015 xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev) 1016 { 1017 struct net_local *lp = netdev_priv(dev); 1018 struct sk_buff *new_skb; 1019 unsigned int len; 1020 unsigned long flags; 1021 1022 len = orig_skb->len; 1023 1024 new_skb = orig_skb; 1025 1026 spin_lock_irqsave(&lp->reset_lock, flags); 1027 if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) { 1028 /* If the Emaclite Tx buffer is busy, stop the Tx queue and 1029 * defer the skb for transmission during the ISR, after the 1030 * current transmission is complete 1031 */ 1032 netif_stop_queue(dev); 1033 lp->deferred_skb = new_skb; 1034 /* Take the time stamp now, since we can't do this in an ISR. */ 1035 skb_tx_timestamp(new_skb); 1036 spin_unlock_irqrestore(&lp->reset_lock, flags); 1037 return NETDEV_TX_OK; 1038 } 1039 spin_unlock_irqrestore(&lp->reset_lock, flags); 1040 1041 skb_tx_timestamp(new_skb); 1042 1043 dev->stats.tx_bytes += len; 1044 dev_consume_skb_any(new_skb); 1045 1046 return NETDEV_TX_OK; 1047 } 1048 1049 /** 1050 * get_bool - Get a parameter from the OF device 1051 * @ofdev: Pointer to OF device structure 1052 * @s: Property to be retrieved 1053 * 1054 * This function looks for a property in the device node and returns the value 1055 * of the property if its found or 0 if the property is not found. 1056 * 1057 * Return: Value of the parameter if the parameter is found, or 0 otherwise 1058 */ 1059 static bool get_bool(struct platform_device *ofdev, const char *s) 1060 { 1061 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL); 1062 1063 if (!p) { 1064 dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s); 1065 return false; 1066 } 1067 1068 return (bool)*p; 1069 } 1070 1071 /** 1072 * xemaclite_ethtools_get_drvinfo - Get various Axi Emac Lite driver info 1073 * @ndev: Pointer to net_device structure 1074 * @ed: Pointer to ethtool_drvinfo structure 1075 * 1076 * This implements ethtool command for getting the driver information. 1077 * Issue "ethtool -i ethX" under linux prompt to execute this function. 1078 */ 1079 static void xemaclite_ethtools_get_drvinfo(struct net_device *ndev, 1080 struct ethtool_drvinfo *ed) 1081 { 1082 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); 1083 } 1084 1085 static const struct ethtool_ops xemaclite_ethtool_ops = { 1086 .get_drvinfo = xemaclite_ethtools_get_drvinfo, 1087 .get_link = ethtool_op_get_link, 1088 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1089 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1090 }; 1091 1092 static const struct net_device_ops xemaclite_netdev_ops; 1093 1094 /** 1095 * xemaclite_of_probe - Probe method for the Emaclite device. 1096 * @ofdev: Pointer to OF device structure 1097 * 1098 * This function probes for the Emaclite device in the device tree. 1099 * It initializes the driver data structure and the hardware, sets the MAC 1100 * address and registers the network device. 1101 * It also registers a mii_bus for the Emaclite device, if MDIO is included 1102 * in the device. 1103 * 1104 * Return: 0, if the driver is bound to the Emaclite device, or 1105 * a negative error if there is failure. 1106 */ 1107 static int xemaclite_of_probe(struct platform_device *ofdev) 1108 { 1109 struct resource *res; 1110 struct net_device *ndev = NULL; 1111 struct net_local *lp = NULL; 1112 struct device *dev = &ofdev->dev; 1113 1114 int rc = 0; 1115 1116 dev_info(dev, "Device Tree Probing\n"); 1117 1118 /* Create an ethernet device instance */ 1119 ndev = alloc_etherdev(sizeof(struct net_local)); 1120 if (!ndev) 1121 return -ENOMEM; 1122 1123 dev_set_drvdata(dev, ndev); 1124 SET_NETDEV_DEV(ndev, &ofdev->dev); 1125 1126 lp = netdev_priv(ndev); 1127 lp->ndev = ndev; 1128 1129 /* Get IRQ for the device */ 1130 rc = platform_get_irq(ofdev, 0); 1131 if (rc < 0) 1132 goto error; 1133 1134 ndev->irq = rc; 1135 1136 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); 1137 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); 1138 if (IS_ERR(lp->base_addr)) { 1139 rc = PTR_ERR(lp->base_addr); 1140 goto error; 1141 } 1142 1143 ndev->mem_start = res->start; 1144 ndev->mem_end = res->end; 1145 1146 spin_lock_init(&lp->reset_lock); 1147 lp->next_tx_buf_to_use = 0x0; 1148 lp->next_rx_buf_to_use = 0x0; 1149 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); 1150 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); 1151 1152 rc = of_get_ethdev_address(ofdev->dev.of_node, ndev); 1153 if (rc) { 1154 dev_warn(dev, "No MAC address found, using random\n"); 1155 eth_hw_addr_random(ndev); 1156 } 1157 1158 /* Clear the Tx CSR's in case this is a restart */ 1159 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET); 1160 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 1161 1162 /* Set the MAC address in the EmacLite device */ 1163 xemaclite_update_address(lp, ndev->dev_addr); 1164 1165 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0); 1166 xemaclite_mdio_setup(lp, &ofdev->dev); 1167 1168 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr); 1169 1170 ndev->netdev_ops = &xemaclite_netdev_ops; 1171 ndev->ethtool_ops = &xemaclite_ethtool_ops; 1172 ndev->flags &= ~IFF_MULTICAST; 1173 ndev->watchdog_timeo = TX_TIMEOUT; 1174 1175 /* Finally, register the device */ 1176 rc = register_netdev(ndev); 1177 if (rc) { 1178 dev_err(dev, 1179 "Cannot register network device, aborting\n"); 1180 goto put_node; 1181 } 1182 1183 dev_info(dev, 1184 "Xilinx EmacLite at 0x%08lX mapped to 0x%p, irq=%d\n", 1185 (unsigned long __force)ndev->mem_start, lp->base_addr, ndev->irq); 1186 return 0; 1187 1188 put_node: 1189 of_node_put(lp->phy_node); 1190 error: 1191 free_netdev(ndev); 1192 return rc; 1193 } 1194 1195 /** 1196 * xemaclite_of_remove - Unbind the driver from the Emaclite device. 1197 * @of_dev: Pointer to OF device structure 1198 * 1199 * This function is called if a device is physically removed from the system or 1200 * if the driver module is being unloaded. It frees any resources allocated to 1201 * the device. 1202 * 1203 * Return: 0, always. 1204 */ 1205 static int xemaclite_of_remove(struct platform_device *of_dev) 1206 { 1207 struct net_device *ndev = platform_get_drvdata(of_dev); 1208 1209 struct net_local *lp = netdev_priv(ndev); 1210 1211 /* Un-register the mii_bus, if configured */ 1212 if (lp->mii_bus) { 1213 mdiobus_unregister(lp->mii_bus); 1214 mdiobus_free(lp->mii_bus); 1215 lp->mii_bus = NULL; 1216 } 1217 1218 unregister_netdev(ndev); 1219 1220 of_node_put(lp->phy_node); 1221 lp->phy_node = NULL; 1222 1223 free_netdev(ndev); 1224 1225 return 0; 1226 } 1227 1228 #ifdef CONFIG_NET_POLL_CONTROLLER 1229 static void 1230 xemaclite_poll_controller(struct net_device *ndev) 1231 { 1232 disable_irq(ndev->irq); 1233 xemaclite_interrupt(ndev->irq, ndev); 1234 enable_irq(ndev->irq); 1235 } 1236 #endif 1237 1238 /* Ioctl MII Interface */ 1239 static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1240 { 1241 if (!dev->phydev || !netif_running(dev)) 1242 return -EINVAL; 1243 1244 switch (cmd) { 1245 case SIOCGMIIPHY: 1246 case SIOCGMIIREG: 1247 case SIOCSMIIREG: 1248 return phy_mii_ioctl(dev->phydev, rq, cmd); 1249 default: 1250 return -EOPNOTSUPP; 1251 } 1252 } 1253 1254 static const struct net_device_ops xemaclite_netdev_ops = { 1255 .ndo_open = xemaclite_open, 1256 .ndo_stop = xemaclite_close, 1257 .ndo_start_xmit = xemaclite_send, 1258 .ndo_set_mac_address = xemaclite_set_mac_address, 1259 .ndo_tx_timeout = xemaclite_tx_timeout, 1260 .ndo_eth_ioctl = xemaclite_ioctl, 1261 #ifdef CONFIG_NET_POLL_CONTROLLER 1262 .ndo_poll_controller = xemaclite_poll_controller, 1263 #endif 1264 }; 1265 1266 /* Match table for OF platform binding */ 1267 static const struct of_device_id xemaclite_of_match[] = { 1268 { .compatible = "xlnx,opb-ethernetlite-1.01.a", }, 1269 { .compatible = "xlnx,opb-ethernetlite-1.01.b", }, 1270 { .compatible = "xlnx,xps-ethernetlite-1.00.a", }, 1271 { .compatible = "xlnx,xps-ethernetlite-2.00.a", }, 1272 { .compatible = "xlnx,xps-ethernetlite-2.01.a", }, 1273 { .compatible = "xlnx,xps-ethernetlite-3.00.a", }, 1274 { /* end of list */ }, 1275 }; 1276 MODULE_DEVICE_TABLE(of, xemaclite_of_match); 1277 1278 static struct platform_driver xemaclite_of_driver = { 1279 .driver = { 1280 .name = DRIVER_NAME, 1281 .of_match_table = xemaclite_of_match, 1282 }, 1283 .probe = xemaclite_of_probe, 1284 .remove = xemaclite_of_remove, 1285 }; 1286 1287 module_platform_driver(xemaclite_of_driver); 1288 1289 MODULE_AUTHOR("Xilinx, Inc."); 1290 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver"); 1291 MODULE_LICENSE("GPL"); 1292