1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. 4 * 5 * This is a new flat driver which is based on the original emac_lite 6 * driver from John Williams <john.williams@xilinx.com>. 7 * 8 * 2007 - 2013 (c) Xilinx, Inc. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/uaccess.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/skbuff.h> 16 #include <linux/ethtool.h> 17 #include <linux/io.h> 18 #include <linux/slab.h> 19 #include <linux/of_address.h> 20 #include <linux/of_device.h> 21 #include <linux/of_platform.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/phy.h> 25 #include <linux/interrupt.h> 26 #include <linux/iopoll.h> 27 28 #define DRIVER_NAME "xilinx_emaclite" 29 30 /* Register offsets for the EmacLite Core */ 31 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ 32 #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ 33 #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ 34 #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ 35 #define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ 36 #define XEL_GIER_OFFSET 0x07F8 /* GIE Register */ 37 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 38 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 39 40 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 41 #define XEL_RPLR_OFFSET 0x100C /* Rx packet length */ 42 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 43 44 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */ 45 46 /* MDIO Address Register Bit Masks */ 47 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 48 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 49 #define XEL_MDIOADDR_PHYADR_SHIFT 5 50 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 51 52 /* MDIO Write Data Register Bit Masks */ 53 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 54 55 /* MDIO Read Data Register Bit Masks */ 56 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 57 58 /* MDIO Control Register Bit Masks */ 59 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 60 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 61 62 /* Global Interrupt Enable Register (GIER) Bit Masks */ 63 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ 64 65 /* Transmit Status Register (TSR) Bit Masks */ 66 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ 67 #define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ 68 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ 69 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit 70 * only. This is not documented 71 * in the HW spec 72 */ 73 74 /* Define for programming the MAC address into the EmacLite */ 75 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 76 77 /* Receive Status Register (RSR) */ 78 #define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ 79 #define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ 80 81 /* Transmit Packet Length Register (TPLR) */ 82 #define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ 83 84 /* Receive Packet Length Register (RPLR) */ 85 #define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ 86 87 #define XEL_HEADER_OFFSET 12 /* Offset to length field */ 88 #define XEL_HEADER_SHIFT 16 /* Shift value for length */ 89 90 /* General Ethernet Definitions */ 91 #define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ 92 #define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ 93 94 95 96 #define TX_TIMEOUT (60 * HZ) /* Tx timeout is 60 seconds. */ 97 #define ALIGNMENT 4 98 99 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ 100 #define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32)adr)) % ALIGNMENT) 101 102 #ifdef __BIG_ENDIAN 103 #define xemaclite_readl ioread32be 104 #define xemaclite_writel iowrite32be 105 #else 106 #define xemaclite_readl ioread32 107 #define xemaclite_writel iowrite32 108 #endif 109 110 /** 111 * struct net_local - Our private per device data 112 * @ndev: instance of the network device 113 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW 114 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW 115 * @next_tx_buf_to_use: next Tx buffer to write to 116 * @next_rx_buf_to_use: next Rx buffer to read from 117 * @base_addr: base address of the Emaclite device 118 * @reset_lock: lock used for synchronization 119 * @deferred_skb: holds an skb (for transmission at a later time) when the 120 * Tx buffer is not free 121 * @phy_dev: pointer to the PHY device 122 * @phy_node: pointer to the PHY device node 123 * @mii_bus: pointer to the MII bus 124 * @last_link: last link status 125 */ 126 struct net_local { 127 128 struct net_device *ndev; 129 130 bool tx_ping_pong; 131 bool rx_ping_pong; 132 u32 next_tx_buf_to_use; 133 u32 next_rx_buf_to_use; 134 void __iomem *base_addr; 135 136 spinlock_t reset_lock; 137 struct sk_buff *deferred_skb; 138 139 struct phy_device *phy_dev; 140 struct device_node *phy_node; 141 142 struct mii_bus *mii_bus; 143 144 int last_link; 145 }; 146 147 148 /*************************/ 149 /* EmacLite driver calls */ 150 /*************************/ 151 152 /** 153 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device 154 * @drvdata: Pointer to the Emaclite device private data 155 * 156 * This function enables the Tx and Rx interrupts for the Emaclite device along 157 * with the Global Interrupt Enable. 158 */ 159 static void xemaclite_enable_interrupts(struct net_local *drvdata) 160 { 161 u32 reg_data; 162 163 /* Enable the Tx interrupts for the first Buffer */ 164 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 165 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 166 drvdata->base_addr + XEL_TSR_OFFSET); 167 168 /* Enable the Rx interrupts for the first buffer */ 169 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 170 171 /* Enable the Global Interrupt Enable */ 172 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 173 } 174 175 /** 176 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device 177 * @drvdata: Pointer to the Emaclite device private data 178 * 179 * This function disables the Tx and Rx interrupts for the Emaclite device, 180 * along with the Global Interrupt Enable. 181 */ 182 static void xemaclite_disable_interrupts(struct net_local *drvdata) 183 { 184 u32 reg_data; 185 186 /* Disable the Global Interrupt Enable */ 187 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 188 189 /* Disable the Tx interrupts for the first buffer */ 190 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 191 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 192 drvdata->base_addr + XEL_TSR_OFFSET); 193 194 /* Disable the Rx interrupts for the first buffer */ 195 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); 196 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 197 drvdata->base_addr + XEL_RSR_OFFSET); 198 } 199 200 /** 201 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address 202 * @src_ptr: Void pointer to the 16-bit aligned source address 203 * @dest_ptr: Pointer to the 32-bit aligned destination address 204 * @length: Number bytes to write from source to destination 205 * 206 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned 207 * address in the EmacLite device. 208 */ 209 static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr, 210 unsigned length) 211 { 212 u32 align_buffer; 213 u32 *to_u32_ptr; 214 u16 *from_u16_ptr, *to_u16_ptr; 215 216 to_u32_ptr = dest_ptr; 217 from_u16_ptr = src_ptr; 218 align_buffer = 0; 219 220 for (; length > 3; length -= 4) { 221 to_u16_ptr = (u16 *)&align_buffer; 222 *to_u16_ptr++ = *from_u16_ptr++; 223 *to_u16_ptr++ = *from_u16_ptr++; 224 225 /* This barrier resolves occasional issues seen around 226 * cases where the data is not properly flushed out 227 * from the processor store buffers to the destination 228 * memory locations. 229 */ 230 wmb(); 231 232 /* Output a word */ 233 *to_u32_ptr++ = align_buffer; 234 } 235 if (length) { 236 u8 *from_u8_ptr, *to_u8_ptr; 237 238 /* Set up to output the remaining data */ 239 align_buffer = 0; 240 to_u8_ptr = (u8 *)&align_buffer; 241 from_u8_ptr = (u8 *)from_u16_ptr; 242 243 /* Output the remaining data */ 244 for (; length > 0; length--) 245 *to_u8_ptr++ = *from_u8_ptr++; 246 247 /* This barrier resolves occasional issues seen around 248 * cases where the data is not properly flushed out 249 * from the processor store buffers to the destination 250 * memory locations. 251 */ 252 wmb(); 253 *to_u32_ptr = align_buffer; 254 } 255 } 256 257 /** 258 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer 259 * @src_ptr: Pointer to the 32-bit aligned source address 260 * @dest_ptr: Pointer to the 16-bit aligned destination address 261 * @length: Number bytes to read from source to destination 262 * 263 * This function reads data from a 32-bit aligned address in the EmacLite device 264 * to a 16-bit aligned buffer. 265 */ 266 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr, 267 unsigned length) 268 { 269 u16 *to_u16_ptr, *from_u16_ptr; 270 u32 *from_u32_ptr; 271 u32 align_buffer; 272 273 from_u32_ptr = src_ptr; 274 to_u16_ptr = (u16 *)dest_ptr; 275 276 for (; length > 3; length -= 4) { 277 /* Copy each word into the temporary buffer */ 278 align_buffer = *from_u32_ptr++; 279 from_u16_ptr = (u16 *)&align_buffer; 280 281 /* Read data from source */ 282 *to_u16_ptr++ = *from_u16_ptr++; 283 *to_u16_ptr++ = *from_u16_ptr++; 284 } 285 286 if (length) { 287 u8 *to_u8_ptr, *from_u8_ptr; 288 289 /* Set up to read the remaining data */ 290 to_u8_ptr = (u8 *)to_u16_ptr; 291 align_buffer = *from_u32_ptr++; 292 from_u8_ptr = (u8 *)&align_buffer; 293 294 /* Read the remaining data */ 295 for (; length > 0; length--) 296 *to_u8_ptr = *from_u8_ptr; 297 } 298 } 299 300 /** 301 * xemaclite_send_data - Send an Ethernet frame 302 * @drvdata: Pointer to the Emaclite device private data 303 * @data: Pointer to the data to be sent 304 * @byte_count: Total frame size, including header 305 * 306 * This function checks if the Tx buffer of the Emaclite device is free to send 307 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it 308 * returns an error. 309 * 310 * Return: 0 upon success or -1 if the buffer(s) are full. 311 * 312 * Note: The maximum Tx packet size can not be more than Ethernet header 313 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS. 314 */ 315 static int xemaclite_send_data(struct net_local *drvdata, u8 *data, 316 unsigned int byte_count) 317 { 318 u32 reg_data; 319 void __iomem *addr; 320 321 /* Determine the expected Tx buffer address */ 322 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 323 324 /* If the length is too large, truncate it */ 325 if (byte_count > ETH_FRAME_LEN) 326 byte_count = ETH_FRAME_LEN; 327 328 /* Check if the expected buffer is available */ 329 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 330 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 331 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) { 332 333 /* Switch to next buffer if configured */ 334 if (drvdata->tx_ping_pong != 0) 335 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET; 336 } else if (drvdata->tx_ping_pong != 0) { 337 /* If the expected buffer is full, try the other buffer, 338 * if it is configured in HW 339 */ 340 341 addr = (void __iomem __force *)((u32 __force)addr ^ 342 XEL_BUFFER_OFFSET); 343 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 344 345 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 346 XEL_TSR_XMIT_ACTIVE_MASK)) != 0) 347 return -1; /* Buffers were full, return failure */ 348 } else 349 return -1; /* Buffer was full, return failure */ 350 351 /* Write the frame to the buffer */ 352 xemaclite_aligned_write(data, (u32 __force *)addr, byte_count); 353 354 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK), 355 addr + XEL_TPLR_OFFSET); 356 357 /* Update the Tx Status Register to indicate that there is a 358 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which 359 * is used by the interrupt handler to check whether a frame 360 * has been transmitted 361 */ 362 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 363 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK); 364 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET); 365 366 return 0; 367 } 368 369 /** 370 * xemaclite_recv_data - Receive a frame 371 * @drvdata: Pointer to the Emaclite device private data 372 * @data: Address where the data is to be received 373 * @maxlen: Maximum supported ethernet packet length 374 * 375 * This function is intended to be called from the interrupt context or 376 * with a wrapper which waits for the receive frame to be available. 377 * 378 * Return: Total number of bytes received 379 */ 380 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen) 381 { 382 void __iomem *addr; 383 u16 length, proto_type; 384 u32 reg_data; 385 386 /* Determine the expected buffer address */ 387 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); 388 389 /* Verify which buffer has valid data */ 390 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 391 392 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 393 if (drvdata->rx_ping_pong != 0) 394 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET; 395 } else { 396 /* The instance is out of sync, try other buffer if other 397 * buffer is configured, return 0 otherwise. If the instance is 398 * out of sync, do not update the 'next_rx_buf_to_use' since it 399 * will correct on subsequent calls 400 */ 401 if (drvdata->rx_ping_pong != 0) 402 addr = (void __iomem __force *)((u32 __force)addr ^ 403 XEL_BUFFER_OFFSET); 404 else 405 return 0; /* No data was available */ 406 407 /* Verify that buffer has valid data */ 408 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 409 if ((reg_data & XEL_RSR_RECV_DONE_MASK) != 410 XEL_RSR_RECV_DONE_MASK) 411 return 0; /* No data was available */ 412 } 413 414 /* Get the protocol type of the ethernet frame that arrived 415 */ 416 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET + 417 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) & 418 XEL_RPLR_LENGTH_MASK); 419 420 /* Check if received ethernet frame is a raw ethernet frame 421 * or an IP packet or an ARP packet 422 */ 423 if (proto_type > ETH_DATA_LEN) { 424 425 if (proto_type == ETH_P_IP) { 426 length = ((ntohl(xemaclite_readl(addr + 427 XEL_HEADER_IP_LENGTH_OFFSET + 428 XEL_RXBUFF_OFFSET)) >> 429 XEL_HEADER_SHIFT) & 430 XEL_RPLR_LENGTH_MASK); 431 length = min_t(u16, length, ETH_DATA_LEN); 432 length += ETH_HLEN + ETH_FCS_LEN; 433 434 } else if (proto_type == ETH_P_ARP) 435 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN; 436 else 437 /* Field contains type other than IP or ARP, use max 438 * frame size and let user parse it 439 */ 440 length = ETH_FRAME_LEN + ETH_FCS_LEN; 441 } else 442 /* Use the length in the frame, plus the header and trailer */ 443 length = proto_type + ETH_HLEN + ETH_FCS_LEN; 444 445 if (WARN_ON(length > maxlen)) 446 length = maxlen; 447 448 /* Read from the EmacLite device */ 449 xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET), 450 data, length); 451 452 /* Acknowledge the frame */ 453 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 454 reg_data &= ~XEL_RSR_RECV_DONE_MASK; 455 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET); 456 457 return length; 458 } 459 460 /** 461 * xemaclite_update_address - Update the MAC address in the device 462 * @drvdata: Pointer to the Emaclite device private data 463 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) 464 * 465 * Tx must be idle and Rx should be idle for deterministic results. 466 * It is recommended that this function should be called after the 467 * initialization and before transmission of any packets from the device. 468 * The MAC address can be programmed using any of the two transmit 469 * buffers (if configured). 470 */ 471 static void xemaclite_update_address(struct net_local *drvdata, 472 u8 *address_ptr) 473 { 474 void __iomem *addr; 475 u32 reg_data; 476 477 /* Determine the expected Tx buffer address */ 478 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 479 480 xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN); 481 482 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); 483 484 /* Update the MAC address in the EmacLite */ 485 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 486 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); 487 488 /* Wait for EmacLite to finish with the MAC address update */ 489 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) & 490 XEL_TSR_PROG_MAC_ADDR) != 0) 491 ; 492 } 493 494 /** 495 * xemaclite_set_mac_address - Set the MAC address for this device 496 * @dev: Pointer to the network device instance 497 * @address: Void pointer to the sockaddr structure 498 * 499 * This function copies the HW address from the sockaddr strucutre to the 500 * net_device structure and updates the address in HW. 501 * 502 * Return: Error if the net device is busy or 0 if the addr is set 503 * successfully 504 */ 505 static int xemaclite_set_mac_address(struct net_device *dev, void *address) 506 { 507 struct net_local *lp = netdev_priv(dev); 508 struct sockaddr *addr = address; 509 510 if (netif_running(dev)) 511 return -EBUSY; 512 513 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 514 xemaclite_update_address(lp, dev->dev_addr); 515 return 0; 516 } 517 518 /** 519 * xemaclite_tx_timeout - Callback for Tx Timeout 520 * @dev: Pointer to the network device 521 * 522 * This function is called when Tx time out occurs for Emaclite device. 523 */ 524 static void xemaclite_tx_timeout(struct net_device *dev, unsigned int txqueue) 525 { 526 struct net_local *lp = netdev_priv(dev); 527 unsigned long flags; 528 529 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n", 530 TX_TIMEOUT * 1000UL / HZ); 531 532 dev->stats.tx_errors++; 533 534 /* Reset the device */ 535 spin_lock_irqsave(&lp->reset_lock, flags); 536 537 /* Shouldn't really be necessary, but shouldn't hurt */ 538 netif_stop_queue(dev); 539 540 xemaclite_disable_interrupts(lp); 541 xemaclite_enable_interrupts(lp); 542 543 if (lp->deferred_skb) { 544 dev_kfree_skb(lp->deferred_skb); 545 lp->deferred_skb = NULL; 546 dev->stats.tx_errors++; 547 } 548 549 /* To exclude tx timeout */ 550 netif_trans_update(dev); /* prevent tx timeout */ 551 552 /* We're all ready to go. Start the queue */ 553 netif_wake_queue(dev); 554 spin_unlock_irqrestore(&lp->reset_lock, flags); 555 } 556 557 /**********************/ 558 /* Interrupt Handlers */ 559 /**********************/ 560 561 /** 562 * xemaclite_tx_handler - Interrupt handler for frames sent 563 * @dev: Pointer to the network device 564 * 565 * This function updates the number of packets transmitted and handles the 566 * deferred skb, if there is one. 567 */ 568 static void xemaclite_tx_handler(struct net_device *dev) 569 { 570 struct net_local *lp = netdev_priv(dev); 571 572 dev->stats.tx_packets++; 573 574 if (!lp->deferred_skb) 575 return; 576 577 if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data, 578 lp->deferred_skb->len)) 579 return; 580 581 dev->stats.tx_bytes += lp->deferred_skb->len; 582 dev_consume_skb_irq(lp->deferred_skb); 583 lp->deferred_skb = NULL; 584 netif_trans_update(dev); /* prevent tx timeout */ 585 netif_wake_queue(dev); 586 } 587 588 /** 589 * xemaclite_rx_handler- Interrupt handler for frames received 590 * @dev: Pointer to the network device 591 * 592 * This function allocates memory for a socket buffer, fills it with data 593 * received and hands it over to the TCP/IP stack. 594 */ 595 static void xemaclite_rx_handler(struct net_device *dev) 596 { 597 struct net_local *lp = netdev_priv(dev); 598 struct sk_buff *skb; 599 unsigned int align; 600 u32 len; 601 602 len = ETH_FRAME_LEN + ETH_FCS_LEN; 603 skb = netdev_alloc_skb(dev, len + ALIGNMENT); 604 if (!skb) { 605 /* Couldn't get memory. */ 606 dev->stats.rx_dropped++; 607 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n"); 608 return; 609 } 610 611 /* A new skb should have the data halfword aligned, but this code is 612 * here just in case that isn't true. Calculate how many 613 * bytes we should reserve to get the data to start on a word 614 * boundary 615 */ 616 align = BUFFER_ALIGN(skb->data); 617 if (align) 618 skb_reserve(skb, align); 619 620 skb_reserve(skb, 2); 621 622 len = xemaclite_recv_data(lp, (u8 *)skb->data, len); 623 624 if (!len) { 625 dev->stats.rx_errors++; 626 dev_kfree_skb_irq(skb); 627 return; 628 } 629 630 skb_put(skb, len); /* Tell the skb how much data we got */ 631 632 skb->protocol = eth_type_trans(skb, dev); 633 skb_checksum_none_assert(skb); 634 635 dev->stats.rx_packets++; 636 dev->stats.rx_bytes += len; 637 638 if (!skb_defer_rx_timestamp(skb)) 639 netif_rx(skb); /* Send the packet upstream */ 640 } 641 642 /** 643 * xemaclite_interrupt - Interrupt handler for this driver 644 * @irq: Irq of the Emaclite device 645 * @dev_id: Void pointer to the network device instance used as callback 646 * reference 647 * 648 * Return: IRQ_HANDLED 649 * 650 * This function handles the Tx and Rx interrupts of the EmacLite device. 651 */ 652 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id) 653 { 654 bool tx_complete = false; 655 struct net_device *dev = dev_id; 656 struct net_local *lp = netdev_priv(dev); 657 void __iomem *base_addr = lp->base_addr; 658 u32 tx_status; 659 660 /* Check if there is Rx Data available */ 661 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) & 662 XEL_RSR_RECV_DONE_MASK) || 663 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) 664 & XEL_RSR_RECV_DONE_MASK)) 665 666 xemaclite_rx_handler(dev); 667 668 /* Check if the Transmission for the first buffer is completed */ 669 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET); 670 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 671 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 672 673 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 674 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET); 675 676 tx_complete = true; 677 } 678 679 /* Check if the Transmission for the second buffer is completed */ 680 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 681 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 682 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 683 684 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 685 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + 686 XEL_TSR_OFFSET); 687 688 tx_complete = true; 689 } 690 691 /* If there was a Tx interrupt, call the Tx Handler */ 692 if (tx_complete != 0) 693 xemaclite_tx_handler(dev); 694 695 return IRQ_HANDLED; 696 } 697 698 /**********************/ 699 /* MDIO Bus functions */ 700 /**********************/ 701 702 /** 703 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use 704 * @lp: Pointer to the Emaclite device private data 705 * 706 * This function waits till the device is ready to accept a new MDIO 707 * request. 708 * 709 * Return: 0 for success or ETIMEDOUT for a timeout 710 */ 711 712 static int xemaclite_mdio_wait(struct net_local *lp) 713 { 714 u32 val; 715 716 /* wait for the MDIO interface to not be busy or timeout 717 * after some time. 718 */ 719 return readx_poll_timeout(xemaclite_readl, 720 lp->base_addr + XEL_MDIOCTRL_OFFSET, 721 val, !(val & XEL_MDIOCTRL_MDIOSTS_MASK), 722 1000, 20000); 723 } 724 725 /** 726 * xemaclite_mdio_read - Read from a given MII management register 727 * @bus: the mii_bus struct 728 * @phy_id: the phy address 729 * @reg: register number to read from 730 * 731 * This function waits till the device is ready to accept a new MDIO 732 * request and then writes the phy address to the MDIO Address register 733 * and reads data from MDIO Read Data register, when its available. 734 * 735 * Return: Value read from the MII management register 736 */ 737 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) 738 { 739 struct net_local *lp = bus->priv; 740 u32 ctrl_reg; 741 u32 rc; 742 743 if (xemaclite_mdio_wait(lp)) 744 return -ETIMEDOUT; 745 746 /* Write the PHY address, register number and set the OP bit in the 747 * MDIO Address register. Set the Status bit in the MDIO Control 748 * register to start a MDIO read transaction. 749 */ 750 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 751 xemaclite_writel(XEL_MDIOADDR_OP_MASK | 752 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 753 lp->base_addr + XEL_MDIOADDR_OFFSET); 754 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 755 lp->base_addr + XEL_MDIOCTRL_OFFSET); 756 757 if (xemaclite_mdio_wait(lp)) 758 return -ETIMEDOUT; 759 760 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET); 761 762 dev_dbg(&lp->ndev->dev, 763 "%s(phy_id=%i, reg=%x) == %x\n", __func__, 764 phy_id, reg, rc); 765 766 return rc; 767 } 768 769 /** 770 * xemaclite_mdio_write - Write to a given MII management register 771 * @bus: the mii_bus struct 772 * @phy_id: the phy address 773 * @reg: register number to write to 774 * @val: value to write to the register number specified by reg 775 * 776 * This function waits till the device is ready to accept a new MDIO 777 * request and then writes the val to the MDIO Write Data register. 778 * 779 * Return: 0 upon success or a negative error upon failure 780 */ 781 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, 782 u16 val) 783 { 784 struct net_local *lp = bus->priv; 785 u32 ctrl_reg; 786 787 dev_dbg(&lp->ndev->dev, 788 "%s(phy_id=%i, reg=%x, val=%x)\n", __func__, 789 phy_id, reg, val); 790 791 if (xemaclite_mdio_wait(lp)) 792 return -ETIMEDOUT; 793 794 /* Write the PHY address, register number and clear the OP bit in the 795 * MDIO Address register and then write the value into the MDIO Write 796 * Data register. Finally, set the Status bit in the MDIO Control 797 * register to start a MDIO write transaction. 798 */ 799 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 800 xemaclite_writel(~XEL_MDIOADDR_OP_MASK & 801 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 802 lp->base_addr + XEL_MDIOADDR_OFFSET); 803 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); 804 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 805 lp->base_addr + XEL_MDIOCTRL_OFFSET); 806 807 return 0; 808 } 809 810 /** 811 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device 812 * @lp: Pointer to the Emaclite device private data 813 * @dev: Pointer to OF device structure 814 * 815 * This function enables MDIO bus in the Emaclite device and registers a 816 * mii_bus. 817 * 818 * Return: 0 upon success or a negative error upon failure 819 */ 820 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev) 821 { 822 struct mii_bus *bus; 823 int rc; 824 struct resource res; 825 struct device_node *np = of_get_parent(lp->phy_node); 826 struct device_node *npp; 827 828 /* Don't register the MDIO bus if the phy_node or its parent node 829 * can't be found. 830 */ 831 if (!np) { 832 dev_err(dev, "Failed to register mdio bus.\n"); 833 return -ENODEV; 834 } 835 npp = of_get_parent(np); 836 837 of_address_to_resource(npp, 0, &res); 838 if (lp->ndev->mem_start != res.start) { 839 struct phy_device *phydev; 840 phydev = of_phy_find_device(lp->phy_node); 841 if (!phydev) 842 dev_info(dev, 843 "MDIO of the phy is not registered yet\n"); 844 else 845 put_device(&phydev->mdio.dev); 846 return 0; 847 } 848 849 /* Enable the MDIO bus by asserting the enable bit in MDIO Control 850 * register. 851 */ 852 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK, 853 lp->base_addr + XEL_MDIOCTRL_OFFSET); 854 855 bus = mdiobus_alloc(); 856 if (!bus) { 857 dev_err(dev, "Failed to allocate mdiobus\n"); 858 return -ENOMEM; 859 } 860 861 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 862 (unsigned long long)res.start); 863 bus->priv = lp; 864 bus->name = "Xilinx Emaclite MDIO"; 865 bus->read = xemaclite_mdio_read; 866 bus->write = xemaclite_mdio_write; 867 bus->parent = dev; 868 869 rc = of_mdiobus_register(bus, np); 870 if (rc) { 871 dev_err(dev, "Failed to register mdio bus.\n"); 872 goto err_register; 873 } 874 875 lp->mii_bus = bus; 876 877 return 0; 878 879 err_register: 880 mdiobus_free(bus); 881 return rc; 882 } 883 884 /** 885 * xemaclite_adjust_link - Link state callback for the Emaclite device 886 * @ndev: pointer to net_device struct 887 * 888 * There's nothing in the Emaclite device to be configured when the link 889 * state changes. We just print the status. 890 */ 891 static void xemaclite_adjust_link(struct net_device *ndev) 892 { 893 struct net_local *lp = netdev_priv(ndev); 894 struct phy_device *phy = lp->phy_dev; 895 int link_state; 896 897 /* hash together the state values to decide if something has changed */ 898 link_state = phy->speed | (phy->duplex << 1) | phy->link; 899 900 if (lp->last_link != link_state) { 901 lp->last_link = link_state; 902 phy_print_status(phy); 903 } 904 } 905 906 /** 907 * xemaclite_open - Open the network device 908 * @dev: Pointer to the network device 909 * 910 * This function sets the MAC address, requests an IRQ and enables interrupts 911 * for the Emaclite device and starts the Tx queue. 912 * It also connects to the phy device, if MDIO is included in Emaclite device. 913 * 914 * Return: 0 on success. -ENODEV, if PHY cannot be connected. 915 * Non-zero error value on failure. 916 */ 917 static int xemaclite_open(struct net_device *dev) 918 { 919 struct net_local *lp = netdev_priv(dev); 920 int retval; 921 922 /* Just to be safe, stop the device first */ 923 xemaclite_disable_interrupts(lp); 924 925 if (lp->phy_node) { 926 u32 bmcr; 927 928 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 929 xemaclite_adjust_link, 0, 930 PHY_INTERFACE_MODE_MII); 931 if (!lp->phy_dev) { 932 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n"); 933 return -ENODEV; 934 } 935 936 /* EmacLite doesn't support giga-bit speeds */ 937 phy_set_max_speed(lp->phy_dev, SPEED_100); 938 939 /* Don't advertise 1000BASE-T Full/Half duplex speeds */ 940 phy_write(lp->phy_dev, MII_CTRL1000, 0); 941 942 /* Advertise only 10 and 100mbps full/half duplex speeds */ 943 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | 944 ADVERTISE_CSMA); 945 946 /* Restart auto negotiation */ 947 bmcr = phy_read(lp->phy_dev, MII_BMCR); 948 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 949 phy_write(lp->phy_dev, MII_BMCR, bmcr); 950 951 phy_start(lp->phy_dev); 952 } 953 954 /* Set the MAC address each time opened */ 955 xemaclite_update_address(lp, dev->dev_addr); 956 957 /* Grab the IRQ */ 958 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev); 959 if (retval) { 960 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n", 961 dev->irq); 962 if (lp->phy_dev) 963 phy_disconnect(lp->phy_dev); 964 lp->phy_dev = NULL; 965 966 return retval; 967 } 968 969 /* Enable Interrupts */ 970 xemaclite_enable_interrupts(lp); 971 972 /* We're ready to go */ 973 netif_start_queue(dev); 974 975 return 0; 976 } 977 978 /** 979 * xemaclite_close - Close the network device 980 * @dev: Pointer to the network device 981 * 982 * This function stops the Tx queue, disables interrupts and frees the IRQ for 983 * the Emaclite device. 984 * It also disconnects the phy device associated with the Emaclite device. 985 * 986 * Return: 0, always. 987 */ 988 static int xemaclite_close(struct net_device *dev) 989 { 990 struct net_local *lp = netdev_priv(dev); 991 992 netif_stop_queue(dev); 993 xemaclite_disable_interrupts(lp); 994 free_irq(dev->irq, dev); 995 996 if (lp->phy_dev) 997 phy_disconnect(lp->phy_dev); 998 lp->phy_dev = NULL; 999 1000 return 0; 1001 } 1002 1003 /** 1004 * xemaclite_send - Transmit a frame 1005 * @orig_skb: Pointer to the socket buffer to be transmitted 1006 * @dev: Pointer to the network device 1007 * 1008 * This function checks if the Tx buffer of the Emaclite device is free to send 1009 * data. If so, it fills the Tx buffer with data from socket buffer data, 1010 * updates the stats and frees the socket buffer. The Tx completion is signaled 1011 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is 1012 * deferred and the Tx queue is stopped so that the deferred socket buffer can 1013 * be transmitted when the Emaclite device is free to transmit data. 1014 * 1015 * Return: NETDEV_TX_OK, always. 1016 */ 1017 static netdev_tx_t 1018 xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev) 1019 { 1020 struct net_local *lp = netdev_priv(dev); 1021 struct sk_buff *new_skb; 1022 unsigned int len; 1023 unsigned long flags; 1024 1025 len = orig_skb->len; 1026 1027 new_skb = orig_skb; 1028 1029 spin_lock_irqsave(&lp->reset_lock, flags); 1030 if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) { 1031 /* If the Emaclite Tx buffer is busy, stop the Tx queue and 1032 * defer the skb for transmission during the ISR, after the 1033 * current transmission is complete 1034 */ 1035 netif_stop_queue(dev); 1036 lp->deferred_skb = new_skb; 1037 /* Take the time stamp now, since we can't do this in an ISR. */ 1038 skb_tx_timestamp(new_skb); 1039 spin_unlock_irqrestore(&lp->reset_lock, flags); 1040 return NETDEV_TX_OK; 1041 } 1042 spin_unlock_irqrestore(&lp->reset_lock, flags); 1043 1044 skb_tx_timestamp(new_skb); 1045 1046 dev->stats.tx_bytes += len; 1047 dev_consume_skb_any(new_skb); 1048 1049 return NETDEV_TX_OK; 1050 } 1051 1052 /** 1053 * get_bool - Get a parameter from the OF device 1054 * @ofdev: Pointer to OF device structure 1055 * @s: Property to be retrieved 1056 * 1057 * This function looks for a property in the device node and returns the value 1058 * of the property if its found or 0 if the property is not found. 1059 * 1060 * Return: Value of the parameter if the parameter is found, or 0 otherwise 1061 */ 1062 static bool get_bool(struct platform_device *ofdev, const char *s) 1063 { 1064 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL); 1065 1066 if (!p) { 1067 dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s); 1068 return false; 1069 } 1070 1071 return (bool)*p; 1072 } 1073 1074 /** 1075 * xemaclite_ethtools_get_drvinfo - Get various Axi Emac Lite driver info 1076 * @ndev: Pointer to net_device structure 1077 * @ed: Pointer to ethtool_drvinfo structure 1078 * 1079 * This implements ethtool command for getting the driver information. 1080 * Issue "ethtool -i ethX" under linux prompt to execute this function. 1081 */ 1082 static void xemaclite_ethtools_get_drvinfo(struct net_device *ndev, 1083 struct ethtool_drvinfo *ed) 1084 { 1085 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); 1086 } 1087 1088 static const struct ethtool_ops xemaclite_ethtool_ops = { 1089 .get_drvinfo = xemaclite_ethtools_get_drvinfo, 1090 .get_link = ethtool_op_get_link, 1091 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1092 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1093 }; 1094 1095 static const struct net_device_ops xemaclite_netdev_ops; 1096 1097 /** 1098 * xemaclite_of_probe - Probe method for the Emaclite device. 1099 * @ofdev: Pointer to OF device structure 1100 * 1101 * This function probes for the Emaclite device in the device tree. 1102 * It initializes the driver data structure and the hardware, sets the MAC 1103 * address and registers the network device. 1104 * It also registers a mii_bus for the Emaclite device, if MDIO is included 1105 * in the device. 1106 * 1107 * Return: 0, if the driver is bound to the Emaclite device, or 1108 * a negative error if there is failure. 1109 */ 1110 static int xemaclite_of_probe(struct platform_device *ofdev) 1111 { 1112 struct resource *res; 1113 struct net_device *ndev = NULL; 1114 struct net_local *lp = NULL; 1115 struct device *dev = &ofdev->dev; 1116 const void *mac_address; 1117 1118 int rc = 0; 1119 1120 dev_info(dev, "Device Tree Probing\n"); 1121 1122 /* Create an ethernet device instance */ 1123 ndev = alloc_etherdev(sizeof(struct net_local)); 1124 if (!ndev) 1125 return -ENOMEM; 1126 1127 dev_set_drvdata(dev, ndev); 1128 SET_NETDEV_DEV(ndev, &ofdev->dev); 1129 1130 lp = netdev_priv(ndev); 1131 lp->ndev = ndev; 1132 1133 /* Get IRQ for the device */ 1134 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0); 1135 if (!res) { 1136 dev_err(dev, "no IRQ found\n"); 1137 rc = -ENXIO; 1138 goto error; 1139 } 1140 1141 ndev->irq = res->start; 1142 1143 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); 1144 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); 1145 if (IS_ERR(lp->base_addr)) { 1146 rc = PTR_ERR(lp->base_addr); 1147 goto error; 1148 } 1149 1150 ndev->mem_start = res->start; 1151 ndev->mem_end = res->end; 1152 1153 spin_lock_init(&lp->reset_lock); 1154 lp->next_tx_buf_to_use = 0x0; 1155 lp->next_rx_buf_to_use = 0x0; 1156 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); 1157 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); 1158 mac_address = of_get_mac_address(ofdev->dev.of_node); 1159 1160 if (!IS_ERR(mac_address)) { 1161 /* Set the MAC address. */ 1162 ether_addr_copy(ndev->dev_addr, mac_address); 1163 } else { 1164 dev_warn(dev, "No MAC address found, using random\n"); 1165 eth_hw_addr_random(ndev); 1166 } 1167 1168 /* Clear the Tx CSR's in case this is a restart */ 1169 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET); 1170 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 1171 1172 /* Set the MAC address in the EmacLite device */ 1173 xemaclite_update_address(lp, ndev->dev_addr); 1174 1175 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0); 1176 xemaclite_mdio_setup(lp, &ofdev->dev); 1177 1178 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr); 1179 1180 ndev->netdev_ops = &xemaclite_netdev_ops; 1181 ndev->ethtool_ops = &xemaclite_ethtool_ops; 1182 ndev->flags &= ~IFF_MULTICAST; 1183 ndev->watchdog_timeo = TX_TIMEOUT; 1184 1185 /* Finally, register the device */ 1186 rc = register_netdev(ndev); 1187 if (rc) { 1188 dev_err(dev, 1189 "Cannot register network device, aborting\n"); 1190 goto error; 1191 } 1192 1193 dev_info(dev, 1194 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n", 1195 (unsigned int __force)ndev->mem_start, 1196 (unsigned int __force)lp->base_addr, ndev->irq); 1197 return 0; 1198 1199 error: 1200 free_netdev(ndev); 1201 return rc; 1202 } 1203 1204 /** 1205 * xemaclite_of_remove - Unbind the driver from the Emaclite device. 1206 * @of_dev: Pointer to OF device structure 1207 * 1208 * This function is called if a device is physically removed from the system or 1209 * if the driver module is being unloaded. It frees any resources allocated to 1210 * the device. 1211 * 1212 * Return: 0, always. 1213 */ 1214 static int xemaclite_of_remove(struct platform_device *of_dev) 1215 { 1216 struct net_device *ndev = platform_get_drvdata(of_dev); 1217 1218 struct net_local *lp = netdev_priv(ndev); 1219 1220 /* Un-register the mii_bus, if configured */ 1221 if (lp->mii_bus) { 1222 mdiobus_unregister(lp->mii_bus); 1223 mdiobus_free(lp->mii_bus); 1224 lp->mii_bus = NULL; 1225 } 1226 1227 unregister_netdev(ndev); 1228 1229 of_node_put(lp->phy_node); 1230 lp->phy_node = NULL; 1231 1232 free_netdev(ndev); 1233 1234 return 0; 1235 } 1236 1237 #ifdef CONFIG_NET_POLL_CONTROLLER 1238 static void 1239 xemaclite_poll_controller(struct net_device *ndev) 1240 { 1241 disable_irq(ndev->irq); 1242 xemaclite_interrupt(ndev->irq, ndev); 1243 enable_irq(ndev->irq); 1244 } 1245 #endif 1246 1247 /* Ioctl MII Interface */ 1248 static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1249 { 1250 if (!dev->phydev || !netif_running(dev)) 1251 return -EINVAL; 1252 1253 switch (cmd) { 1254 case SIOCGMIIPHY: 1255 case SIOCGMIIREG: 1256 case SIOCSMIIREG: 1257 return phy_mii_ioctl(dev->phydev, rq, cmd); 1258 default: 1259 return -EOPNOTSUPP; 1260 } 1261 } 1262 1263 static const struct net_device_ops xemaclite_netdev_ops = { 1264 .ndo_open = xemaclite_open, 1265 .ndo_stop = xemaclite_close, 1266 .ndo_start_xmit = xemaclite_send, 1267 .ndo_set_mac_address = xemaclite_set_mac_address, 1268 .ndo_tx_timeout = xemaclite_tx_timeout, 1269 .ndo_do_ioctl = xemaclite_ioctl, 1270 #ifdef CONFIG_NET_POLL_CONTROLLER 1271 .ndo_poll_controller = xemaclite_poll_controller, 1272 #endif 1273 }; 1274 1275 /* Match table for OF platform binding */ 1276 static const struct of_device_id xemaclite_of_match[] = { 1277 { .compatible = "xlnx,opb-ethernetlite-1.01.a", }, 1278 { .compatible = "xlnx,opb-ethernetlite-1.01.b", }, 1279 { .compatible = "xlnx,xps-ethernetlite-1.00.a", }, 1280 { .compatible = "xlnx,xps-ethernetlite-2.00.a", }, 1281 { .compatible = "xlnx,xps-ethernetlite-2.01.a", }, 1282 { .compatible = "xlnx,xps-ethernetlite-3.00.a", }, 1283 { /* end of list */ }, 1284 }; 1285 MODULE_DEVICE_TABLE(of, xemaclite_of_match); 1286 1287 static struct platform_driver xemaclite_of_driver = { 1288 .driver = { 1289 .name = DRIVER_NAME, 1290 .of_match_table = xemaclite_of_match, 1291 }, 1292 .probe = xemaclite_of_probe, 1293 .remove = xemaclite_of_remove, 1294 }; 1295 1296 module_platform_driver(xemaclite_of_driver); 1297 1298 MODULE_AUTHOR("Xilinx, Inc."); 1299 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver"); 1300 MODULE_LICENSE("GPL"); 1301