1 /* 2 * Xilinx EmacLite Linux driver for the Xilinx Ethernet MAC Lite device. 3 * 4 * This is a new flat driver which is based on the original emac_lite 5 * driver from John Williams <john.williams@xilinx.com>. 6 * 7 * 2007 - 2013 (c) Xilinx, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/uaccess.h> 17 #include <linux/netdevice.h> 18 #include <linux/etherdevice.h> 19 #include <linux/skbuff.h> 20 #include <linux/ethtool.h> 21 #include <linux/io.h> 22 #include <linux/slab.h> 23 #include <linux/of_address.h> 24 #include <linux/of_device.h> 25 #include <linux/of_platform.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/phy.h> 29 #include <linux/interrupt.h> 30 #include <linux/iopoll.h> 31 32 #define DRIVER_NAME "xilinx_emaclite" 33 34 /* Register offsets for the EmacLite Core */ 35 #define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */ 36 #define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */ 37 #define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */ 38 #define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */ 39 #define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */ 40 #define XEL_GIER_OFFSET 0x07F8 /* GIE Register */ 41 #define XEL_TSR_OFFSET 0x07FC /* Tx status */ 42 #define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */ 43 44 #define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */ 45 #define XEL_RPLR_OFFSET 0x100C /* Rx packet length */ 46 #define XEL_RSR_OFFSET 0x17FC /* Rx status */ 47 48 #define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */ 49 50 /* MDIO Address Register Bit Masks */ 51 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */ 52 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */ 53 #define XEL_MDIOADDR_PHYADR_SHIFT 5 54 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */ 55 56 /* MDIO Write Data Register Bit Masks */ 57 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */ 58 59 /* MDIO Read Data Register Bit Masks */ 60 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */ 61 62 /* MDIO Control Register Bit Masks */ 63 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */ 64 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */ 65 66 /* Global Interrupt Enable Register (GIER) Bit Masks */ 67 #define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */ 68 69 /* Transmit Status Register (TSR) Bit Masks */ 70 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */ 71 #define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */ 72 #define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */ 73 #define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000 /* Buffer is active, SW bit 74 * only. This is not documented 75 * in the HW spec 76 */ 77 78 /* Define for programming the MAC address into the EmacLite */ 79 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK) 80 81 /* Receive Status Register (RSR) */ 82 #define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */ 83 #define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */ 84 85 /* Transmit Packet Length Register (TPLR) */ 86 #define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */ 87 88 /* Receive Packet Length Register (RPLR) */ 89 #define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */ 90 91 #define XEL_HEADER_OFFSET 12 /* Offset to length field */ 92 #define XEL_HEADER_SHIFT 16 /* Shift value for length */ 93 94 /* General Ethernet Definitions */ 95 #define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ 96 #define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ 97 98 99 100 #define TX_TIMEOUT (60 * HZ) /* Tx timeout is 60 seconds. */ 101 #define ALIGNMENT 4 102 103 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ 104 #define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32)adr)) % ALIGNMENT) 105 106 #ifdef __BIG_ENDIAN 107 #define xemaclite_readl ioread32be 108 #define xemaclite_writel iowrite32be 109 #else 110 #define xemaclite_readl ioread32 111 #define xemaclite_writel iowrite32 112 #endif 113 114 /** 115 * struct net_local - Our private per device data 116 * @ndev: instance of the network device 117 * @tx_ping_pong: indicates whether Tx Pong buffer is configured in HW 118 * @rx_ping_pong: indicates whether Rx Pong buffer is configured in HW 119 * @next_tx_buf_to_use: next Tx buffer to write to 120 * @next_rx_buf_to_use: next Rx buffer to read from 121 * @base_addr: base address of the Emaclite device 122 * @reset_lock: lock used for synchronization 123 * @deferred_skb: holds an skb (for transmission at a later time) when the 124 * Tx buffer is not free 125 * @phy_dev: pointer to the PHY device 126 * @phy_node: pointer to the PHY device node 127 * @mii_bus: pointer to the MII bus 128 * @last_link: last link status 129 */ 130 struct net_local { 131 132 struct net_device *ndev; 133 134 bool tx_ping_pong; 135 bool rx_ping_pong; 136 u32 next_tx_buf_to_use; 137 u32 next_rx_buf_to_use; 138 void __iomem *base_addr; 139 140 spinlock_t reset_lock; 141 struct sk_buff *deferred_skb; 142 143 struct phy_device *phy_dev; 144 struct device_node *phy_node; 145 146 struct mii_bus *mii_bus; 147 148 int last_link; 149 }; 150 151 152 /*************************/ 153 /* EmacLite driver calls */ 154 /*************************/ 155 156 /** 157 * xemaclite_enable_interrupts - Enable the interrupts for the EmacLite device 158 * @drvdata: Pointer to the Emaclite device private data 159 * 160 * This function enables the Tx and Rx interrupts for the Emaclite device along 161 * with the Global Interrupt Enable. 162 */ 163 static void xemaclite_enable_interrupts(struct net_local *drvdata) 164 { 165 u32 reg_data; 166 167 /* Enable the Tx interrupts for the first Buffer */ 168 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 169 xemaclite_writel(reg_data | XEL_TSR_XMIT_IE_MASK, 170 drvdata->base_addr + XEL_TSR_OFFSET); 171 172 /* Enable the Rx interrupts for the first buffer */ 173 xemaclite_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); 174 175 /* Enable the Global Interrupt Enable */ 176 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 177 } 178 179 /** 180 * xemaclite_disable_interrupts - Disable the interrupts for the EmacLite device 181 * @drvdata: Pointer to the Emaclite device private data 182 * 183 * This function disables the Tx and Rx interrupts for the Emaclite device, 184 * along with the Global Interrupt Enable. 185 */ 186 static void xemaclite_disable_interrupts(struct net_local *drvdata) 187 { 188 u32 reg_data; 189 190 /* Disable the Global Interrupt Enable */ 191 xemaclite_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); 192 193 /* Disable the Tx interrupts for the first buffer */ 194 reg_data = xemaclite_readl(drvdata->base_addr + XEL_TSR_OFFSET); 195 xemaclite_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), 196 drvdata->base_addr + XEL_TSR_OFFSET); 197 198 /* Disable the Rx interrupts for the first buffer */ 199 reg_data = xemaclite_readl(drvdata->base_addr + XEL_RSR_OFFSET); 200 xemaclite_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), 201 drvdata->base_addr + XEL_RSR_OFFSET); 202 } 203 204 /** 205 * xemaclite_aligned_write - Write from 16-bit aligned to 32-bit aligned address 206 * @src_ptr: Void pointer to the 16-bit aligned source address 207 * @dest_ptr: Pointer to the 32-bit aligned destination address 208 * @length: Number bytes to write from source to destination 209 * 210 * This function writes data from a 16-bit aligned buffer to a 32-bit aligned 211 * address in the EmacLite device. 212 */ 213 static void xemaclite_aligned_write(void *src_ptr, u32 *dest_ptr, 214 unsigned length) 215 { 216 u32 align_buffer; 217 u32 *to_u32_ptr; 218 u16 *from_u16_ptr, *to_u16_ptr; 219 220 to_u32_ptr = dest_ptr; 221 from_u16_ptr = src_ptr; 222 align_buffer = 0; 223 224 for (; length > 3; length -= 4) { 225 to_u16_ptr = (u16 *)&align_buffer; 226 *to_u16_ptr++ = *from_u16_ptr++; 227 *to_u16_ptr++ = *from_u16_ptr++; 228 229 /* This barrier resolves occasional issues seen around 230 * cases where the data is not properly flushed out 231 * from the processor store buffers to the destination 232 * memory locations. 233 */ 234 wmb(); 235 236 /* Output a word */ 237 *to_u32_ptr++ = align_buffer; 238 } 239 if (length) { 240 u8 *from_u8_ptr, *to_u8_ptr; 241 242 /* Set up to output the remaining data */ 243 align_buffer = 0; 244 to_u8_ptr = (u8 *)&align_buffer; 245 from_u8_ptr = (u8 *)from_u16_ptr; 246 247 /* Output the remaining data */ 248 for (; length > 0; length--) 249 *to_u8_ptr++ = *from_u8_ptr++; 250 251 /* This barrier resolves occasional issues seen around 252 * cases where the data is not properly flushed out 253 * from the processor store buffers to the destination 254 * memory locations. 255 */ 256 wmb(); 257 *to_u32_ptr = align_buffer; 258 } 259 } 260 261 /** 262 * xemaclite_aligned_read - Read from 32-bit aligned to 16-bit aligned buffer 263 * @src_ptr: Pointer to the 32-bit aligned source address 264 * @dest_ptr: Pointer to the 16-bit aligned destination address 265 * @length: Number bytes to read from source to destination 266 * 267 * This function reads data from a 32-bit aligned address in the EmacLite device 268 * to a 16-bit aligned buffer. 269 */ 270 static void xemaclite_aligned_read(u32 *src_ptr, u8 *dest_ptr, 271 unsigned length) 272 { 273 u16 *to_u16_ptr, *from_u16_ptr; 274 u32 *from_u32_ptr; 275 u32 align_buffer; 276 277 from_u32_ptr = src_ptr; 278 to_u16_ptr = (u16 *)dest_ptr; 279 280 for (; length > 3; length -= 4) { 281 /* Copy each word into the temporary buffer */ 282 align_buffer = *from_u32_ptr++; 283 from_u16_ptr = (u16 *)&align_buffer; 284 285 /* Read data from source */ 286 *to_u16_ptr++ = *from_u16_ptr++; 287 *to_u16_ptr++ = *from_u16_ptr++; 288 } 289 290 if (length) { 291 u8 *to_u8_ptr, *from_u8_ptr; 292 293 /* Set up to read the remaining data */ 294 to_u8_ptr = (u8 *)to_u16_ptr; 295 align_buffer = *from_u32_ptr++; 296 from_u8_ptr = (u8 *)&align_buffer; 297 298 /* Read the remaining data */ 299 for (; length > 0; length--) 300 *to_u8_ptr = *from_u8_ptr; 301 } 302 } 303 304 /** 305 * xemaclite_send_data - Send an Ethernet frame 306 * @drvdata: Pointer to the Emaclite device private data 307 * @data: Pointer to the data to be sent 308 * @byte_count: Total frame size, including header 309 * 310 * This function checks if the Tx buffer of the Emaclite device is free to send 311 * data. If so, it fills the Tx buffer with data for transmission. Otherwise, it 312 * returns an error. 313 * 314 * Return: 0 upon success or -1 if the buffer(s) are full. 315 * 316 * Note: The maximum Tx packet size can not be more than Ethernet header 317 * (14 Bytes) + Maximum MTU (1500 bytes). This is excluding FCS. 318 */ 319 static int xemaclite_send_data(struct net_local *drvdata, u8 *data, 320 unsigned int byte_count) 321 { 322 u32 reg_data; 323 void __iomem *addr; 324 325 /* Determine the expected Tx buffer address */ 326 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 327 328 /* If the length is too large, truncate it */ 329 if (byte_count > ETH_FRAME_LEN) 330 byte_count = ETH_FRAME_LEN; 331 332 /* Check if the expected buffer is available */ 333 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 334 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 335 XEL_TSR_XMIT_ACTIVE_MASK)) == 0) { 336 337 /* Switch to next buffer if configured */ 338 if (drvdata->tx_ping_pong != 0) 339 drvdata->next_tx_buf_to_use ^= XEL_BUFFER_OFFSET; 340 } else if (drvdata->tx_ping_pong != 0) { 341 /* If the expected buffer is full, try the other buffer, 342 * if it is configured in HW 343 */ 344 345 addr = (void __iomem __force *)((u32 __force)addr ^ 346 XEL_BUFFER_OFFSET); 347 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 348 349 if ((reg_data & (XEL_TSR_XMIT_BUSY_MASK | 350 XEL_TSR_XMIT_ACTIVE_MASK)) != 0) 351 return -1; /* Buffers were full, return failure */ 352 } else 353 return -1; /* Buffer was full, return failure */ 354 355 /* Write the frame to the buffer */ 356 xemaclite_aligned_write(data, (u32 __force *)addr, byte_count); 357 358 xemaclite_writel((byte_count & XEL_TPLR_LENGTH_MASK), 359 addr + XEL_TPLR_OFFSET); 360 361 /* Update the Tx Status Register to indicate that there is a 362 * frame to send. Set the XEL_TSR_XMIT_ACTIVE_MASK flag which 363 * is used by the interrupt handler to check whether a frame 364 * has been transmitted 365 */ 366 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 367 reg_data |= (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_XMIT_ACTIVE_MASK); 368 xemaclite_writel(reg_data, addr + XEL_TSR_OFFSET); 369 370 return 0; 371 } 372 373 /** 374 * xemaclite_recv_data - Receive a frame 375 * @drvdata: Pointer to the Emaclite device private data 376 * @data: Address where the data is to be received 377 * @maxlen: Maximum supported ethernet packet length 378 * 379 * This function is intended to be called from the interrupt context or 380 * with a wrapper which waits for the receive frame to be available. 381 * 382 * Return: Total number of bytes received 383 */ 384 static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen) 385 { 386 void __iomem *addr; 387 u16 length, proto_type; 388 u32 reg_data; 389 390 /* Determine the expected buffer address */ 391 addr = (drvdata->base_addr + drvdata->next_rx_buf_to_use); 392 393 /* Verify which buffer has valid data */ 394 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 395 396 if ((reg_data & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) { 397 if (drvdata->rx_ping_pong != 0) 398 drvdata->next_rx_buf_to_use ^= XEL_BUFFER_OFFSET; 399 } else { 400 /* The instance is out of sync, try other buffer if other 401 * buffer is configured, return 0 otherwise. If the instance is 402 * out of sync, do not update the 'next_rx_buf_to_use' since it 403 * will correct on subsequent calls 404 */ 405 if (drvdata->rx_ping_pong != 0) 406 addr = (void __iomem __force *)((u32 __force)addr ^ 407 XEL_BUFFER_OFFSET); 408 else 409 return 0; /* No data was available */ 410 411 /* Verify that buffer has valid data */ 412 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 413 if ((reg_data & XEL_RSR_RECV_DONE_MASK) != 414 XEL_RSR_RECV_DONE_MASK) 415 return 0; /* No data was available */ 416 } 417 418 /* Get the protocol type of the ethernet frame that arrived 419 */ 420 proto_type = ((ntohl(xemaclite_readl(addr + XEL_HEADER_OFFSET + 421 XEL_RXBUFF_OFFSET)) >> XEL_HEADER_SHIFT) & 422 XEL_RPLR_LENGTH_MASK); 423 424 /* Check if received ethernet frame is a raw ethernet frame 425 * or an IP packet or an ARP packet 426 */ 427 if (proto_type > ETH_DATA_LEN) { 428 429 if (proto_type == ETH_P_IP) { 430 length = ((ntohl(xemaclite_readl(addr + 431 XEL_HEADER_IP_LENGTH_OFFSET + 432 XEL_RXBUFF_OFFSET)) >> 433 XEL_HEADER_SHIFT) & 434 XEL_RPLR_LENGTH_MASK); 435 length = min_t(u16, length, ETH_DATA_LEN); 436 length += ETH_HLEN + ETH_FCS_LEN; 437 438 } else if (proto_type == ETH_P_ARP) 439 length = XEL_ARP_PACKET_SIZE + ETH_HLEN + ETH_FCS_LEN; 440 else 441 /* Field contains type other than IP or ARP, use max 442 * frame size and let user parse it 443 */ 444 length = ETH_FRAME_LEN + ETH_FCS_LEN; 445 } else 446 /* Use the length in the frame, plus the header and trailer */ 447 length = proto_type + ETH_HLEN + ETH_FCS_LEN; 448 449 if (WARN_ON(length > maxlen)) 450 length = maxlen; 451 452 /* Read from the EmacLite device */ 453 xemaclite_aligned_read((u32 __force *)(addr + XEL_RXBUFF_OFFSET), 454 data, length); 455 456 /* Acknowledge the frame */ 457 reg_data = xemaclite_readl(addr + XEL_RSR_OFFSET); 458 reg_data &= ~XEL_RSR_RECV_DONE_MASK; 459 xemaclite_writel(reg_data, addr + XEL_RSR_OFFSET); 460 461 return length; 462 } 463 464 /** 465 * xemaclite_update_address - Update the MAC address in the device 466 * @drvdata: Pointer to the Emaclite device private data 467 * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) 468 * 469 * Tx must be idle and Rx should be idle for deterministic results. 470 * It is recommended that this function should be called after the 471 * initialization and before transmission of any packets from the device. 472 * The MAC address can be programmed using any of the two transmit 473 * buffers (if configured). 474 */ 475 static void xemaclite_update_address(struct net_local *drvdata, 476 u8 *address_ptr) 477 { 478 void __iomem *addr; 479 u32 reg_data; 480 481 /* Determine the expected Tx buffer address */ 482 addr = drvdata->base_addr + drvdata->next_tx_buf_to_use; 483 484 xemaclite_aligned_write(address_ptr, (u32 __force *)addr, ETH_ALEN); 485 486 xemaclite_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); 487 488 /* Update the MAC address in the EmacLite */ 489 reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); 490 xemaclite_writel(reg_data | XEL_TSR_PROG_MAC_ADDR, addr + XEL_TSR_OFFSET); 491 492 /* Wait for EmacLite to finish with the MAC address update */ 493 while ((xemaclite_readl(addr + XEL_TSR_OFFSET) & 494 XEL_TSR_PROG_MAC_ADDR) != 0) 495 ; 496 } 497 498 /** 499 * xemaclite_set_mac_address - Set the MAC address for this device 500 * @dev: Pointer to the network device instance 501 * @address: Void pointer to the sockaddr structure 502 * 503 * This function copies the HW address from the sockaddr strucutre to the 504 * net_device structure and updates the address in HW. 505 * 506 * Return: Error if the net device is busy or 0 if the addr is set 507 * successfully 508 */ 509 static int xemaclite_set_mac_address(struct net_device *dev, void *address) 510 { 511 struct net_local *lp = netdev_priv(dev); 512 struct sockaddr *addr = address; 513 514 if (netif_running(dev)) 515 return -EBUSY; 516 517 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 518 xemaclite_update_address(lp, dev->dev_addr); 519 return 0; 520 } 521 522 /** 523 * xemaclite_tx_timeout - Callback for Tx Timeout 524 * @dev: Pointer to the network device 525 * 526 * This function is called when Tx time out occurs for Emaclite device. 527 */ 528 static void xemaclite_tx_timeout(struct net_device *dev) 529 { 530 struct net_local *lp = netdev_priv(dev); 531 unsigned long flags; 532 533 dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n", 534 TX_TIMEOUT * 1000UL / HZ); 535 536 dev->stats.tx_errors++; 537 538 /* Reset the device */ 539 spin_lock_irqsave(&lp->reset_lock, flags); 540 541 /* Shouldn't really be necessary, but shouldn't hurt */ 542 netif_stop_queue(dev); 543 544 xemaclite_disable_interrupts(lp); 545 xemaclite_enable_interrupts(lp); 546 547 if (lp->deferred_skb) { 548 dev_kfree_skb(lp->deferred_skb); 549 lp->deferred_skb = NULL; 550 dev->stats.tx_errors++; 551 } 552 553 /* To exclude tx timeout */ 554 netif_trans_update(dev); /* prevent tx timeout */ 555 556 /* We're all ready to go. Start the queue */ 557 netif_wake_queue(dev); 558 spin_unlock_irqrestore(&lp->reset_lock, flags); 559 } 560 561 /**********************/ 562 /* Interrupt Handlers */ 563 /**********************/ 564 565 /** 566 * xemaclite_tx_handler - Interrupt handler for frames sent 567 * @dev: Pointer to the network device 568 * 569 * This function updates the number of packets transmitted and handles the 570 * deferred skb, if there is one. 571 */ 572 static void xemaclite_tx_handler(struct net_device *dev) 573 { 574 struct net_local *lp = netdev_priv(dev); 575 576 dev->stats.tx_packets++; 577 578 if (!lp->deferred_skb) 579 return; 580 581 if (xemaclite_send_data(lp, (u8 *)lp->deferred_skb->data, 582 lp->deferred_skb->len)) 583 return; 584 585 dev->stats.tx_bytes += lp->deferred_skb->len; 586 dev_consume_skb_irq(lp->deferred_skb); 587 lp->deferred_skb = NULL; 588 netif_trans_update(dev); /* prevent tx timeout */ 589 netif_wake_queue(dev); 590 } 591 592 /** 593 * xemaclite_rx_handler- Interrupt handler for frames received 594 * @dev: Pointer to the network device 595 * 596 * This function allocates memory for a socket buffer, fills it with data 597 * received and hands it over to the TCP/IP stack. 598 */ 599 static void xemaclite_rx_handler(struct net_device *dev) 600 { 601 struct net_local *lp = netdev_priv(dev); 602 struct sk_buff *skb; 603 unsigned int align; 604 u32 len; 605 606 len = ETH_FRAME_LEN + ETH_FCS_LEN; 607 skb = netdev_alloc_skb(dev, len + ALIGNMENT); 608 if (!skb) { 609 /* Couldn't get memory. */ 610 dev->stats.rx_dropped++; 611 dev_err(&lp->ndev->dev, "Could not allocate receive buffer\n"); 612 return; 613 } 614 615 /* A new skb should have the data halfword aligned, but this code is 616 * here just in case that isn't true. Calculate how many 617 * bytes we should reserve to get the data to start on a word 618 * boundary 619 */ 620 align = BUFFER_ALIGN(skb->data); 621 if (align) 622 skb_reserve(skb, align); 623 624 skb_reserve(skb, 2); 625 626 len = xemaclite_recv_data(lp, (u8 *)skb->data, len); 627 628 if (!len) { 629 dev->stats.rx_errors++; 630 dev_kfree_skb_irq(skb); 631 return; 632 } 633 634 skb_put(skb, len); /* Tell the skb how much data we got */ 635 636 skb->protocol = eth_type_trans(skb, dev); 637 skb_checksum_none_assert(skb); 638 639 dev->stats.rx_packets++; 640 dev->stats.rx_bytes += len; 641 642 if (!skb_defer_rx_timestamp(skb)) 643 netif_rx(skb); /* Send the packet upstream */ 644 } 645 646 /** 647 * xemaclite_interrupt - Interrupt handler for this driver 648 * @irq: Irq of the Emaclite device 649 * @dev_id: Void pointer to the network device instance used as callback 650 * reference 651 * 652 * Return: IRQ_HANDLED 653 * 654 * This function handles the Tx and Rx interrupts of the EmacLite device. 655 */ 656 static irqreturn_t xemaclite_interrupt(int irq, void *dev_id) 657 { 658 bool tx_complete = false; 659 struct net_device *dev = dev_id; 660 struct net_local *lp = netdev_priv(dev); 661 void __iomem *base_addr = lp->base_addr; 662 u32 tx_status; 663 664 /* Check if there is Rx Data available */ 665 if ((xemaclite_readl(base_addr + XEL_RSR_OFFSET) & 666 XEL_RSR_RECV_DONE_MASK) || 667 (xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_RSR_OFFSET) 668 & XEL_RSR_RECV_DONE_MASK)) 669 670 xemaclite_rx_handler(dev); 671 672 /* Check if the Transmission for the first buffer is completed */ 673 tx_status = xemaclite_readl(base_addr + XEL_TSR_OFFSET); 674 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 675 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 676 677 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 678 xemaclite_writel(tx_status, base_addr + XEL_TSR_OFFSET); 679 680 tx_complete = true; 681 } 682 683 /* Check if the Transmission for the second buffer is completed */ 684 tx_status = xemaclite_readl(base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 685 if (((tx_status & XEL_TSR_XMIT_BUSY_MASK) == 0) && 686 (tx_status & XEL_TSR_XMIT_ACTIVE_MASK) != 0) { 687 688 tx_status &= ~XEL_TSR_XMIT_ACTIVE_MASK; 689 xemaclite_writel(tx_status, base_addr + XEL_BUFFER_OFFSET + 690 XEL_TSR_OFFSET); 691 692 tx_complete = true; 693 } 694 695 /* If there was a Tx interrupt, call the Tx Handler */ 696 if (tx_complete != 0) 697 xemaclite_tx_handler(dev); 698 699 return IRQ_HANDLED; 700 } 701 702 /**********************/ 703 /* MDIO Bus functions */ 704 /**********************/ 705 706 /** 707 * xemaclite_mdio_wait - Wait for the MDIO to be ready to use 708 * @lp: Pointer to the Emaclite device private data 709 * 710 * This function waits till the device is ready to accept a new MDIO 711 * request. 712 * 713 * Return: 0 for success or ETIMEDOUT for a timeout 714 */ 715 716 static int xemaclite_mdio_wait(struct net_local *lp) 717 { 718 u32 val; 719 720 /* wait for the MDIO interface to not be busy or timeout 721 * after some time. 722 */ 723 return readx_poll_timeout(xemaclite_readl, 724 lp->base_addr + XEL_MDIOCTRL_OFFSET, 725 val, !(val & XEL_MDIOCTRL_MDIOSTS_MASK), 726 1000, 20000); 727 } 728 729 /** 730 * xemaclite_mdio_read - Read from a given MII management register 731 * @bus: the mii_bus struct 732 * @phy_id: the phy address 733 * @reg: register number to read from 734 * 735 * This function waits till the device is ready to accept a new MDIO 736 * request and then writes the phy address to the MDIO Address register 737 * and reads data from MDIO Read Data register, when its available. 738 * 739 * Return: Value read from the MII management register 740 */ 741 static int xemaclite_mdio_read(struct mii_bus *bus, int phy_id, int reg) 742 { 743 struct net_local *lp = bus->priv; 744 u32 ctrl_reg; 745 u32 rc; 746 747 if (xemaclite_mdio_wait(lp)) 748 return -ETIMEDOUT; 749 750 /* Write the PHY address, register number and set the OP bit in the 751 * MDIO Address register. Set the Status bit in the MDIO Control 752 * register to start a MDIO read transaction. 753 */ 754 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 755 xemaclite_writel(XEL_MDIOADDR_OP_MASK | 756 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 757 lp->base_addr + XEL_MDIOADDR_OFFSET); 758 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 759 lp->base_addr + XEL_MDIOCTRL_OFFSET); 760 761 if (xemaclite_mdio_wait(lp)) 762 return -ETIMEDOUT; 763 764 rc = xemaclite_readl(lp->base_addr + XEL_MDIORD_OFFSET); 765 766 dev_dbg(&lp->ndev->dev, 767 "%s(phy_id=%i, reg=%x) == %x\n", __func__, 768 phy_id, reg, rc); 769 770 return rc; 771 } 772 773 /** 774 * xemaclite_mdio_write - Write to a given MII management register 775 * @bus: the mii_bus struct 776 * @phy_id: the phy address 777 * @reg: register number to write to 778 * @val: value to write to the register number specified by reg 779 * 780 * This function waits till the device is ready to accept a new MDIO 781 * request and then writes the val to the MDIO Write Data register. 782 * 783 * Return: 0 upon success or a negative error upon failure 784 */ 785 static int xemaclite_mdio_write(struct mii_bus *bus, int phy_id, int reg, 786 u16 val) 787 { 788 struct net_local *lp = bus->priv; 789 u32 ctrl_reg; 790 791 dev_dbg(&lp->ndev->dev, 792 "%s(phy_id=%i, reg=%x, val=%x)\n", __func__, 793 phy_id, reg, val); 794 795 if (xemaclite_mdio_wait(lp)) 796 return -ETIMEDOUT; 797 798 /* Write the PHY address, register number and clear the OP bit in the 799 * MDIO Address register and then write the value into the MDIO Write 800 * Data register. Finally, set the Status bit in the MDIO Control 801 * register to start a MDIO write transaction. 802 */ 803 ctrl_reg = xemaclite_readl(lp->base_addr + XEL_MDIOCTRL_OFFSET); 804 xemaclite_writel(~XEL_MDIOADDR_OP_MASK & 805 ((phy_id << XEL_MDIOADDR_PHYADR_SHIFT) | reg), 806 lp->base_addr + XEL_MDIOADDR_OFFSET); 807 xemaclite_writel(val, lp->base_addr + XEL_MDIOWR_OFFSET); 808 xemaclite_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, 809 lp->base_addr + XEL_MDIOCTRL_OFFSET); 810 811 return 0; 812 } 813 814 /** 815 * xemaclite_mdio_setup - Register mii_bus for the Emaclite device 816 * @lp: Pointer to the Emaclite device private data 817 * @dev: Pointer to OF device structure 818 * 819 * This function enables MDIO bus in the Emaclite device and registers a 820 * mii_bus. 821 * 822 * Return: 0 upon success or a negative error upon failure 823 */ 824 static int xemaclite_mdio_setup(struct net_local *lp, struct device *dev) 825 { 826 struct mii_bus *bus; 827 int rc; 828 struct resource res; 829 struct device_node *np = of_get_parent(lp->phy_node); 830 struct device_node *npp; 831 832 /* Don't register the MDIO bus if the phy_node or its parent node 833 * can't be found. 834 */ 835 if (!np) { 836 dev_err(dev, "Failed to register mdio bus.\n"); 837 return -ENODEV; 838 } 839 npp = of_get_parent(np); 840 841 of_address_to_resource(npp, 0, &res); 842 if (lp->ndev->mem_start != res.start) { 843 struct phy_device *phydev; 844 phydev = of_phy_find_device(lp->phy_node); 845 if (!phydev) 846 dev_info(dev, 847 "MDIO of the phy is not registered yet\n"); 848 else 849 put_device(&phydev->mdio.dev); 850 return 0; 851 } 852 853 /* Enable the MDIO bus by asserting the enable bit in MDIO Control 854 * register. 855 */ 856 xemaclite_writel(XEL_MDIOCTRL_MDIOEN_MASK, 857 lp->base_addr + XEL_MDIOCTRL_OFFSET); 858 859 bus = mdiobus_alloc(); 860 if (!bus) { 861 dev_err(dev, "Failed to allocate mdiobus\n"); 862 return -ENOMEM; 863 } 864 865 snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", 866 (unsigned long long)res.start); 867 bus->priv = lp; 868 bus->name = "Xilinx Emaclite MDIO"; 869 bus->read = xemaclite_mdio_read; 870 bus->write = xemaclite_mdio_write; 871 bus->parent = dev; 872 873 rc = of_mdiobus_register(bus, np); 874 if (rc) { 875 dev_err(dev, "Failed to register mdio bus.\n"); 876 goto err_register; 877 } 878 879 lp->mii_bus = bus; 880 881 return 0; 882 883 err_register: 884 mdiobus_free(bus); 885 return rc; 886 } 887 888 /** 889 * xemaclite_adjust_link - Link state callback for the Emaclite device 890 * @ndev: pointer to net_device struct 891 * 892 * There's nothing in the Emaclite device to be configured when the link 893 * state changes. We just print the status. 894 */ 895 static void xemaclite_adjust_link(struct net_device *ndev) 896 { 897 struct net_local *lp = netdev_priv(ndev); 898 struct phy_device *phy = lp->phy_dev; 899 int link_state; 900 901 /* hash together the state values to decide if something has changed */ 902 link_state = phy->speed | (phy->duplex << 1) | phy->link; 903 904 if (lp->last_link != link_state) { 905 lp->last_link = link_state; 906 phy_print_status(phy); 907 } 908 } 909 910 /** 911 * xemaclite_open - Open the network device 912 * @dev: Pointer to the network device 913 * 914 * This function sets the MAC address, requests an IRQ and enables interrupts 915 * for the Emaclite device and starts the Tx queue. 916 * It also connects to the phy device, if MDIO is included in Emaclite device. 917 * 918 * Return: 0 on success. -ENODEV, if PHY cannot be connected. 919 * Non-zero error value on failure. 920 */ 921 static int xemaclite_open(struct net_device *dev) 922 { 923 struct net_local *lp = netdev_priv(dev); 924 int retval; 925 926 /* Just to be safe, stop the device first */ 927 xemaclite_disable_interrupts(lp); 928 929 if (lp->phy_node) { 930 u32 bmcr; 931 932 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node, 933 xemaclite_adjust_link, 0, 934 PHY_INTERFACE_MODE_MII); 935 if (!lp->phy_dev) { 936 dev_err(&lp->ndev->dev, "of_phy_connect() failed\n"); 937 return -ENODEV; 938 } 939 940 /* EmacLite doesn't support giga-bit speeds */ 941 phy_set_max_speed(lp->phy_dev, SPEED_100); 942 943 /* Don't advertise 1000BASE-T Full/Half duplex speeds */ 944 phy_write(lp->phy_dev, MII_CTRL1000, 0); 945 946 /* Advertise only 10 and 100mbps full/half duplex speeds */ 947 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | 948 ADVERTISE_CSMA); 949 950 /* Restart auto negotiation */ 951 bmcr = phy_read(lp->phy_dev, MII_BMCR); 952 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 953 phy_write(lp->phy_dev, MII_BMCR, bmcr); 954 955 phy_start(lp->phy_dev); 956 } 957 958 /* Set the MAC address each time opened */ 959 xemaclite_update_address(lp, dev->dev_addr); 960 961 /* Grab the IRQ */ 962 retval = request_irq(dev->irq, xemaclite_interrupt, 0, dev->name, dev); 963 if (retval) { 964 dev_err(&lp->ndev->dev, "Could not allocate interrupt %d\n", 965 dev->irq); 966 if (lp->phy_dev) 967 phy_disconnect(lp->phy_dev); 968 lp->phy_dev = NULL; 969 970 return retval; 971 } 972 973 /* Enable Interrupts */ 974 xemaclite_enable_interrupts(lp); 975 976 /* We're ready to go */ 977 netif_start_queue(dev); 978 979 return 0; 980 } 981 982 /** 983 * xemaclite_close - Close the network device 984 * @dev: Pointer to the network device 985 * 986 * This function stops the Tx queue, disables interrupts and frees the IRQ for 987 * the Emaclite device. 988 * It also disconnects the phy device associated with the Emaclite device. 989 * 990 * Return: 0, always. 991 */ 992 static int xemaclite_close(struct net_device *dev) 993 { 994 struct net_local *lp = netdev_priv(dev); 995 996 netif_stop_queue(dev); 997 xemaclite_disable_interrupts(lp); 998 free_irq(dev->irq, dev); 999 1000 if (lp->phy_dev) 1001 phy_disconnect(lp->phy_dev); 1002 lp->phy_dev = NULL; 1003 1004 return 0; 1005 } 1006 1007 /** 1008 * xemaclite_send - Transmit a frame 1009 * @orig_skb: Pointer to the socket buffer to be transmitted 1010 * @dev: Pointer to the network device 1011 * 1012 * This function checks if the Tx buffer of the Emaclite device is free to send 1013 * data. If so, it fills the Tx buffer with data from socket buffer data, 1014 * updates the stats and frees the socket buffer. The Tx completion is signaled 1015 * by an interrupt. If the Tx buffer isn't free, then the socket buffer is 1016 * deferred and the Tx queue is stopped so that the deferred socket buffer can 1017 * be transmitted when the Emaclite device is free to transmit data. 1018 * 1019 * Return: NETDEV_TX_OK, always. 1020 */ 1021 static netdev_tx_t 1022 xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev) 1023 { 1024 struct net_local *lp = netdev_priv(dev); 1025 struct sk_buff *new_skb; 1026 unsigned int len; 1027 unsigned long flags; 1028 1029 len = orig_skb->len; 1030 1031 new_skb = orig_skb; 1032 1033 spin_lock_irqsave(&lp->reset_lock, flags); 1034 if (xemaclite_send_data(lp, (u8 *)new_skb->data, len) != 0) { 1035 /* If the Emaclite Tx buffer is busy, stop the Tx queue and 1036 * defer the skb for transmission during the ISR, after the 1037 * current transmission is complete 1038 */ 1039 netif_stop_queue(dev); 1040 lp->deferred_skb = new_skb; 1041 /* Take the time stamp now, since we can't do this in an ISR. */ 1042 skb_tx_timestamp(new_skb); 1043 spin_unlock_irqrestore(&lp->reset_lock, flags); 1044 return NETDEV_TX_OK; 1045 } 1046 spin_unlock_irqrestore(&lp->reset_lock, flags); 1047 1048 skb_tx_timestamp(new_skb); 1049 1050 dev->stats.tx_bytes += len; 1051 dev_consume_skb_any(new_skb); 1052 1053 return NETDEV_TX_OK; 1054 } 1055 1056 /** 1057 * get_bool - Get a parameter from the OF device 1058 * @ofdev: Pointer to OF device structure 1059 * @s: Property to be retrieved 1060 * 1061 * This function looks for a property in the device node and returns the value 1062 * of the property if its found or 0 if the property is not found. 1063 * 1064 * Return: Value of the parameter if the parameter is found, or 0 otherwise 1065 */ 1066 static bool get_bool(struct platform_device *ofdev, const char *s) 1067 { 1068 u32 *p = (u32 *)of_get_property(ofdev->dev.of_node, s, NULL); 1069 1070 if (!p) { 1071 dev_warn(&ofdev->dev, "Parameter %s not found, defaulting to false\n", s); 1072 return false; 1073 } 1074 1075 return (bool)*p; 1076 } 1077 1078 /** 1079 * xemaclite_ethtools_get_drvinfo - Get various Axi Emac Lite driver info 1080 * @ndev: Pointer to net_device structure 1081 * @ed: Pointer to ethtool_drvinfo structure 1082 * 1083 * This implements ethtool command for getting the driver information. 1084 * Issue "ethtool -i ethX" under linux prompt to execute this function. 1085 */ 1086 static void xemaclite_ethtools_get_drvinfo(struct net_device *ndev, 1087 struct ethtool_drvinfo *ed) 1088 { 1089 strlcpy(ed->driver, DRIVER_NAME, sizeof(ed->driver)); 1090 } 1091 1092 static const struct ethtool_ops xemaclite_ethtool_ops = { 1093 .get_drvinfo = xemaclite_ethtools_get_drvinfo, 1094 .get_link = ethtool_op_get_link, 1095 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1096 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1097 }; 1098 1099 static const struct net_device_ops xemaclite_netdev_ops; 1100 1101 /** 1102 * xemaclite_of_probe - Probe method for the Emaclite device. 1103 * @ofdev: Pointer to OF device structure 1104 * 1105 * This function probes for the Emaclite device in the device tree. 1106 * It initializes the driver data structure and the hardware, sets the MAC 1107 * address and registers the network device. 1108 * It also registers a mii_bus for the Emaclite device, if MDIO is included 1109 * in the device. 1110 * 1111 * Return: 0, if the driver is bound to the Emaclite device, or 1112 * a negative error if there is failure. 1113 */ 1114 static int xemaclite_of_probe(struct platform_device *ofdev) 1115 { 1116 struct resource *res; 1117 struct net_device *ndev = NULL; 1118 struct net_local *lp = NULL; 1119 struct device *dev = &ofdev->dev; 1120 const void *mac_address; 1121 1122 int rc = 0; 1123 1124 dev_info(dev, "Device Tree Probing\n"); 1125 1126 /* Create an ethernet device instance */ 1127 ndev = alloc_etherdev(sizeof(struct net_local)); 1128 if (!ndev) 1129 return -ENOMEM; 1130 1131 dev_set_drvdata(dev, ndev); 1132 SET_NETDEV_DEV(ndev, &ofdev->dev); 1133 1134 lp = netdev_priv(ndev); 1135 lp->ndev = ndev; 1136 1137 /* Get IRQ for the device */ 1138 res = platform_get_resource(ofdev, IORESOURCE_IRQ, 0); 1139 if (!res) { 1140 dev_err(dev, "no IRQ found\n"); 1141 rc = -ENXIO; 1142 goto error; 1143 } 1144 1145 ndev->irq = res->start; 1146 1147 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0); 1148 lp->base_addr = devm_ioremap_resource(&ofdev->dev, res); 1149 if (IS_ERR(lp->base_addr)) { 1150 rc = PTR_ERR(lp->base_addr); 1151 goto error; 1152 } 1153 1154 ndev->mem_start = res->start; 1155 ndev->mem_end = res->end; 1156 1157 spin_lock_init(&lp->reset_lock); 1158 lp->next_tx_buf_to_use = 0x0; 1159 lp->next_rx_buf_to_use = 0x0; 1160 lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong"); 1161 lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong"); 1162 mac_address = of_get_mac_address(ofdev->dev.of_node); 1163 1164 if (!IS_ERR(mac_address)) { 1165 /* Set the MAC address. */ 1166 ether_addr_copy(ndev->dev_addr, mac_address); 1167 } else { 1168 dev_warn(dev, "No MAC address found, using random\n"); 1169 eth_hw_addr_random(ndev); 1170 } 1171 1172 /* Clear the Tx CSR's in case this is a restart */ 1173 xemaclite_writel(0, lp->base_addr + XEL_TSR_OFFSET); 1174 xemaclite_writel(0, lp->base_addr + XEL_BUFFER_OFFSET + XEL_TSR_OFFSET); 1175 1176 /* Set the MAC address in the EmacLite device */ 1177 xemaclite_update_address(lp, ndev->dev_addr); 1178 1179 lp->phy_node = of_parse_phandle(ofdev->dev.of_node, "phy-handle", 0); 1180 xemaclite_mdio_setup(lp, &ofdev->dev); 1181 1182 dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr); 1183 1184 ndev->netdev_ops = &xemaclite_netdev_ops; 1185 ndev->ethtool_ops = &xemaclite_ethtool_ops; 1186 ndev->flags &= ~IFF_MULTICAST; 1187 ndev->watchdog_timeo = TX_TIMEOUT; 1188 1189 /* Finally, register the device */ 1190 rc = register_netdev(ndev); 1191 if (rc) { 1192 dev_err(dev, 1193 "Cannot register network device, aborting\n"); 1194 goto error; 1195 } 1196 1197 dev_info(dev, 1198 "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n", 1199 (unsigned int __force)ndev->mem_start, 1200 (unsigned int __force)lp->base_addr, ndev->irq); 1201 return 0; 1202 1203 error: 1204 free_netdev(ndev); 1205 return rc; 1206 } 1207 1208 /** 1209 * xemaclite_of_remove - Unbind the driver from the Emaclite device. 1210 * @of_dev: Pointer to OF device structure 1211 * 1212 * This function is called if a device is physically removed from the system or 1213 * if the driver module is being unloaded. It frees any resources allocated to 1214 * the device. 1215 * 1216 * Return: 0, always. 1217 */ 1218 static int xemaclite_of_remove(struct platform_device *of_dev) 1219 { 1220 struct net_device *ndev = platform_get_drvdata(of_dev); 1221 1222 struct net_local *lp = netdev_priv(ndev); 1223 1224 /* Un-register the mii_bus, if configured */ 1225 if (lp->mii_bus) { 1226 mdiobus_unregister(lp->mii_bus); 1227 mdiobus_free(lp->mii_bus); 1228 lp->mii_bus = NULL; 1229 } 1230 1231 unregister_netdev(ndev); 1232 1233 of_node_put(lp->phy_node); 1234 lp->phy_node = NULL; 1235 1236 free_netdev(ndev); 1237 1238 return 0; 1239 } 1240 1241 #ifdef CONFIG_NET_POLL_CONTROLLER 1242 static void 1243 xemaclite_poll_controller(struct net_device *ndev) 1244 { 1245 disable_irq(ndev->irq); 1246 xemaclite_interrupt(ndev->irq, ndev); 1247 enable_irq(ndev->irq); 1248 } 1249 #endif 1250 1251 /* Ioctl MII Interface */ 1252 static int xemaclite_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1253 { 1254 if (!dev->phydev || !netif_running(dev)) 1255 return -EINVAL; 1256 1257 switch (cmd) { 1258 case SIOCGMIIPHY: 1259 case SIOCGMIIREG: 1260 case SIOCSMIIREG: 1261 return phy_mii_ioctl(dev->phydev, rq, cmd); 1262 default: 1263 return -EOPNOTSUPP; 1264 } 1265 } 1266 1267 static const struct net_device_ops xemaclite_netdev_ops = { 1268 .ndo_open = xemaclite_open, 1269 .ndo_stop = xemaclite_close, 1270 .ndo_start_xmit = xemaclite_send, 1271 .ndo_set_mac_address = xemaclite_set_mac_address, 1272 .ndo_tx_timeout = xemaclite_tx_timeout, 1273 .ndo_do_ioctl = xemaclite_ioctl, 1274 #ifdef CONFIG_NET_POLL_CONTROLLER 1275 .ndo_poll_controller = xemaclite_poll_controller, 1276 #endif 1277 }; 1278 1279 /* Match table for OF platform binding */ 1280 static const struct of_device_id xemaclite_of_match[] = { 1281 { .compatible = "xlnx,opb-ethernetlite-1.01.a", }, 1282 { .compatible = "xlnx,opb-ethernetlite-1.01.b", }, 1283 { .compatible = "xlnx,xps-ethernetlite-1.00.a", }, 1284 { .compatible = "xlnx,xps-ethernetlite-2.00.a", }, 1285 { .compatible = "xlnx,xps-ethernetlite-2.01.a", }, 1286 { .compatible = "xlnx,xps-ethernetlite-3.00.a", }, 1287 { /* end of list */ }, 1288 }; 1289 MODULE_DEVICE_TABLE(of, xemaclite_of_match); 1290 1291 static struct platform_driver xemaclite_of_driver = { 1292 .driver = { 1293 .name = DRIVER_NAME, 1294 .of_match_table = xemaclite_of_match, 1295 }, 1296 .probe = xemaclite_of_probe, 1297 .remove = xemaclite_of_remove, 1298 }; 1299 1300 module_platform_driver(xemaclite_of_driver); 1301 1302 MODULE_AUTHOR("Xilinx, Inc."); 1303 MODULE_DESCRIPTION("Xilinx Ethernet MAC Lite driver"); 1304 MODULE_LICENSE("GPL"); 1305