1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/gpio/machine.h> 5 #include <linux/gpio/driver.h> 6 #include <linux/gpio/property.h> 7 #include <linux/clk-provider.h> 8 #include <linux/clkdev.h> 9 #include <linux/i2c.h> 10 #include <linux/pci.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/pcs/pcs-xpcs.h> 14 #include <linux/phylink.h> 15 16 #include "../libwx/wx_type.h" 17 #include "../libwx/wx_lib.h" 18 #include "../libwx/wx_hw.h" 19 #include "txgbe_type.h" 20 #include "txgbe_phy.h" 21 #include "txgbe_hw.h" 22 23 #define TXGBE_I2C_CLK_DEV_NAME "i2c_dw" 24 25 static int txgbe_swnodes_register(struct txgbe *txgbe) 26 { 27 struct txgbe_nodes *nodes = &txgbe->nodes; 28 struct pci_dev *pdev = txgbe->wx->pdev; 29 struct software_node *swnodes; 30 u32 id; 31 32 id = pci_dev_id(pdev); 33 34 snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id); 35 snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id); 36 snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id); 37 snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id); 38 39 swnodes = nodes->swnodes; 40 41 /* GPIO 0: tx fault 42 * GPIO 1: tx disable 43 * GPIO 2: sfp module absent 44 * GPIO 3: rx signal lost 45 * GPIO 4: rate select, 1G(0) 10G(1) 46 * GPIO 5: rate select, 1G(0) 10G(1) 47 */ 48 nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default"); 49 swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props); 50 nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH); 51 nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH); 52 nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW); 53 nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH); 54 nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH); 55 nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH); 56 57 nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c"); 58 nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model"); 59 nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ); 60 swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props); 61 nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]); 62 63 nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp"); 64 nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref); 65 nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref); 66 nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref); 67 nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref); 68 nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref); 69 nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref); 70 nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref); 71 swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props); 72 nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]); 73 74 nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status"); 75 nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref); 76 swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props); 77 78 nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO]; 79 nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C]; 80 nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP]; 81 nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK]; 82 83 return software_node_register_node_group(nodes->group); 84 } 85 86 static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum) 87 { 88 struct wx *wx = bus->priv; 89 u32 offset, val; 90 91 if (addr) 92 return -EOPNOTSUPP; 93 94 offset = devnum << 16 | regnum; 95 96 /* Set the LAN port indicator to IDA_ADDR */ 97 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 98 99 /* Read the data from IDA_DATA register */ 100 val = rd32(wx, TXGBE_XPCS_IDA_DATA); 101 102 return (u16)val; 103 } 104 105 static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val) 106 { 107 struct wx *wx = bus->priv; 108 u32 offset; 109 110 if (addr) 111 return -EOPNOTSUPP; 112 113 offset = devnum << 16 | regnum; 114 115 /* Set the LAN port indicator to IDA_ADDR */ 116 wr32(wx, TXGBE_XPCS_IDA_ADDR, offset); 117 118 /* Write the data to IDA_DATA register */ 119 wr32(wx, TXGBE_XPCS_IDA_DATA, val); 120 121 return 0; 122 } 123 124 static int txgbe_mdio_pcs_init(struct txgbe *txgbe) 125 { 126 struct mii_bus *mii_bus; 127 struct dw_xpcs *xpcs; 128 struct pci_dev *pdev; 129 struct wx *wx; 130 int ret = 0; 131 132 wx = txgbe->wx; 133 pdev = wx->pdev; 134 135 mii_bus = devm_mdiobus_alloc(&pdev->dev); 136 if (!mii_bus) 137 return -ENOMEM; 138 139 mii_bus->name = "txgbe_pcs_mdio_bus"; 140 mii_bus->read_c45 = &txgbe_pcs_read; 141 mii_bus->write_c45 = &txgbe_pcs_write; 142 mii_bus->parent = &pdev->dev; 143 mii_bus->phy_mask = ~0; 144 mii_bus->priv = wx; 145 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x", 146 pci_dev_id(pdev)); 147 148 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 149 if (ret) 150 return ret; 151 152 xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER); 153 if (IS_ERR(xpcs)) 154 return PTR_ERR(xpcs); 155 156 txgbe->xpcs = xpcs; 157 158 return 0; 159 } 160 161 static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config, 162 phy_interface_t interface) 163 { 164 struct wx *wx = phylink_to_wx(config); 165 struct txgbe *txgbe = wx->priv; 166 167 if (interface == PHY_INTERFACE_MODE_10GBASER) 168 return &txgbe->xpcs->pcs; 169 170 return NULL; 171 } 172 173 static void txgbe_mac_config(struct phylink_config *config, unsigned int mode, 174 const struct phylink_link_state *state) 175 { 176 } 177 178 static void txgbe_mac_link_down(struct phylink_config *config, 179 unsigned int mode, phy_interface_t interface) 180 { 181 struct wx *wx = phylink_to_wx(config); 182 183 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 184 } 185 186 static void txgbe_mac_link_up(struct phylink_config *config, 187 struct phy_device *phy, 188 unsigned int mode, phy_interface_t interface, 189 int speed, int duplex, 190 bool tx_pause, bool rx_pause) 191 { 192 struct wx *wx = phylink_to_wx(config); 193 u32 txcfg, wdg; 194 195 wx_fc_enable(wx, tx_pause, rx_pause); 196 197 txcfg = rd32(wx, WX_MAC_TX_CFG); 198 txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK; 199 200 switch (speed) { 201 case SPEED_10000: 202 txcfg |= WX_MAC_TX_CFG_SPEED_10G; 203 break; 204 case SPEED_1000: 205 case SPEED_100: 206 case SPEED_10: 207 txcfg |= WX_MAC_TX_CFG_SPEED_1G; 208 break; 209 default: 210 break; 211 } 212 213 wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE); 214 215 /* Re configure MAC Rx */ 216 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 217 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 218 wdg = rd32(wx, WX_MAC_WDG_TIMEOUT); 219 wr32(wx, WX_MAC_WDG_TIMEOUT, wdg); 220 } 221 222 static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode, 223 phy_interface_t interface) 224 { 225 struct wx *wx = phylink_to_wx(config); 226 227 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 228 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0); 229 230 return txgbe_disable_sec_tx_path(wx); 231 } 232 233 static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode, 234 phy_interface_t interface) 235 { 236 struct wx *wx = phylink_to_wx(config); 237 238 txgbe_enable_sec_tx_path(wx); 239 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 240 241 return 0; 242 } 243 244 static const struct phylink_mac_ops txgbe_mac_ops = { 245 .mac_select_pcs = txgbe_phylink_mac_select, 246 .mac_prepare = txgbe_mac_prepare, 247 .mac_finish = txgbe_mac_finish, 248 .mac_config = txgbe_mac_config, 249 .mac_link_down = txgbe_mac_link_down, 250 .mac_link_up = txgbe_mac_link_up, 251 }; 252 253 static int txgbe_phylink_init(struct txgbe *txgbe) 254 { 255 struct fwnode_handle *fwnode = NULL; 256 struct phylink_config *config; 257 struct wx *wx = txgbe->wx; 258 phy_interface_t phy_mode; 259 struct phylink *phylink; 260 261 config = &wx->phylink_config; 262 config->dev = &wx->netdev->dev; 263 config->type = PHYLINK_NETDEV; 264 config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD | 265 MAC_SYM_PAUSE | MAC_ASYM_PAUSE; 266 267 if (wx->media_type == sp_media_copper) { 268 phy_mode = PHY_INTERFACE_MODE_XAUI; 269 __set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces); 270 } else { 271 phy_mode = PHY_INTERFACE_MODE_10GBASER; 272 fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]); 273 __set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces); 274 __set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces); 275 __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); 276 } 277 278 phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops); 279 if (IS_ERR(phylink)) 280 return PTR_ERR(phylink); 281 282 if (wx->phydev) { 283 int ret; 284 285 ret = phylink_connect_phy(phylink, wx->phydev); 286 if (ret) { 287 phylink_destroy(phylink); 288 return ret; 289 } 290 } 291 292 wx->phylink = phylink; 293 294 return 0; 295 } 296 297 irqreturn_t txgbe_link_irq_handler(int irq, void *data) 298 { 299 struct txgbe *txgbe = data; 300 struct wx *wx = txgbe->wx; 301 u32 status; 302 bool up; 303 304 status = rd32(wx, TXGBE_CFG_PORT_ST); 305 up = !!(status & TXGBE_CFG_PORT_ST_LINK_UP); 306 307 phylink_mac_change(wx->phylink, up); 308 309 return IRQ_HANDLED; 310 } 311 312 static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset) 313 { 314 struct wx *wx = gpiochip_get_data(chip); 315 int val; 316 317 val = rd32m(wx, WX_GPIO_EXT, BIT(offset)); 318 319 return !!(val & BIT(offset)); 320 } 321 322 static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 323 { 324 struct wx *wx = gpiochip_get_data(chip); 325 u32 val; 326 327 val = rd32(wx, WX_GPIO_DDR); 328 if (BIT(offset) & val) 329 return GPIO_LINE_DIRECTION_OUT; 330 331 return GPIO_LINE_DIRECTION_IN; 332 } 333 334 static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset) 335 { 336 struct wx *wx = gpiochip_get_data(chip); 337 unsigned long flags; 338 339 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 340 wr32m(wx, WX_GPIO_DDR, BIT(offset), 0); 341 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 342 343 return 0; 344 } 345 346 static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset, 347 int val) 348 { 349 struct wx *wx = gpiochip_get_data(chip); 350 unsigned long flags; 351 u32 set; 352 353 set = val ? BIT(offset) : 0; 354 355 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 356 wr32m(wx, WX_GPIO_DR, BIT(offset), set); 357 wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset)); 358 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 359 360 return 0; 361 } 362 363 static void txgbe_gpio_irq_ack(struct irq_data *d) 364 { 365 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 366 irq_hw_number_t hwirq = irqd_to_hwirq(d); 367 struct wx *wx = gpiochip_get_data(gc); 368 unsigned long flags; 369 370 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 371 wr32(wx, WX_GPIO_EOI, BIT(hwirq)); 372 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 373 } 374 375 static void txgbe_gpio_irq_mask(struct irq_data *d) 376 { 377 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 378 irq_hw_number_t hwirq = irqd_to_hwirq(d); 379 struct wx *wx = gpiochip_get_data(gc); 380 unsigned long flags; 381 382 gpiochip_disable_irq(gc, hwirq); 383 384 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 385 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq)); 386 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 387 } 388 389 static void txgbe_gpio_irq_unmask(struct irq_data *d) 390 { 391 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 392 irq_hw_number_t hwirq = irqd_to_hwirq(d); 393 struct wx *wx = gpiochip_get_data(gc); 394 unsigned long flags; 395 396 gpiochip_enable_irq(gc, hwirq); 397 398 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 399 wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0); 400 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 401 } 402 403 static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset) 404 { 405 struct wx *wx = gpiochip_get_data(gc); 406 u32 pol, val; 407 408 pol = rd32(wx, WX_GPIO_POLARITY); 409 val = rd32(wx, WX_GPIO_EXT); 410 411 if (val & BIT(offset)) 412 pol &= ~BIT(offset); 413 else 414 pol |= BIT(offset); 415 416 wr32(wx, WX_GPIO_POLARITY, pol); 417 } 418 419 static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type) 420 { 421 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 422 irq_hw_number_t hwirq = irqd_to_hwirq(d); 423 struct wx *wx = gpiochip_get_data(gc); 424 u32 level, polarity, mask; 425 unsigned long flags; 426 427 mask = BIT(hwirq); 428 429 if (type & IRQ_TYPE_LEVEL_MASK) { 430 level = 0; 431 irq_set_handler_locked(d, handle_level_irq); 432 } else { 433 level = mask; 434 irq_set_handler_locked(d, handle_edge_irq); 435 } 436 437 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) 438 polarity = mask; 439 else 440 polarity = 0; 441 442 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 443 444 wr32m(wx, WX_GPIO_INTEN, mask, mask); 445 wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level); 446 if (type == IRQ_TYPE_EDGE_BOTH) 447 txgbe_toggle_trigger(gc, hwirq); 448 else 449 wr32m(wx, WX_GPIO_POLARITY, mask, polarity); 450 451 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 452 453 return 0; 454 } 455 456 static const struct irq_chip txgbe_gpio_irq_chip = { 457 .name = "txgbe-gpio-irq", 458 .irq_ack = txgbe_gpio_irq_ack, 459 .irq_mask = txgbe_gpio_irq_mask, 460 .irq_unmask = txgbe_gpio_irq_unmask, 461 .irq_set_type = txgbe_gpio_set_type, 462 .flags = IRQCHIP_IMMUTABLE, 463 GPIOCHIP_IRQ_RESOURCE_HELPERS, 464 }; 465 466 irqreturn_t txgbe_gpio_irq_handler(int irq, void *data) 467 { 468 struct txgbe *txgbe = data; 469 struct wx *wx = txgbe->wx; 470 irq_hw_number_t hwirq; 471 unsigned long gpioirq; 472 struct gpio_chip *gc; 473 unsigned long flags; 474 475 gpioirq = rd32(wx, WX_GPIO_INTSTATUS); 476 477 gc = txgbe->gpio; 478 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) { 479 int gpio = irq_find_mapping(gc->irq.domain, hwirq); 480 struct irq_data *d = irq_get_irq_data(gpio); 481 u32 irq_type = irq_get_trigger_type(gpio); 482 483 txgbe_gpio_irq_ack(d); 484 handle_nested_irq(gpio); 485 486 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 487 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 488 txgbe_toggle_trigger(gc, hwirq); 489 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 490 } 491 } 492 493 return IRQ_HANDLED; 494 } 495 496 void txgbe_reinit_gpio_intr(struct wx *wx) 497 { 498 struct txgbe *txgbe = wx->priv; 499 irq_hw_number_t hwirq; 500 unsigned long gpioirq; 501 struct gpio_chip *gc; 502 unsigned long flags; 503 504 /* for gpio interrupt pending before irq enable */ 505 gpioirq = rd32(wx, WX_GPIO_INTSTATUS); 506 507 gc = txgbe->gpio; 508 for_each_set_bit(hwirq, &gpioirq, gc->ngpio) { 509 int gpio = irq_find_mapping(gc->irq.domain, hwirq); 510 struct irq_data *d = irq_get_irq_data(gpio); 511 u32 irq_type = irq_get_trigger_type(gpio); 512 513 txgbe_gpio_irq_ack(d); 514 515 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 516 raw_spin_lock_irqsave(&wx->gpio_lock, flags); 517 txgbe_toggle_trigger(gc, hwirq); 518 raw_spin_unlock_irqrestore(&wx->gpio_lock, flags); 519 } 520 } 521 } 522 523 static int txgbe_gpio_init(struct txgbe *txgbe) 524 { 525 struct gpio_irq_chip *girq; 526 struct gpio_chip *gc; 527 struct device *dev; 528 struct wx *wx; 529 int ret; 530 531 wx = txgbe->wx; 532 dev = &wx->pdev->dev; 533 534 raw_spin_lock_init(&wx->gpio_lock); 535 536 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 537 if (!gc) 538 return -ENOMEM; 539 540 gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x", 541 pci_dev_id(wx->pdev)); 542 if (!gc->label) 543 return -ENOMEM; 544 545 gc->base = -1; 546 gc->ngpio = 6; 547 gc->owner = THIS_MODULE; 548 gc->parent = dev; 549 gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]); 550 gc->get = txgbe_gpio_get; 551 gc->get_direction = txgbe_gpio_get_direction; 552 gc->direction_input = txgbe_gpio_direction_in; 553 gc->direction_output = txgbe_gpio_direction_out; 554 555 girq = &gc->irq; 556 gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip); 557 girq->default_type = IRQ_TYPE_NONE; 558 girq->handler = handle_bad_irq; 559 560 ret = devm_gpiochip_add_data(dev, gc, wx); 561 if (ret) 562 return ret; 563 564 txgbe->gpio = gc; 565 566 return 0; 567 } 568 569 static int txgbe_clock_register(struct txgbe *txgbe) 570 { 571 struct pci_dev *pdev = txgbe->wx->pdev; 572 struct clk_lookup *clock; 573 char clk_name[32]; 574 struct clk *clk; 575 576 snprintf(clk_name, sizeof(clk_name), "%s.%d", 577 TXGBE_I2C_CLK_DEV_NAME, pci_dev_id(pdev)); 578 579 clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000); 580 if (IS_ERR(clk)) 581 return PTR_ERR(clk); 582 583 clock = clkdev_create(clk, NULL, clk_name); 584 if (!clock) { 585 clk_unregister(clk); 586 return -ENOMEM; 587 } 588 589 txgbe->clk = clk; 590 txgbe->clock = clock; 591 592 return 0; 593 } 594 595 static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val) 596 { 597 struct wx *wx = context; 598 599 *val = rd32(wx, reg + TXGBE_I2C_BASE); 600 601 return 0; 602 } 603 604 static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val) 605 { 606 struct wx *wx = context; 607 608 wr32(wx, reg + TXGBE_I2C_BASE, val); 609 610 return 0; 611 } 612 613 static const struct regmap_config i2c_regmap_config = { 614 .reg_bits = 32, 615 .val_bits = 32, 616 .reg_read = txgbe_i2c_read, 617 .reg_write = txgbe_i2c_write, 618 .fast_io = true, 619 }; 620 621 static int txgbe_i2c_register(struct txgbe *txgbe) 622 { 623 struct platform_device_info info = {}; 624 struct platform_device *i2c_dev; 625 struct regmap *i2c_regmap; 626 struct pci_dev *pdev; 627 struct wx *wx; 628 629 wx = txgbe->wx; 630 pdev = wx->pdev; 631 i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config); 632 if (IS_ERR(i2c_regmap)) { 633 wx_err(wx, "failed to init I2C regmap\n"); 634 return PTR_ERR(i2c_regmap); 635 } 636 637 info.parent = &pdev->dev; 638 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]); 639 info.name = TXGBE_I2C_CLK_DEV_NAME; 640 info.id = pci_dev_id(pdev); 641 642 info.res = &DEFINE_RES_IRQ(pdev->irq); 643 info.num_res = 1; 644 i2c_dev = platform_device_register_full(&info); 645 if (IS_ERR(i2c_dev)) 646 return PTR_ERR(i2c_dev); 647 648 txgbe->i2c_dev = i2c_dev; 649 650 return 0; 651 } 652 653 static int txgbe_sfp_register(struct txgbe *txgbe) 654 { 655 struct pci_dev *pdev = txgbe->wx->pdev; 656 struct platform_device_info info = {}; 657 struct platform_device *sfp_dev; 658 659 info.parent = &pdev->dev; 660 info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]); 661 info.name = "sfp"; 662 info.id = pci_dev_id(pdev); 663 sfp_dev = platform_device_register_full(&info); 664 if (IS_ERR(sfp_dev)) 665 return PTR_ERR(sfp_dev); 666 667 txgbe->sfp_dev = sfp_dev; 668 669 return 0; 670 } 671 672 static int txgbe_ext_phy_init(struct txgbe *txgbe) 673 { 674 struct phy_device *phydev; 675 struct mii_bus *mii_bus; 676 struct pci_dev *pdev; 677 struct wx *wx; 678 int ret = 0; 679 680 wx = txgbe->wx; 681 pdev = wx->pdev; 682 683 mii_bus = devm_mdiobus_alloc(&pdev->dev); 684 if (!mii_bus) 685 return -ENOMEM; 686 687 mii_bus->name = "txgbe_mii_bus"; 688 mii_bus->read_c45 = &wx_phy_read_reg_mdi_c45; 689 mii_bus->write_c45 = &wx_phy_write_reg_mdi_c45; 690 mii_bus->parent = &pdev->dev; 691 mii_bus->phy_mask = GENMASK(31, 1); 692 mii_bus->priv = wx; 693 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x", 694 (pdev->bus->number << 8) | pdev->devfn); 695 696 ret = devm_mdiobus_register(&pdev->dev, mii_bus); 697 if (ret) { 698 wx_err(wx, "failed to register MDIO bus: %d\n", ret); 699 return ret; 700 } 701 702 phydev = phy_find_first(mii_bus); 703 if (!phydev) { 704 wx_err(wx, "no PHY found\n"); 705 return -ENODEV; 706 } 707 708 phy_attached_info(phydev); 709 710 wx->link = 0; 711 wx->speed = 0; 712 wx->duplex = 0; 713 wx->phydev = phydev; 714 715 ret = txgbe_phylink_init(txgbe); 716 if (ret) { 717 wx_err(wx, "failed to init phylink: %d\n", ret); 718 return ret; 719 } 720 721 return 0; 722 } 723 724 int txgbe_init_phy(struct txgbe *txgbe) 725 { 726 struct wx *wx = txgbe->wx; 727 int ret; 728 729 if (txgbe->wx->media_type == sp_media_copper) 730 return txgbe_ext_phy_init(txgbe); 731 732 ret = txgbe_swnodes_register(txgbe); 733 if (ret) { 734 wx_err(wx, "failed to register software nodes\n"); 735 return ret; 736 } 737 738 ret = txgbe_mdio_pcs_init(txgbe); 739 if (ret) { 740 wx_err(wx, "failed to init mdio pcs: %d\n", ret); 741 goto err_unregister_swnode; 742 } 743 744 ret = txgbe_phylink_init(txgbe); 745 if (ret) { 746 wx_err(wx, "failed to init phylink\n"); 747 goto err_destroy_xpcs; 748 } 749 750 ret = txgbe_gpio_init(txgbe); 751 if (ret) { 752 wx_err(wx, "failed to init gpio\n"); 753 goto err_destroy_phylink; 754 } 755 756 ret = txgbe_clock_register(txgbe); 757 if (ret) { 758 wx_err(wx, "failed to register clock: %d\n", ret); 759 goto err_destroy_phylink; 760 } 761 762 ret = txgbe_i2c_register(txgbe); 763 if (ret) { 764 wx_err(wx, "failed to init i2c interface: %d\n", ret); 765 goto err_unregister_clk; 766 } 767 768 ret = txgbe_sfp_register(txgbe); 769 if (ret) { 770 wx_err(wx, "failed to register sfp\n"); 771 goto err_unregister_i2c; 772 } 773 774 return 0; 775 776 err_unregister_i2c: 777 platform_device_unregister(txgbe->i2c_dev); 778 err_unregister_clk: 779 clkdev_drop(txgbe->clock); 780 clk_unregister(txgbe->clk); 781 err_destroy_phylink: 782 phylink_destroy(wx->phylink); 783 err_destroy_xpcs: 784 xpcs_destroy(txgbe->xpcs); 785 err_unregister_swnode: 786 software_node_unregister_node_group(txgbe->nodes.group); 787 788 return ret; 789 } 790 791 void txgbe_remove_phy(struct txgbe *txgbe) 792 { 793 if (txgbe->wx->media_type == sp_media_copper) { 794 phylink_disconnect_phy(txgbe->wx->phylink); 795 phylink_destroy(txgbe->wx->phylink); 796 return; 797 } 798 799 platform_device_unregister(txgbe->sfp_dev); 800 platform_device_unregister(txgbe->i2c_dev); 801 clkdev_drop(txgbe->clock); 802 clk_unregister(txgbe->clk); 803 phylink_destroy(txgbe->wx->phylink); 804 xpcs_destroy(txgbe->xpcs); 805 software_node_unregister_node_group(txgbe->nodes.group); 806 } 807