1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/types.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/netdevice.h> 8 #include <linux/string.h> 9 #include <linux/etherdevice.h> 10 #include <linux/phylink.h> 11 #include <net/udp_tunnel.h> 12 #include <net/ip.h> 13 #include <linux/if_vlan.h> 14 15 #include "../libwx/wx_type.h" 16 #include "../libwx/wx_lib.h" 17 #include "../libwx/wx_ptp.h" 18 #include "../libwx/wx_hw.h" 19 #include "../libwx/wx_mbx.h" 20 #include "../libwx/wx_sriov.h" 21 #include "txgbe_type.h" 22 #include "txgbe_hw.h" 23 #include "txgbe_phy.h" 24 #include "txgbe_aml.h" 25 #include "txgbe_irq.h" 26 #include "txgbe_fdir.h" 27 #include "txgbe_ethtool.h" 28 29 char txgbe_driver_name[] = "txgbe"; 30 31 /* txgbe_pci_tbl - PCI Device ID Table 32 * 33 * Wildcard entries (PCI_ANY_ID) should come last 34 * Last entry must be all 0s 35 * 36 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, 37 * Class, Class Mask, private data (not used) } 38 */ 39 static const struct pci_device_id txgbe_pci_tbl[] = { 40 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_SP1000), 0}, 41 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_WX1820), 0}, 42 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5010), 0}, 43 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5110), 0}, 44 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5025), 0}, 45 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5125), 0}, 46 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5040), 0}, 47 { PCI_VDEVICE(WANGXUN, TXGBE_DEV_ID_AML5140), 0}, 48 /* required last entry */ 49 { .device = 0 } 50 }; 51 52 #define DEFAULT_DEBUG_LEVEL_SHIFT 3 53 54 static void txgbe_check_minimum_link(struct wx *wx) 55 { 56 struct pci_dev *pdev; 57 58 pdev = wx->pdev; 59 pcie_print_link_status(pdev); 60 } 61 62 /** 63 * txgbe_enumerate_functions - Get the number of ports this device has 64 * @wx: wx structure 65 * 66 * This function enumerates the phsyical functions co-located on a single slot, 67 * in order to determine how many ports a device has. This is most useful in 68 * determining the required GT/s of PCIe bandwidth necessary for optimal 69 * performance. 70 **/ 71 static int txgbe_enumerate_functions(struct wx *wx) 72 { 73 struct pci_dev *entry, *pdev = wx->pdev; 74 int physfns = 0; 75 76 list_for_each_entry(entry, &pdev->bus->devices, bus_list) { 77 /* When the devices on the bus don't all match our device ID, 78 * we can't reliably determine the correct number of 79 * functions. This can occur if a function has been direct 80 * attached to a virtual machine using VT-d. 81 */ 82 if (entry->vendor != pdev->vendor || 83 entry->device != pdev->device) 84 return -EINVAL; 85 86 physfns++; 87 } 88 89 return physfns; 90 } 91 92 static void txgbe_sfp_detection_subtask(struct wx *wx) 93 { 94 int err; 95 96 if (!test_bit(WX_FLAG_NEED_SFP_RESET, wx->flags)) 97 return; 98 99 /* wait for SFP module ready */ 100 msleep(200); 101 102 err = txgbe_identify_sfp(wx); 103 if (err) 104 return; 105 106 clear_bit(WX_FLAG_NEED_SFP_RESET, wx->flags); 107 } 108 109 static void txgbe_link_config_subtask(struct wx *wx) 110 { 111 int err; 112 113 if (!test_bit(WX_FLAG_NEED_LINK_CONFIG, wx->flags)) 114 return; 115 116 err = txgbe_set_phy_link(wx); 117 if (err) 118 return; 119 120 clear_bit(WX_FLAG_NEED_LINK_CONFIG, wx->flags); 121 } 122 123 /** 124 * txgbe_service_task - manages and runs subtasks 125 * @work: pointer to work_struct containing our data 126 **/ 127 static void txgbe_service_task(struct work_struct *work) 128 { 129 struct wx *wx = container_of(work, struct wx, service_task); 130 131 txgbe_sfp_detection_subtask(wx); 132 txgbe_link_config_subtask(wx); 133 134 wx_service_event_complete(wx); 135 } 136 137 static void txgbe_init_service(struct wx *wx) 138 { 139 timer_setup(&wx->service_timer, wx_service_timer, 0); 140 INIT_WORK(&wx->service_task, txgbe_service_task); 141 clear_bit(WX_STATE_SERVICE_SCHED, wx->state); 142 } 143 144 static void txgbe_up_complete(struct wx *wx) 145 { 146 struct net_device *netdev = wx->netdev; 147 u32 reg; 148 149 wx_control_hw(wx, true); 150 wx_configure_vectors(wx); 151 152 /* make sure to complete pre-operations */ 153 smp_mb__before_atomic(); 154 wx_napi_enable_all(wx); 155 156 switch (wx->mac.type) { 157 case wx_mac_aml40: 158 reg = rd32(wx, TXGBE_AML_MAC_TX_CFG); 159 reg &= ~TXGBE_AML_MAC_TX_CFG_SPEED_MASK; 160 reg |= TXGBE_AML_MAC_TX_CFG_SPEED_40G; 161 wr32(wx, WX_MAC_TX_CFG, reg); 162 txgbe_enable_sec_tx_path(wx); 163 netif_carrier_on(wx->netdev); 164 break; 165 case wx_mac_aml: 166 /* Enable TX laser */ 167 wr32m(wx, WX_GPIO_DR, TXGBE_GPIOBIT_1, 0); 168 txgbe_setup_link(wx); 169 phylink_start(wx->phylink); 170 break; 171 case wx_mac_sp: 172 phylink_start(wx->phylink); 173 break; 174 default: 175 break; 176 } 177 178 /* clear any pending interrupts, may auto mask */ 179 rd32(wx, WX_PX_IC(0)); 180 rd32(wx, WX_PX_IC(1)); 181 rd32(wx, WX_PX_MISC_IC); 182 txgbe_irq_enable(wx, true); 183 184 /* enable transmits */ 185 netif_tx_start_all_queues(netdev); 186 mod_timer(&wx->service_timer, jiffies); 187 188 /* Set PF Reset Done bit so PF/VF Mail Ops can work */ 189 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_PFRSTD, 190 WX_CFG_PORT_CTL_PFRSTD); 191 /* update setting rx tx for all active vfs */ 192 wx_set_all_vfs(wx); 193 } 194 195 static void txgbe_reset(struct wx *wx) 196 { 197 struct net_device *netdev = wx->netdev; 198 u8 old_addr[ETH_ALEN]; 199 int err; 200 201 err = txgbe_reset_hw(wx); 202 if (err != 0) 203 wx_err(wx, "Hardware Error: %d\n", err); 204 205 wx_start_hw(wx); 206 /* do not flush user set addresses */ 207 memcpy(old_addr, &wx->mac_table[0].addr, netdev->addr_len); 208 wx_flush_sw_mac_table(wx); 209 wx_mac_set_default_filter(wx, old_addr); 210 211 if (test_bit(WX_STATE_PTP_RUNNING, wx->state)) 212 wx_ptp_reset(wx); 213 } 214 215 static void txgbe_disable_device(struct wx *wx) 216 { 217 struct net_device *netdev = wx->netdev; 218 u32 i; 219 220 wx_disable_pcie_master(wx); 221 /* disable receives */ 222 wx_disable_rx(wx); 223 224 /* disable all enabled rx queues */ 225 for (i = 0; i < wx->num_rx_queues; i++) 226 /* this call also flushes the previous write */ 227 wx_disable_rx_queue(wx, wx->rx_ring[i]); 228 229 netif_tx_stop_all_queues(netdev); 230 netif_tx_disable(netdev); 231 232 wx_irq_disable(wx); 233 wx_napi_disable_all(wx); 234 235 timer_delete_sync(&wx->service_timer); 236 237 if (wx->bus.func < 2) 238 wr32m(wx, TXGBE_MIS_PRB_CTL, TXGBE_MIS_PRB_CTL_LAN_UP(wx->bus.func), 0); 239 else 240 wx_err(wx, "%s: invalid bus lan id %d\n", 241 __func__, wx->bus.func); 242 243 if (wx->num_vfs) { 244 /* Clear EITR Select mapping */ 245 wr32(wx, WX_PX_ITRSEL, 0); 246 /* Mark all the VFs as inactive */ 247 for (i = 0; i < wx->num_vfs; i++) 248 wx->vfinfo[i].clear_to_send = 0; 249 /* update setting rx tx for all active vfs */ 250 wx_set_all_vfs(wx); 251 } 252 253 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 254 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 255 /* disable mac transmiter */ 256 wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0); 257 } 258 259 /* disable transmits in the hardware now that interrupts are off */ 260 for (i = 0; i < wx->num_tx_queues; i++) { 261 u8 reg_idx = wx->tx_ring[i]->reg_idx; 262 263 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH); 264 } 265 266 /* Disable the Tx DMA engine */ 267 wr32m(wx, WX_TDM_CTL, WX_TDM_CTL_TE, 0); 268 269 wx_update_stats(wx); 270 } 271 272 void txgbe_down(struct wx *wx) 273 { 274 txgbe_disable_device(wx); 275 txgbe_reset(wx); 276 277 switch (wx->mac.type) { 278 case wx_mac_aml40: 279 netif_carrier_off(wx->netdev); 280 break; 281 case wx_mac_aml: 282 phylink_stop(wx->phylink); 283 /* Disable TX laser */ 284 wr32m(wx, WX_GPIO_DR, TXGBE_GPIOBIT_1, TXGBE_GPIOBIT_1); 285 break; 286 case wx_mac_sp: 287 phylink_stop(wx->phylink); 288 break; 289 default: 290 break; 291 } 292 293 wx_clean_all_tx_rings(wx); 294 wx_clean_all_rx_rings(wx); 295 } 296 297 void txgbe_up(struct wx *wx) 298 { 299 wx_configure(wx); 300 wx_ptp_init(wx); 301 txgbe_up_complete(wx); 302 } 303 304 /** 305 * txgbe_init_type_code - Initialize the shared code 306 * @wx: pointer to hardware structure 307 **/ 308 static void txgbe_init_type_code(struct wx *wx) 309 { 310 u8 device_type = wx->subsystem_device_id & 0xF0; 311 312 switch (wx->device_id) { 313 case TXGBE_DEV_ID_SP1000: 314 case TXGBE_DEV_ID_WX1820: 315 wx->mac.type = wx_mac_sp; 316 break; 317 case TXGBE_DEV_ID_AML5010: 318 case TXGBE_DEV_ID_AML5110: 319 case TXGBE_DEV_ID_AML5025: 320 case TXGBE_DEV_ID_AML5125: 321 wx->mac.type = wx_mac_aml; 322 break; 323 case TXGBE_DEV_ID_AML5040: 324 case TXGBE_DEV_ID_AML5140: 325 wx->mac.type = wx_mac_aml40; 326 break; 327 default: 328 wx->mac.type = wx_mac_unknown; 329 break; 330 } 331 332 switch (device_type) { 333 case TXGBE_ID_SFP: 334 wx->media_type = wx_media_fiber; 335 break; 336 case TXGBE_ID_XAUI: 337 case TXGBE_ID_SGMII: 338 wx->media_type = wx_media_copper; 339 break; 340 case TXGBE_ID_KR_KX_KX4: 341 case TXGBE_ID_MAC_XAUI: 342 case TXGBE_ID_MAC_SGMII: 343 wx->media_type = wx_media_backplane; 344 break; 345 case TXGBE_ID_SFI_XAUI: 346 if (wx->bus.func == 0) 347 wx->media_type = wx_media_fiber; 348 else 349 wx->media_type = wx_media_copper; 350 break; 351 default: 352 wx->media_type = wx_media_unknown; 353 break; 354 } 355 } 356 357 /** 358 * txgbe_sw_init - Initialize general software structures (struct wx) 359 * @wx: board private structure to initialize 360 **/ 361 static int txgbe_sw_init(struct wx *wx) 362 { 363 u16 msix_count = 0; 364 int err; 365 366 wx->mac.num_rar_entries = TXGBE_RAR_ENTRIES; 367 wx->mac.max_tx_queues = TXGBE_MAX_TXQ; 368 wx->mac.max_rx_queues = TXGBE_MAX_RXQ; 369 wx->mac.mcft_size = TXGBE_MC_TBL_SIZE; 370 wx->mac.vft_size = TXGBE_VFT_TBL_SIZE; 371 wx->mac.rx_pb_size = TXGBE_RX_PB_SIZE; 372 wx->mac.tx_pb_size = TXGBE_TDB_PB_SZ; 373 374 /* PCI config space info */ 375 err = wx_sw_init(wx); 376 if (err < 0) 377 return err; 378 379 txgbe_init_type_code(wx); 380 381 /* Set common capability flags and settings */ 382 wx->max_q_vectors = TXGBE_MAX_MSIX_VECTORS; 383 err = wx_get_pcie_msix_counts(wx, &msix_count, TXGBE_MAX_MSIX_VECTORS); 384 if (err) 385 wx_err(wx, "Do not support MSI-X\n"); 386 wx->mac.max_msix_vectors = msix_count; 387 388 wx->ring_feature[RING_F_RSS].limit = min_t(int, TXGBE_MAX_RSS_INDICES, 389 num_online_cpus()); 390 wx->rss_enabled = true; 391 392 wx->ring_feature[RING_F_FDIR].limit = min_t(int, TXGBE_MAX_FDIR_INDICES, 393 num_online_cpus()); 394 set_bit(WX_FLAG_FDIR_CAPABLE, wx->flags); 395 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 396 wx->atr_sample_rate = TXGBE_DEFAULT_ATR_SAMPLE_RATE; 397 wx->atr = txgbe_atr; 398 wx->configure_fdir = txgbe_configure_fdir; 399 400 set_bit(WX_FLAG_RSC_CAPABLE, wx->flags); 401 set_bit(WX_FLAG_MULTI_64_FUNC, wx->flags); 402 403 /* enable itr by default in dynamic mode */ 404 wx->adaptive_itr = true; 405 wx->rx_itr_setting = 1; 406 wx->tx_itr_setting = 1; 407 408 /* set default ring sizes */ 409 wx->tx_ring_count = TXGBE_DEFAULT_TXD; 410 wx->rx_ring_count = TXGBE_DEFAULT_RXD; 411 wx->mbx.size = WX_VXMAILBOX_SIZE; 412 413 /* set default work limits */ 414 wx->tx_work_limit = TXGBE_DEFAULT_TX_WORK; 415 wx->rx_work_limit = TXGBE_DEFAULT_RX_WORK; 416 417 wx->setup_tc = txgbe_setup_tc; 418 wx->do_reset = txgbe_do_reset; 419 set_bit(0, &wx->fwd_bitmask); 420 421 switch (wx->mac.type) { 422 case wx_mac_sp: 423 break; 424 case wx_mac_aml: 425 case wx_mac_aml40: 426 set_bit(WX_FLAG_SWFW_RING, wx->flags); 427 wx->swfw_index = 0; 428 break; 429 default: 430 break; 431 } 432 433 return 0; 434 } 435 436 static void txgbe_init_fdir(struct txgbe *txgbe) 437 { 438 txgbe->fdir_filter_count = 0; 439 spin_lock_init(&txgbe->fdir_perfect_lock); 440 } 441 442 /** 443 * txgbe_open - Called when a network interface is made active 444 * @netdev: network interface device structure 445 * 446 * Returns 0 on success, negative value on failure 447 * 448 * The open entry point is called when a network interface is made 449 * active by the system (IFF_UP). 450 **/ 451 static int txgbe_open(struct net_device *netdev) 452 { 453 struct wx *wx = netdev_priv(netdev); 454 int err; 455 456 err = wx_setup_resources(wx); 457 if (err) 458 goto err_reset; 459 460 wx_configure(wx); 461 462 err = txgbe_setup_misc_irq(wx->priv); 463 if (err) 464 goto err_free_resources; 465 466 err = txgbe_request_queue_irqs(wx); 467 if (err) 468 goto err_free_misc_irq; 469 470 /* Notify the stack of the actual queue counts. */ 471 err = netif_set_real_num_tx_queues(netdev, wx->num_tx_queues); 472 if (err) 473 goto err_free_irq; 474 475 err = netif_set_real_num_rx_queues(netdev, wx->num_rx_queues); 476 if (err) 477 goto err_free_irq; 478 479 wx_ptp_init(wx); 480 481 txgbe_up_complete(wx); 482 483 return 0; 484 485 err_free_irq: 486 wx_free_irq(wx); 487 err_free_misc_irq: 488 txgbe_free_misc_irq(wx->priv); 489 wx_reset_interrupt_capability(wx); 490 err_free_resources: 491 wx_free_resources(wx); 492 err_reset: 493 txgbe_reset(wx); 494 495 return err; 496 } 497 498 /** 499 * txgbe_close_suspend - actions necessary to both suspend and close flows 500 * @wx: the private wx struct 501 * 502 * This function should contain the necessary work common to both suspending 503 * and closing of the device. 504 */ 505 static void txgbe_close_suspend(struct wx *wx) 506 { 507 wx_ptp_suspend(wx); 508 txgbe_disable_device(wx); 509 wx_free_resources(wx); 510 } 511 512 /** 513 * txgbe_close - Disables a network interface 514 * @netdev: network interface device structure 515 * 516 * Returns 0, this is not allowed to fail 517 * 518 * The close entry point is called when an interface is de-activated 519 * by the OS. The hardware is still under the drivers control, but 520 * needs to be disabled. A global MAC reset is issued to stop the 521 * hardware, and all transmit and receive resources are freed. 522 **/ 523 static int txgbe_close(struct net_device *netdev) 524 { 525 struct wx *wx = netdev_priv(netdev); 526 527 wx_ptp_stop(wx); 528 txgbe_down(wx); 529 wx_free_irq(wx); 530 txgbe_free_misc_irq(wx->priv); 531 wx_free_resources(wx); 532 txgbe_fdir_filter_exit(wx); 533 wx_control_hw(wx, false); 534 535 return 0; 536 } 537 538 static void txgbe_dev_shutdown(struct pci_dev *pdev) 539 { 540 struct wx *wx = pci_get_drvdata(pdev); 541 struct net_device *netdev; 542 543 netdev = wx->netdev; 544 netif_device_detach(netdev); 545 546 rtnl_lock(); 547 if (netif_running(netdev)) 548 txgbe_close_suspend(wx); 549 rtnl_unlock(); 550 551 wx_control_hw(wx, false); 552 553 pci_disable_device(pdev); 554 } 555 556 static void txgbe_shutdown(struct pci_dev *pdev) 557 { 558 txgbe_dev_shutdown(pdev); 559 560 if (system_state == SYSTEM_POWER_OFF) { 561 pci_wake_from_d3(pdev, false); 562 pci_set_power_state(pdev, PCI_D3hot); 563 } 564 } 565 566 /** 567 * txgbe_setup_tc - routine to configure net_device for multiple traffic 568 * classes. 569 * 570 * @dev: net device to configure 571 * @tc: number of traffic classes to enable 572 */ 573 int txgbe_setup_tc(struct net_device *dev, u8 tc) 574 { 575 struct wx *wx = netdev_priv(dev); 576 577 /* Hardware has to reinitialize queues and interrupts to 578 * match packet buffer alignment. Unfortunately, the 579 * hardware is not flexible enough to do this dynamically. 580 */ 581 if (netif_running(dev)) 582 txgbe_close(dev); 583 else 584 txgbe_reset(wx); 585 586 wx_clear_interrupt_scheme(wx); 587 588 if (tc) 589 netdev_set_num_tc(dev, tc); 590 else 591 netdev_reset_tc(dev); 592 593 wx_init_interrupt_scheme(wx); 594 595 if (netif_running(dev)) 596 txgbe_open(dev); 597 598 return 0; 599 } 600 601 static void txgbe_reinit_locked(struct wx *wx) 602 { 603 int err = 0; 604 605 netif_trans_update(wx->netdev); 606 607 err = wx_set_state_reset(wx); 608 if (err) { 609 wx_err(wx, "wait device reset timeout\n"); 610 return; 611 } 612 613 txgbe_down(wx); 614 txgbe_up(wx); 615 616 clear_bit(WX_STATE_RESETTING, wx->state); 617 } 618 619 void txgbe_do_reset(struct net_device *netdev) 620 { 621 struct wx *wx = netdev_priv(netdev); 622 623 if (netif_running(netdev)) 624 txgbe_reinit_locked(wx); 625 else 626 txgbe_reset(wx); 627 } 628 629 static int txgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table) 630 { 631 struct wx *wx = netdev_priv(dev); 632 struct udp_tunnel_info ti; 633 634 udp_tunnel_nic_get_port(dev, table, 0, &ti); 635 switch (ti.type) { 636 case UDP_TUNNEL_TYPE_VXLAN: 637 wr32(wx, TXGBE_CFG_VXLAN, ntohs(ti.port)); 638 break; 639 case UDP_TUNNEL_TYPE_VXLAN_GPE: 640 wr32(wx, TXGBE_CFG_VXLAN_GPE, ntohs(ti.port)); 641 break; 642 case UDP_TUNNEL_TYPE_GENEVE: 643 wr32(wx, TXGBE_CFG_GENEVE, ntohs(ti.port)); 644 break; 645 default: 646 break; 647 } 648 649 return 0; 650 } 651 652 static const struct udp_tunnel_nic_info txgbe_udp_tunnels = { 653 .sync_table = txgbe_udp_tunnel_sync, 654 .flags = UDP_TUNNEL_NIC_INFO_OPEN_ONLY, 655 .tables = { 656 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, }, 657 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN_GPE, }, 658 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, }, 659 }, 660 }; 661 662 static const struct net_device_ops txgbe_netdev_ops = { 663 .ndo_open = txgbe_open, 664 .ndo_stop = txgbe_close, 665 .ndo_change_mtu = wx_change_mtu, 666 .ndo_start_xmit = wx_xmit_frame, 667 .ndo_set_rx_mode = wx_set_rx_mode, 668 .ndo_set_features = wx_set_features, 669 .ndo_fix_features = wx_fix_features, 670 .ndo_features_check = wx_features_check, 671 .ndo_validate_addr = eth_validate_addr, 672 .ndo_set_mac_address = wx_set_mac, 673 .ndo_get_stats64 = wx_get_stats64, 674 .ndo_vlan_rx_add_vid = wx_vlan_rx_add_vid, 675 .ndo_vlan_rx_kill_vid = wx_vlan_rx_kill_vid, 676 .ndo_hwtstamp_set = wx_hwtstamp_set, 677 .ndo_hwtstamp_get = wx_hwtstamp_get, 678 }; 679 680 /** 681 * txgbe_probe - Device Initialization Routine 682 * @pdev: PCI device information struct 683 * @ent: entry in txgbe_pci_tbl 684 * 685 * Returns 0 on success, negative on failure 686 * 687 * txgbe_probe initializes an adapter identified by a pci_dev structure. 688 * The OS initialization, configuring of the wx private structure, 689 * and a hardware reset occur. 690 **/ 691 static int txgbe_probe(struct pci_dev *pdev, 692 const struct pci_device_id __always_unused *ent) 693 { 694 struct net_device *netdev; 695 int err, expected_gts; 696 struct wx *wx = NULL; 697 struct txgbe *txgbe; 698 699 u16 eeprom_verh = 0, eeprom_verl = 0, offset = 0; 700 u16 eeprom_cfg_blkh = 0, eeprom_cfg_blkl = 0; 701 u16 build = 0, major = 0, patch = 0; 702 u32 etrack_id = 0; 703 704 err = pci_enable_device_mem(pdev); 705 if (err) 706 return err; 707 708 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 709 if (err) { 710 dev_err(&pdev->dev, 711 "No usable DMA configuration, aborting\n"); 712 goto err_pci_disable_dev; 713 } 714 715 err = pci_request_selected_regions(pdev, 716 pci_select_bars(pdev, IORESOURCE_MEM), 717 txgbe_driver_name); 718 if (err) { 719 dev_err(&pdev->dev, 720 "pci_request_selected_regions failed 0x%x\n", err); 721 goto err_pci_disable_dev; 722 } 723 724 pci_set_master(pdev); 725 726 netdev = devm_alloc_etherdev_mqs(&pdev->dev, 727 sizeof(struct wx), 728 TXGBE_MAX_TX_QUEUES, 729 TXGBE_MAX_RX_QUEUES); 730 if (!netdev) { 731 err = -ENOMEM; 732 goto err_pci_release_regions; 733 } 734 735 SET_NETDEV_DEV(netdev, &pdev->dev); 736 737 wx = netdev_priv(netdev); 738 wx->netdev = netdev; 739 wx->pdev = pdev; 740 741 wx->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; 742 743 wx->hw_addr = devm_ioremap(&pdev->dev, 744 pci_resource_start(pdev, 0), 745 pci_resource_len(pdev, 0)); 746 if (!wx->hw_addr) { 747 err = -EIO; 748 goto err_pci_release_regions; 749 } 750 751 /* The sapphire supports up to 63 VFs per pf, but physical 752 * function also need one pool for basic networking. 753 */ 754 pci_sriov_set_totalvfs(pdev, TXGBE_MAX_VFS_DRV_LIMIT); 755 wx->driver_name = txgbe_driver_name; 756 txgbe_set_ethtool_ops(netdev); 757 netdev->netdev_ops = &txgbe_netdev_ops; 758 netdev->udp_tunnel_nic_info = &txgbe_udp_tunnels; 759 760 /* setup the private structure */ 761 err = txgbe_sw_init(wx); 762 if (err) 763 goto err_pci_release_regions; 764 765 /* check if flash load is done after hw power up */ 766 err = wx_check_flash_load(wx, TXGBE_SPI_ILDR_STATUS_PERST); 767 if (err) 768 goto err_free_mac_table; 769 err = wx_check_flash_load(wx, TXGBE_SPI_ILDR_STATUS_PWRRST); 770 if (err) 771 goto err_free_mac_table; 772 773 err = wx_mng_present(wx); 774 if (err) { 775 dev_err(&pdev->dev, "Management capability is not present\n"); 776 goto err_free_mac_table; 777 } 778 779 err = txgbe_reset_hw(wx); 780 if (err) { 781 dev_err(&pdev->dev, "HW Init failed: %d\n", err); 782 goto err_free_mac_table; 783 } 784 785 netdev->features = NETIF_F_SG | 786 NETIF_F_TSO | 787 NETIF_F_TSO6 | 788 NETIF_F_RXHASH | 789 NETIF_F_RXCSUM | 790 NETIF_F_HW_CSUM; 791 792 netdev->gso_partial_features = NETIF_F_GSO_ENCAP_ALL; 793 netdev->features |= netdev->gso_partial_features; 794 netdev->features |= NETIF_F_SCTP_CRC; 795 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; 796 netdev->hw_enc_features |= netdev->vlan_features; 797 netdev->features |= NETIF_F_VLAN_FEATURES; 798 /* copy netdev features into list of user selectable features */ 799 netdev->hw_features |= netdev->features | NETIF_F_RXALL; 800 netdev->hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC; 801 netdev->features |= NETIF_F_HIGHDMA; 802 netdev->hw_features |= NETIF_F_GRO; 803 netdev->features |= NETIF_F_GRO; 804 netdev->features |= NETIF_F_RX_UDP_TUNNEL_PORT; 805 806 netdev->priv_flags |= IFF_UNICAST_FLT; 807 netdev->priv_flags |= IFF_SUPP_NOFCS; 808 netdev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 809 810 netdev->min_mtu = ETH_MIN_MTU; 811 netdev->max_mtu = WX_MAX_JUMBO_FRAME_SIZE - 812 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); 813 814 /* make sure the EEPROM is good */ 815 err = txgbe_validate_eeprom_checksum(wx, NULL); 816 if (err != 0) { 817 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n"); 818 wr32(wx, WX_MIS_RST, WX_MIS_RST_SW_RST); 819 err = -EIO; 820 goto err_free_mac_table; 821 } 822 823 eth_hw_addr_set(netdev, wx->mac.perm_addr); 824 wx_mac_set_default_filter(wx, wx->mac.perm_addr); 825 826 txgbe_init_service(wx); 827 828 err = wx_init_interrupt_scheme(wx); 829 if (err) 830 goto err_cancel_service; 831 832 /* Save off EEPROM version number and Option Rom version which 833 * together make a unique identify for the eeprom 834 */ 835 wx_read_ee_hostif(wx, 836 wx->eeprom.sw_region_offset + TXGBE_EEPROM_VERSION_H, 837 &eeprom_verh); 838 wx_read_ee_hostif(wx, 839 wx->eeprom.sw_region_offset + TXGBE_EEPROM_VERSION_L, 840 &eeprom_verl); 841 etrack_id = (eeprom_verh << 16) | eeprom_verl; 842 843 wx_read_ee_hostif(wx, 844 wx->eeprom.sw_region_offset + TXGBE_ISCSI_BOOT_CONFIG, 845 &offset); 846 847 /* Make sure offset to SCSI block is valid */ 848 if (!(offset == 0x0) && !(offset == 0xffff)) { 849 wx_read_ee_hostif(wx, offset + 0x84, &eeprom_cfg_blkh); 850 wx_read_ee_hostif(wx, offset + 0x83, &eeprom_cfg_blkl); 851 852 /* Only display Option Rom if exist */ 853 if (eeprom_cfg_blkl && eeprom_cfg_blkh) { 854 major = eeprom_cfg_blkl >> 8; 855 build = (eeprom_cfg_blkl << 8) | (eeprom_cfg_blkh >> 8); 856 patch = eeprom_cfg_blkh & 0x00ff; 857 858 snprintf(wx->eeprom_id, sizeof(wx->eeprom_id), 859 "0x%08x, %d.%d.%d", etrack_id, major, build, 860 patch); 861 } else { 862 snprintf(wx->eeprom_id, sizeof(wx->eeprom_id), 863 "0x%08x", etrack_id); 864 } 865 } else { 866 snprintf(wx->eeprom_id, sizeof(wx->eeprom_id), 867 "0x%08x", etrack_id); 868 } 869 870 if (etrack_id < 0x20010) 871 dev_warn(&pdev->dev, "Please upgrade the firmware to 0x20010 or above.\n"); 872 873 err = txgbe_test_hostif(wx); 874 if (err != 0) { 875 dev_err(&pdev->dev, "Mismatched Firmware version\n"); 876 err = -EIO; 877 goto err_release_hw; 878 } 879 880 txgbe = devm_kzalloc(&pdev->dev, sizeof(*txgbe), GFP_KERNEL); 881 if (!txgbe) { 882 err = -ENOMEM; 883 goto err_release_hw; 884 } 885 886 txgbe->wx = wx; 887 wx->priv = txgbe; 888 889 txgbe_init_fdir(txgbe); 890 891 err = txgbe_init_phy(txgbe); 892 if (err) 893 goto err_release_hw; 894 895 err = register_netdev(netdev); 896 if (err) 897 goto err_remove_phy; 898 899 pci_set_drvdata(pdev, wx); 900 901 netif_tx_stop_all_queues(netdev); 902 903 /* calculate the expected PCIe bandwidth required for optimal 904 * performance. Note that some older parts will never have enough 905 * bandwidth due to being older generation PCIe parts. We clamp these 906 * parts to ensure that no warning is displayed, as this could confuse 907 * users otherwise. 908 */ 909 expected_gts = txgbe_enumerate_functions(wx) * 10; 910 911 /* don't check link if we failed to enumerate functions */ 912 if (expected_gts > 0) 913 txgbe_check_minimum_link(wx); 914 else 915 dev_warn(&pdev->dev, "Failed to enumerate PF devices.\n"); 916 917 return 0; 918 919 err_remove_phy: 920 txgbe_remove_phy(txgbe); 921 err_release_hw: 922 wx_clear_interrupt_scheme(wx); 923 wx_control_hw(wx, false); 924 err_cancel_service: 925 timer_delete_sync(&wx->service_timer); 926 cancel_work_sync(&wx->service_task); 927 err_free_mac_table: 928 kfree(wx->rss_key); 929 kfree(wx->mac_table); 930 err_pci_release_regions: 931 pci_release_selected_regions(pdev, 932 pci_select_bars(pdev, IORESOURCE_MEM)); 933 err_pci_disable_dev: 934 pci_disable_device(pdev); 935 return err; 936 } 937 938 /** 939 * txgbe_remove - Device Removal Routine 940 * @pdev: PCI device information struct 941 * 942 * txgbe_remove is called by the PCI subsystem to alert the driver 943 * that it should release a PCI device. The could be caused by a 944 * Hot-Plug event, or because the driver is going to be removed from 945 * memory. 946 **/ 947 static void txgbe_remove(struct pci_dev *pdev) 948 { 949 struct wx *wx = pci_get_drvdata(pdev); 950 struct txgbe *txgbe = wx->priv; 951 struct net_device *netdev; 952 953 cancel_work_sync(&wx->service_task); 954 955 netdev = wx->netdev; 956 wx_disable_sriov(wx); 957 unregister_netdev(netdev); 958 959 txgbe_remove_phy(txgbe); 960 wx_free_isb_resources(wx); 961 962 pci_release_selected_regions(pdev, 963 pci_select_bars(pdev, IORESOURCE_MEM)); 964 965 kfree(wx->rss_key); 966 kfree(wx->mac_table); 967 wx_clear_interrupt_scheme(wx); 968 969 pci_disable_device(pdev); 970 } 971 972 static struct pci_driver txgbe_driver = { 973 .name = txgbe_driver_name, 974 .id_table = txgbe_pci_tbl, 975 .probe = txgbe_probe, 976 .remove = txgbe_remove, 977 .shutdown = txgbe_shutdown, 978 .sriov_configure = wx_pci_sriov_configure, 979 }; 980 981 module_pci_driver(txgbe_driver); 982 983 MODULE_DEVICE_TABLE(pci, txgbe_pci_tbl); 984 MODULE_AUTHOR("Beijing WangXun Technology Co., Ltd, <software@trustnetic.com>"); 985 MODULE_DESCRIPTION("WangXun(R) 10/25/40 Gigabit PCI Express Network Driver"); 986 MODULE_LICENSE("GPL"); 987