1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2024 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/irqdomain.h> 5 #include <linux/pci.h> 6 7 #include "../libwx/wx_type.h" 8 #include "../libwx/wx_lib.h" 9 #include "../libwx/wx_hw.h" 10 #include "../libwx/wx_sriov.h" 11 #include "txgbe_type.h" 12 #include "txgbe_phy.h" 13 #include "txgbe_irq.h" 14 15 /** 16 * txgbe_irq_enable - Enable default interrupt generation settings 17 * @wx: pointer to private structure 18 * @queues: enable irqs for queues 19 **/ 20 void txgbe_irq_enable(struct wx *wx, bool queues) 21 { 22 wr32(wx, WX_PX_MISC_IEN, TXGBE_PX_MISC_IEN_MASK); 23 24 /* unmask interrupt */ 25 wx_intr_enable(wx, TXGBE_INTR_MISC); 26 if (queues) 27 wx_intr_enable(wx, TXGBE_INTR_QALL(wx)); 28 } 29 30 /** 31 * txgbe_request_queue_irqs - Initialize MSI-X queue interrupts 32 * @wx: board private structure 33 * 34 * Allocate MSI-X queue vectors and request interrupts from the kernel. 35 **/ 36 int txgbe_request_queue_irqs(struct wx *wx) 37 { 38 struct net_device *netdev = wx->netdev; 39 int vector, err; 40 41 if (!wx->pdev->msix_enabled) 42 return 0; 43 44 for (vector = 0; vector < wx->num_q_vectors; vector++) { 45 struct wx_q_vector *q_vector = wx->q_vector[vector]; 46 struct msix_entry *entry = &wx->msix_q_entries[vector]; 47 48 if (q_vector->tx.ring && q_vector->rx.ring) 49 snprintf(q_vector->name, sizeof(q_vector->name) - 1, 50 "%s-TxRx-%d", netdev->name, entry->entry); 51 else 52 /* skip this unused q_vector */ 53 continue; 54 55 err = request_irq(entry->vector, wx_msix_clean_rings, 0, 56 q_vector->name, q_vector); 57 if (err) { 58 wx_err(wx, "request_irq failed for MSIX interrupt %s Error: %d\n", 59 q_vector->name, err); 60 goto free_queue_irqs; 61 } 62 } 63 64 return 0; 65 66 free_queue_irqs: 67 while (vector) { 68 vector--; 69 free_irq(wx->msix_q_entries[vector].vector, 70 wx->q_vector[vector]); 71 } 72 wx_reset_interrupt_capability(wx); 73 return err; 74 } 75 76 static int txgbe_request_link_irq(struct txgbe *txgbe) 77 { 78 txgbe->link_irq = irq_find_mapping(txgbe->misc.domain, TXGBE_IRQ_LINK); 79 return request_threaded_irq(txgbe->link_irq, NULL, 80 txgbe_link_irq_handler, 81 IRQF_ONESHOT, "txgbe-link-irq", txgbe); 82 } 83 84 static const struct irq_chip txgbe_irq_chip = { 85 .name = "txgbe-misc-irq", 86 }; 87 88 static int txgbe_misc_irq_domain_map(struct irq_domain *d, 89 unsigned int irq, 90 irq_hw_number_t hwirq) 91 { 92 struct txgbe *txgbe = d->host_data; 93 94 irq_set_chip_data(irq, txgbe); 95 irq_set_chip(irq, &txgbe->misc.chip); 96 irq_set_nested_thread(irq, true); 97 irq_set_noprobe(irq); 98 99 return 0; 100 } 101 102 static const struct irq_domain_ops txgbe_misc_irq_domain_ops = { 103 .map = txgbe_misc_irq_domain_map, 104 }; 105 106 static irqreturn_t txgbe_misc_irq_handle(int irq, void *data) 107 { 108 struct wx_q_vector *q_vector; 109 struct txgbe *txgbe = data; 110 struct wx *wx = txgbe->wx; 111 u32 eicr; 112 113 if (wx->pdev->msix_enabled) { 114 eicr = wx_misc_isb(wx, WX_ISB_MISC); 115 if (!eicr) 116 return IRQ_NONE; 117 txgbe->eicr = eicr; 118 if (eicr & TXGBE_PX_MISC_IC_VF_MBOX) { 119 wx_msg_task(txgbe->wx); 120 wx_intr_enable(wx, TXGBE_INTR_MISC); 121 } 122 return IRQ_WAKE_THREAD; 123 } 124 125 eicr = wx_misc_isb(wx, WX_ISB_VEC0); 126 if (!eicr) { 127 /* shared interrupt alert! 128 * the interrupt that we masked before the ICR read. 129 */ 130 if (netif_running(wx->netdev)) 131 txgbe_irq_enable(wx, true); 132 return IRQ_NONE; /* Not our interrupt */ 133 } 134 wx->isb_mem[WX_ISB_VEC0] = 0; 135 if (!(wx->pdev->msi_enabled)) 136 wr32(wx, WX_PX_INTA, 1); 137 138 /* would disable interrupts here but it is auto disabled */ 139 q_vector = wx->q_vector[0]; 140 napi_schedule_irqoff(&q_vector->napi); 141 142 eicr = wx_misc_isb(wx, WX_ISB_MISC); 143 if (!eicr) 144 return IRQ_NONE; 145 txgbe->eicr = eicr; 146 147 return IRQ_WAKE_THREAD; 148 } 149 150 static irqreturn_t txgbe_misc_irq_thread_fn(int irq, void *data) 151 { 152 struct txgbe *txgbe = data; 153 struct wx *wx = txgbe->wx; 154 unsigned int nhandled = 0; 155 unsigned int sub_irq; 156 u32 eicr; 157 158 eicr = txgbe->eicr; 159 if (eicr & (TXGBE_PX_MISC_ETH_LK | TXGBE_PX_MISC_ETH_LKDN | 160 TXGBE_PX_MISC_ETH_AN)) { 161 sub_irq = irq_find_mapping(txgbe->misc.domain, TXGBE_IRQ_LINK); 162 handle_nested_irq(sub_irq); 163 nhandled++; 164 } 165 166 wx_intr_enable(wx, TXGBE_INTR_MISC); 167 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 168 } 169 170 static void txgbe_del_irq_domain(struct txgbe *txgbe) 171 { 172 int hwirq, virq; 173 174 for (hwirq = 0; hwirq < txgbe->misc.nirqs; hwirq++) { 175 virq = irq_find_mapping(txgbe->misc.domain, hwirq); 176 irq_dispose_mapping(virq); 177 } 178 179 irq_domain_remove(txgbe->misc.domain); 180 } 181 182 void txgbe_free_misc_irq(struct txgbe *txgbe) 183 { 184 if (txgbe->wx->mac.type == wx_mac_aml) 185 return; 186 187 free_irq(txgbe->link_irq, txgbe); 188 free_irq(txgbe->misc.irq, txgbe); 189 txgbe_del_irq_domain(txgbe); 190 } 191 192 int txgbe_setup_misc_irq(struct txgbe *txgbe) 193 { 194 unsigned long flags = IRQF_ONESHOT; 195 struct wx *wx = txgbe->wx; 196 int hwirq, err; 197 198 if (wx->mac.type == wx_mac_aml) 199 goto skip_sp_irq; 200 201 txgbe->misc.nirqs = TXGBE_IRQ_MAX; 202 txgbe->misc.domain = irq_domain_add_simple(NULL, txgbe->misc.nirqs, 0, 203 &txgbe_misc_irq_domain_ops, txgbe); 204 if (!txgbe->misc.domain) 205 return -ENOMEM; 206 207 for (hwirq = 0; hwirq < txgbe->misc.nirqs; hwirq++) 208 irq_create_mapping(txgbe->misc.domain, hwirq); 209 210 txgbe->misc.chip = txgbe_irq_chip; 211 if (wx->pdev->msix_enabled) { 212 txgbe->misc.irq = wx->msix_entry->vector; 213 } else { 214 txgbe->misc.irq = wx->pdev->irq; 215 if (!wx->pdev->msi_enabled) 216 flags |= IRQF_SHARED; 217 } 218 219 err = request_threaded_irq(txgbe->misc.irq, txgbe_misc_irq_handle, 220 txgbe_misc_irq_thread_fn, 221 flags, 222 wx->netdev->name, txgbe); 223 if (err) 224 goto del_misc_irq; 225 226 err = txgbe_request_link_irq(txgbe); 227 if (err) 228 goto free_msic_irq; 229 230 skip_sp_irq: 231 wx->misc_irq_domain = true; 232 233 return 0; 234 235 free_msic_irq: 236 free_irq(txgbe->misc.irq, txgbe); 237 del_misc_irq: 238 txgbe_del_irq_domain(txgbe); 239 240 return err; 241 } 242