1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <net/ip6_checksum.h> 6 #include <net/page_pool/helpers.h> 7 #include <net/inet_ecn.h> 8 #include <linux/iopoll.h> 9 #include <linux/sctp.h> 10 #include <linux/pci.h> 11 #include <net/tcp.h> 12 #include <net/ip.h> 13 14 #include "wx_type.h" 15 #include "wx_lib.h" 16 #include "wx_ptp.h" 17 #include "wx_hw.h" 18 19 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 20 static struct wx_dec_ptype wx_ptype_lookup[256] = { 21 /* L2: mac */ 22 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 23 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2), 24 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 25 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 26 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 27 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 28 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 29 30 /* L2: ethertype filter */ 31 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 32 33 /* L3: ip non-tunnel */ 34 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3), 35 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3), 36 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4), 37 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4), 38 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4), 39 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3), 40 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3), 41 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3), 42 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4), 43 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4), 44 45 /* L2: fcoe */ 46 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 47 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 48 49 /* IPv4 --> IPv4/IPv6 */ 50 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3), 51 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3), 52 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4), 53 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4), 54 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4), 55 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3), 56 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3), 57 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4), 58 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4), 59 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4), 60 61 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */ 62 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3), 63 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3), 64 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3), 65 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4), 66 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4), 67 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4), 68 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3), 69 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3), 70 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4), 71 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4), 72 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4), 73 74 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */ 75 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3), 76 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3), 77 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3), 78 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4), 79 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4), 80 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4), 81 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3), 82 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3), 83 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4), 84 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4), 85 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4), 86 87 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */ 88 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3), 89 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3), 90 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3), 91 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4), 92 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4), 93 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4), 94 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3), 95 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3), 96 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4), 97 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4), 98 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4), 99 100 /* IPv6 --> IPv4/IPv6 */ 101 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3), 102 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3), 103 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4), 104 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4), 105 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4), 106 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3), 107 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3), 108 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4), 109 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4), 110 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4), 111 112 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */ 113 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3), 114 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3), 115 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3), 116 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4), 117 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4), 118 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4), 119 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3), 120 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3), 121 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4), 122 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4), 123 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4), 124 125 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */ 126 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3), 127 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3), 128 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3), 129 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4), 130 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4), 131 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4), 132 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3), 133 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3), 134 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4), 135 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4), 136 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4), 137 138 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */ 139 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3), 140 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3), 141 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3), 142 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4), 143 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4), 144 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4), 145 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3), 146 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3), 147 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4), 148 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4), 149 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4), 150 }; 151 152 struct wx_dec_ptype wx_decode_ptype(const u8 ptype) 153 { 154 return wx_ptype_lookup[ptype]; 155 } 156 EXPORT_SYMBOL(wx_decode_ptype); 157 158 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */ 159 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc, 160 const u32 stat_err_bits) 161 { 162 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 163 } 164 165 static void wx_dma_sync_frag(struct wx_ring *rx_ring, 166 struct wx_rx_buffer *rx_buffer) 167 { 168 struct sk_buff *skb = rx_buffer->skb; 169 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 170 171 dma_sync_single_range_for_cpu(rx_ring->dev, 172 WX_CB(skb)->dma, 173 skb_frag_off(frag), 174 skb_frag_size(frag), 175 DMA_FROM_DEVICE); 176 177 /* If the page was released, just unmap it. */ 178 if (unlikely(WX_CB(skb)->page_released)) 179 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 180 } 181 182 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring, 183 union wx_rx_desc *rx_desc, 184 struct sk_buff **skb, 185 int *rx_buffer_pgcnt) 186 { 187 struct wx_rx_buffer *rx_buffer; 188 unsigned int size; 189 190 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 191 size = le16_to_cpu(rx_desc->wb.upper.length); 192 193 #if (PAGE_SIZE < 8192) 194 *rx_buffer_pgcnt = page_count(rx_buffer->page); 195 #else 196 *rx_buffer_pgcnt = 0; 197 #endif 198 199 prefetchw(rx_buffer->page); 200 *skb = rx_buffer->skb; 201 202 /* Delay unmapping of the first packet. It carries the header 203 * information, HW may still access the header after the writeback. 204 * Only unmap it when EOP is reached 205 */ 206 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) { 207 if (!*skb) 208 goto skip_sync; 209 } else { 210 if (*skb) 211 wx_dma_sync_frag(rx_ring, rx_buffer); 212 } 213 214 /* we are reusing so sync this buffer for CPU use */ 215 dma_sync_single_range_for_cpu(rx_ring->dev, 216 rx_buffer->dma, 217 rx_buffer->page_offset, 218 size, 219 DMA_FROM_DEVICE); 220 skip_sync: 221 return rx_buffer; 222 } 223 224 static void wx_put_rx_buffer(struct wx_ring *rx_ring, 225 struct wx_rx_buffer *rx_buffer, 226 struct sk_buff *skb, 227 int rx_buffer_pgcnt) 228 { 229 if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma) 230 /* the page has been released from the ring */ 231 WX_CB(skb)->page_released = true; 232 233 /* clear contents of rx_buffer */ 234 rx_buffer->page = NULL; 235 rx_buffer->skb = NULL; 236 } 237 238 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring, 239 struct wx_rx_buffer *rx_buffer, 240 union wx_rx_desc *rx_desc) 241 { 242 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 243 #if (PAGE_SIZE < 8192) 244 unsigned int truesize = WX_RX_BUFSZ; 245 #else 246 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 247 #endif 248 struct sk_buff *skb = rx_buffer->skb; 249 250 if (!skb) { 251 void *page_addr = page_address(rx_buffer->page) + 252 rx_buffer->page_offset; 253 254 /* prefetch first cache line of first page */ 255 net_prefetch(page_addr); 256 257 /* allocate a skb to store the frags */ 258 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256); 259 if (unlikely(!skb)) 260 return NULL; 261 262 /* we will be copying header into skb->data in 263 * pskb_may_pull so it is in our interest to prefetch 264 * it now to avoid a possible cache miss 265 */ 266 prefetchw(skb->data); 267 268 if (size <= WX_RXBUFFER_256) { 269 memcpy(__skb_put(skb, size), page_addr, 270 ALIGN(size, sizeof(long))); 271 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true); 272 return skb; 273 } 274 275 skb_mark_for_recycle(skb); 276 277 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) 278 WX_CB(skb)->dma = rx_buffer->dma; 279 280 skb_add_rx_frag(skb, 0, rx_buffer->page, 281 rx_buffer->page_offset, 282 size, truesize); 283 goto out; 284 285 } else { 286 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 287 rx_buffer->page_offset, size, truesize); 288 } 289 290 out: 291 #if (PAGE_SIZE < 8192) 292 /* flip page offset to other buffer */ 293 rx_buffer->page_offset ^= truesize; 294 #else 295 /* move offset up to the next cache line */ 296 rx_buffer->page_offset += truesize; 297 #endif 298 299 return skb; 300 } 301 302 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring, 303 struct wx_rx_buffer *bi) 304 { 305 struct page *page = bi->page; 306 dma_addr_t dma; 307 308 /* since we are recycling buffers we should seldom need to alloc */ 309 if (likely(page)) 310 return true; 311 312 page = page_pool_dev_alloc_pages(rx_ring->page_pool); 313 WARN_ON(!page); 314 dma = page_pool_get_dma_addr(page); 315 316 bi->page_dma = dma; 317 bi->page = page; 318 bi->page_offset = 0; 319 320 return true; 321 } 322 323 /** 324 * wx_alloc_rx_buffers - Replace used receive buffers 325 * @rx_ring: ring to place buffers on 326 * @cleaned_count: number of buffers to replace 327 **/ 328 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count) 329 { 330 u16 i = rx_ring->next_to_use; 331 union wx_rx_desc *rx_desc; 332 struct wx_rx_buffer *bi; 333 334 /* nothing to do */ 335 if (!cleaned_count) 336 return; 337 338 rx_desc = WX_RX_DESC(rx_ring, i); 339 bi = &rx_ring->rx_buffer_info[i]; 340 i -= rx_ring->count; 341 342 do { 343 if (!wx_alloc_mapped_page(rx_ring, bi)) 344 break; 345 346 /* sync the buffer for use by the device */ 347 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 348 bi->page_offset, 349 WX_RX_BUFSZ, 350 DMA_FROM_DEVICE); 351 352 rx_desc->read.pkt_addr = 353 cpu_to_le64(bi->page_dma + bi->page_offset); 354 355 rx_desc++; 356 bi++; 357 i++; 358 if (unlikely(!i)) { 359 rx_desc = WX_RX_DESC(rx_ring, 0); 360 bi = rx_ring->rx_buffer_info; 361 i -= rx_ring->count; 362 } 363 364 /* clear the status bits for the next_to_use descriptor */ 365 rx_desc->wb.upper.status_error = 0; 366 367 cleaned_count--; 368 } while (cleaned_count); 369 370 i += rx_ring->count; 371 372 if (rx_ring->next_to_use != i) { 373 rx_ring->next_to_use = i; 374 /* update next to alloc since we have filled the ring */ 375 rx_ring->next_to_alloc = i; 376 377 /* Force memory writes to complete before letting h/w 378 * know there are new descriptors to fetch. (Only 379 * applicable for weak-ordered memory model archs, 380 * such as IA-64). 381 */ 382 wmb(); 383 writel(i, rx_ring->tail); 384 } 385 } 386 387 u16 wx_desc_unused(struct wx_ring *ring) 388 { 389 u16 ntc = ring->next_to_clean; 390 u16 ntu = ring->next_to_use; 391 392 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 393 } 394 395 /** 396 * wx_is_non_eop - process handling of non-EOP buffers 397 * @rx_ring: Rx ring being processed 398 * @rx_desc: Rx descriptor for current buffer 399 * @skb: Current socket buffer containing buffer in progress 400 * 401 * This function updates next to clean. If the buffer is an EOP buffer 402 * this function exits returning false, otherwise it will place the 403 * sk_buff in the next buffer to be chained and return true indicating 404 * that this is in fact a non-EOP buffer. 405 **/ 406 static bool wx_is_non_eop(struct wx_ring *rx_ring, 407 union wx_rx_desc *rx_desc, 408 struct sk_buff *skb) 409 { 410 u32 ntc = rx_ring->next_to_clean + 1; 411 412 /* fetch, update, and store next to clean */ 413 ntc = (ntc < rx_ring->count) ? ntc : 0; 414 rx_ring->next_to_clean = ntc; 415 416 prefetch(WX_RX_DESC(rx_ring, ntc)); 417 418 /* if we are the last buffer then there is nothing else to do */ 419 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))) 420 return false; 421 422 rx_ring->rx_buffer_info[ntc].skb = skb; 423 rx_ring->rx_stats.non_eop_descs++; 424 425 return true; 426 } 427 428 static void wx_pull_tail(struct sk_buff *skb) 429 { 430 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 431 unsigned int pull_len; 432 unsigned char *va; 433 434 /* it is valid to use page_address instead of kmap since we are 435 * working with pages allocated out of the lomem pool per 436 * alloc_page(GFP_ATOMIC) 437 */ 438 va = skb_frag_address(frag); 439 440 /* we need the header to contain the greater of either ETH_HLEN or 441 * 60 bytes if the skb->len is less than 60 for skb_pad. 442 */ 443 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256); 444 445 /* align pull length to size of long to optimize memcpy performance */ 446 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 447 448 /* update all of the pointers */ 449 skb_frag_size_sub(frag, pull_len); 450 skb_frag_off_add(frag, pull_len); 451 skb->data_len -= pull_len; 452 skb->tail += pull_len; 453 } 454 455 /** 456 * wx_cleanup_headers - Correct corrupted or empty headers 457 * @rx_ring: rx descriptor ring packet is being transacted on 458 * @rx_desc: pointer to the EOP Rx descriptor 459 * @skb: pointer to current skb being fixed 460 * 461 * Check for corrupted packet headers caused by senders on the local L2 462 * embedded NIC switch not setting up their Tx Descriptors right. These 463 * should be very rare. 464 * 465 * Also address the case where we are pulling data in on pages only 466 * and as such no data is present in the skb header. 467 * 468 * In addition if skb is not at least 60 bytes we need to pad it so that 469 * it is large enough to qualify as a valid Ethernet frame. 470 * 471 * Returns true if an error was encountered and skb was freed. 472 **/ 473 static bool wx_cleanup_headers(struct wx_ring *rx_ring, 474 union wx_rx_desc *rx_desc, 475 struct sk_buff *skb) 476 { 477 struct net_device *netdev = rx_ring->netdev; 478 479 /* verify that the packet does not have any known errors */ 480 if (!netdev || 481 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) && 482 !(netdev->features & NETIF_F_RXALL))) { 483 dev_kfree_skb_any(skb); 484 return true; 485 } 486 487 /* place header in linear portion of buffer */ 488 if (!skb_headlen(skb)) 489 wx_pull_tail(skb); 490 491 /* if eth_skb_pad returns an error the skb was freed */ 492 if (eth_skb_pad(skb)) 493 return true; 494 495 return false; 496 } 497 498 static void wx_rx_hash(struct wx_ring *ring, 499 union wx_rx_desc *rx_desc, 500 struct sk_buff *skb) 501 { 502 u16 rss_type; 503 504 if (!(ring->netdev->features & NETIF_F_RXHASH)) 505 return; 506 507 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 508 WX_RXD_RSSTYPE_MASK; 509 510 if (!rss_type) 511 return; 512 513 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 514 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 515 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 516 } 517 518 /** 519 * wx_rx_checksum - indicate in skb if hw indicated a good cksum 520 * @ring: structure containing ring specific data 521 * @rx_desc: current Rx descriptor being processed 522 * @skb: skb currently being received and modified 523 **/ 524 static void wx_rx_checksum(struct wx_ring *ring, 525 union wx_rx_desc *rx_desc, 526 struct sk_buff *skb) 527 { 528 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc)); 529 530 skb_checksum_none_assert(skb); 531 /* Rx csum disabled */ 532 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 533 return; 534 535 /* if IPv4 header checksum error */ 536 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) && 537 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) || 538 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) && 539 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) { 540 ring->rx_stats.csum_err++; 541 return; 542 } 543 544 /* L4 checksum offload flag must set for the below code to work */ 545 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS)) 546 return; 547 548 /* Hardware can't guarantee csum if IPv6 Dest Header found */ 549 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && WX_RXD_IPV6EX(rx_desc)) 550 return; 551 552 /* if L4 checksum error */ 553 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) { 554 ring->rx_stats.csum_err++; 555 return; 556 } 557 558 /* It must be a TCP or UDP or SCTP packet with a valid checksum */ 559 skb->ip_summed = CHECKSUM_UNNECESSARY; 560 561 /* If there is an outer header present that might contain a checksum 562 * we need to bump the checksum level by 1 to reflect the fact that 563 * we are indicating we validated the inner checksum. 564 */ 565 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG) 566 __skb_incr_checksum_unnecessary(skb); 567 ring->rx_stats.csum_good_cnt++; 568 } 569 570 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc, 571 struct sk_buff *skb) 572 { 573 u16 ethertype; 574 u8 idx = 0; 575 576 if ((ring->netdev->features & 577 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) && 578 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) { 579 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 580 0x1c0) >> 6; 581 ethertype = ring->q_vector->wx->tpid[idx]; 582 __vlan_hwaccel_put_tag(skb, htons(ethertype), 583 le16_to_cpu(rx_desc->wb.upper.vlan)); 584 } 585 } 586 587 /** 588 * wx_process_skb_fields - Populate skb header fields from Rx descriptor 589 * @rx_ring: rx descriptor ring packet is being transacted on 590 * @rx_desc: pointer to the EOP Rx descriptor 591 * @skb: pointer to current skb being populated 592 * 593 * This function checks the ring, descriptor, and packet information in 594 * order to populate the hash, checksum, protocol, and 595 * other fields within the skb. 596 **/ 597 static void wx_process_skb_fields(struct wx_ring *rx_ring, 598 union wx_rx_desc *rx_desc, 599 struct sk_buff *skb) 600 { 601 struct wx *wx = netdev_priv(rx_ring->netdev); 602 603 wx_rx_hash(rx_ring, rx_desc, skb); 604 wx_rx_checksum(rx_ring, rx_desc, skb); 605 606 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, wx->flags)) && 607 unlikely(wx_test_staterr(rx_desc, WX_RXD_STAT_TS))) { 608 wx_ptp_rx_hwtstamp(rx_ring->q_vector->wx, skb); 609 rx_ring->last_rx_timestamp = jiffies; 610 } 611 612 wx_rx_vlan(rx_ring, rx_desc, skb); 613 skb_record_rx_queue(skb, rx_ring->queue_index); 614 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 615 } 616 617 /** 618 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 619 * @q_vector: structure containing interrupt and ring information 620 * @rx_ring: rx descriptor ring to transact packets on 621 * @budget: Total limit on number of packets to process 622 * 623 * This function provides a "bounce buffer" approach to Rx interrupt 624 * processing. The advantage to this is that on systems that have 625 * expensive overhead for IOMMU access this provides a means of avoiding 626 * it by maintaining the mapping of the page to the system. 627 * 628 * Returns amount of work completed. 629 **/ 630 static int wx_clean_rx_irq(struct wx_q_vector *q_vector, 631 struct wx_ring *rx_ring, 632 int budget) 633 { 634 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 635 u16 cleaned_count = wx_desc_unused(rx_ring); 636 637 do { 638 struct wx_rx_buffer *rx_buffer; 639 union wx_rx_desc *rx_desc; 640 struct sk_buff *skb; 641 int rx_buffer_pgcnt; 642 643 /* return some buffers to hardware, one at a time is too slow */ 644 if (cleaned_count >= WX_RX_BUFFER_WRITE) { 645 wx_alloc_rx_buffers(rx_ring, cleaned_count); 646 cleaned_count = 0; 647 } 648 649 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean); 650 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD)) 651 break; 652 653 /* This memory barrier is needed to keep us from reading 654 * any other fields out of the rx_desc until we know the 655 * descriptor has been written back 656 */ 657 dma_rmb(); 658 659 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt); 660 661 /* retrieve a buffer from the ring */ 662 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc); 663 664 /* exit if we failed to retrieve a buffer */ 665 if (!skb) { 666 rx_ring->rx_stats.alloc_rx_buff_failed++; 667 break; 668 } 669 670 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 671 cleaned_count++; 672 673 /* place incomplete frames back on ring for completion */ 674 if (wx_is_non_eop(rx_ring, rx_desc, skb)) 675 continue; 676 677 /* verify the packet layout is correct */ 678 if (wx_cleanup_headers(rx_ring, rx_desc, skb)) 679 continue; 680 681 /* probably a little skewed due to removing CRC */ 682 total_rx_bytes += skb->len; 683 684 /* populate checksum, timestamp, VLAN, and protocol */ 685 wx_process_skb_fields(rx_ring, rx_desc, skb); 686 napi_gro_receive(&q_vector->napi, skb); 687 688 /* update budget accounting */ 689 total_rx_packets++; 690 } while (likely(total_rx_packets < budget)); 691 692 u64_stats_update_begin(&rx_ring->syncp); 693 rx_ring->stats.packets += total_rx_packets; 694 rx_ring->stats.bytes += total_rx_bytes; 695 u64_stats_update_end(&rx_ring->syncp); 696 q_vector->rx.total_packets += total_rx_packets; 697 q_vector->rx.total_bytes += total_rx_bytes; 698 699 return total_rx_packets; 700 } 701 702 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring) 703 { 704 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 705 } 706 707 /** 708 * wx_clean_tx_irq - Reclaim resources after transmit completes 709 * @q_vector: structure containing interrupt and ring information 710 * @tx_ring: tx ring to clean 711 * @napi_budget: Used to determine if we are in netpoll 712 **/ 713 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector, 714 struct wx_ring *tx_ring, int napi_budget) 715 { 716 unsigned int budget = q_vector->wx->tx_work_limit; 717 unsigned int total_bytes = 0, total_packets = 0; 718 struct wx *wx = netdev_priv(tx_ring->netdev); 719 unsigned int i = tx_ring->next_to_clean; 720 struct wx_tx_buffer *tx_buffer; 721 union wx_tx_desc *tx_desc; 722 723 if (!netif_carrier_ok(tx_ring->netdev)) 724 return true; 725 726 tx_buffer = &tx_ring->tx_buffer_info[i]; 727 tx_desc = WX_TX_DESC(tx_ring, i); 728 i -= tx_ring->count; 729 730 do { 731 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch; 732 733 /* if next_to_watch is not set then there is no work pending */ 734 if (!eop_desc) 735 break; 736 737 /* prevent any other reads prior to eop_desc */ 738 smp_rmb(); 739 740 /* if DD is not set pending work has not been completed */ 741 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) 742 break; 743 744 /* clear next_to_watch to prevent false hangs */ 745 tx_buffer->next_to_watch = NULL; 746 747 /* update the statistics for this packet */ 748 total_bytes += tx_buffer->bytecount; 749 total_packets += tx_buffer->gso_segs; 750 751 /* schedule check for Tx timestamp */ 752 if (unlikely(test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state)) && 753 skb_shinfo(tx_buffer->skb)->tx_flags & SKBTX_IN_PROGRESS) 754 ptp_schedule_worker(wx->ptp_clock, 0); 755 756 /* free the skb */ 757 napi_consume_skb(tx_buffer->skb, napi_budget); 758 759 /* unmap skb header data */ 760 dma_unmap_single(tx_ring->dev, 761 dma_unmap_addr(tx_buffer, dma), 762 dma_unmap_len(tx_buffer, len), 763 DMA_TO_DEVICE); 764 765 /* clear tx_buffer data */ 766 dma_unmap_len_set(tx_buffer, len, 0); 767 768 /* unmap remaining buffers */ 769 while (tx_desc != eop_desc) { 770 tx_buffer++; 771 tx_desc++; 772 i++; 773 if (unlikely(!i)) { 774 i -= tx_ring->count; 775 tx_buffer = tx_ring->tx_buffer_info; 776 tx_desc = WX_TX_DESC(tx_ring, 0); 777 } 778 779 /* unmap any remaining paged data */ 780 if (dma_unmap_len(tx_buffer, len)) { 781 dma_unmap_page(tx_ring->dev, 782 dma_unmap_addr(tx_buffer, dma), 783 dma_unmap_len(tx_buffer, len), 784 DMA_TO_DEVICE); 785 dma_unmap_len_set(tx_buffer, len, 0); 786 } 787 } 788 789 /* move us one more past the eop_desc for start of next pkt */ 790 tx_buffer++; 791 tx_desc++; 792 i++; 793 if (unlikely(!i)) { 794 i -= tx_ring->count; 795 tx_buffer = tx_ring->tx_buffer_info; 796 tx_desc = WX_TX_DESC(tx_ring, 0); 797 } 798 799 /* issue prefetch for next Tx descriptor */ 800 prefetch(tx_desc); 801 802 /* update budget accounting */ 803 budget--; 804 } while (likely(budget)); 805 806 i += tx_ring->count; 807 tx_ring->next_to_clean = i; 808 u64_stats_update_begin(&tx_ring->syncp); 809 tx_ring->stats.bytes += total_bytes; 810 tx_ring->stats.packets += total_packets; 811 u64_stats_update_end(&tx_ring->syncp); 812 q_vector->tx.total_bytes += total_bytes; 813 q_vector->tx.total_packets += total_packets; 814 815 netdev_tx_completed_queue(wx_txring_txq(tx_ring), 816 total_packets, total_bytes); 817 818 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 819 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 820 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 821 /* Make sure that anybody stopping the queue after this 822 * sees the new next_to_clean. 823 */ 824 smp_mb(); 825 826 if (__netif_subqueue_stopped(tx_ring->netdev, 827 tx_ring->queue_index) && 828 netif_running(tx_ring->netdev)) { 829 netif_wake_subqueue(tx_ring->netdev, 830 tx_ring->queue_index); 831 ++tx_ring->tx_stats.restart_queue; 832 } 833 } 834 835 return !!budget; 836 } 837 838 /** 839 * wx_poll - NAPI polling RX/TX cleanup routine 840 * @napi: napi struct with our devices info in it 841 * @budget: amount of work driver is allowed to do this pass, in packets 842 * 843 * This function will clean all queues associated with a q_vector. 844 **/ 845 static int wx_poll(struct napi_struct *napi, int budget) 846 { 847 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi); 848 int per_ring_budget, work_done = 0; 849 struct wx *wx = q_vector->wx; 850 bool clean_complete = true; 851 struct wx_ring *ring; 852 853 wx_for_each_ring(ring, q_vector->tx) { 854 if (!wx_clean_tx_irq(q_vector, ring, budget)) 855 clean_complete = false; 856 } 857 858 /* Exit if we are called by netpoll */ 859 if (budget <= 0) 860 return budget; 861 862 /* attempt to distribute budget to each queue fairly, but don't allow 863 * the budget to go below 1 because we'll exit polling 864 */ 865 if (q_vector->rx.count > 1) 866 per_ring_budget = max(budget / q_vector->rx.count, 1); 867 else 868 per_ring_budget = budget; 869 870 wx_for_each_ring(ring, q_vector->rx) { 871 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget); 872 873 work_done += cleaned; 874 if (cleaned >= per_ring_budget) 875 clean_complete = false; 876 } 877 878 /* If all work not completed, return budget and keep polling */ 879 if (!clean_complete) 880 return budget; 881 882 /* all work done, exit the polling mode */ 883 if (likely(napi_complete_done(napi, work_done))) { 884 if (netif_running(wx->netdev)) 885 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx)); 886 } 887 888 return min(work_done, budget - 1); 889 } 890 891 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size) 892 { 893 if (likely(wx_desc_unused(tx_ring) >= size)) 894 return 0; 895 896 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 897 898 /* For the next check */ 899 smp_mb(); 900 901 /* We need to check again in a case another CPU has just 902 * made room available. 903 */ 904 if (likely(wx_desc_unused(tx_ring) < size)) 905 return -EBUSY; 906 907 /* A reprieve! - use start_queue because it doesn't call schedule */ 908 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 909 ++tx_ring->tx_stats.restart_queue; 910 911 return 0; 912 } 913 914 static u32 wx_tx_cmd_type(u32 tx_flags) 915 { 916 /* set type for advanced descriptor with frame checksum insertion */ 917 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS; 918 919 /* set HW vlan bit if vlan is present */ 920 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE); 921 /* set segmentation enable bits for TSO/FSO */ 922 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE); 923 /* set timestamp bit if present */ 924 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP); 925 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC); 926 927 return cmd_type; 928 } 929 930 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc, 931 u32 tx_flags, unsigned int paylen) 932 { 933 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT; 934 935 /* enable L4 checksum for TSO and TX checksum offload */ 936 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS); 937 /* enable IPv4 checksum for TSO */ 938 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS); 939 /* enable outer IPv4 checksum for TSO */ 940 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4, 941 WX_TXD_EIPCS); 942 /* Check Context must be set if Tx switch is enabled, which it 943 * always is for case where virtual functions are running 944 */ 945 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC); 946 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC, 947 WX_TXD_IPSEC); 948 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 949 } 950 951 static int wx_tx_map(struct wx_ring *tx_ring, 952 struct wx_tx_buffer *first, 953 const u8 hdr_len) 954 { 955 struct sk_buff *skb = first->skb; 956 struct wx_tx_buffer *tx_buffer; 957 u32 tx_flags = first->tx_flags; 958 u16 i = tx_ring->next_to_use; 959 unsigned int data_len, size; 960 union wx_tx_desc *tx_desc; 961 skb_frag_t *frag; 962 dma_addr_t dma; 963 u32 cmd_type; 964 965 cmd_type = wx_tx_cmd_type(tx_flags); 966 tx_desc = WX_TX_DESC(tx_ring, i); 967 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 968 969 size = skb_headlen(skb); 970 data_len = skb->data_len; 971 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 972 973 tx_buffer = first; 974 975 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 976 if (dma_mapping_error(tx_ring->dev, dma)) 977 goto dma_error; 978 979 /* record length, and DMA address */ 980 dma_unmap_len_set(tx_buffer, len, size); 981 dma_unmap_addr_set(tx_buffer, dma, dma); 982 983 tx_desc->read.buffer_addr = cpu_to_le64(dma); 984 985 while (unlikely(size > WX_MAX_DATA_PER_TXD)) { 986 tx_desc->read.cmd_type_len = 987 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD); 988 989 i++; 990 tx_desc++; 991 if (i == tx_ring->count) { 992 tx_desc = WX_TX_DESC(tx_ring, 0); 993 i = 0; 994 } 995 tx_desc->read.olinfo_status = 0; 996 997 dma += WX_MAX_DATA_PER_TXD; 998 size -= WX_MAX_DATA_PER_TXD; 999 1000 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1001 } 1002 1003 if (likely(!data_len)) 1004 break; 1005 1006 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 1007 1008 i++; 1009 tx_desc++; 1010 if (i == tx_ring->count) { 1011 tx_desc = WX_TX_DESC(tx_ring, 0); 1012 i = 0; 1013 } 1014 tx_desc->read.olinfo_status = 0; 1015 1016 size = skb_frag_size(frag); 1017 1018 data_len -= size; 1019 1020 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1021 DMA_TO_DEVICE); 1022 1023 tx_buffer = &tx_ring->tx_buffer_info[i]; 1024 } 1025 1026 /* write last descriptor with RS and EOP bits */ 1027 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS; 1028 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1029 1030 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount); 1031 1032 /* set the timestamp */ 1033 first->time_stamp = jiffies; 1034 skb_tx_timestamp(skb); 1035 1036 /* Force memory writes to complete before letting h/w know there 1037 * are new descriptors to fetch. (Only applicable for weak-ordered 1038 * memory model archs, such as IA-64). 1039 * 1040 * We also need this memory barrier to make certain all of the 1041 * status bits have been updated before next_to_watch is written. 1042 */ 1043 wmb(); 1044 1045 /* set next_to_watch value indicating a packet is present */ 1046 first->next_to_watch = tx_desc; 1047 1048 i++; 1049 if (i == tx_ring->count) 1050 i = 0; 1051 1052 tx_ring->next_to_use = i; 1053 1054 wx_maybe_stop_tx(tx_ring, DESC_NEEDED); 1055 1056 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more()) 1057 writel(i, tx_ring->tail); 1058 1059 return 0; 1060 dma_error: 1061 dev_err(tx_ring->dev, "TX DMA map failed\n"); 1062 1063 /* clear dma mappings for failed tx_buffer_info map */ 1064 for (;;) { 1065 tx_buffer = &tx_ring->tx_buffer_info[i]; 1066 if (dma_unmap_len(tx_buffer, len)) 1067 dma_unmap_page(tx_ring->dev, 1068 dma_unmap_addr(tx_buffer, dma), 1069 dma_unmap_len(tx_buffer, len), 1070 DMA_TO_DEVICE); 1071 dma_unmap_len_set(tx_buffer, len, 0); 1072 if (tx_buffer == first) 1073 break; 1074 if (i == 0) 1075 i += tx_ring->count; 1076 i--; 1077 } 1078 1079 dev_kfree_skb_any(first->skb); 1080 first->skb = NULL; 1081 1082 tx_ring->next_to_use = i; 1083 1084 return -ENOMEM; 1085 } 1086 1087 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens, 1088 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1089 { 1090 struct wx_tx_context_desc *context_desc; 1091 u16 i = tx_ring->next_to_use; 1092 1093 context_desc = WX_TX_CTXTDESC(tx_ring, i); 1094 i++; 1095 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1096 1097 /* set bits to identify this as an advanced context descriptor */ 1098 type_tucmd |= WX_TXD_DTYP_CTXT; 1099 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1100 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1101 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1102 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1103 } 1104 1105 static void wx_get_ipv6_proto(struct sk_buff *skb, int offset, u8 *nexthdr) 1106 { 1107 struct ipv6hdr *hdr = (struct ipv6hdr *)(skb->data + offset); 1108 1109 *nexthdr = hdr->nexthdr; 1110 offset += sizeof(struct ipv6hdr); 1111 while (ipv6_ext_hdr(*nexthdr)) { 1112 struct ipv6_opt_hdr _hdr, *hp; 1113 1114 if (*nexthdr == NEXTHDR_NONE) 1115 return; 1116 hp = skb_header_pointer(skb, offset, sizeof(_hdr), &_hdr); 1117 if (!hp) 1118 return; 1119 if (*nexthdr == NEXTHDR_FRAGMENT) 1120 break; 1121 *nexthdr = hp->nexthdr; 1122 } 1123 } 1124 1125 union network_header { 1126 struct iphdr *ipv4; 1127 struct ipv6hdr *ipv6; 1128 void *raw; 1129 }; 1130 1131 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first) 1132 { 1133 u8 tun_prot = 0, l4_prot = 0, ptype = 0; 1134 struct sk_buff *skb = first->skb; 1135 1136 if (skb->encapsulation) { 1137 union network_header hdr; 1138 1139 switch (first->protocol) { 1140 case htons(ETH_P_IP): 1141 tun_prot = ip_hdr(skb)->protocol; 1142 ptype = WX_PTYPE_TUN_IPV4; 1143 break; 1144 case htons(ETH_P_IPV6): 1145 wx_get_ipv6_proto(skb, skb_network_offset(skb), &tun_prot); 1146 ptype = WX_PTYPE_TUN_IPV6; 1147 break; 1148 default: 1149 return ptype; 1150 } 1151 1152 if (tun_prot == IPPROTO_IPIP) { 1153 hdr.raw = (void *)inner_ip_hdr(skb); 1154 ptype |= WX_PTYPE_PKT_IPIP; 1155 } else if (tun_prot == IPPROTO_UDP) { 1156 hdr.raw = (void *)inner_ip_hdr(skb); 1157 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1158 skb->inner_protocol != htons(ETH_P_TEB)) { 1159 ptype |= WX_PTYPE_PKT_IG; 1160 } else { 1161 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1162 == htons(ETH_P_8021Q)) 1163 ptype |= WX_PTYPE_PKT_IGMV; 1164 else 1165 ptype |= WX_PTYPE_PKT_IGM; 1166 } 1167 1168 } else if (tun_prot == IPPROTO_GRE) { 1169 hdr.raw = (void *)inner_ip_hdr(skb); 1170 if (skb->inner_protocol == htons(ETH_P_IP) || 1171 skb->inner_protocol == htons(ETH_P_IPV6)) { 1172 ptype |= WX_PTYPE_PKT_IG; 1173 } else { 1174 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1175 == htons(ETH_P_8021Q)) 1176 ptype |= WX_PTYPE_PKT_IGMV; 1177 else 1178 ptype |= WX_PTYPE_PKT_IGM; 1179 } 1180 } else { 1181 return ptype; 1182 } 1183 1184 switch (hdr.ipv4->version) { 1185 case IPVERSION: 1186 l4_prot = hdr.ipv4->protocol; 1187 break; 1188 case 6: 1189 wx_get_ipv6_proto(skb, skb_inner_network_offset(skb), &l4_prot); 1190 ptype |= WX_PTYPE_PKT_IPV6; 1191 break; 1192 default: 1193 return ptype; 1194 } 1195 } else { 1196 switch (first->protocol) { 1197 case htons(ETH_P_IP): 1198 l4_prot = ip_hdr(skb)->protocol; 1199 ptype = WX_PTYPE_PKT_IP; 1200 break; 1201 case htons(ETH_P_IPV6): 1202 wx_get_ipv6_proto(skb, skb_network_offset(skb), &l4_prot); 1203 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6; 1204 break; 1205 default: 1206 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC; 1207 } 1208 } 1209 switch (l4_prot) { 1210 case IPPROTO_TCP: 1211 ptype |= WX_PTYPE_TYP_TCP; 1212 break; 1213 case IPPROTO_UDP: 1214 ptype |= WX_PTYPE_TYP_UDP; 1215 break; 1216 case IPPROTO_SCTP: 1217 ptype |= WX_PTYPE_TYP_SCTP; 1218 break; 1219 default: 1220 ptype |= WX_PTYPE_TYP_IP; 1221 break; 1222 } 1223 1224 return ptype; 1225 } 1226 1227 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1228 u8 *hdr_len, u8 ptype) 1229 { 1230 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1231 struct net_device *netdev = tx_ring->netdev; 1232 u32 l4len, tunhdr_eiplen_tunlen = 0; 1233 struct sk_buff *skb = first->skb; 1234 bool enc = skb->encapsulation; 1235 struct ipv6hdr *ipv6h; 1236 struct tcphdr *tcph; 1237 struct iphdr *iph; 1238 u8 tun_prot = 0; 1239 int err; 1240 1241 if (skb->ip_summed != CHECKSUM_PARTIAL) 1242 return 0; 1243 1244 if (!skb_is_gso(skb)) 1245 return 0; 1246 1247 err = skb_cow_head(skb, 0); 1248 if (err < 0) 1249 return err; 1250 1251 /* indicates the inner headers in the skbuff are valid. */ 1252 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb); 1253 if (iph->version == 4) { 1254 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1255 iph->tot_len = 0; 1256 iph->check = 0; 1257 tcph->check = ~csum_tcpudp_magic(iph->saddr, 1258 iph->daddr, 0, 1259 IPPROTO_TCP, 0); 1260 first->tx_flags |= WX_TX_FLAGS_TSO | 1261 WX_TX_FLAGS_CSUM | 1262 WX_TX_FLAGS_IPV4 | 1263 WX_TX_FLAGS_CC; 1264 } else if (iph->version == 6 && skb_is_gso_v6(skb)) { 1265 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 1266 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1267 ipv6h->payload_len = 0; 1268 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, 1269 &ipv6h->daddr, 0, 1270 IPPROTO_TCP, 0); 1271 first->tx_flags |= WX_TX_FLAGS_TSO | 1272 WX_TX_FLAGS_CSUM | 1273 WX_TX_FLAGS_CC; 1274 } 1275 1276 /* compute header lengths */ 1277 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 1278 *hdr_len = enc ? skb_inner_transport_offset(skb) : 1279 skb_transport_offset(skb); 1280 *hdr_len += l4len; 1281 1282 /* update gso size and bytecount with header size */ 1283 first->gso_segs = skb_shinfo(skb)->gso_segs; 1284 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1285 1286 /* mss_l4len_id: use 0 as index for TSO */ 1287 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT; 1288 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT; 1289 1290 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 1291 if (enc) { 1292 switch (first->protocol) { 1293 case htons(ETH_P_IP): 1294 tun_prot = ip_hdr(skb)->protocol; 1295 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4; 1296 break; 1297 case htons(ETH_P_IPV6): 1298 tun_prot = ipv6_hdr(skb)->nexthdr; 1299 break; 1300 default: 1301 break; 1302 } 1303 switch (tun_prot) { 1304 case IPPROTO_UDP: 1305 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1306 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1307 WX_TXD_OUTER_IPLEN_SHIFT) | 1308 (((skb_inner_mac_header(skb) - 1309 skb_transport_header(skb)) >> 1) << 1310 WX_TXD_TUNNEL_LEN_SHIFT); 1311 break; 1312 case IPPROTO_GRE: 1313 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1314 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1315 WX_TXD_OUTER_IPLEN_SHIFT) | 1316 (((skb_inner_mac_header(skb) - 1317 skb_transport_header(skb)) >> 1) << 1318 WX_TXD_TUNNEL_LEN_SHIFT); 1319 break; 1320 case IPPROTO_IPIP: 1321 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1322 (char *)ip_hdr(skb)) >> 2) << 1323 WX_TXD_OUTER_IPLEN_SHIFT; 1324 break; 1325 default: 1326 break; 1327 } 1328 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1; 1329 } else { 1330 vlan_macip_lens = skb_network_header_len(skb) >> 1; 1331 } 1332 1333 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT; 1334 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1335 1336 type_tucmd = ptype << 24; 1337 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1338 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1339 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1340 WX_TX_FLAGS_HW_VLAN, 1341 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1342 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1343 type_tucmd, mss_l4len_idx); 1344 1345 return 1; 1346 } 1347 1348 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1349 u8 ptype) 1350 { 1351 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0; 1352 struct net_device *netdev = tx_ring->netdev; 1353 u32 mss_l4len_idx = 0, type_tucmd; 1354 struct sk_buff *skb = first->skb; 1355 u8 tun_prot = 0; 1356 1357 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1358 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) && 1359 !(first->tx_flags & WX_TX_FLAGS_CC)) 1360 return; 1361 vlan_macip_lens = skb_network_offset(skb) << 1362 WX_TXD_MACLEN_SHIFT; 1363 } else { 1364 u8 l4_prot = 0; 1365 union { 1366 struct iphdr *ipv4; 1367 struct ipv6hdr *ipv6; 1368 u8 *raw; 1369 } network_hdr; 1370 union { 1371 struct tcphdr *tcphdr; 1372 u8 *raw; 1373 } transport_hdr; 1374 1375 if (skb->encapsulation) { 1376 network_hdr.raw = skb_inner_network_header(skb); 1377 transport_hdr.raw = skb_inner_transport_header(skb); 1378 vlan_macip_lens = skb_network_offset(skb) << 1379 WX_TXD_MACLEN_SHIFT; 1380 switch (first->protocol) { 1381 case htons(ETH_P_IP): 1382 tun_prot = ip_hdr(skb)->protocol; 1383 break; 1384 case htons(ETH_P_IPV6): 1385 tun_prot = ipv6_hdr(skb)->nexthdr; 1386 break; 1387 default: 1388 return; 1389 } 1390 switch (tun_prot) { 1391 case IPPROTO_UDP: 1392 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1393 tunhdr_eiplen_tunlen |= 1394 ((skb_network_header_len(skb) >> 2) << 1395 WX_TXD_OUTER_IPLEN_SHIFT) | 1396 (((skb_inner_mac_header(skb) - 1397 skb_transport_header(skb)) >> 1) << 1398 WX_TXD_TUNNEL_LEN_SHIFT); 1399 break; 1400 case IPPROTO_GRE: 1401 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1402 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1403 WX_TXD_OUTER_IPLEN_SHIFT) | 1404 (((skb_inner_mac_header(skb) - 1405 skb_transport_header(skb)) >> 1) << 1406 WX_TXD_TUNNEL_LEN_SHIFT); 1407 break; 1408 case IPPROTO_IPIP: 1409 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1410 (char *)ip_hdr(skb)) >> 2) << 1411 WX_TXD_OUTER_IPLEN_SHIFT; 1412 break; 1413 default: 1414 break; 1415 } 1416 1417 } else { 1418 network_hdr.raw = skb_network_header(skb); 1419 transport_hdr.raw = skb_transport_header(skb); 1420 vlan_macip_lens = skb_network_offset(skb) << 1421 WX_TXD_MACLEN_SHIFT; 1422 } 1423 1424 switch (network_hdr.ipv4->version) { 1425 case IPVERSION: 1426 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1427 l4_prot = network_hdr.ipv4->protocol; 1428 break; 1429 case 6: 1430 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1431 l4_prot = network_hdr.ipv6->nexthdr; 1432 break; 1433 default: 1434 break; 1435 } 1436 1437 switch (l4_prot) { 1438 case IPPROTO_TCP: 1439 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 1440 WX_TXD_L4LEN_SHIFT; 1441 break; 1442 case IPPROTO_SCTP: 1443 mss_l4len_idx = sizeof(struct sctphdr) << 1444 WX_TXD_L4LEN_SHIFT; 1445 break; 1446 case IPPROTO_UDP: 1447 mss_l4len_idx = sizeof(struct udphdr) << 1448 WX_TXD_L4LEN_SHIFT; 1449 break; 1450 default: 1451 break; 1452 } 1453 1454 /* update TX checksum flag */ 1455 first->tx_flags |= WX_TX_FLAGS_CSUM; 1456 } 1457 first->tx_flags |= WX_TX_FLAGS_CC; 1458 /* vlan_macip_lens: MACLEN, VLAN tag */ 1459 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1460 1461 type_tucmd = ptype << 24; 1462 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1463 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1464 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1465 WX_TX_FLAGS_HW_VLAN, 1466 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1467 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1468 type_tucmd, mss_l4len_idx); 1469 } 1470 1471 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb, 1472 struct wx_ring *tx_ring) 1473 { 1474 struct wx *wx = netdev_priv(tx_ring->netdev); 1475 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1476 struct wx_tx_buffer *first; 1477 u8 hdr_len = 0, ptype; 1478 unsigned short f; 1479 u32 tx_flags = 0; 1480 int tso; 1481 1482 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD, 1483 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD, 1484 * + 2 desc gap to keep tail from touching head, 1485 * + 1 desc for context descriptor, 1486 * otherwise try next time 1487 */ 1488 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1489 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)-> 1490 frags[f])); 1491 1492 if (wx_maybe_stop_tx(tx_ring, count + 3)) { 1493 tx_ring->tx_stats.tx_busy++; 1494 return NETDEV_TX_BUSY; 1495 } 1496 1497 /* record the location of the first descriptor for this packet */ 1498 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1499 first->skb = skb; 1500 first->bytecount = skb->len; 1501 first->gso_segs = 1; 1502 1503 /* if we have a HW VLAN tag being added default to the HW one */ 1504 if (skb_vlan_tag_present(skb)) { 1505 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT; 1506 tx_flags |= WX_TX_FLAGS_HW_VLAN; 1507 } 1508 1509 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1510 wx->ptp_clock) { 1511 if (wx->tstamp_config.tx_type == HWTSTAMP_TX_ON && 1512 !test_and_set_bit_lock(WX_STATE_PTP_TX_IN_PROGRESS, 1513 wx->state)) { 1514 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1515 tx_flags |= WX_TX_FLAGS_TSTAMP; 1516 wx->ptp_tx_skb = skb_get(skb); 1517 wx->ptp_tx_start = jiffies; 1518 } else { 1519 wx->tx_hwtstamp_skipped++; 1520 } 1521 } 1522 1523 /* record initial flags and protocol */ 1524 first->tx_flags = tx_flags; 1525 first->protocol = vlan_get_protocol(skb); 1526 1527 ptype = wx_encode_tx_desc_ptype(first); 1528 1529 tso = wx_tso(tx_ring, first, &hdr_len, ptype); 1530 if (tso < 0) 1531 goto out_drop; 1532 else if (!tso) 1533 wx_tx_csum(tx_ring, first, ptype); 1534 1535 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate) 1536 wx->atr(tx_ring, first, ptype); 1537 1538 if (wx_tx_map(tx_ring, first, hdr_len)) 1539 goto cleanup_tx_tstamp; 1540 1541 return NETDEV_TX_OK; 1542 out_drop: 1543 dev_kfree_skb_any(first->skb); 1544 first->skb = NULL; 1545 cleanup_tx_tstamp: 1546 if (unlikely(tx_flags & WX_TX_FLAGS_TSTAMP)) { 1547 dev_kfree_skb_any(wx->ptp_tx_skb); 1548 wx->ptp_tx_skb = NULL; 1549 wx->tx_hwtstamp_errors++; 1550 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 1551 } 1552 1553 return NETDEV_TX_OK; 1554 } 1555 1556 netdev_tx_t wx_xmit_frame(struct sk_buff *skb, 1557 struct net_device *netdev) 1558 { 1559 unsigned int r_idx = skb->queue_mapping; 1560 struct wx *wx = netdev_priv(netdev); 1561 struct wx_ring *tx_ring; 1562 1563 if (!netif_carrier_ok(netdev)) { 1564 dev_kfree_skb_any(skb); 1565 return NETDEV_TX_OK; 1566 } 1567 1568 /* The minimum packet size for olinfo paylen is 17 so pad the skb 1569 * in order to meet this minimum size requirement. 1570 */ 1571 if (skb_put_padto(skb, 17)) 1572 return NETDEV_TX_OK; 1573 1574 if (r_idx >= wx->num_tx_queues) 1575 r_idx = r_idx % wx->num_tx_queues; 1576 tx_ring = wx->tx_ring[r_idx]; 1577 1578 return wx_xmit_frame_ring(skb, tx_ring); 1579 } 1580 EXPORT_SYMBOL(wx_xmit_frame); 1581 1582 void wx_napi_enable_all(struct wx *wx) 1583 { 1584 struct wx_q_vector *q_vector; 1585 int q_idx; 1586 1587 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1588 q_vector = wx->q_vector[q_idx]; 1589 napi_enable(&q_vector->napi); 1590 } 1591 } 1592 EXPORT_SYMBOL(wx_napi_enable_all); 1593 1594 void wx_napi_disable_all(struct wx *wx) 1595 { 1596 struct wx_q_vector *q_vector; 1597 int q_idx; 1598 1599 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1600 q_vector = wx->q_vector[q_idx]; 1601 napi_disable(&q_vector->napi); 1602 } 1603 } 1604 EXPORT_SYMBOL(wx_napi_disable_all); 1605 1606 /** 1607 * wx_set_rss_queues: Allocate queues for RSS 1608 * @wx: board private structure to initialize 1609 * 1610 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1611 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1612 * 1613 **/ 1614 static void wx_set_rss_queues(struct wx *wx) 1615 { 1616 struct wx_ring_feature *f; 1617 1618 /* set mask for 16 queue limit of RSS */ 1619 f = &wx->ring_feature[RING_F_RSS]; 1620 f->indices = f->limit; 1621 1622 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 1623 goto out; 1624 1625 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 1626 1627 /* Use Flow Director in addition to RSS to ensure the best 1628 * distribution of flows across cores, even when an FDIR flow 1629 * isn't matched. 1630 */ 1631 if (f->indices > 1) { 1632 f = &wx->ring_feature[RING_F_FDIR]; 1633 1634 f->indices = f->limit; 1635 1636 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 1637 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 1638 } 1639 1640 out: 1641 wx->num_rx_queues = f->indices; 1642 wx->num_tx_queues = f->indices; 1643 } 1644 1645 static void wx_set_num_queues(struct wx *wx) 1646 { 1647 /* Start with base case */ 1648 wx->num_rx_queues = 1; 1649 wx->num_tx_queues = 1; 1650 wx->queues_per_pool = 1; 1651 1652 wx_set_rss_queues(wx); 1653 } 1654 1655 /** 1656 * wx_acquire_msix_vectors - acquire MSI-X vectors 1657 * @wx: board private structure 1658 * 1659 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will 1660 * return a negative error code if unable to acquire MSI-X vectors for any 1661 * reason. 1662 */ 1663 static int wx_acquire_msix_vectors(struct wx *wx) 1664 { 1665 struct irq_affinity affd = { .pre_vectors = 1 }; 1666 int nvecs, i; 1667 1668 /* We start by asking for one vector per queue pair */ 1669 nvecs = max(wx->num_rx_queues, wx->num_tx_queues); 1670 nvecs = min_t(int, nvecs, num_online_cpus()); 1671 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors); 1672 1673 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry), 1674 GFP_KERNEL); 1675 if (!wx->msix_q_entries) 1676 return -ENOMEM; 1677 1678 /* One for non-queue interrupts */ 1679 nvecs += 1; 1680 1681 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry), 1682 GFP_KERNEL); 1683 if (!wx->msix_entry) { 1684 kfree(wx->msix_q_entries); 1685 wx->msix_q_entries = NULL; 1686 return -ENOMEM; 1687 } 1688 1689 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs, 1690 nvecs, 1691 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, 1692 &affd); 1693 if (nvecs < 0) { 1694 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs); 1695 kfree(wx->msix_q_entries); 1696 wx->msix_q_entries = NULL; 1697 kfree(wx->msix_entry); 1698 wx->msix_entry = NULL; 1699 return nvecs; 1700 } 1701 1702 wx->msix_entry->entry = 0; 1703 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0); 1704 nvecs -= 1; 1705 for (i = 0; i < nvecs; i++) { 1706 wx->msix_q_entries[i].entry = i; 1707 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i + 1); 1708 } 1709 1710 wx->num_q_vectors = nvecs; 1711 1712 return 0; 1713 } 1714 1715 /** 1716 * wx_set_interrupt_capability - set MSI-X or MSI if supported 1717 * @wx: board private structure to initialize 1718 * 1719 * Attempt to configure the interrupts using the best available 1720 * capabilities of the hardware and the kernel. 1721 **/ 1722 static int wx_set_interrupt_capability(struct wx *wx) 1723 { 1724 struct pci_dev *pdev = wx->pdev; 1725 int nvecs, ret; 1726 1727 /* We will try to get MSI-X interrupts first */ 1728 ret = wx_acquire_msix_vectors(wx); 1729 if (ret == 0 || (ret == -ENOMEM)) 1730 return ret; 1731 1732 /* Disable RSS */ 1733 dev_warn(&wx->pdev->dev, "Disabling RSS support\n"); 1734 wx->ring_feature[RING_F_RSS].limit = 1; 1735 1736 wx_set_num_queues(wx); 1737 1738 /* minmum one for queue, one for misc*/ 1739 nvecs = 1; 1740 nvecs = pci_alloc_irq_vectors(pdev, nvecs, 1741 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX); 1742 if (nvecs == 1) { 1743 if (pdev->msi_enabled) 1744 wx_err(wx, "Fallback to MSI.\n"); 1745 else 1746 wx_err(wx, "Fallback to INTx.\n"); 1747 } else { 1748 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs); 1749 return nvecs; 1750 } 1751 1752 pdev->irq = pci_irq_vector(pdev, 0); 1753 wx->num_q_vectors = 1; 1754 1755 return 0; 1756 } 1757 1758 /** 1759 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS 1760 * @wx: board private structure to initialize 1761 * 1762 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV. 1763 * 1764 **/ 1765 static void wx_cache_ring_rss(struct wx *wx) 1766 { 1767 u16 i; 1768 1769 for (i = 0; i < wx->num_rx_queues; i++) 1770 wx->rx_ring[i]->reg_idx = i; 1771 1772 for (i = 0; i < wx->num_tx_queues; i++) 1773 wx->tx_ring[i]->reg_idx = i; 1774 } 1775 1776 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head) 1777 { 1778 ring->next = head->ring; 1779 head->ring = ring; 1780 head->count++; 1781 } 1782 1783 /** 1784 * wx_alloc_q_vector - Allocate memory for a single interrupt vector 1785 * @wx: board private structure to initialize 1786 * @v_count: q_vectors allocated on wx, used for ring interleaving 1787 * @v_idx: index of vector in wx struct 1788 * @txr_count: total number of Tx rings to allocate 1789 * @txr_idx: index of first Tx ring to allocate 1790 * @rxr_count: total number of Rx rings to allocate 1791 * @rxr_idx: index of first Rx ring to allocate 1792 * 1793 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1794 **/ 1795 static int wx_alloc_q_vector(struct wx *wx, 1796 unsigned int v_count, unsigned int v_idx, 1797 unsigned int txr_count, unsigned int txr_idx, 1798 unsigned int rxr_count, unsigned int rxr_idx) 1799 { 1800 struct wx_q_vector *q_vector; 1801 int ring_count, default_itr; 1802 struct wx_ring *ring; 1803 1804 /* note this will allocate space for the ring structure as well! */ 1805 ring_count = txr_count + rxr_count; 1806 1807 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 1808 GFP_KERNEL); 1809 if (!q_vector) 1810 return -ENOMEM; 1811 1812 /* initialize NAPI */ 1813 netif_napi_add(wx->netdev, &q_vector->napi, 1814 wx_poll); 1815 1816 /* tie q_vector and wx together */ 1817 wx->q_vector[v_idx] = q_vector; 1818 q_vector->wx = wx; 1819 q_vector->v_idx = v_idx; 1820 if (cpu_online(v_idx)) 1821 q_vector->numa_node = cpu_to_node(v_idx); 1822 1823 /* initialize pointer to rings */ 1824 ring = q_vector->ring; 1825 1826 switch (wx->mac.type) { 1827 case wx_mac_sp: 1828 case wx_mac_aml: 1829 default_itr = WX_12K_ITR; 1830 break; 1831 default: 1832 default_itr = WX_7K_ITR; 1833 break; 1834 } 1835 1836 /* initialize ITR */ 1837 if (txr_count && !rxr_count) 1838 /* tx only vector */ 1839 q_vector->itr = wx->tx_itr_setting ? 1840 default_itr : wx->tx_itr_setting; 1841 else 1842 /* rx or rx/tx vector */ 1843 q_vector->itr = wx->rx_itr_setting ? 1844 default_itr : wx->rx_itr_setting; 1845 1846 while (txr_count) { 1847 /* assign generic ring traits */ 1848 ring->dev = &wx->pdev->dev; 1849 ring->netdev = wx->netdev; 1850 1851 /* configure backlink on ring */ 1852 ring->q_vector = q_vector; 1853 1854 /* update q_vector Tx values */ 1855 wx_add_ring(ring, &q_vector->tx); 1856 1857 /* apply Tx specific ring traits */ 1858 ring->count = wx->tx_ring_count; 1859 1860 ring->queue_index = txr_idx; 1861 1862 /* assign ring to wx */ 1863 wx->tx_ring[txr_idx] = ring; 1864 1865 /* update count and index */ 1866 txr_count--; 1867 txr_idx += v_count; 1868 1869 /* push pointer to next ring */ 1870 ring++; 1871 } 1872 1873 while (rxr_count) { 1874 /* assign generic ring traits */ 1875 ring->dev = &wx->pdev->dev; 1876 ring->netdev = wx->netdev; 1877 1878 /* configure backlink on ring */ 1879 ring->q_vector = q_vector; 1880 1881 /* update q_vector Rx values */ 1882 wx_add_ring(ring, &q_vector->rx); 1883 1884 /* apply Rx specific ring traits */ 1885 ring->count = wx->rx_ring_count; 1886 ring->queue_index = rxr_idx; 1887 1888 /* assign ring to wx */ 1889 wx->rx_ring[rxr_idx] = ring; 1890 1891 /* update count and index */ 1892 rxr_count--; 1893 rxr_idx += v_count; 1894 1895 /* push pointer to next ring */ 1896 ring++; 1897 } 1898 1899 return 0; 1900 } 1901 1902 /** 1903 * wx_free_q_vector - Free memory allocated for specific interrupt vector 1904 * @wx: board private structure to initialize 1905 * @v_idx: Index of vector to be freed 1906 * 1907 * This function frees the memory allocated to the q_vector. In addition if 1908 * NAPI is enabled it will delete any references to the NAPI struct prior 1909 * to freeing the q_vector. 1910 **/ 1911 static void wx_free_q_vector(struct wx *wx, int v_idx) 1912 { 1913 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 1914 struct wx_ring *ring; 1915 1916 wx_for_each_ring(ring, q_vector->tx) 1917 wx->tx_ring[ring->queue_index] = NULL; 1918 1919 wx_for_each_ring(ring, q_vector->rx) 1920 wx->rx_ring[ring->queue_index] = NULL; 1921 1922 wx->q_vector[v_idx] = NULL; 1923 netif_napi_del(&q_vector->napi); 1924 kfree_rcu(q_vector, rcu); 1925 } 1926 1927 /** 1928 * wx_alloc_q_vectors - Allocate memory for interrupt vectors 1929 * @wx: board private structure to initialize 1930 * 1931 * We allocate one q_vector per queue interrupt. If allocation fails we 1932 * return -ENOMEM. 1933 **/ 1934 static int wx_alloc_q_vectors(struct wx *wx) 1935 { 1936 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1937 unsigned int rxr_remaining = wx->num_rx_queues; 1938 unsigned int txr_remaining = wx->num_tx_queues; 1939 unsigned int q_vectors = wx->num_q_vectors; 1940 int rqpv, tqpv; 1941 int err; 1942 1943 for (; v_idx < q_vectors; v_idx++) { 1944 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1945 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1946 err = wx_alloc_q_vector(wx, q_vectors, v_idx, 1947 tqpv, txr_idx, 1948 rqpv, rxr_idx); 1949 1950 if (err) 1951 goto err_out; 1952 1953 /* update counts and index */ 1954 rxr_remaining -= rqpv; 1955 txr_remaining -= tqpv; 1956 rxr_idx++; 1957 txr_idx++; 1958 } 1959 1960 return 0; 1961 1962 err_out: 1963 wx->num_tx_queues = 0; 1964 wx->num_rx_queues = 0; 1965 wx->num_q_vectors = 0; 1966 1967 while (v_idx--) 1968 wx_free_q_vector(wx, v_idx); 1969 1970 return -ENOMEM; 1971 } 1972 1973 /** 1974 * wx_free_q_vectors - Free memory allocated for interrupt vectors 1975 * @wx: board private structure to initialize 1976 * 1977 * This function frees the memory allocated to the q_vectors. In addition if 1978 * NAPI is enabled it will delete any references to the NAPI struct prior 1979 * to freeing the q_vector. 1980 **/ 1981 static void wx_free_q_vectors(struct wx *wx) 1982 { 1983 int v_idx = wx->num_q_vectors; 1984 1985 wx->num_tx_queues = 0; 1986 wx->num_rx_queues = 0; 1987 wx->num_q_vectors = 0; 1988 1989 while (v_idx--) 1990 wx_free_q_vector(wx, v_idx); 1991 } 1992 1993 void wx_reset_interrupt_capability(struct wx *wx) 1994 { 1995 struct pci_dev *pdev = wx->pdev; 1996 1997 if (!pdev->msi_enabled && !pdev->msix_enabled) 1998 return; 1999 2000 if (pdev->msix_enabled) { 2001 kfree(wx->msix_q_entries); 2002 wx->msix_q_entries = NULL; 2003 kfree(wx->msix_entry); 2004 wx->msix_entry = NULL; 2005 } 2006 pci_free_irq_vectors(wx->pdev); 2007 } 2008 EXPORT_SYMBOL(wx_reset_interrupt_capability); 2009 2010 /** 2011 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings 2012 * @wx: board private structure to clear interrupt scheme on 2013 * 2014 * We go through and clear interrupt specific resources and reset the structure 2015 * to pre-load conditions 2016 **/ 2017 void wx_clear_interrupt_scheme(struct wx *wx) 2018 { 2019 wx_free_q_vectors(wx); 2020 wx_reset_interrupt_capability(wx); 2021 } 2022 EXPORT_SYMBOL(wx_clear_interrupt_scheme); 2023 2024 int wx_init_interrupt_scheme(struct wx *wx) 2025 { 2026 int ret; 2027 2028 /* Number of supported queues */ 2029 wx_set_num_queues(wx); 2030 2031 /* Set interrupt mode */ 2032 ret = wx_set_interrupt_capability(wx); 2033 if (ret) { 2034 wx_err(wx, "Allocate irq vectors for failed.\n"); 2035 return ret; 2036 } 2037 2038 /* Allocate memory for queues */ 2039 ret = wx_alloc_q_vectors(wx); 2040 if (ret) { 2041 wx_err(wx, "Unable to allocate memory for queue vectors.\n"); 2042 wx_reset_interrupt_capability(wx); 2043 return ret; 2044 } 2045 2046 wx_cache_ring_rss(wx); 2047 2048 return 0; 2049 } 2050 EXPORT_SYMBOL(wx_init_interrupt_scheme); 2051 2052 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data) 2053 { 2054 struct wx_q_vector *q_vector = data; 2055 2056 /* EIAM disabled interrupts (on this vector) for us */ 2057 if (q_vector->rx.ring || q_vector->tx.ring) 2058 napi_schedule_irqoff(&q_vector->napi); 2059 2060 return IRQ_HANDLED; 2061 } 2062 EXPORT_SYMBOL(wx_msix_clean_rings); 2063 2064 void wx_free_irq(struct wx *wx) 2065 { 2066 struct pci_dev *pdev = wx->pdev; 2067 int vector; 2068 2069 if (!(pdev->msix_enabled)) { 2070 if (!wx->misc_irq_domain) 2071 free_irq(pdev->irq, wx); 2072 return; 2073 } 2074 2075 for (vector = 0; vector < wx->num_q_vectors; vector++) { 2076 struct wx_q_vector *q_vector = wx->q_vector[vector]; 2077 struct msix_entry *entry = &wx->msix_q_entries[vector]; 2078 2079 /* free only the irqs that were actually requested */ 2080 if (!q_vector->rx.ring && !q_vector->tx.ring) 2081 continue; 2082 2083 free_irq(entry->vector, q_vector); 2084 } 2085 2086 if (!wx->misc_irq_domain) 2087 free_irq(wx->msix_entry->vector, wx); 2088 } 2089 EXPORT_SYMBOL(wx_free_irq); 2090 2091 /** 2092 * wx_setup_isb_resources - allocate interrupt status resources 2093 * @wx: board private structure 2094 * 2095 * Return 0 on success, negative on failure 2096 **/ 2097 int wx_setup_isb_resources(struct wx *wx) 2098 { 2099 struct pci_dev *pdev = wx->pdev; 2100 2101 if (wx->isb_mem) 2102 return 0; 2103 2104 wx->isb_mem = dma_alloc_coherent(&pdev->dev, 2105 sizeof(u32) * 4, 2106 &wx->isb_dma, 2107 GFP_KERNEL); 2108 if (!wx->isb_mem) { 2109 wx_err(wx, "Alloc isb_mem failed\n"); 2110 return -ENOMEM; 2111 } 2112 2113 return 0; 2114 } 2115 EXPORT_SYMBOL(wx_setup_isb_resources); 2116 2117 /** 2118 * wx_free_isb_resources - allocate all queues Rx resources 2119 * @wx: board private structure 2120 * 2121 * Return 0 on success, negative on failure 2122 **/ 2123 void wx_free_isb_resources(struct wx *wx) 2124 { 2125 struct pci_dev *pdev = wx->pdev; 2126 2127 dma_free_coherent(&pdev->dev, sizeof(u32) * 4, 2128 wx->isb_mem, wx->isb_dma); 2129 wx->isb_mem = NULL; 2130 } 2131 EXPORT_SYMBOL(wx_free_isb_resources); 2132 2133 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx) 2134 { 2135 u32 cur_tag = 0; 2136 2137 cur_tag = wx->isb_mem[WX_ISB_HEADER]; 2138 wx->isb_tag[idx] = cur_tag; 2139 2140 return (__force u32)cpu_to_le32(wx->isb_mem[idx]); 2141 } 2142 EXPORT_SYMBOL(wx_misc_isb); 2143 2144 /** 2145 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 2146 * @wx: pointer to wx struct 2147 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 2148 * @queue: queue to map the corresponding interrupt to 2149 * @msix_vector: the vector to map to the corresponding queue 2150 * 2151 **/ 2152 static void wx_set_ivar(struct wx *wx, s8 direction, 2153 u16 queue, u16 msix_vector) 2154 { 2155 u32 ivar, index; 2156 2157 if (direction == -1) { 2158 /* other causes */ 2159 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2160 index = 0; 2161 ivar = rd32(wx, WX_PX_MISC_IVAR); 2162 ivar &= ~(0xFF << index); 2163 ivar |= (msix_vector << index); 2164 wr32(wx, WX_PX_MISC_IVAR, ivar); 2165 } else { 2166 /* tx or rx causes */ 2167 msix_vector += 1; /* offset for queue vectors */ 2168 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2169 index = ((16 * (queue & 1)) + (8 * direction)); 2170 ivar = rd32(wx, WX_PX_IVAR(queue >> 1)); 2171 ivar &= ~(0xFF << index); 2172 ivar |= (msix_vector << index); 2173 wr32(wx, WX_PX_IVAR(queue >> 1), ivar); 2174 } 2175 } 2176 2177 /** 2178 * wx_write_eitr - write EITR register in hardware specific way 2179 * @q_vector: structure containing interrupt and ring information 2180 * 2181 * This function is made to be called by ethtool and by the driver 2182 * when it needs to update EITR registers at runtime. Hardware 2183 * specific quirks/differences are taken care of here. 2184 */ 2185 void wx_write_eitr(struct wx_q_vector *q_vector) 2186 { 2187 struct wx *wx = q_vector->wx; 2188 int v_idx = q_vector->v_idx; 2189 u32 itr_reg; 2190 2191 switch (wx->mac.type) { 2192 case wx_mac_sp: 2193 itr_reg = q_vector->itr & WX_SP_MAX_EITR; 2194 break; 2195 case wx_mac_aml: 2196 itr_reg = (q_vector->itr >> 3) & WX_AML_MAX_EITR; 2197 break; 2198 default: 2199 itr_reg = q_vector->itr & WX_EM_MAX_EITR; 2200 break; 2201 } 2202 2203 itr_reg |= WX_PX_ITR_CNT_WDIS; 2204 2205 wr32(wx, WX_PX_ITR(v_idx + 1), itr_reg); 2206 } 2207 2208 /** 2209 * wx_configure_vectors - Configure vectors for hardware 2210 * @wx: board private structure 2211 * 2212 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx 2213 * interrupts. 2214 **/ 2215 void wx_configure_vectors(struct wx *wx) 2216 { 2217 struct pci_dev *pdev = wx->pdev; 2218 u32 eitrsel = 0; 2219 u16 v_idx; 2220 2221 if (pdev->msix_enabled) { 2222 /* Populate MSIX to EITR Select */ 2223 wr32(wx, WX_PX_ITRSEL, eitrsel); 2224 /* use EIAM to auto-mask when MSI-X interrupt is asserted 2225 * this saves a register write for every interrupt 2226 */ 2227 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL); 2228 } else { 2229 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 2230 * specifically only auto mask tx and rx interrupts. 2231 */ 2232 wr32(wx, WX_PX_GPIE, 0); 2233 } 2234 2235 /* Populate the IVAR table and set the ITR values to the 2236 * corresponding register. 2237 */ 2238 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) { 2239 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2240 struct wx_ring *ring; 2241 2242 wx_for_each_ring(ring, q_vector->rx) 2243 wx_set_ivar(wx, 0, ring->reg_idx, v_idx); 2244 2245 wx_for_each_ring(ring, q_vector->tx) 2246 wx_set_ivar(wx, 1, ring->reg_idx, v_idx); 2247 2248 wx_write_eitr(q_vector); 2249 } 2250 2251 wx_set_ivar(wx, -1, 0, 0); 2252 if (pdev->msix_enabled) 2253 wr32(wx, WX_PX_ITR(0), 1950); 2254 } 2255 EXPORT_SYMBOL(wx_configure_vectors); 2256 2257 /** 2258 * wx_clean_rx_ring - Free Rx Buffers per Queue 2259 * @rx_ring: ring to free buffers from 2260 **/ 2261 static void wx_clean_rx_ring(struct wx_ring *rx_ring) 2262 { 2263 struct wx_rx_buffer *rx_buffer; 2264 u16 i = rx_ring->next_to_clean; 2265 2266 rx_buffer = &rx_ring->rx_buffer_info[i]; 2267 2268 /* Free all the Rx ring sk_buffs */ 2269 while (i != rx_ring->next_to_alloc) { 2270 if (rx_buffer->skb) { 2271 struct sk_buff *skb = rx_buffer->skb; 2272 2273 if (WX_CB(skb)->page_released) 2274 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2275 2276 dev_kfree_skb(skb); 2277 } 2278 2279 /* Invalidate cache lines that may have been written to by 2280 * device so that we avoid corrupting memory. 2281 */ 2282 dma_sync_single_range_for_cpu(rx_ring->dev, 2283 rx_buffer->dma, 2284 rx_buffer->page_offset, 2285 WX_RX_BUFSZ, 2286 DMA_FROM_DEVICE); 2287 2288 /* free resources associated with mapping */ 2289 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2290 2291 i++; 2292 rx_buffer++; 2293 if (i == rx_ring->count) { 2294 i = 0; 2295 rx_buffer = rx_ring->rx_buffer_info; 2296 } 2297 } 2298 2299 rx_ring->next_to_alloc = 0; 2300 rx_ring->next_to_clean = 0; 2301 rx_ring->next_to_use = 0; 2302 } 2303 2304 /** 2305 * wx_clean_all_rx_rings - Free Rx Buffers for all queues 2306 * @wx: board private structure 2307 **/ 2308 void wx_clean_all_rx_rings(struct wx *wx) 2309 { 2310 int i; 2311 2312 for (i = 0; i < wx->num_rx_queues; i++) 2313 wx_clean_rx_ring(wx->rx_ring[i]); 2314 } 2315 EXPORT_SYMBOL(wx_clean_all_rx_rings); 2316 2317 /** 2318 * wx_free_rx_resources - Free Rx Resources 2319 * @rx_ring: ring to clean the resources from 2320 * 2321 * Free all receive software resources 2322 **/ 2323 static void wx_free_rx_resources(struct wx_ring *rx_ring) 2324 { 2325 wx_clean_rx_ring(rx_ring); 2326 kvfree(rx_ring->rx_buffer_info); 2327 rx_ring->rx_buffer_info = NULL; 2328 2329 /* if not set, then don't free */ 2330 if (!rx_ring->desc) 2331 return; 2332 2333 dma_free_coherent(rx_ring->dev, rx_ring->size, 2334 rx_ring->desc, rx_ring->dma); 2335 2336 rx_ring->desc = NULL; 2337 2338 if (rx_ring->page_pool) { 2339 page_pool_destroy(rx_ring->page_pool); 2340 rx_ring->page_pool = NULL; 2341 } 2342 } 2343 2344 /** 2345 * wx_free_all_rx_resources - Free Rx Resources for All Queues 2346 * @wx: pointer to hardware structure 2347 * 2348 * Free all receive software resources 2349 **/ 2350 static void wx_free_all_rx_resources(struct wx *wx) 2351 { 2352 int i; 2353 2354 for (i = 0; i < wx->num_rx_queues; i++) 2355 wx_free_rx_resources(wx->rx_ring[i]); 2356 } 2357 2358 /** 2359 * wx_clean_tx_ring - Free Tx Buffers 2360 * @tx_ring: ring to be cleaned 2361 **/ 2362 static void wx_clean_tx_ring(struct wx_ring *tx_ring) 2363 { 2364 struct wx_tx_buffer *tx_buffer; 2365 u16 i = tx_ring->next_to_clean; 2366 2367 tx_buffer = &tx_ring->tx_buffer_info[i]; 2368 2369 while (i != tx_ring->next_to_use) { 2370 union wx_tx_desc *eop_desc, *tx_desc; 2371 2372 /* Free all the Tx ring sk_buffs */ 2373 dev_kfree_skb_any(tx_buffer->skb); 2374 2375 /* unmap skb header data */ 2376 dma_unmap_single(tx_ring->dev, 2377 dma_unmap_addr(tx_buffer, dma), 2378 dma_unmap_len(tx_buffer, len), 2379 DMA_TO_DEVICE); 2380 2381 /* check for eop_desc to determine the end of the packet */ 2382 eop_desc = tx_buffer->next_to_watch; 2383 tx_desc = WX_TX_DESC(tx_ring, i); 2384 2385 /* unmap remaining buffers */ 2386 while (tx_desc != eop_desc) { 2387 tx_buffer++; 2388 tx_desc++; 2389 i++; 2390 if (unlikely(i == tx_ring->count)) { 2391 i = 0; 2392 tx_buffer = tx_ring->tx_buffer_info; 2393 tx_desc = WX_TX_DESC(tx_ring, 0); 2394 } 2395 2396 /* unmap any remaining paged data */ 2397 if (dma_unmap_len(tx_buffer, len)) 2398 dma_unmap_page(tx_ring->dev, 2399 dma_unmap_addr(tx_buffer, dma), 2400 dma_unmap_len(tx_buffer, len), 2401 DMA_TO_DEVICE); 2402 } 2403 2404 /* move us one more past the eop_desc for start of next pkt */ 2405 tx_buffer++; 2406 i++; 2407 if (unlikely(i == tx_ring->count)) { 2408 i = 0; 2409 tx_buffer = tx_ring->tx_buffer_info; 2410 } 2411 } 2412 2413 netdev_tx_reset_queue(wx_txring_txq(tx_ring)); 2414 2415 /* reset next_to_use and next_to_clean */ 2416 tx_ring->next_to_use = 0; 2417 tx_ring->next_to_clean = 0; 2418 } 2419 2420 /** 2421 * wx_clean_all_tx_rings - Free Tx Buffers for all queues 2422 * @wx: board private structure 2423 **/ 2424 void wx_clean_all_tx_rings(struct wx *wx) 2425 { 2426 int i; 2427 2428 for (i = 0; i < wx->num_tx_queues; i++) 2429 wx_clean_tx_ring(wx->tx_ring[i]); 2430 } 2431 EXPORT_SYMBOL(wx_clean_all_tx_rings); 2432 2433 /** 2434 * wx_free_tx_resources - Free Tx Resources per Queue 2435 * @tx_ring: Tx descriptor ring for a specific queue 2436 * 2437 * Free all transmit software resources 2438 **/ 2439 static void wx_free_tx_resources(struct wx_ring *tx_ring) 2440 { 2441 wx_clean_tx_ring(tx_ring); 2442 kvfree(tx_ring->tx_buffer_info); 2443 tx_ring->tx_buffer_info = NULL; 2444 2445 /* if not set, then don't free */ 2446 if (!tx_ring->desc) 2447 return; 2448 2449 dma_free_coherent(tx_ring->dev, tx_ring->size, 2450 tx_ring->desc, tx_ring->dma); 2451 tx_ring->desc = NULL; 2452 } 2453 2454 /** 2455 * wx_free_all_tx_resources - Free Tx Resources for All Queues 2456 * @wx: pointer to hardware structure 2457 * 2458 * Free all transmit software resources 2459 **/ 2460 static void wx_free_all_tx_resources(struct wx *wx) 2461 { 2462 int i; 2463 2464 for (i = 0; i < wx->num_tx_queues; i++) 2465 wx_free_tx_resources(wx->tx_ring[i]); 2466 } 2467 2468 void wx_free_resources(struct wx *wx) 2469 { 2470 wx_free_all_rx_resources(wx); 2471 wx_free_all_tx_resources(wx); 2472 } 2473 EXPORT_SYMBOL(wx_free_resources); 2474 2475 static int wx_alloc_page_pool(struct wx_ring *rx_ring) 2476 { 2477 int ret = 0; 2478 2479 struct page_pool_params pp_params = { 2480 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2481 .order = 0, 2482 .pool_size = rx_ring->size, 2483 .nid = dev_to_node(rx_ring->dev), 2484 .dev = rx_ring->dev, 2485 .dma_dir = DMA_FROM_DEVICE, 2486 .offset = 0, 2487 .max_len = PAGE_SIZE, 2488 }; 2489 2490 rx_ring->page_pool = page_pool_create(&pp_params); 2491 if (IS_ERR(rx_ring->page_pool)) { 2492 ret = PTR_ERR(rx_ring->page_pool); 2493 rx_ring->page_pool = NULL; 2494 } 2495 2496 return ret; 2497 } 2498 2499 /** 2500 * wx_setup_rx_resources - allocate Rx resources (Descriptors) 2501 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2502 * 2503 * Returns 0 on success, negative on failure 2504 **/ 2505 static int wx_setup_rx_resources(struct wx_ring *rx_ring) 2506 { 2507 struct device *dev = rx_ring->dev; 2508 int orig_node = dev_to_node(dev); 2509 int numa_node = NUMA_NO_NODE; 2510 int size, ret; 2511 2512 size = sizeof(struct wx_rx_buffer) * rx_ring->count; 2513 2514 if (rx_ring->q_vector) 2515 numa_node = rx_ring->q_vector->numa_node; 2516 2517 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2518 if (!rx_ring->rx_buffer_info) 2519 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL); 2520 if (!rx_ring->rx_buffer_info) 2521 goto err; 2522 2523 /* Round up to nearest 4K */ 2524 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc); 2525 rx_ring->size = ALIGN(rx_ring->size, 4096); 2526 2527 set_dev_node(dev, numa_node); 2528 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2529 &rx_ring->dma, GFP_KERNEL); 2530 if (!rx_ring->desc) { 2531 set_dev_node(dev, orig_node); 2532 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2533 &rx_ring->dma, GFP_KERNEL); 2534 } 2535 2536 if (!rx_ring->desc) 2537 goto err; 2538 2539 rx_ring->next_to_clean = 0; 2540 rx_ring->next_to_use = 0; 2541 2542 ret = wx_alloc_page_pool(rx_ring); 2543 if (ret < 0) { 2544 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret); 2545 goto err_desc; 2546 } 2547 2548 return 0; 2549 2550 err_desc: 2551 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2552 err: 2553 kvfree(rx_ring->rx_buffer_info); 2554 rx_ring->rx_buffer_info = NULL; 2555 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2556 return -ENOMEM; 2557 } 2558 2559 /** 2560 * wx_setup_all_rx_resources - allocate all queues Rx resources 2561 * @wx: pointer to hardware structure 2562 * 2563 * If this function returns with an error, then it's possible one or 2564 * more of the rings is populated (while the rest are not). It is the 2565 * callers duty to clean those orphaned rings. 2566 * 2567 * Return 0 on success, negative on failure 2568 **/ 2569 static int wx_setup_all_rx_resources(struct wx *wx) 2570 { 2571 int i, err = 0; 2572 2573 for (i = 0; i < wx->num_rx_queues; i++) { 2574 err = wx_setup_rx_resources(wx->rx_ring[i]); 2575 if (!err) 2576 continue; 2577 2578 wx_err(wx, "Allocation for Rx Queue %u failed\n", i); 2579 goto err_setup_rx; 2580 } 2581 2582 return 0; 2583 err_setup_rx: 2584 /* rewind the index freeing the rings as we go */ 2585 while (i--) 2586 wx_free_rx_resources(wx->rx_ring[i]); 2587 return err; 2588 } 2589 2590 /** 2591 * wx_setup_tx_resources - allocate Tx resources (Descriptors) 2592 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2593 * 2594 * Return 0 on success, negative on failure 2595 **/ 2596 static int wx_setup_tx_resources(struct wx_ring *tx_ring) 2597 { 2598 struct device *dev = tx_ring->dev; 2599 int orig_node = dev_to_node(dev); 2600 int numa_node = NUMA_NO_NODE; 2601 int size; 2602 2603 size = sizeof(struct wx_tx_buffer) * tx_ring->count; 2604 2605 if (tx_ring->q_vector) 2606 numa_node = tx_ring->q_vector->numa_node; 2607 2608 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2609 if (!tx_ring->tx_buffer_info) 2610 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL); 2611 if (!tx_ring->tx_buffer_info) 2612 goto err; 2613 2614 /* round up to nearest 4K */ 2615 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc); 2616 tx_ring->size = ALIGN(tx_ring->size, 4096); 2617 2618 set_dev_node(dev, numa_node); 2619 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2620 &tx_ring->dma, GFP_KERNEL); 2621 if (!tx_ring->desc) { 2622 set_dev_node(dev, orig_node); 2623 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2624 &tx_ring->dma, GFP_KERNEL); 2625 } 2626 2627 if (!tx_ring->desc) 2628 goto err; 2629 2630 tx_ring->next_to_use = 0; 2631 tx_ring->next_to_clean = 0; 2632 2633 return 0; 2634 2635 err: 2636 kvfree(tx_ring->tx_buffer_info); 2637 tx_ring->tx_buffer_info = NULL; 2638 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2639 return -ENOMEM; 2640 } 2641 2642 /** 2643 * wx_setup_all_tx_resources - allocate all queues Tx resources 2644 * @wx: pointer to private structure 2645 * 2646 * If this function returns with an error, then it's possible one or 2647 * more of the rings is populated (while the rest are not). It is the 2648 * callers duty to clean those orphaned rings. 2649 * 2650 * Return 0 on success, negative on failure 2651 **/ 2652 static int wx_setup_all_tx_resources(struct wx *wx) 2653 { 2654 int i, err = 0; 2655 2656 for (i = 0; i < wx->num_tx_queues; i++) { 2657 err = wx_setup_tx_resources(wx->tx_ring[i]); 2658 if (!err) 2659 continue; 2660 2661 wx_err(wx, "Allocation for Tx Queue %u failed\n", i); 2662 goto err_setup_tx; 2663 } 2664 2665 return 0; 2666 err_setup_tx: 2667 /* rewind the index freeing the rings as we go */ 2668 while (i--) 2669 wx_free_tx_resources(wx->tx_ring[i]); 2670 return err; 2671 } 2672 2673 int wx_setup_resources(struct wx *wx) 2674 { 2675 int err; 2676 2677 /* allocate transmit descriptors */ 2678 err = wx_setup_all_tx_resources(wx); 2679 if (err) 2680 return err; 2681 2682 /* allocate receive descriptors */ 2683 err = wx_setup_all_rx_resources(wx); 2684 if (err) 2685 goto err_free_tx; 2686 2687 err = wx_setup_isb_resources(wx); 2688 if (err) 2689 goto err_free_rx; 2690 2691 return 0; 2692 2693 err_free_rx: 2694 wx_free_all_rx_resources(wx); 2695 err_free_tx: 2696 wx_free_all_tx_resources(wx); 2697 2698 return err; 2699 } 2700 EXPORT_SYMBOL(wx_setup_resources); 2701 2702 /** 2703 * wx_get_stats64 - Get System Network Statistics 2704 * @netdev: network interface device structure 2705 * @stats: storage space for 64bit statistics 2706 */ 2707 void wx_get_stats64(struct net_device *netdev, 2708 struct rtnl_link_stats64 *stats) 2709 { 2710 struct wx *wx = netdev_priv(netdev); 2711 struct wx_hw_stats *hwstats; 2712 int i; 2713 2714 wx_update_stats(wx); 2715 2716 rcu_read_lock(); 2717 for (i = 0; i < wx->num_rx_queues; i++) { 2718 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]); 2719 u64 bytes, packets; 2720 unsigned int start; 2721 2722 if (ring) { 2723 do { 2724 start = u64_stats_fetch_begin(&ring->syncp); 2725 packets = ring->stats.packets; 2726 bytes = ring->stats.bytes; 2727 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2728 stats->rx_packets += packets; 2729 stats->rx_bytes += bytes; 2730 } 2731 } 2732 2733 for (i = 0; i < wx->num_tx_queues; i++) { 2734 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]); 2735 u64 bytes, packets; 2736 unsigned int start; 2737 2738 if (ring) { 2739 do { 2740 start = u64_stats_fetch_begin(&ring->syncp); 2741 packets = ring->stats.packets; 2742 bytes = ring->stats.bytes; 2743 } while (u64_stats_fetch_retry(&ring->syncp, 2744 start)); 2745 stats->tx_packets += packets; 2746 stats->tx_bytes += bytes; 2747 } 2748 } 2749 2750 rcu_read_unlock(); 2751 2752 hwstats = &wx->stats; 2753 stats->rx_errors = hwstats->crcerrs + hwstats->rlec; 2754 stats->multicast = hwstats->qmprc; 2755 stats->rx_length_errors = hwstats->rlec; 2756 stats->rx_crc_errors = hwstats->crcerrs; 2757 } 2758 EXPORT_SYMBOL(wx_get_stats64); 2759 2760 int wx_set_features(struct net_device *netdev, netdev_features_t features) 2761 { 2762 netdev_features_t changed = netdev->features ^ features; 2763 struct wx *wx = netdev_priv(netdev); 2764 bool need_reset = false; 2765 2766 if (features & NETIF_F_RXHASH) { 2767 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 2768 WX_RDB_RA_CTL_RSS_EN); 2769 wx->rss_enabled = true; 2770 } else { 2771 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0); 2772 wx->rss_enabled = false; 2773 } 2774 2775 netdev->features = features; 2776 2777 if (changed & NETIF_F_HW_VLAN_CTAG_RX && wx->do_reset) 2778 wx->do_reset(netdev); 2779 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER)) 2780 wx_set_rx_mode(netdev); 2781 2782 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 2783 return 0; 2784 2785 /* Check if Flow Director n-tuple support was enabled or disabled. If 2786 * the state changed, we need to reset. 2787 */ 2788 switch (features & NETIF_F_NTUPLE) { 2789 case NETIF_F_NTUPLE: 2790 /* turn off ATR, enable perfect filters and reset */ 2791 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 2792 need_reset = true; 2793 2794 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 2795 break; 2796 default: 2797 /* turn off perfect filters, enable ATR and reset */ 2798 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 2799 need_reset = true; 2800 2801 /* We cannot enable ATR if RSS is disabled */ 2802 if (wx->ring_feature[RING_F_RSS].limit <= 1) 2803 break; 2804 2805 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 2806 break; 2807 } 2808 2809 if (need_reset && wx->do_reset) 2810 wx->do_reset(netdev); 2811 2812 return 0; 2813 } 2814 EXPORT_SYMBOL(wx_set_features); 2815 2816 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \ 2817 NETIF_F_HW_VLAN_STAG_RX) 2818 2819 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \ 2820 NETIF_F_HW_VLAN_STAG_TX) 2821 2822 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \ 2823 NETIF_F_HW_VLAN_STAG_FILTER) 2824 2825 netdev_features_t wx_fix_features(struct net_device *netdev, 2826 netdev_features_t features) 2827 { 2828 netdev_features_t changed = netdev->features ^ features; 2829 struct wx *wx = netdev_priv(netdev); 2830 2831 if (changed & NETIF_VLAN_STRIPPING_FEATURES) { 2832 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES && 2833 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) { 2834 features &= ~NETIF_VLAN_STRIPPING_FEATURES; 2835 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES; 2836 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off."); 2837 } 2838 } 2839 2840 if (changed & NETIF_VLAN_INSERTION_FEATURES) { 2841 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES && 2842 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) { 2843 features &= ~NETIF_VLAN_INSERTION_FEATURES; 2844 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES; 2845 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off."); 2846 } 2847 } 2848 2849 if (changed & NETIF_VLAN_FILTERING_FEATURES) { 2850 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES && 2851 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) { 2852 features &= ~NETIF_VLAN_FILTERING_FEATURES; 2853 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES; 2854 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off."); 2855 } 2856 } 2857 2858 return features; 2859 } 2860 EXPORT_SYMBOL(wx_fix_features); 2861 2862 void wx_set_ring(struct wx *wx, u32 new_tx_count, 2863 u32 new_rx_count, struct wx_ring *temp_ring) 2864 { 2865 int i, err = 0; 2866 2867 /* Setup new Tx resources and free the old Tx resources in that order. 2868 * We can then assign the new resources to the rings via a memcpy. 2869 * The advantage to this approach is that we are guaranteed to still 2870 * have resources even in the case of an allocation failure. 2871 */ 2872 if (new_tx_count != wx->tx_ring_count) { 2873 for (i = 0; i < wx->num_tx_queues; i++) { 2874 memcpy(&temp_ring[i], wx->tx_ring[i], 2875 sizeof(struct wx_ring)); 2876 2877 temp_ring[i].count = new_tx_count; 2878 err = wx_setup_tx_resources(&temp_ring[i]); 2879 if (err) { 2880 wx_err(wx, "setup new tx resources failed, keep using the old config\n"); 2881 while (i) { 2882 i--; 2883 wx_free_tx_resources(&temp_ring[i]); 2884 } 2885 return; 2886 } 2887 } 2888 2889 for (i = 0; i < wx->num_tx_queues; i++) { 2890 wx_free_tx_resources(wx->tx_ring[i]); 2891 2892 memcpy(wx->tx_ring[i], &temp_ring[i], 2893 sizeof(struct wx_ring)); 2894 } 2895 2896 wx->tx_ring_count = new_tx_count; 2897 } 2898 2899 /* Repeat the process for the Rx rings if needed */ 2900 if (new_rx_count != wx->rx_ring_count) { 2901 for (i = 0; i < wx->num_rx_queues; i++) { 2902 memcpy(&temp_ring[i], wx->rx_ring[i], 2903 sizeof(struct wx_ring)); 2904 2905 temp_ring[i].count = new_rx_count; 2906 err = wx_setup_rx_resources(&temp_ring[i]); 2907 if (err) { 2908 wx_err(wx, "setup new rx resources failed, keep using the old config\n"); 2909 while (i) { 2910 i--; 2911 wx_free_rx_resources(&temp_ring[i]); 2912 } 2913 return; 2914 } 2915 } 2916 2917 for (i = 0; i < wx->num_rx_queues; i++) { 2918 wx_free_rx_resources(wx->rx_ring[i]); 2919 memcpy(wx->rx_ring[i], &temp_ring[i], 2920 sizeof(struct wx_ring)); 2921 } 2922 2923 wx->rx_ring_count = new_rx_count; 2924 } 2925 } 2926 EXPORT_SYMBOL(wx_set_ring); 2927 2928 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers."); 2929 MODULE_LICENSE("GPL"); 2930