1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <net/ip6_checksum.h> 6 #include <net/page_pool/helpers.h> 7 #include <net/inet_ecn.h> 8 #include <linux/iopoll.h> 9 #include <linux/sctp.h> 10 #include <linux/pci.h> 11 #include <net/tcp.h> 12 #include <net/ip.h> 13 14 #include "wx_type.h" 15 #include "wx_lib.h" 16 #include "wx_hw.h" 17 18 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 19 static struct wx_dec_ptype wx_ptype_lookup[256] = { 20 /* L2: mac */ 21 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 22 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2), 23 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 24 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 25 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 26 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 27 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 28 29 /* L2: ethertype filter */ 30 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 31 32 /* L3: ip non-tunnel */ 33 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3), 34 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3), 35 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4), 36 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4), 37 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4), 38 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3), 39 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3), 40 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3), 41 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4), 42 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4), 43 44 /* L2: fcoe */ 45 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 46 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 47 48 /* IPv4 --> IPv4/IPv6 */ 49 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3), 50 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3), 51 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4), 52 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4), 53 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4), 54 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3), 55 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3), 56 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4), 57 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4), 58 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4), 59 60 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */ 61 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3), 62 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3), 63 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3), 64 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4), 65 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4), 66 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4), 67 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3), 68 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3), 69 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4), 70 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4), 71 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4), 72 73 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */ 74 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3), 75 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3), 76 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3), 77 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4), 78 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4), 79 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4), 80 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3), 81 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3), 82 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4), 83 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4), 84 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4), 85 86 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */ 87 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3), 88 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3), 89 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3), 90 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4), 91 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4), 92 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4), 93 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3), 94 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3), 95 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4), 96 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4), 97 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4), 98 99 /* IPv6 --> IPv4/IPv6 */ 100 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3), 101 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3), 102 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4), 103 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4), 104 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4), 105 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3), 106 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3), 107 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4), 108 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4), 109 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4), 110 111 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */ 112 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3), 113 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3), 114 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3), 115 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4), 116 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4), 117 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4), 118 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3), 119 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3), 120 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4), 121 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4), 122 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4), 123 124 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */ 125 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3), 126 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3), 127 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3), 128 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4), 129 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4), 130 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4), 131 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3), 132 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3), 133 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4), 134 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4), 135 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4), 136 137 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */ 138 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3), 139 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3), 140 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3), 141 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4), 142 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4), 143 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4), 144 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3), 145 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3), 146 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4), 147 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4), 148 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4), 149 }; 150 151 struct wx_dec_ptype wx_decode_ptype(const u8 ptype) 152 { 153 return wx_ptype_lookup[ptype]; 154 } 155 EXPORT_SYMBOL(wx_decode_ptype); 156 157 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */ 158 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc, 159 const u32 stat_err_bits) 160 { 161 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 162 } 163 164 static void wx_dma_sync_frag(struct wx_ring *rx_ring, 165 struct wx_rx_buffer *rx_buffer) 166 { 167 struct sk_buff *skb = rx_buffer->skb; 168 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 169 170 dma_sync_single_range_for_cpu(rx_ring->dev, 171 WX_CB(skb)->dma, 172 skb_frag_off(frag), 173 skb_frag_size(frag), 174 DMA_FROM_DEVICE); 175 176 /* If the page was released, just unmap it. */ 177 if (unlikely(WX_CB(skb)->page_released)) 178 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 179 } 180 181 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring, 182 union wx_rx_desc *rx_desc, 183 struct sk_buff **skb, 184 int *rx_buffer_pgcnt) 185 { 186 struct wx_rx_buffer *rx_buffer; 187 unsigned int size; 188 189 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 190 size = le16_to_cpu(rx_desc->wb.upper.length); 191 192 #if (PAGE_SIZE < 8192) 193 *rx_buffer_pgcnt = page_count(rx_buffer->page); 194 #else 195 *rx_buffer_pgcnt = 0; 196 #endif 197 198 prefetchw(rx_buffer->page); 199 *skb = rx_buffer->skb; 200 201 /* Delay unmapping of the first packet. It carries the header 202 * information, HW may still access the header after the writeback. 203 * Only unmap it when EOP is reached 204 */ 205 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) { 206 if (!*skb) 207 goto skip_sync; 208 } else { 209 if (*skb) 210 wx_dma_sync_frag(rx_ring, rx_buffer); 211 } 212 213 /* we are reusing so sync this buffer for CPU use */ 214 dma_sync_single_range_for_cpu(rx_ring->dev, 215 rx_buffer->dma, 216 rx_buffer->page_offset, 217 size, 218 DMA_FROM_DEVICE); 219 skip_sync: 220 return rx_buffer; 221 } 222 223 static void wx_put_rx_buffer(struct wx_ring *rx_ring, 224 struct wx_rx_buffer *rx_buffer, 225 struct sk_buff *skb, 226 int rx_buffer_pgcnt) 227 { 228 if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma) 229 /* the page has been released from the ring */ 230 WX_CB(skb)->page_released = true; 231 232 /* clear contents of rx_buffer */ 233 rx_buffer->page = NULL; 234 rx_buffer->skb = NULL; 235 } 236 237 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring, 238 struct wx_rx_buffer *rx_buffer, 239 union wx_rx_desc *rx_desc) 240 { 241 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 242 #if (PAGE_SIZE < 8192) 243 unsigned int truesize = WX_RX_BUFSZ; 244 #else 245 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 246 #endif 247 struct sk_buff *skb = rx_buffer->skb; 248 249 if (!skb) { 250 void *page_addr = page_address(rx_buffer->page) + 251 rx_buffer->page_offset; 252 253 /* prefetch first cache line of first page */ 254 prefetch(page_addr); 255 #if L1_CACHE_BYTES < 128 256 prefetch(page_addr + L1_CACHE_BYTES); 257 #endif 258 259 /* allocate a skb to store the frags */ 260 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256); 261 if (unlikely(!skb)) 262 return NULL; 263 264 /* we will be copying header into skb->data in 265 * pskb_may_pull so it is in our interest to prefetch 266 * it now to avoid a possible cache miss 267 */ 268 prefetchw(skb->data); 269 270 if (size <= WX_RXBUFFER_256) { 271 memcpy(__skb_put(skb, size), page_addr, 272 ALIGN(size, sizeof(long))); 273 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true); 274 return skb; 275 } 276 277 skb_mark_for_recycle(skb); 278 279 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) 280 WX_CB(skb)->dma = rx_buffer->dma; 281 282 skb_add_rx_frag(skb, 0, rx_buffer->page, 283 rx_buffer->page_offset, 284 size, truesize); 285 goto out; 286 287 } else { 288 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 289 rx_buffer->page_offset, size, truesize); 290 } 291 292 out: 293 #if (PAGE_SIZE < 8192) 294 /* flip page offset to other buffer */ 295 rx_buffer->page_offset ^= truesize; 296 #else 297 /* move offset up to the next cache line */ 298 rx_buffer->page_offset += truesize; 299 #endif 300 301 return skb; 302 } 303 304 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring, 305 struct wx_rx_buffer *bi) 306 { 307 struct page *page = bi->page; 308 dma_addr_t dma; 309 310 /* since we are recycling buffers we should seldom need to alloc */ 311 if (likely(page)) 312 return true; 313 314 page = page_pool_dev_alloc_pages(rx_ring->page_pool); 315 WARN_ON(!page); 316 dma = page_pool_get_dma_addr(page); 317 318 bi->page_dma = dma; 319 bi->page = page; 320 bi->page_offset = 0; 321 322 return true; 323 } 324 325 /** 326 * wx_alloc_rx_buffers - Replace used receive buffers 327 * @rx_ring: ring to place buffers on 328 * @cleaned_count: number of buffers to replace 329 **/ 330 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count) 331 { 332 u16 i = rx_ring->next_to_use; 333 union wx_rx_desc *rx_desc; 334 struct wx_rx_buffer *bi; 335 336 /* nothing to do */ 337 if (!cleaned_count) 338 return; 339 340 rx_desc = WX_RX_DESC(rx_ring, i); 341 bi = &rx_ring->rx_buffer_info[i]; 342 i -= rx_ring->count; 343 344 do { 345 if (!wx_alloc_mapped_page(rx_ring, bi)) 346 break; 347 348 /* sync the buffer for use by the device */ 349 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 350 bi->page_offset, 351 WX_RX_BUFSZ, 352 DMA_FROM_DEVICE); 353 354 rx_desc->read.pkt_addr = 355 cpu_to_le64(bi->page_dma + bi->page_offset); 356 357 rx_desc++; 358 bi++; 359 i++; 360 if (unlikely(!i)) { 361 rx_desc = WX_RX_DESC(rx_ring, 0); 362 bi = rx_ring->rx_buffer_info; 363 i -= rx_ring->count; 364 } 365 366 /* clear the status bits for the next_to_use descriptor */ 367 rx_desc->wb.upper.status_error = 0; 368 369 cleaned_count--; 370 } while (cleaned_count); 371 372 i += rx_ring->count; 373 374 if (rx_ring->next_to_use != i) { 375 rx_ring->next_to_use = i; 376 /* update next to alloc since we have filled the ring */ 377 rx_ring->next_to_alloc = i; 378 379 /* Force memory writes to complete before letting h/w 380 * know there are new descriptors to fetch. (Only 381 * applicable for weak-ordered memory model archs, 382 * such as IA-64). 383 */ 384 wmb(); 385 writel(i, rx_ring->tail); 386 } 387 } 388 389 u16 wx_desc_unused(struct wx_ring *ring) 390 { 391 u16 ntc = ring->next_to_clean; 392 u16 ntu = ring->next_to_use; 393 394 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 395 } 396 397 /** 398 * wx_is_non_eop - process handling of non-EOP buffers 399 * @rx_ring: Rx ring being processed 400 * @rx_desc: Rx descriptor for current buffer 401 * @skb: Current socket buffer containing buffer in progress 402 * 403 * This function updates next to clean. If the buffer is an EOP buffer 404 * this function exits returning false, otherwise it will place the 405 * sk_buff in the next buffer to be chained and return true indicating 406 * that this is in fact a non-EOP buffer. 407 **/ 408 static bool wx_is_non_eop(struct wx_ring *rx_ring, 409 union wx_rx_desc *rx_desc, 410 struct sk_buff *skb) 411 { 412 u32 ntc = rx_ring->next_to_clean + 1; 413 414 /* fetch, update, and store next to clean */ 415 ntc = (ntc < rx_ring->count) ? ntc : 0; 416 rx_ring->next_to_clean = ntc; 417 418 prefetch(WX_RX_DESC(rx_ring, ntc)); 419 420 /* if we are the last buffer then there is nothing else to do */ 421 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))) 422 return false; 423 424 rx_ring->rx_buffer_info[ntc].skb = skb; 425 rx_ring->rx_stats.non_eop_descs++; 426 427 return true; 428 } 429 430 static void wx_pull_tail(struct sk_buff *skb) 431 { 432 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 433 unsigned int pull_len; 434 unsigned char *va; 435 436 /* it is valid to use page_address instead of kmap since we are 437 * working with pages allocated out of the lomem pool per 438 * alloc_page(GFP_ATOMIC) 439 */ 440 va = skb_frag_address(frag); 441 442 /* we need the header to contain the greater of either ETH_HLEN or 443 * 60 bytes if the skb->len is less than 60 for skb_pad. 444 */ 445 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256); 446 447 /* align pull length to size of long to optimize memcpy performance */ 448 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 449 450 /* update all of the pointers */ 451 skb_frag_size_sub(frag, pull_len); 452 skb_frag_off_add(frag, pull_len); 453 skb->data_len -= pull_len; 454 skb->tail += pull_len; 455 } 456 457 /** 458 * wx_cleanup_headers - Correct corrupted or empty headers 459 * @rx_ring: rx descriptor ring packet is being transacted on 460 * @rx_desc: pointer to the EOP Rx descriptor 461 * @skb: pointer to current skb being fixed 462 * 463 * Check for corrupted packet headers caused by senders on the local L2 464 * embedded NIC switch not setting up their Tx Descriptors right. These 465 * should be very rare. 466 * 467 * Also address the case where we are pulling data in on pages only 468 * and as such no data is present in the skb header. 469 * 470 * In addition if skb is not at least 60 bytes we need to pad it so that 471 * it is large enough to qualify as a valid Ethernet frame. 472 * 473 * Returns true if an error was encountered and skb was freed. 474 **/ 475 static bool wx_cleanup_headers(struct wx_ring *rx_ring, 476 union wx_rx_desc *rx_desc, 477 struct sk_buff *skb) 478 { 479 struct net_device *netdev = rx_ring->netdev; 480 481 /* verify that the packet does not have any known errors */ 482 if (!netdev || 483 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) && 484 !(netdev->features & NETIF_F_RXALL))) { 485 dev_kfree_skb_any(skb); 486 return true; 487 } 488 489 /* place header in linear portion of buffer */ 490 if (!skb_headlen(skb)) 491 wx_pull_tail(skb); 492 493 /* if eth_skb_pad returns an error the skb was freed */ 494 if (eth_skb_pad(skb)) 495 return true; 496 497 return false; 498 } 499 500 static void wx_rx_hash(struct wx_ring *ring, 501 union wx_rx_desc *rx_desc, 502 struct sk_buff *skb) 503 { 504 u16 rss_type; 505 506 if (!(ring->netdev->features & NETIF_F_RXHASH)) 507 return; 508 509 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 510 WX_RXD_RSSTYPE_MASK; 511 512 if (!rss_type) 513 return; 514 515 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 516 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 517 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 518 } 519 520 /** 521 * wx_rx_checksum - indicate in skb if hw indicated a good cksum 522 * @ring: structure containing ring specific data 523 * @rx_desc: current Rx descriptor being processed 524 * @skb: skb currently being received and modified 525 **/ 526 static void wx_rx_checksum(struct wx_ring *ring, 527 union wx_rx_desc *rx_desc, 528 struct sk_buff *skb) 529 { 530 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc)); 531 532 skb_checksum_none_assert(skb); 533 /* Rx csum disabled */ 534 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 535 return; 536 537 /* if IPv4 header checksum error */ 538 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) && 539 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) || 540 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) && 541 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) { 542 ring->rx_stats.csum_err++; 543 return; 544 } 545 546 /* L4 checksum offload flag must set for the below code to work */ 547 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS)) 548 return; 549 550 /* Hardware can't guarantee csum if IPv6 Dest Header found */ 551 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && WX_RXD_IPV6EX(rx_desc)) 552 return; 553 554 /* if L4 checksum error */ 555 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) { 556 ring->rx_stats.csum_err++; 557 return; 558 } 559 560 /* It must be a TCP or UDP or SCTP packet with a valid checksum */ 561 skb->ip_summed = CHECKSUM_UNNECESSARY; 562 563 /* If there is an outer header present that might contain a checksum 564 * we need to bump the checksum level by 1 to reflect the fact that 565 * we are indicating we validated the inner checksum. 566 */ 567 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG) 568 __skb_incr_checksum_unnecessary(skb); 569 ring->rx_stats.csum_good_cnt++; 570 } 571 572 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc, 573 struct sk_buff *skb) 574 { 575 u16 ethertype; 576 u8 idx = 0; 577 578 if ((ring->netdev->features & 579 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) && 580 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) { 581 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 582 0x1c0) >> 6; 583 ethertype = ring->q_vector->wx->tpid[idx]; 584 __vlan_hwaccel_put_tag(skb, htons(ethertype), 585 le16_to_cpu(rx_desc->wb.upper.vlan)); 586 } 587 } 588 589 /** 590 * wx_process_skb_fields - Populate skb header fields from Rx descriptor 591 * @rx_ring: rx descriptor ring packet is being transacted on 592 * @rx_desc: pointer to the EOP Rx descriptor 593 * @skb: pointer to current skb being populated 594 * 595 * This function checks the ring, descriptor, and packet information in 596 * order to populate the hash, checksum, protocol, and 597 * other fields within the skb. 598 **/ 599 static void wx_process_skb_fields(struct wx_ring *rx_ring, 600 union wx_rx_desc *rx_desc, 601 struct sk_buff *skb) 602 { 603 wx_rx_hash(rx_ring, rx_desc, skb); 604 wx_rx_checksum(rx_ring, rx_desc, skb); 605 wx_rx_vlan(rx_ring, rx_desc, skb); 606 skb_record_rx_queue(skb, rx_ring->queue_index); 607 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 608 } 609 610 /** 611 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 612 * @q_vector: structure containing interrupt and ring information 613 * @rx_ring: rx descriptor ring to transact packets on 614 * @budget: Total limit on number of packets to process 615 * 616 * This function provides a "bounce buffer" approach to Rx interrupt 617 * processing. The advantage to this is that on systems that have 618 * expensive overhead for IOMMU access this provides a means of avoiding 619 * it by maintaining the mapping of the page to the system. 620 * 621 * Returns amount of work completed. 622 **/ 623 static int wx_clean_rx_irq(struct wx_q_vector *q_vector, 624 struct wx_ring *rx_ring, 625 int budget) 626 { 627 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 628 u16 cleaned_count = wx_desc_unused(rx_ring); 629 630 do { 631 struct wx_rx_buffer *rx_buffer; 632 union wx_rx_desc *rx_desc; 633 struct sk_buff *skb; 634 int rx_buffer_pgcnt; 635 636 /* return some buffers to hardware, one at a time is too slow */ 637 if (cleaned_count >= WX_RX_BUFFER_WRITE) { 638 wx_alloc_rx_buffers(rx_ring, cleaned_count); 639 cleaned_count = 0; 640 } 641 642 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean); 643 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD)) 644 break; 645 646 /* This memory barrier is needed to keep us from reading 647 * any other fields out of the rx_desc until we know the 648 * descriptor has been written back 649 */ 650 dma_rmb(); 651 652 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt); 653 654 /* retrieve a buffer from the ring */ 655 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc); 656 657 /* exit if we failed to retrieve a buffer */ 658 if (!skb) { 659 rx_ring->rx_stats.alloc_rx_buff_failed++; 660 break; 661 } 662 663 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 664 cleaned_count++; 665 666 /* place incomplete frames back on ring for completion */ 667 if (wx_is_non_eop(rx_ring, rx_desc, skb)) 668 continue; 669 670 /* verify the packet layout is correct */ 671 if (wx_cleanup_headers(rx_ring, rx_desc, skb)) 672 continue; 673 674 /* probably a little skewed due to removing CRC */ 675 total_rx_bytes += skb->len; 676 677 /* populate checksum, timestamp, VLAN, and protocol */ 678 wx_process_skb_fields(rx_ring, rx_desc, skb); 679 napi_gro_receive(&q_vector->napi, skb); 680 681 /* update budget accounting */ 682 total_rx_packets++; 683 } while (likely(total_rx_packets < budget)); 684 685 u64_stats_update_begin(&rx_ring->syncp); 686 rx_ring->stats.packets += total_rx_packets; 687 rx_ring->stats.bytes += total_rx_bytes; 688 u64_stats_update_end(&rx_ring->syncp); 689 q_vector->rx.total_packets += total_rx_packets; 690 q_vector->rx.total_bytes += total_rx_bytes; 691 692 return total_rx_packets; 693 } 694 695 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring) 696 { 697 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 698 } 699 700 /** 701 * wx_clean_tx_irq - Reclaim resources after transmit completes 702 * @q_vector: structure containing interrupt and ring information 703 * @tx_ring: tx ring to clean 704 * @napi_budget: Used to determine if we are in netpoll 705 **/ 706 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector, 707 struct wx_ring *tx_ring, int napi_budget) 708 { 709 unsigned int budget = q_vector->wx->tx_work_limit; 710 unsigned int total_bytes = 0, total_packets = 0; 711 unsigned int i = tx_ring->next_to_clean; 712 struct wx_tx_buffer *tx_buffer; 713 union wx_tx_desc *tx_desc; 714 715 if (!netif_carrier_ok(tx_ring->netdev)) 716 return true; 717 718 tx_buffer = &tx_ring->tx_buffer_info[i]; 719 tx_desc = WX_TX_DESC(tx_ring, i); 720 i -= tx_ring->count; 721 722 do { 723 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch; 724 725 /* if next_to_watch is not set then there is no work pending */ 726 if (!eop_desc) 727 break; 728 729 /* prevent any other reads prior to eop_desc */ 730 smp_rmb(); 731 732 /* if DD is not set pending work has not been completed */ 733 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) 734 break; 735 736 /* clear next_to_watch to prevent false hangs */ 737 tx_buffer->next_to_watch = NULL; 738 739 /* update the statistics for this packet */ 740 total_bytes += tx_buffer->bytecount; 741 total_packets += tx_buffer->gso_segs; 742 743 /* free the skb */ 744 napi_consume_skb(tx_buffer->skb, napi_budget); 745 746 /* unmap skb header data */ 747 dma_unmap_single(tx_ring->dev, 748 dma_unmap_addr(tx_buffer, dma), 749 dma_unmap_len(tx_buffer, len), 750 DMA_TO_DEVICE); 751 752 /* clear tx_buffer data */ 753 dma_unmap_len_set(tx_buffer, len, 0); 754 755 /* unmap remaining buffers */ 756 while (tx_desc != eop_desc) { 757 tx_buffer++; 758 tx_desc++; 759 i++; 760 if (unlikely(!i)) { 761 i -= tx_ring->count; 762 tx_buffer = tx_ring->tx_buffer_info; 763 tx_desc = WX_TX_DESC(tx_ring, 0); 764 } 765 766 /* unmap any remaining paged data */ 767 if (dma_unmap_len(tx_buffer, len)) { 768 dma_unmap_page(tx_ring->dev, 769 dma_unmap_addr(tx_buffer, dma), 770 dma_unmap_len(tx_buffer, len), 771 DMA_TO_DEVICE); 772 dma_unmap_len_set(tx_buffer, len, 0); 773 } 774 } 775 776 /* move us one more past the eop_desc for start of next pkt */ 777 tx_buffer++; 778 tx_desc++; 779 i++; 780 if (unlikely(!i)) { 781 i -= tx_ring->count; 782 tx_buffer = tx_ring->tx_buffer_info; 783 tx_desc = WX_TX_DESC(tx_ring, 0); 784 } 785 786 /* issue prefetch for next Tx descriptor */ 787 prefetch(tx_desc); 788 789 /* update budget accounting */ 790 budget--; 791 } while (likely(budget)); 792 793 i += tx_ring->count; 794 tx_ring->next_to_clean = i; 795 u64_stats_update_begin(&tx_ring->syncp); 796 tx_ring->stats.bytes += total_bytes; 797 tx_ring->stats.packets += total_packets; 798 u64_stats_update_end(&tx_ring->syncp); 799 q_vector->tx.total_bytes += total_bytes; 800 q_vector->tx.total_packets += total_packets; 801 802 netdev_tx_completed_queue(wx_txring_txq(tx_ring), 803 total_packets, total_bytes); 804 805 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 806 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 807 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 808 /* Make sure that anybody stopping the queue after this 809 * sees the new next_to_clean. 810 */ 811 smp_mb(); 812 813 if (__netif_subqueue_stopped(tx_ring->netdev, 814 tx_ring->queue_index) && 815 netif_running(tx_ring->netdev)) { 816 netif_wake_subqueue(tx_ring->netdev, 817 tx_ring->queue_index); 818 ++tx_ring->tx_stats.restart_queue; 819 } 820 } 821 822 return !!budget; 823 } 824 825 /** 826 * wx_poll - NAPI polling RX/TX cleanup routine 827 * @napi: napi struct with our devices info in it 828 * @budget: amount of work driver is allowed to do this pass, in packets 829 * 830 * This function will clean all queues associated with a q_vector. 831 **/ 832 static int wx_poll(struct napi_struct *napi, int budget) 833 { 834 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi); 835 int per_ring_budget, work_done = 0; 836 struct wx *wx = q_vector->wx; 837 bool clean_complete = true; 838 struct wx_ring *ring; 839 840 wx_for_each_ring(ring, q_vector->tx) { 841 if (!wx_clean_tx_irq(q_vector, ring, budget)) 842 clean_complete = false; 843 } 844 845 /* Exit if we are called by netpoll */ 846 if (budget <= 0) 847 return budget; 848 849 /* attempt to distribute budget to each queue fairly, but don't allow 850 * the budget to go below 1 because we'll exit polling 851 */ 852 if (q_vector->rx.count > 1) 853 per_ring_budget = max(budget / q_vector->rx.count, 1); 854 else 855 per_ring_budget = budget; 856 857 wx_for_each_ring(ring, q_vector->rx) { 858 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget); 859 860 work_done += cleaned; 861 if (cleaned >= per_ring_budget) 862 clean_complete = false; 863 } 864 865 /* If all work not completed, return budget and keep polling */ 866 if (!clean_complete) 867 return budget; 868 869 /* all work done, exit the polling mode */ 870 if (likely(napi_complete_done(napi, work_done))) { 871 if (netif_running(wx->netdev)) 872 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx)); 873 } 874 875 return min(work_done, budget - 1); 876 } 877 878 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size) 879 { 880 if (likely(wx_desc_unused(tx_ring) >= size)) 881 return 0; 882 883 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 884 885 /* For the next check */ 886 smp_mb(); 887 888 /* We need to check again in a case another CPU has just 889 * made room available. 890 */ 891 if (likely(wx_desc_unused(tx_ring) < size)) 892 return -EBUSY; 893 894 /* A reprieve! - use start_queue because it doesn't call schedule */ 895 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 896 ++tx_ring->tx_stats.restart_queue; 897 898 return 0; 899 } 900 901 static u32 wx_tx_cmd_type(u32 tx_flags) 902 { 903 /* set type for advanced descriptor with frame checksum insertion */ 904 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS; 905 906 /* set HW vlan bit if vlan is present */ 907 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE); 908 /* set segmentation enable bits for TSO/FSO */ 909 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE); 910 /* set timestamp bit if present */ 911 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP); 912 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC); 913 914 return cmd_type; 915 } 916 917 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc, 918 u32 tx_flags, unsigned int paylen) 919 { 920 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT; 921 922 /* enable L4 checksum for TSO and TX checksum offload */ 923 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS); 924 /* enable IPv4 checksum for TSO */ 925 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS); 926 /* enable outer IPv4 checksum for TSO */ 927 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4, 928 WX_TXD_EIPCS); 929 /* Check Context must be set if Tx switch is enabled, which it 930 * always is for case where virtual functions are running 931 */ 932 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC); 933 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC, 934 WX_TXD_IPSEC); 935 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 936 } 937 938 static void wx_tx_map(struct wx_ring *tx_ring, 939 struct wx_tx_buffer *first, 940 const u8 hdr_len) 941 { 942 struct sk_buff *skb = first->skb; 943 struct wx_tx_buffer *tx_buffer; 944 u32 tx_flags = first->tx_flags; 945 u16 i = tx_ring->next_to_use; 946 unsigned int data_len, size; 947 union wx_tx_desc *tx_desc; 948 skb_frag_t *frag; 949 dma_addr_t dma; 950 u32 cmd_type; 951 952 cmd_type = wx_tx_cmd_type(tx_flags); 953 tx_desc = WX_TX_DESC(tx_ring, i); 954 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 955 956 size = skb_headlen(skb); 957 data_len = skb->data_len; 958 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 959 960 tx_buffer = first; 961 962 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 963 if (dma_mapping_error(tx_ring->dev, dma)) 964 goto dma_error; 965 966 /* record length, and DMA address */ 967 dma_unmap_len_set(tx_buffer, len, size); 968 dma_unmap_addr_set(tx_buffer, dma, dma); 969 970 tx_desc->read.buffer_addr = cpu_to_le64(dma); 971 972 while (unlikely(size > WX_MAX_DATA_PER_TXD)) { 973 tx_desc->read.cmd_type_len = 974 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD); 975 976 i++; 977 tx_desc++; 978 if (i == tx_ring->count) { 979 tx_desc = WX_TX_DESC(tx_ring, 0); 980 i = 0; 981 } 982 tx_desc->read.olinfo_status = 0; 983 984 dma += WX_MAX_DATA_PER_TXD; 985 size -= WX_MAX_DATA_PER_TXD; 986 987 tx_desc->read.buffer_addr = cpu_to_le64(dma); 988 } 989 990 if (likely(!data_len)) 991 break; 992 993 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 994 995 i++; 996 tx_desc++; 997 if (i == tx_ring->count) { 998 tx_desc = WX_TX_DESC(tx_ring, 0); 999 i = 0; 1000 } 1001 tx_desc->read.olinfo_status = 0; 1002 1003 size = skb_frag_size(frag); 1004 1005 data_len -= size; 1006 1007 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1008 DMA_TO_DEVICE); 1009 1010 tx_buffer = &tx_ring->tx_buffer_info[i]; 1011 } 1012 1013 /* write last descriptor with RS and EOP bits */ 1014 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS; 1015 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1016 1017 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount); 1018 1019 skb_tx_timestamp(skb); 1020 1021 /* Force memory writes to complete before letting h/w know there 1022 * are new descriptors to fetch. (Only applicable for weak-ordered 1023 * memory model archs, such as IA-64). 1024 * 1025 * We also need this memory barrier to make certain all of the 1026 * status bits have been updated before next_to_watch is written. 1027 */ 1028 wmb(); 1029 1030 /* set next_to_watch value indicating a packet is present */ 1031 first->next_to_watch = tx_desc; 1032 1033 i++; 1034 if (i == tx_ring->count) 1035 i = 0; 1036 1037 tx_ring->next_to_use = i; 1038 1039 wx_maybe_stop_tx(tx_ring, DESC_NEEDED); 1040 1041 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more()) 1042 writel(i, tx_ring->tail); 1043 1044 return; 1045 dma_error: 1046 dev_err(tx_ring->dev, "TX DMA map failed\n"); 1047 1048 /* clear dma mappings for failed tx_buffer_info map */ 1049 for (;;) { 1050 tx_buffer = &tx_ring->tx_buffer_info[i]; 1051 if (dma_unmap_len(tx_buffer, len)) 1052 dma_unmap_page(tx_ring->dev, 1053 dma_unmap_addr(tx_buffer, dma), 1054 dma_unmap_len(tx_buffer, len), 1055 DMA_TO_DEVICE); 1056 dma_unmap_len_set(tx_buffer, len, 0); 1057 if (tx_buffer == first) 1058 break; 1059 if (i == 0) 1060 i += tx_ring->count; 1061 i--; 1062 } 1063 1064 dev_kfree_skb_any(first->skb); 1065 first->skb = NULL; 1066 1067 tx_ring->next_to_use = i; 1068 } 1069 1070 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens, 1071 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1072 { 1073 struct wx_tx_context_desc *context_desc; 1074 u16 i = tx_ring->next_to_use; 1075 1076 context_desc = WX_TX_CTXTDESC(tx_ring, i); 1077 i++; 1078 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1079 1080 /* set bits to identify this as an advanced context descriptor */ 1081 type_tucmd |= WX_TXD_DTYP_CTXT; 1082 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1083 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1084 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1085 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1086 } 1087 1088 static void wx_get_ipv6_proto(struct sk_buff *skb, int offset, u8 *nexthdr) 1089 { 1090 struct ipv6hdr *hdr = (struct ipv6hdr *)(skb->data + offset); 1091 1092 *nexthdr = hdr->nexthdr; 1093 offset += sizeof(struct ipv6hdr); 1094 while (ipv6_ext_hdr(*nexthdr)) { 1095 struct ipv6_opt_hdr _hdr, *hp; 1096 1097 if (*nexthdr == NEXTHDR_NONE) 1098 return; 1099 hp = skb_header_pointer(skb, offset, sizeof(_hdr), &_hdr); 1100 if (!hp) 1101 return; 1102 if (*nexthdr == NEXTHDR_FRAGMENT) 1103 break; 1104 *nexthdr = hp->nexthdr; 1105 } 1106 } 1107 1108 union network_header { 1109 struct iphdr *ipv4; 1110 struct ipv6hdr *ipv6; 1111 void *raw; 1112 }; 1113 1114 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first) 1115 { 1116 u8 tun_prot = 0, l4_prot = 0, ptype = 0; 1117 struct sk_buff *skb = first->skb; 1118 1119 if (skb->encapsulation) { 1120 union network_header hdr; 1121 1122 switch (first->protocol) { 1123 case htons(ETH_P_IP): 1124 tun_prot = ip_hdr(skb)->protocol; 1125 ptype = WX_PTYPE_TUN_IPV4; 1126 break; 1127 case htons(ETH_P_IPV6): 1128 wx_get_ipv6_proto(skb, skb_network_offset(skb), &tun_prot); 1129 ptype = WX_PTYPE_TUN_IPV6; 1130 break; 1131 default: 1132 return ptype; 1133 } 1134 1135 if (tun_prot == IPPROTO_IPIP) { 1136 hdr.raw = (void *)inner_ip_hdr(skb); 1137 ptype |= WX_PTYPE_PKT_IPIP; 1138 } else if (tun_prot == IPPROTO_UDP) { 1139 hdr.raw = (void *)inner_ip_hdr(skb); 1140 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1141 skb->inner_protocol != htons(ETH_P_TEB)) { 1142 ptype |= WX_PTYPE_PKT_IG; 1143 } else { 1144 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1145 == htons(ETH_P_8021Q)) 1146 ptype |= WX_PTYPE_PKT_IGMV; 1147 else 1148 ptype |= WX_PTYPE_PKT_IGM; 1149 } 1150 1151 } else if (tun_prot == IPPROTO_GRE) { 1152 hdr.raw = (void *)inner_ip_hdr(skb); 1153 if (skb->inner_protocol == htons(ETH_P_IP) || 1154 skb->inner_protocol == htons(ETH_P_IPV6)) { 1155 ptype |= WX_PTYPE_PKT_IG; 1156 } else { 1157 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1158 == htons(ETH_P_8021Q)) 1159 ptype |= WX_PTYPE_PKT_IGMV; 1160 else 1161 ptype |= WX_PTYPE_PKT_IGM; 1162 } 1163 } else { 1164 return ptype; 1165 } 1166 1167 switch (hdr.ipv4->version) { 1168 case IPVERSION: 1169 l4_prot = hdr.ipv4->protocol; 1170 break; 1171 case 6: 1172 wx_get_ipv6_proto(skb, skb_inner_network_offset(skb), &l4_prot); 1173 ptype |= WX_PTYPE_PKT_IPV6; 1174 break; 1175 default: 1176 return ptype; 1177 } 1178 } else { 1179 switch (first->protocol) { 1180 case htons(ETH_P_IP): 1181 l4_prot = ip_hdr(skb)->protocol; 1182 ptype = WX_PTYPE_PKT_IP; 1183 break; 1184 case htons(ETH_P_IPV6): 1185 wx_get_ipv6_proto(skb, skb_network_offset(skb), &l4_prot); 1186 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6; 1187 break; 1188 default: 1189 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC; 1190 } 1191 } 1192 switch (l4_prot) { 1193 case IPPROTO_TCP: 1194 ptype |= WX_PTYPE_TYP_TCP; 1195 break; 1196 case IPPROTO_UDP: 1197 ptype |= WX_PTYPE_TYP_UDP; 1198 break; 1199 case IPPROTO_SCTP: 1200 ptype |= WX_PTYPE_TYP_SCTP; 1201 break; 1202 default: 1203 ptype |= WX_PTYPE_TYP_IP; 1204 break; 1205 } 1206 1207 return ptype; 1208 } 1209 1210 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1211 u8 *hdr_len, u8 ptype) 1212 { 1213 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1214 struct net_device *netdev = tx_ring->netdev; 1215 u32 l4len, tunhdr_eiplen_tunlen = 0; 1216 struct sk_buff *skb = first->skb; 1217 bool enc = skb->encapsulation; 1218 struct ipv6hdr *ipv6h; 1219 struct tcphdr *tcph; 1220 struct iphdr *iph; 1221 u8 tun_prot = 0; 1222 int err; 1223 1224 if (skb->ip_summed != CHECKSUM_PARTIAL) 1225 return 0; 1226 1227 if (!skb_is_gso(skb)) 1228 return 0; 1229 1230 err = skb_cow_head(skb, 0); 1231 if (err < 0) 1232 return err; 1233 1234 /* indicates the inner headers in the skbuff are valid. */ 1235 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb); 1236 if (iph->version == 4) { 1237 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1238 iph->tot_len = 0; 1239 iph->check = 0; 1240 tcph->check = ~csum_tcpudp_magic(iph->saddr, 1241 iph->daddr, 0, 1242 IPPROTO_TCP, 0); 1243 first->tx_flags |= WX_TX_FLAGS_TSO | 1244 WX_TX_FLAGS_CSUM | 1245 WX_TX_FLAGS_IPV4 | 1246 WX_TX_FLAGS_CC; 1247 } else if (iph->version == 6 && skb_is_gso_v6(skb)) { 1248 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 1249 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1250 ipv6h->payload_len = 0; 1251 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, 1252 &ipv6h->daddr, 0, 1253 IPPROTO_TCP, 0); 1254 first->tx_flags |= WX_TX_FLAGS_TSO | 1255 WX_TX_FLAGS_CSUM | 1256 WX_TX_FLAGS_CC; 1257 } 1258 1259 /* compute header lengths */ 1260 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 1261 *hdr_len = enc ? skb_inner_transport_offset(skb) : 1262 skb_transport_offset(skb); 1263 *hdr_len += l4len; 1264 1265 /* update gso size and bytecount with header size */ 1266 first->gso_segs = skb_shinfo(skb)->gso_segs; 1267 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1268 1269 /* mss_l4len_id: use 0 as index for TSO */ 1270 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT; 1271 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT; 1272 1273 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 1274 if (enc) { 1275 switch (first->protocol) { 1276 case htons(ETH_P_IP): 1277 tun_prot = ip_hdr(skb)->protocol; 1278 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4; 1279 break; 1280 case htons(ETH_P_IPV6): 1281 tun_prot = ipv6_hdr(skb)->nexthdr; 1282 break; 1283 default: 1284 break; 1285 } 1286 switch (tun_prot) { 1287 case IPPROTO_UDP: 1288 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1289 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1290 WX_TXD_OUTER_IPLEN_SHIFT) | 1291 (((skb_inner_mac_header(skb) - 1292 skb_transport_header(skb)) >> 1) << 1293 WX_TXD_TUNNEL_LEN_SHIFT); 1294 break; 1295 case IPPROTO_GRE: 1296 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1297 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1298 WX_TXD_OUTER_IPLEN_SHIFT) | 1299 (((skb_inner_mac_header(skb) - 1300 skb_transport_header(skb)) >> 1) << 1301 WX_TXD_TUNNEL_LEN_SHIFT); 1302 break; 1303 case IPPROTO_IPIP: 1304 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1305 (char *)ip_hdr(skb)) >> 2) << 1306 WX_TXD_OUTER_IPLEN_SHIFT; 1307 break; 1308 default: 1309 break; 1310 } 1311 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1; 1312 } else { 1313 vlan_macip_lens = skb_network_header_len(skb) >> 1; 1314 } 1315 1316 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT; 1317 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1318 1319 type_tucmd = ptype << 24; 1320 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1321 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1322 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1323 WX_TX_FLAGS_HW_VLAN, 1324 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1325 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1326 type_tucmd, mss_l4len_idx); 1327 1328 return 1; 1329 } 1330 1331 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1332 u8 ptype) 1333 { 1334 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0; 1335 struct net_device *netdev = tx_ring->netdev; 1336 u32 mss_l4len_idx = 0, type_tucmd; 1337 struct sk_buff *skb = first->skb; 1338 u8 tun_prot = 0; 1339 1340 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1341 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) && 1342 !(first->tx_flags & WX_TX_FLAGS_CC)) 1343 return; 1344 vlan_macip_lens = skb_network_offset(skb) << 1345 WX_TXD_MACLEN_SHIFT; 1346 } else { 1347 u8 l4_prot = 0; 1348 union { 1349 struct iphdr *ipv4; 1350 struct ipv6hdr *ipv6; 1351 u8 *raw; 1352 } network_hdr; 1353 union { 1354 struct tcphdr *tcphdr; 1355 u8 *raw; 1356 } transport_hdr; 1357 1358 if (skb->encapsulation) { 1359 network_hdr.raw = skb_inner_network_header(skb); 1360 transport_hdr.raw = skb_inner_transport_header(skb); 1361 vlan_macip_lens = skb_network_offset(skb) << 1362 WX_TXD_MACLEN_SHIFT; 1363 switch (first->protocol) { 1364 case htons(ETH_P_IP): 1365 tun_prot = ip_hdr(skb)->protocol; 1366 break; 1367 case htons(ETH_P_IPV6): 1368 tun_prot = ipv6_hdr(skb)->nexthdr; 1369 break; 1370 default: 1371 return; 1372 } 1373 switch (tun_prot) { 1374 case IPPROTO_UDP: 1375 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1376 tunhdr_eiplen_tunlen |= 1377 ((skb_network_header_len(skb) >> 2) << 1378 WX_TXD_OUTER_IPLEN_SHIFT) | 1379 (((skb_inner_mac_header(skb) - 1380 skb_transport_header(skb)) >> 1) << 1381 WX_TXD_TUNNEL_LEN_SHIFT); 1382 break; 1383 case IPPROTO_GRE: 1384 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1385 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1386 WX_TXD_OUTER_IPLEN_SHIFT) | 1387 (((skb_inner_mac_header(skb) - 1388 skb_transport_header(skb)) >> 1) << 1389 WX_TXD_TUNNEL_LEN_SHIFT); 1390 break; 1391 case IPPROTO_IPIP: 1392 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1393 (char *)ip_hdr(skb)) >> 2) << 1394 WX_TXD_OUTER_IPLEN_SHIFT; 1395 break; 1396 default: 1397 break; 1398 } 1399 1400 } else { 1401 network_hdr.raw = skb_network_header(skb); 1402 transport_hdr.raw = skb_transport_header(skb); 1403 vlan_macip_lens = skb_network_offset(skb) << 1404 WX_TXD_MACLEN_SHIFT; 1405 } 1406 1407 switch (network_hdr.ipv4->version) { 1408 case IPVERSION: 1409 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1410 l4_prot = network_hdr.ipv4->protocol; 1411 break; 1412 case 6: 1413 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1414 l4_prot = network_hdr.ipv6->nexthdr; 1415 break; 1416 default: 1417 break; 1418 } 1419 1420 switch (l4_prot) { 1421 case IPPROTO_TCP: 1422 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 1423 WX_TXD_L4LEN_SHIFT; 1424 break; 1425 case IPPROTO_SCTP: 1426 mss_l4len_idx = sizeof(struct sctphdr) << 1427 WX_TXD_L4LEN_SHIFT; 1428 break; 1429 case IPPROTO_UDP: 1430 mss_l4len_idx = sizeof(struct udphdr) << 1431 WX_TXD_L4LEN_SHIFT; 1432 break; 1433 default: 1434 break; 1435 } 1436 1437 /* update TX checksum flag */ 1438 first->tx_flags |= WX_TX_FLAGS_CSUM; 1439 } 1440 first->tx_flags |= WX_TX_FLAGS_CC; 1441 /* vlan_macip_lens: MACLEN, VLAN tag */ 1442 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1443 1444 type_tucmd = ptype << 24; 1445 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1446 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1447 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1448 WX_TX_FLAGS_HW_VLAN, 1449 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1450 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1451 type_tucmd, mss_l4len_idx); 1452 } 1453 1454 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb, 1455 struct wx_ring *tx_ring) 1456 { 1457 struct wx *wx = netdev_priv(tx_ring->netdev); 1458 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1459 struct wx_tx_buffer *first; 1460 u8 hdr_len = 0, ptype; 1461 unsigned short f; 1462 u32 tx_flags = 0; 1463 int tso; 1464 1465 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD, 1466 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD, 1467 * + 2 desc gap to keep tail from touching head, 1468 * + 1 desc for context descriptor, 1469 * otherwise try next time 1470 */ 1471 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1472 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)-> 1473 frags[f])); 1474 1475 if (wx_maybe_stop_tx(tx_ring, count + 3)) { 1476 tx_ring->tx_stats.tx_busy++; 1477 return NETDEV_TX_BUSY; 1478 } 1479 1480 /* record the location of the first descriptor for this packet */ 1481 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1482 first->skb = skb; 1483 first->bytecount = skb->len; 1484 first->gso_segs = 1; 1485 1486 /* if we have a HW VLAN tag being added default to the HW one */ 1487 if (skb_vlan_tag_present(skb)) { 1488 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT; 1489 tx_flags |= WX_TX_FLAGS_HW_VLAN; 1490 } 1491 1492 /* record initial flags and protocol */ 1493 first->tx_flags = tx_flags; 1494 first->protocol = vlan_get_protocol(skb); 1495 1496 ptype = wx_encode_tx_desc_ptype(first); 1497 1498 tso = wx_tso(tx_ring, first, &hdr_len, ptype); 1499 if (tso < 0) 1500 goto out_drop; 1501 else if (!tso) 1502 wx_tx_csum(tx_ring, first, ptype); 1503 1504 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate) 1505 wx->atr(tx_ring, first, ptype); 1506 1507 wx_tx_map(tx_ring, first, hdr_len); 1508 1509 return NETDEV_TX_OK; 1510 out_drop: 1511 dev_kfree_skb_any(first->skb); 1512 first->skb = NULL; 1513 1514 return NETDEV_TX_OK; 1515 } 1516 1517 netdev_tx_t wx_xmit_frame(struct sk_buff *skb, 1518 struct net_device *netdev) 1519 { 1520 unsigned int r_idx = skb->queue_mapping; 1521 struct wx *wx = netdev_priv(netdev); 1522 struct wx_ring *tx_ring; 1523 1524 if (!netif_carrier_ok(netdev)) { 1525 dev_kfree_skb_any(skb); 1526 return NETDEV_TX_OK; 1527 } 1528 1529 /* The minimum packet size for olinfo paylen is 17 so pad the skb 1530 * in order to meet this minimum size requirement. 1531 */ 1532 if (skb_put_padto(skb, 17)) 1533 return NETDEV_TX_OK; 1534 1535 if (r_idx >= wx->num_tx_queues) 1536 r_idx = r_idx % wx->num_tx_queues; 1537 tx_ring = wx->tx_ring[r_idx]; 1538 1539 return wx_xmit_frame_ring(skb, tx_ring); 1540 } 1541 EXPORT_SYMBOL(wx_xmit_frame); 1542 1543 void wx_napi_enable_all(struct wx *wx) 1544 { 1545 struct wx_q_vector *q_vector; 1546 int q_idx; 1547 1548 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1549 q_vector = wx->q_vector[q_idx]; 1550 napi_enable(&q_vector->napi); 1551 } 1552 } 1553 EXPORT_SYMBOL(wx_napi_enable_all); 1554 1555 void wx_napi_disable_all(struct wx *wx) 1556 { 1557 struct wx_q_vector *q_vector; 1558 int q_idx; 1559 1560 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1561 q_vector = wx->q_vector[q_idx]; 1562 napi_disable(&q_vector->napi); 1563 } 1564 } 1565 EXPORT_SYMBOL(wx_napi_disable_all); 1566 1567 /** 1568 * wx_set_rss_queues: Allocate queues for RSS 1569 * @wx: board private structure to initialize 1570 * 1571 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1572 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1573 * 1574 **/ 1575 static void wx_set_rss_queues(struct wx *wx) 1576 { 1577 struct wx_ring_feature *f; 1578 1579 /* set mask for 16 queue limit of RSS */ 1580 f = &wx->ring_feature[RING_F_RSS]; 1581 f->indices = f->limit; 1582 1583 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 1584 goto out; 1585 1586 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 1587 1588 /* Use Flow Director in addition to RSS to ensure the best 1589 * distribution of flows across cores, even when an FDIR flow 1590 * isn't matched. 1591 */ 1592 if (f->indices > 1) { 1593 f = &wx->ring_feature[RING_F_FDIR]; 1594 1595 f->indices = f->limit; 1596 1597 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 1598 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 1599 } 1600 1601 out: 1602 wx->num_rx_queues = f->indices; 1603 wx->num_tx_queues = f->indices; 1604 } 1605 1606 static void wx_set_num_queues(struct wx *wx) 1607 { 1608 /* Start with base case */ 1609 wx->num_rx_queues = 1; 1610 wx->num_tx_queues = 1; 1611 wx->queues_per_pool = 1; 1612 1613 wx_set_rss_queues(wx); 1614 } 1615 1616 /** 1617 * wx_acquire_msix_vectors - acquire MSI-X vectors 1618 * @wx: board private structure 1619 * 1620 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will 1621 * return a negative error code if unable to acquire MSI-X vectors for any 1622 * reason. 1623 */ 1624 static int wx_acquire_msix_vectors(struct wx *wx) 1625 { 1626 struct irq_affinity affd = { .pre_vectors = 1 }; 1627 int nvecs, i; 1628 1629 /* We start by asking for one vector per queue pair */ 1630 nvecs = max(wx->num_rx_queues, wx->num_tx_queues); 1631 nvecs = min_t(int, nvecs, num_online_cpus()); 1632 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors); 1633 1634 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry), 1635 GFP_KERNEL); 1636 if (!wx->msix_q_entries) 1637 return -ENOMEM; 1638 1639 /* One for non-queue interrupts */ 1640 nvecs += 1; 1641 1642 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry), 1643 GFP_KERNEL); 1644 if (!wx->msix_entry) { 1645 kfree(wx->msix_q_entries); 1646 wx->msix_q_entries = NULL; 1647 return -ENOMEM; 1648 } 1649 1650 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs, 1651 nvecs, 1652 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, 1653 &affd); 1654 if (nvecs < 0) { 1655 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs); 1656 kfree(wx->msix_q_entries); 1657 wx->msix_q_entries = NULL; 1658 kfree(wx->msix_entry); 1659 wx->msix_entry = NULL; 1660 return nvecs; 1661 } 1662 1663 wx->msix_entry->entry = 0; 1664 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0); 1665 nvecs -= 1; 1666 for (i = 0; i < nvecs; i++) { 1667 wx->msix_q_entries[i].entry = i; 1668 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i + 1); 1669 } 1670 1671 wx->num_q_vectors = nvecs; 1672 1673 return 0; 1674 } 1675 1676 /** 1677 * wx_set_interrupt_capability - set MSI-X or MSI if supported 1678 * @wx: board private structure to initialize 1679 * 1680 * Attempt to configure the interrupts using the best available 1681 * capabilities of the hardware and the kernel. 1682 **/ 1683 static int wx_set_interrupt_capability(struct wx *wx) 1684 { 1685 struct pci_dev *pdev = wx->pdev; 1686 int nvecs, ret; 1687 1688 /* We will try to get MSI-X interrupts first */ 1689 ret = wx_acquire_msix_vectors(wx); 1690 if (ret == 0 || (ret == -ENOMEM)) 1691 return ret; 1692 1693 /* Disable RSS */ 1694 dev_warn(&wx->pdev->dev, "Disabling RSS support\n"); 1695 wx->ring_feature[RING_F_RSS].limit = 1; 1696 1697 wx_set_num_queues(wx); 1698 1699 /* minmum one for queue, one for misc*/ 1700 nvecs = 1; 1701 nvecs = pci_alloc_irq_vectors(pdev, nvecs, 1702 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX); 1703 if (nvecs == 1) { 1704 if (pdev->msi_enabled) 1705 wx_err(wx, "Fallback to MSI.\n"); 1706 else 1707 wx_err(wx, "Fallback to INTx.\n"); 1708 } else { 1709 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs); 1710 return nvecs; 1711 } 1712 1713 pdev->irq = pci_irq_vector(pdev, 0); 1714 1715 return 0; 1716 } 1717 1718 /** 1719 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS 1720 * @wx: board private structure to initialize 1721 * 1722 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV. 1723 * 1724 **/ 1725 static void wx_cache_ring_rss(struct wx *wx) 1726 { 1727 u16 i; 1728 1729 for (i = 0; i < wx->num_rx_queues; i++) 1730 wx->rx_ring[i]->reg_idx = i; 1731 1732 for (i = 0; i < wx->num_tx_queues; i++) 1733 wx->tx_ring[i]->reg_idx = i; 1734 } 1735 1736 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head) 1737 { 1738 ring->next = head->ring; 1739 head->ring = ring; 1740 head->count++; 1741 } 1742 1743 /** 1744 * wx_alloc_q_vector - Allocate memory for a single interrupt vector 1745 * @wx: board private structure to initialize 1746 * @v_count: q_vectors allocated on wx, used for ring interleaving 1747 * @v_idx: index of vector in wx struct 1748 * @txr_count: total number of Tx rings to allocate 1749 * @txr_idx: index of first Tx ring to allocate 1750 * @rxr_count: total number of Rx rings to allocate 1751 * @rxr_idx: index of first Rx ring to allocate 1752 * 1753 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1754 **/ 1755 static int wx_alloc_q_vector(struct wx *wx, 1756 unsigned int v_count, unsigned int v_idx, 1757 unsigned int txr_count, unsigned int txr_idx, 1758 unsigned int rxr_count, unsigned int rxr_idx) 1759 { 1760 struct wx_q_vector *q_vector; 1761 int ring_count, default_itr; 1762 struct wx_ring *ring; 1763 1764 /* note this will allocate space for the ring structure as well! */ 1765 ring_count = txr_count + rxr_count; 1766 1767 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 1768 GFP_KERNEL); 1769 if (!q_vector) 1770 return -ENOMEM; 1771 1772 /* initialize NAPI */ 1773 netif_napi_add(wx->netdev, &q_vector->napi, 1774 wx_poll); 1775 1776 /* tie q_vector and wx together */ 1777 wx->q_vector[v_idx] = q_vector; 1778 q_vector->wx = wx; 1779 q_vector->v_idx = v_idx; 1780 if (cpu_online(v_idx)) 1781 q_vector->numa_node = cpu_to_node(v_idx); 1782 1783 /* initialize pointer to rings */ 1784 ring = q_vector->ring; 1785 1786 if (wx->mac.type == wx_mac_sp) 1787 default_itr = WX_12K_ITR; 1788 else 1789 default_itr = WX_7K_ITR; 1790 /* initialize ITR */ 1791 if (txr_count && !rxr_count) 1792 /* tx only vector */ 1793 q_vector->itr = wx->tx_itr_setting ? 1794 default_itr : wx->tx_itr_setting; 1795 else 1796 /* rx or rx/tx vector */ 1797 q_vector->itr = wx->rx_itr_setting ? 1798 default_itr : wx->rx_itr_setting; 1799 1800 while (txr_count) { 1801 /* assign generic ring traits */ 1802 ring->dev = &wx->pdev->dev; 1803 ring->netdev = wx->netdev; 1804 1805 /* configure backlink on ring */ 1806 ring->q_vector = q_vector; 1807 1808 /* update q_vector Tx values */ 1809 wx_add_ring(ring, &q_vector->tx); 1810 1811 /* apply Tx specific ring traits */ 1812 ring->count = wx->tx_ring_count; 1813 1814 ring->queue_index = txr_idx; 1815 1816 /* assign ring to wx */ 1817 wx->tx_ring[txr_idx] = ring; 1818 1819 /* update count and index */ 1820 txr_count--; 1821 txr_idx += v_count; 1822 1823 /* push pointer to next ring */ 1824 ring++; 1825 } 1826 1827 while (rxr_count) { 1828 /* assign generic ring traits */ 1829 ring->dev = &wx->pdev->dev; 1830 ring->netdev = wx->netdev; 1831 1832 /* configure backlink on ring */ 1833 ring->q_vector = q_vector; 1834 1835 /* update q_vector Rx values */ 1836 wx_add_ring(ring, &q_vector->rx); 1837 1838 /* apply Rx specific ring traits */ 1839 ring->count = wx->rx_ring_count; 1840 ring->queue_index = rxr_idx; 1841 1842 /* assign ring to wx */ 1843 wx->rx_ring[rxr_idx] = ring; 1844 1845 /* update count and index */ 1846 rxr_count--; 1847 rxr_idx += v_count; 1848 1849 /* push pointer to next ring */ 1850 ring++; 1851 } 1852 1853 return 0; 1854 } 1855 1856 /** 1857 * wx_free_q_vector - Free memory allocated for specific interrupt vector 1858 * @wx: board private structure to initialize 1859 * @v_idx: Index of vector to be freed 1860 * 1861 * This function frees the memory allocated to the q_vector. In addition if 1862 * NAPI is enabled it will delete any references to the NAPI struct prior 1863 * to freeing the q_vector. 1864 **/ 1865 static void wx_free_q_vector(struct wx *wx, int v_idx) 1866 { 1867 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 1868 struct wx_ring *ring; 1869 1870 wx_for_each_ring(ring, q_vector->tx) 1871 wx->tx_ring[ring->queue_index] = NULL; 1872 1873 wx_for_each_ring(ring, q_vector->rx) 1874 wx->rx_ring[ring->queue_index] = NULL; 1875 1876 wx->q_vector[v_idx] = NULL; 1877 netif_napi_del(&q_vector->napi); 1878 kfree_rcu(q_vector, rcu); 1879 } 1880 1881 /** 1882 * wx_alloc_q_vectors - Allocate memory for interrupt vectors 1883 * @wx: board private structure to initialize 1884 * 1885 * We allocate one q_vector per queue interrupt. If allocation fails we 1886 * return -ENOMEM. 1887 **/ 1888 static int wx_alloc_q_vectors(struct wx *wx) 1889 { 1890 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1891 unsigned int rxr_remaining = wx->num_rx_queues; 1892 unsigned int txr_remaining = wx->num_tx_queues; 1893 unsigned int q_vectors = wx->num_q_vectors; 1894 int rqpv, tqpv; 1895 int err; 1896 1897 for (; v_idx < q_vectors; v_idx++) { 1898 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1899 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1900 err = wx_alloc_q_vector(wx, q_vectors, v_idx, 1901 tqpv, txr_idx, 1902 rqpv, rxr_idx); 1903 1904 if (err) 1905 goto err_out; 1906 1907 /* update counts and index */ 1908 rxr_remaining -= rqpv; 1909 txr_remaining -= tqpv; 1910 rxr_idx++; 1911 txr_idx++; 1912 } 1913 1914 return 0; 1915 1916 err_out: 1917 wx->num_tx_queues = 0; 1918 wx->num_rx_queues = 0; 1919 wx->num_q_vectors = 0; 1920 1921 while (v_idx--) 1922 wx_free_q_vector(wx, v_idx); 1923 1924 return -ENOMEM; 1925 } 1926 1927 /** 1928 * wx_free_q_vectors - Free memory allocated for interrupt vectors 1929 * @wx: board private structure to initialize 1930 * 1931 * This function frees the memory allocated to the q_vectors. In addition if 1932 * NAPI is enabled it will delete any references to the NAPI struct prior 1933 * to freeing the q_vector. 1934 **/ 1935 static void wx_free_q_vectors(struct wx *wx) 1936 { 1937 int v_idx = wx->num_q_vectors; 1938 1939 wx->num_tx_queues = 0; 1940 wx->num_rx_queues = 0; 1941 wx->num_q_vectors = 0; 1942 1943 while (v_idx--) 1944 wx_free_q_vector(wx, v_idx); 1945 } 1946 1947 void wx_reset_interrupt_capability(struct wx *wx) 1948 { 1949 struct pci_dev *pdev = wx->pdev; 1950 1951 if (!pdev->msi_enabled && !pdev->msix_enabled) 1952 return; 1953 1954 if (pdev->msix_enabled) { 1955 kfree(wx->msix_q_entries); 1956 wx->msix_q_entries = NULL; 1957 kfree(wx->msix_entry); 1958 wx->msix_entry = NULL; 1959 } 1960 pci_free_irq_vectors(wx->pdev); 1961 } 1962 EXPORT_SYMBOL(wx_reset_interrupt_capability); 1963 1964 /** 1965 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings 1966 * @wx: board private structure to clear interrupt scheme on 1967 * 1968 * We go through and clear interrupt specific resources and reset the structure 1969 * to pre-load conditions 1970 **/ 1971 void wx_clear_interrupt_scheme(struct wx *wx) 1972 { 1973 wx_free_q_vectors(wx); 1974 wx_reset_interrupt_capability(wx); 1975 } 1976 EXPORT_SYMBOL(wx_clear_interrupt_scheme); 1977 1978 int wx_init_interrupt_scheme(struct wx *wx) 1979 { 1980 int ret; 1981 1982 /* Number of supported queues */ 1983 wx_set_num_queues(wx); 1984 1985 /* Set interrupt mode */ 1986 ret = wx_set_interrupt_capability(wx); 1987 if (ret) { 1988 wx_err(wx, "Allocate irq vectors for failed.\n"); 1989 return ret; 1990 } 1991 1992 /* Allocate memory for queues */ 1993 ret = wx_alloc_q_vectors(wx); 1994 if (ret) { 1995 wx_err(wx, "Unable to allocate memory for queue vectors.\n"); 1996 wx_reset_interrupt_capability(wx); 1997 return ret; 1998 } 1999 2000 wx_cache_ring_rss(wx); 2001 2002 return 0; 2003 } 2004 EXPORT_SYMBOL(wx_init_interrupt_scheme); 2005 2006 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data) 2007 { 2008 struct wx_q_vector *q_vector = data; 2009 2010 /* EIAM disabled interrupts (on this vector) for us */ 2011 if (q_vector->rx.ring || q_vector->tx.ring) 2012 napi_schedule_irqoff(&q_vector->napi); 2013 2014 return IRQ_HANDLED; 2015 } 2016 EXPORT_SYMBOL(wx_msix_clean_rings); 2017 2018 void wx_free_irq(struct wx *wx) 2019 { 2020 struct pci_dev *pdev = wx->pdev; 2021 int vector; 2022 2023 if (!(pdev->msix_enabled)) { 2024 free_irq(pdev->irq, wx); 2025 return; 2026 } 2027 2028 for (vector = 0; vector < wx->num_q_vectors; vector++) { 2029 struct wx_q_vector *q_vector = wx->q_vector[vector]; 2030 struct msix_entry *entry = &wx->msix_q_entries[vector]; 2031 2032 /* free only the irqs that were actually requested */ 2033 if (!q_vector->rx.ring && !q_vector->tx.ring) 2034 continue; 2035 2036 free_irq(entry->vector, q_vector); 2037 } 2038 2039 if (wx->mac.type == wx_mac_em) 2040 free_irq(wx->msix_entry->vector, wx); 2041 } 2042 EXPORT_SYMBOL(wx_free_irq); 2043 2044 /** 2045 * wx_setup_isb_resources - allocate interrupt status resources 2046 * @wx: board private structure 2047 * 2048 * Return 0 on success, negative on failure 2049 **/ 2050 int wx_setup_isb_resources(struct wx *wx) 2051 { 2052 struct pci_dev *pdev = wx->pdev; 2053 2054 wx->isb_mem = dma_alloc_coherent(&pdev->dev, 2055 sizeof(u32) * 4, 2056 &wx->isb_dma, 2057 GFP_KERNEL); 2058 if (!wx->isb_mem) { 2059 wx_err(wx, "Alloc isb_mem failed\n"); 2060 return -ENOMEM; 2061 } 2062 2063 return 0; 2064 } 2065 EXPORT_SYMBOL(wx_setup_isb_resources); 2066 2067 /** 2068 * wx_free_isb_resources - allocate all queues Rx resources 2069 * @wx: board private structure 2070 * 2071 * Return 0 on success, negative on failure 2072 **/ 2073 void wx_free_isb_resources(struct wx *wx) 2074 { 2075 struct pci_dev *pdev = wx->pdev; 2076 2077 dma_free_coherent(&pdev->dev, sizeof(u32) * 4, 2078 wx->isb_mem, wx->isb_dma); 2079 wx->isb_mem = NULL; 2080 } 2081 EXPORT_SYMBOL(wx_free_isb_resources); 2082 2083 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx) 2084 { 2085 u32 cur_tag = 0; 2086 2087 cur_tag = wx->isb_mem[WX_ISB_HEADER]; 2088 wx->isb_tag[idx] = cur_tag; 2089 2090 return (__force u32)cpu_to_le32(wx->isb_mem[idx]); 2091 } 2092 EXPORT_SYMBOL(wx_misc_isb); 2093 2094 /** 2095 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 2096 * @wx: pointer to wx struct 2097 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 2098 * @queue: queue to map the corresponding interrupt to 2099 * @msix_vector: the vector to map to the corresponding queue 2100 * 2101 **/ 2102 static void wx_set_ivar(struct wx *wx, s8 direction, 2103 u16 queue, u16 msix_vector) 2104 { 2105 u32 ivar, index; 2106 2107 if (direction == -1) { 2108 /* other causes */ 2109 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2110 index = 0; 2111 ivar = rd32(wx, WX_PX_MISC_IVAR); 2112 ivar &= ~(0xFF << index); 2113 ivar |= (msix_vector << index); 2114 wr32(wx, WX_PX_MISC_IVAR, ivar); 2115 } else { 2116 /* tx or rx causes */ 2117 msix_vector += 1; /* offset for queue vectors */ 2118 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2119 index = ((16 * (queue & 1)) + (8 * direction)); 2120 ivar = rd32(wx, WX_PX_IVAR(queue >> 1)); 2121 ivar &= ~(0xFF << index); 2122 ivar |= (msix_vector << index); 2123 wr32(wx, WX_PX_IVAR(queue >> 1), ivar); 2124 } 2125 } 2126 2127 /** 2128 * wx_write_eitr - write EITR register in hardware specific way 2129 * @q_vector: structure containing interrupt and ring information 2130 * 2131 * This function is made to be called by ethtool and by the driver 2132 * when it needs to update EITR registers at runtime. Hardware 2133 * specific quirks/differences are taken care of here. 2134 */ 2135 void wx_write_eitr(struct wx_q_vector *q_vector) 2136 { 2137 struct wx *wx = q_vector->wx; 2138 int v_idx = q_vector->v_idx; 2139 u32 itr_reg; 2140 2141 if (wx->mac.type == wx_mac_sp) 2142 itr_reg = q_vector->itr & WX_SP_MAX_EITR; 2143 else 2144 itr_reg = q_vector->itr & WX_EM_MAX_EITR; 2145 2146 itr_reg |= WX_PX_ITR_CNT_WDIS; 2147 2148 wr32(wx, WX_PX_ITR(v_idx + 1), itr_reg); 2149 } 2150 2151 /** 2152 * wx_configure_vectors - Configure vectors for hardware 2153 * @wx: board private structure 2154 * 2155 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx 2156 * interrupts. 2157 **/ 2158 void wx_configure_vectors(struct wx *wx) 2159 { 2160 struct pci_dev *pdev = wx->pdev; 2161 u32 eitrsel = 0; 2162 u16 v_idx; 2163 2164 if (pdev->msix_enabled) { 2165 /* Populate MSIX to EITR Select */ 2166 wr32(wx, WX_PX_ITRSEL, eitrsel); 2167 /* use EIAM to auto-mask when MSI-X interrupt is asserted 2168 * this saves a register write for every interrupt 2169 */ 2170 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL); 2171 } else { 2172 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 2173 * specifically only auto mask tx and rx interrupts. 2174 */ 2175 wr32(wx, WX_PX_GPIE, 0); 2176 } 2177 2178 /* Populate the IVAR table and set the ITR values to the 2179 * corresponding register. 2180 */ 2181 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) { 2182 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2183 struct wx_ring *ring; 2184 2185 wx_for_each_ring(ring, q_vector->rx) 2186 wx_set_ivar(wx, 0, ring->reg_idx, v_idx); 2187 2188 wx_for_each_ring(ring, q_vector->tx) 2189 wx_set_ivar(wx, 1, ring->reg_idx, v_idx); 2190 2191 wx_write_eitr(q_vector); 2192 } 2193 2194 wx_set_ivar(wx, -1, 0, 0); 2195 if (pdev->msix_enabled) 2196 wr32(wx, WX_PX_ITR(0), 1950); 2197 } 2198 EXPORT_SYMBOL(wx_configure_vectors); 2199 2200 /** 2201 * wx_clean_rx_ring - Free Rx Buffers per Queue 2202 * @rx_ring: ring to free buffers from 2203 **/ 2204 static void wx_clean_rx_ring(struct wx_ring *rx_ring) 2205 { 2206 struct wx_rx_buffer *rx_buffer; 2207 u16 i = rx_ring->next_to_clean; 2208 2209 rx_buffer = &rx_ring->rx_buffer_info[i]; 2210 2211 /* Free all the Rx ring sk_buffs */ 2212 while (i != rx_ring->next_to_alloc) { 2213 if (rx_buffer->skb) { 2214 struct sk_buff *skb = rx_buffer->skb; 2215 2216 if (WX_CB(skb)->page_released) 2217 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2218 2219 dev_kfree_skb(skb); 2220 } 2221 2222 /* Invalidate cache lines that may have been written to by 2223 * device so that we avoid corrupting memory. 2224 */ 2225 dma_sync_single_range_for_cpu(rx_ring->dev, 2226 rx_buffer->dma, 2227 rx_buffer->page_offset, 2228 WX_RX_BUFSZ, 2229 DMA_FROM_DEVICE); 2230 2231 /* free resources associated with mapping */ 2232 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2233 2234 i++; 2235 rx_buffer++; 2236 if (i == rx_ring->count) { 2237 i = 0; 2238 rx_buffer = rx_ring->rx_buffer_info; 2239 } 2240 } 2241 2242 rx_ring->next_to_alloc = 0; 2243 rx_ring->next_to_clean = 0; 2244 rx_ring->next_to_use = 0; 2245 } 2246 2247 /** 2248 * wx_clean_all_rx_rings - Free Rx Buffers for all queues 2249 * @wx: board private structure 2250 **/ 2251 void wx_clean_all_rx_rings(struct wx *wx) 2252 { 2253 int i; 2254 2255 for (i = 0; i < wx->num_rx_queues; i++) 2256 wx_clean_rx_ring(wx->rx_ring[i]); 2257 } 2258 EXPORT_SYMBOL(wx_clean_all_rx_rings); 2259 2260 /** 2261 * wx_free_rx_resources - Free Rx Resources 2262 * @rx_ring: ring to clean the resources from 2263 * 2264 * Free all receive software resources 2265 **/ 2266 static void wx_free_rx_resources(struct wx_ring *rx_ring) 2267 { 2268 wx_clean_rx_ring(rx_ring); 2269 kvfree(rx_ring->rx_buffer_info); 2270 rx_ring->rx_buffer_info = NULL; 2271 2272 /* if not set, then don't free */ 2273 if (!rx_ring->desc) 2274 return; 2275 2276 dma_free_coherent(rx_ring->dev, rx_ring->size, 2277 rx_ring->desc, rx_ring->dma); 2278 2279 rx_ring->desc = NULL; 2280 2281 if (rx_ring->page_pool) { 2282 page_pool_destroy(rx_ring->page_pool); 2283 rx_ring->page_pool = NULL; 2284 } 2285 } 2286 2287 /** 2288 * wx_free_all_rx_resources - Free Rx Resources for All Queues 2289 * @wx: pointer to hardware structure 2290 * 2291 * Free all receive software resources 2292 **/ 2293 static void wx_free_all_rx_resources(struct wx *wx) 2294 { 2295 int i; 2296 2297 for (i = 0; i < wx->num_rx_queues; i++) 2298 wx_free_rx_resources(wx->rx_ring[i]); 2299 } 2300 2301 /** 2302 * wx_clean_tx_ring - Free Tx Buffers 2303 * @tx_ring: ring to be cleaned 2304 **/ 2305 static void wx_clean_tx_ring(struct wx_ring *tx_ring) 2306 { 2307 struct wx_tx_buffer *tx_buffer; 2308 u16 i = tx_ring->next_to_clean; 2309 2310 tx_buffer = &tx_ring->tx_buffer_info[i]; 2311 2312 while (i != tx_ring->next_to_use) { 2313 union wx_tx_desc *eop_desc, *tx_desc; 2314 2315 /* Free all the Tx ring sk_buffs */ 2316 dev_kfree_skb_any(tx_buffer->skb); 2317 2318 /* unmap skb header data */ 2319 dma_unmap_single(tx_ring->dev, 2320 dma_unmap_addr(tx_buffer, dma), 2321 dma_unmap_len(tx_buffer, len), 2322 DMA_TO_DEVICE); 2323 2324 /* check for eop_desc to determine the end of the packet */ 2325 eop_desc = tx_buffer->next_to_watch; 2326 tx_desc = WX_TX_DESC(tx_ring, i); 2327 2328 /* unmap remaining buffers */ 2329 while (tx_desc != eop_desc) { 2330 tx_buffer++; 2331 tx_desc++; 2332 i++; 2333 if (unlikely(i == tx_ring->count)) { 2334 i = 0; 2335 tx_buffer = tx_ring->tx_buffer_info; 2336 tx_desc = WX_TX_DESC(tx_ring, 0); 2337 } 2338 2339 /* unmap any remaining paged data */ 2340 if (dma_unmap_len(tx_buffer, len)) 2341 dma_unmap_page(tx_ring->dev, 2342 dma_unmap_addr(tx_buffer, dma), 2343 dma_unmap_len(tx_buffer, len), 2344 DMA_TO_DEVICE); 2345 } 2346 2347 /* move us one more past the eop_desc for start of next pkt */ 2348 tx_buffer++; 2349 i++; 2350 if (unlikely(i == tx_ring->count)) { 2351 i = 0; 2352 tx_buffer = tx_ring->tx_buffer_info; 2353 } 2354 } 2355 2356 netdev_tx_reset_queue(wx_txring_txq(tx_ring)); 2357 2358 /* reset next_to_use and next_to_clean */ 2359 tx_ring->next_to_use = 0; 2360 tx_ring->next_to_clean = 0; 2361 } 2362 2363 /** 2364 * wx_clean_all_tx_rings - Free Tx Buffers for all queues 2365 * @wx: board private structure 2366 **/ 2367 void wx_clean_all_tx_rings(struct wx *wx) 2368 { 2369 int i; 2370 2371 for (i = 0; i < wx->num_tx_queues; i++) 2372 wx_clean_tx_ring(wx->tx_ring[i]); 2373 } 2374 EXPORT_SYMBOL(wx_clean_all_tx_rings); 2375 2376 /** 2377 * wx_free_tx_resources - Free Tx Resources per Queue 2378 * @tx_ring: Tx descriptor ring for a specific queue 2379 * 2380 * Free all transmit software resources 2381 **/ 2382 static void wx_free_tx_resources(struct wx_ring *tx_ring) 2383 { 2384 wx_clean_tx_ring(tx_ring); 2385 kvfree(tx_ring->tx_buffer_info); 2386 tx_ring->tx_buffer_info = NULL; 2387 2388 /* if not set, then don't free */ 2389 if (!tx_ring->desc) 2390 return; 2391 2392 dma_free_coherent(tx_ring->dev, tx_ring->size, 2393 tx_ring->desc, tx_ring->dma); 2394 tx_ring->desc = NULL; 2395 } 2396 2397 /** 2398 * wx_free_all_tx_resources - Free Tx Resources for All Queues 2399 * @wx: pointer to hardware structure 2400 * 2401 * Free all transmit software resources 2402 **/ 2403 static void wx_free_all_tx_resources(struct wx *wx) 2404 { 2405 int i; 2406 2407 for (i = 0; i < wx->num_tx_queues; i++) 2408 wx_free_tx_resources(wx->tx_ring[i]); 2409 } 2410 2411 void wx_free_resources(struct wx *wx) 2412 { 2413 wx_free_isb_resources(wx); 2414 wx_free_all_rx_resources(wx); 2415 wx_free_all_tx_resources(wx); 2416 } 2417 EXPORT_SYMBOL(wx_free_resources); 2418 2419 static int wx_alloc_page_pool(struct wx_ring *rx_ring) 2420 { 2421 int ret = 0; 2422 2423 struct page_pool_params pp_params = { 2424 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2425 .order = 0, 2426 .pool_size = rx_ring->size, 2427 .nid = dev_to_node(rx_ring->dev), 2428 .dev = rx_ring->dev, 2429 .dma_dir = DMA_FROM_DEVICE, 2430 .offset = 0, 2431 .max_len = PAGE_SIZE, 2432 }; 2433 2434 rx_ring->page_pool = page_pool_create(&pp_params); 2435 if (IS_ERR(rx_ring->page_pool)) { 2436 ret = PTR_ERR(rx_ring->page_pool); 2437 rx_ring->page_pool = NULL; 2438 } 2439 2440 return ret; 2441 } 2442 2443 /** 2444 * wx_setup_rx_resources - allocate Rx resources (Descriptors) 2445 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2446 * 2447 * Returns 0 on success, negative on failure 2448 **/ 2449 static int wx_setup_rx_resources(struct wx_ring *rx_ring) 2450 { 2451 struct device *dev = rx_ring->dev; 2452 int orig_node = dev_to_node(dev); 2453 int numa_node = NUMA_NO_NODE; 2454 int size, ret; 2455 2456 size = sizeof(struct wx_rx_buffer) * rx_ring->count; 2457 2458 if (rx_ring->q_vector) 2459 numa_node = rx_ring->q_vector->numa_node; 2460 2461 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2462 if (!rx_ring->rx_buffer_info) 2463 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL); 2464 if (!rx_ring->rx_buffer_info) 2465 goto err; 2466 2467 /* Round up to nearest 4K */ 2468 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc); 2469 rx_ring->size = ALIGN(rx_ring->size, 4096); 2470 2471 set_dev_node(dev, numa_node); 2472 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2473 &rx_ring->dma, GFP_KERNEL); 2474 if (!rx_ring->desc) { 2475 set_dev_node(dev, orig_node); 2476 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2477 &rx_ring->dma, GFP_KERNEL); 2478 } 2479 2480 if (!rx_ring->desc) 2481 goto err; 2482 2483 rx_ring->next_to_clean = 0; 2484 rx_ring->next_to_use = 0; 2485 2486 ret = wx_alloc_page_pool(rx_ring); 2487 if (ret < 0) { 2488 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret); 2489 goto err_desc; 2490 } 2491 2492 return 0; 2493 2494 err_desc: 2495 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2496 err: 2497 kvfree(rx_ring->rx_buffer_info); 2498 rx_ring->rx_buffer_info = NULL; 2499 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2500 return -ENOMEM; 2501 } 2502 2503 /** 2504 * wx_setup_all_rx_resources - allocate all queues Rx resources 2505 * @wx: pointer to hardware structure 2506 * 2507 * If this function returns with an error, then it's possible one or 2508 * more of the rings is populated (while the rest are not). It is the 2509 * callers duty to clean those orphaned rings. 2510 * 2511 * Return 0 on success, negative on failure 2512 **/ 2513 static int wx_setup_all_rx_resources(struct wx *wx) 2514 { 2515 int i, err = 0; 2516 2517 for (i = 0; i < wx->num_rx_queues; i++) { 2518 err = wx_setup_rx_resources(wx->rx_ring[i]); 2519 if (!err) 2520 continue; 2521 2522 wx_err(wx, "Allocation for Rx Queue %u failed\n", i); 2523 goto err_setup_rx; 2524 } 2525 2526 return 0; 2527 err_setup_rx: 2528 /* rewind the index freeing the rings as we go */ 2529 while (i--) 2530 wx_free_rx_resources(wx->rx_ring[i]); 2531 return err; 2532 } 2533 2534 /** 2535 * wx_setup_tx_resources - allocate Tx resources (Descriptors) 2536 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2537 * 2538 * Return 0 on success, negative on failure 2539 **/ 2540 static int wx_setup_tx_resources(struct wx_ring *tx_ring) 2541 { 2542 struct device *dev = tx_ring->dev; 2543 int orig_node = dev_to_node(dev); 2544 int numa_node = NUMA_NO_NODE; 2545 int size; 2546 2547 size = sizeof(struct wx_tx_buffer) * tx_ring->count; 2548 2549 if (tx_ring->q_vector) 2550 numa_node = tx_ring->q_vector->numa_node; 2551 2552 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2553 if (!tx_ring->tx_buffer_info) 2554 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL); 2555 if (!tx_ring->tx_buffer_info) 2556 goto err; 2557 2558 /* round up to nearest 4K */ 2559 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc); 2560 tx_ring->size = ALIGN(tx_ring->size, 4096); 2561 2562 set_dev_node(dev, numa_node); 2563 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2564 &tx_ring->dma, GFP_KERNEL); 2565 if (!tx_ring->desc) { 2566 set_dev_node(dev, orig_node); 2567 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2568 &tx_ring->dma, GFP_KERNEL); 2569 } 2570 2571 if (!tx_ring->desc) 2572 goto err; 2573 2574 tx_ring->next_to_use = 0; 2575 tx_ring->next_to_clean = 0; 2576 2577 return 0; 2578 2579 err: 2580 kvfree(tx_ring->tx_buffer_info); 2581 tx_ring->tx_buffer_info = NULL; 2582 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2583 return -ENOMEM; 2584 } 2585 2586 /** 2587 * wx_setup_all_tx_resources - allocate all queues Tx resources 2588 * @wx: pointer to private structure 2589 * 2590 * If this function returns with an error, then it's possible one or 2591 * more of the rings is populated (while the rest are not). It is the 2592 * callers duty to clean those orphaned rings. 2593 * 2594 * Return 0 on success, negative on failure 2595 **/ 2596 static int wx_setup_all_tx_resources(struct wx *wx) 2597 { 2598 int i, err = 0; 2599 2600 for (i = 0; i < wx->num_tx_queues; i++) { 2601 err = wx_setup_tx_resources(wx->tx_ring[i]); 2602 if (!err) 2603 continue; 2604 2605 wx_err(wx, "Allocation for Tx Queue %u failed\n", i); 2606 goto err_setup_tx; 2607 } 2608 2609 return 0; 2610 err_setup_tx: 2611 /* rewind the index freeing the rings as we go */ 2612 while (i--) 2613 wx_free_tx_resources(wx->tx_ring[i]); 2614 return err; 2615 } 2616 2617 int wx_setup_resources(struct wx *wx) 2618 { 2619 int err; 2620 2621 /* allocate transmit descriptors */ 2622 err = wx_setup_all_tx_resources(wx); 2623 if (err) 2624 return err; 2625 2626 /* allocate receive descriptors */ 2627 err = wx_setup_all_rx_resources(wx); 2628 if (err) 2629 goto err_free_tx; 2630 2631 err = wx_setup_isb_resources(wx); 2632 if (err) 2633 goto err_free_rx; 2634 2635 return 0; 2636 2637 err_free_rx: 2638 wx_free_all_rx_resources(wx); 2639 err_free_tx: 2640 wx_free_all_tx_resources(wx); 2641 2642 return err; 2643 } 2644 EXPORT_SYMBOL(wx_setup_resources); 2645 2646 /** 2647 * wx_get_stats64 - Get System Network Statistics 2648 * @netdev: network interface device structure 2649 * @stats: storage space for 64bit statistics 2650 */ 2651 void wx_get_stats64(struct net_device *netdev, 2652 struct rtnl_link_stats64 *stats) 2653 { 2654 struct wx *wx = netdev_priv(netdev); 2655 struct wx_hw_stats *hwstats; 2656 int i; 2657 2658 wx_update_stats(wx); 2659 2660 rcu_read_lock(); 2661 for (i = 0; i < wx->num_rx_queues; i++) { 2662 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]); 2663 u64 bytes, packets; 2664 unsigned int start; 2665 2666 if (ring) { 2667 do { 2668 start = u64_stats_fetch_begin(&ring->syncp); 2669 packets = ring->stats.packets; 2670 bytes = ring->stats.bytes; 2671 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2672 stats->rx_packets += packets; 2673 stats->rx_bytes += bytes; 2674 } 2675 } 2676 2677 for (i = 0; i < wx->num_tx_queues; i++) { 2678 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]); 2679 u64 bytes, packets; 2680 unsigned int start; 2681 2682 if (ring) { 2683 do { 2684 start = u64_stats_fetch_begin(&ring->syncp); 2685 packets = ring->stats.packets; 2686 bytes = ring->stats.bytes; 2687 } while (u64_stats_fetch_retry(&ring->syncp, 2688 start)); 2689 stats->tx_packets += packets; 2690 stats->tx_bytes += bytes; 2691 } 2692 } 2693 2694 rcu_read_unlock(); 2695 2696 hwstats = &wx->stats; 2697 stats->rx_errors = hwstats->crcerrs + hwstats->rlec; 2698 stats->multicast = hwstats->qmprc; 2699 stats->rx_length_errors = hwstats->rlec; 2700 stats->rx_crc_errors = hwstats->crcerrs; 2701 } 2702 EXPORT_SYMBOL(wx_get_stats64); 2703 2704 int wx_set_features(struct net_device *netdev, netdev_features_t features) 2705 { 2706 netdev_features_t changed = netdev->features ^ features; 2707 struct wx *wx = netdev_priv(netdev); 2708 bool need_reset = false; 2709 2710 if (features & NETIF_F_RXHASH) { 2711 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 2712 WX_RDB_RA_CTL_RSS_EN); 2713 wx->rss_enabled = true; 2714 } else { 2715 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0); 2716 wx->rss_enabled = false; 2717 } 2718 2719 netdev->features = features; 2720 2721 if (wx->mac.type == wx_mac_sp && changed & NETIF_F_HW_VLAN_CTAG_RX) 2722 wx->do_reset(netdev); 2723 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER)) 2724 wx_set_rx_mode(netdev); 2725 2726 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 2727 return 0; 2728 2729 /* Check if Flow Director n-tuple support was enabled or disabled. If 2730 * the state changed, we need to reset. 2731 */ 2732 switch (features & NETIF_F_NTUPLE) { 2733 case NETIF_F_NTUPLE: 2734 /* turn off ATR, enable perfect filters and reset */ 2735 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 2736 need_reset = true; 2737 2738 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 2739 break; 2740 default: 2741 /* turn off perfect filters, enable ATR and reset */ 2742 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 2743 need_reset = true; 2744 2745 /* We cannot enable ATR if RSS is disabled */ 2746 if (wx->ring_feature[RING_F_RSS].limit <= 1) 2747 break; 2748 2749 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 2750 break; 2751 } 2752 2753 if (need_reset) 2754 wx->do_reset(netdev); 2755 2756 return 0; 2757 } 2758 EXPORT_SYMBOL(wx_set_features); 2759 2760 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \ 2761 NETIF_F_HW_VLAN_STAG_RX) 2762 2763 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \ 2764 NETIF_F_HW_VLAN_STAG_TX) 2765 2766 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \ 2767 NETIF_F_HW_VLAN_STAG_FILTER) 2768 2769 netdev_features_t wx_fix_features(struct net_device *netdev, 2770 netdev_features_t features) 2771 { 2772 netdev_features_t changed = netdev->features ^ features; 2773 struct wx *wx = netdev_priv(netdev); 2774 2775 if (changed & NETIF_VLAN_STRIPPING_FEATURES) { 2776 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES && 2777 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) { 2778 features &= ~NETIF_VLAN_STRIPPING_FEATURES; 2779 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES; 2780 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off."); 2781 } 2782 } 2783 2784 if (changed & NETIF_VLAN_INSERTION_FEATURES) { 2785 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES && 2786 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) { 2787 features &= ~NETIF_VLAN_INSERTION_FEATURES; 2788 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES; 2789 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off."); 2790 } 2791 } 2792 2793 if (changed & NETIF_VLAN_FILTERING_FEATURES) { 2794 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES && 2795 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) { 2796 features &= ~NETIF_VLAN_FILTERING_FEATURES; 2797 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES; 2798 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off."); 2799 } 2800 } 2801 2802 return features; 2803 } 2804 EXPORT_SYMBOL(wx_fix_features); 2805 2806 void wx_set_ring(struct wx *wx, u32 new_tx_count, 2807 u32 new_rx_count, struct wx_ring *temp_ring) 2808 { 2809 int i, err = 0; 2810 2811 /* Setup new Tx resources and free the old Tx resources in that order. 2812 * We can then assign the new resources to the rings via a memcpy. 2813 * The advantage to this approach is that we are guaranteed to still 2814 * have resources even in the case of an allocation failure. 2815 */ 2816 if (new_tx_count != wx->tx_ring_count) { 2817 for (i = 0; i < wx->num_tx_queues; i++) { 2818 memcpy(&temp_ring[i], wx->tx_ring[i], 2819 sizeof(struct wx_ring)); 2820 2821 temp_ring[i].count = new_tx_count; 2822 err = wx_setup_tx_resources(&temp_ring[i]); 2823 if (err) { 2824 wx_err(wx, "setup new tx resources failed, keep using the old config\n"); 2825 while (i) { 2826 i--; 2827 wx_free_tx_resources(&temp_ring[i]); 2828 } 2829 return; 2830 } 2831 } 2832 2833 for (i = 0; i < wx->num_tx_queues; i++) { 2834 wx_free_tx_resources(wx->tx_ring[i]); 2835 2836 memcpy(wx->tx_ring[i], &temp_ring[i], 2837 sizeof(struct wx_ring)); 2838 } 2839 2840 wx->tx_ring_count = new_tx_count; 2841 } 2842 2843 /* Repeat the process for the Rx rings if needed */ 2844 if (new_rx_count != wx->rx_ring_count) { 2845 for (i = 0; i < wx->num_rx_queues; i++) { 2846 memcpy(&temp_ring[i], wx->rx_ring[i], 2847 sizeof(struct wx_ring)); 2848 2849 temp_ring[i].count = new_rx_count; 2850 err = wx_setup_rx_resources(&temp_ring[i]); 2851 if (err) { 2852 wx_err(wx, "setup new rx resources failed, keep using the old config\n"); 2853 while (i) { 2854 i--; 2855 wx_free_rx_resources(&temp_ring[i]); 2856 } 2857 return; 2858 } 2859 } 2860 2861 for (i = 0; i < wx->num_rx_queues; i++) { 2862 wx_free_rx_resources(wx->rx_ring[i]); 2863 memcpy(wx->rx_ring[i], &temp_ring[i], 2864 sizeof(struct wx_ring)); 2865 } 2866 2867 wx->rx_ring_count = new_rx_count; 2868 } 2869 } 2870 EXPORT_SYMBOL(wx_set_ring); 2871 2872 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers."); 2873 MODULE_LICENSE("GPL"); 2874