1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <net/ip6_checksum.h> 6 #include <net/page_pool/helpers.h> 7 #include <net/inet_ecn.h> 8 #include <linux/iopoll.h> 9 #include <linux/sctp.h> 10 #include <linux/pci.h> 11 #include <net/tcp.h> 12 #include <net/ip.h> 13 14 #include "wx_type.h" 15 #include "wx_lib.h" 16 #include "wx_ptp.h" 17 #include "wx_hw.h" 18 19 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 20 static struct wx_dec_ptype wx_ptype_lookup[256] = { 21 /* L2: mac */ 22 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 23 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2), 24 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 25 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 26 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 27 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 28 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 29 30 /* L2: ethertype filter */ 31 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 32 33 /* L3: ip non-tunnel */ 34 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3), 35 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3), 36 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4), 37 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4), 38 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4), 39 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3), 40 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3), 41 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3), 42 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4), 43 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4), 44 45 /* L2: fcoe */ 46 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 47 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 48 49 /* IPv4 --> IPv4/IPv6 */ 50 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3), 51 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3), 52 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4), 53 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4), 54 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4), 55 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3), 56 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3), 57 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4), 58 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4), 59 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4), 60 61 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */ 62 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3), 63 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3), 64 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3), 65 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4), 66 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4), 67 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4), 68 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3), 69 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3), 70 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4), 71 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4), 72 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4), 73 74 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */ 75 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3), 76 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3), 77 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3), 78 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4), 79 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4), 80 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4), 81 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3), 82 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3), 83 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4), 84 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4), 85 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4), 86 87 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */ 88 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3), 89 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3), 90 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3), 91 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4), 92 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4), 93 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4), 94 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3), 95 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3), 96 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4), 97 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4), 98 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4), 99 100 /* IPv6 --> IPv4/IPv6 */ 101 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3), 102 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3), 103 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4), 104 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4), 105 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4), 106 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3), 107 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3), 108 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4), 109 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4), 110 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4), 111 112 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */ 113 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3), 114 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3), 115 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3), 116 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4), 117 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4), 118 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4), 119 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3), 120 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3), 121 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4), 122 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4), 123 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4), 124 125 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */ 126 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3), 127 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3), 128 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3), 129 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4), 130 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4), 131 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4), 132 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3), 133 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3), 134 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4), 135 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4), 136 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4), 137 138 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */ 139 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3), 140 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3), 141 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3), 142 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4), 143 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4), 144 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4), 145 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3), 146 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3), 147 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4), 148 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4), 149 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4), 150 }; 151 152 struct wx_dec_ptype wx_decode_ptype(const u8 ptype) 153 { 154 return wx_ptype_lookup[ptype]; 155 } 156 EXPORT_SYMBOL(wx_decode_ptype); 157 158 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */ 159 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc, 160 const u32 stat_err_bits) 161 { 162 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 163 } 164 165 static void wx_dma_sync_frag(struct wx_ring *rx_ring, 166 struct wx_rx_buffer *rx_buffer) 167 { 168 struct sk_buff *skb = rx_buffer->skb; 169 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 170 171 dma_sync_single_range_for_cpu(rx_ring->dev, 172 WX_CB(skb)->dma, 173 skb_frag_off(frag), 174 skb_frag_size(frag), 175 DMA_FROM_DEVICE); 176 177 /* If the page was released, just unmap it. */ 178 if (unlikely(WX_CB(skb)->page_released)) 179 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 180 } 181 182 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring, 183 union wx_rx_desc *rx_desc, 184 struct sk_buff **skb, 185 int *rx_buffer_pgcnt) 186 { 187 struct wx_rx_buffer *rx_buffer; 188 unsigned int size; 189 190 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 191 size = le16_to_cpu(rx_desc->wb.upper.length); 192 193 #if (PAGE_SIZE < 8192) 194 *rx_buffer_pgcnt = page_count(rx_buffer->page); 195 #else 196 *rx_buffer_pgcnt = 0; 197 #endif 198 199 prefetchw(rx_buffer->page); 200 *skb = rx_buffer->skb; 201 202 /* Delay unmapping of the first packet. It carries the header 203 * information, HW may still access the header after the writeback. 204 * Only unmap it when EOP is reached 205 */ 206 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) { 207 if (!*skb) 208 goto skip_sync; 209 } else { 210 if (*skb) 211 wx_dma_sync_frag(rx_ring, rx_buffer); 212 } 213 214 /* we are reusing so sync this buffer for CPU use */ 215 dma_sync_single_range_for_cpu(rx_ring->dev, 216 rx_buffer->dma, 217 rx_buffer->page_offset, 218 size, 219 DMA_FROM_DEVICE); 220 skip_sync: 221 return rx_buffer; 222 } 223 224 static void wx_put_rx_buffer(struct wx_ring *rx_ring, 225 struct wx_rx_buffer *rx_buffer, 226 struct sk_buff *skb, 227 int rx_buffer_pgcnt) 228 { 229 if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma) 230 /* the page has been released from the ring */ 231 WX_CB(skb)->page_released = true; 232 233 /* clear contents of rx_buffer */ 234 rx_buffer->page = NULL; 235 rx_buffer->skb = NULL; 236 } 237 238 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring, 239 struct wx_rx_buffer *rx_buffer, 240 union wx_rx_desc *rx_desc) 241 { 242 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 243 #if (PAGE_SIZE < 8192) 244 unsigned int truesize = WX_RX_BUFSZ; 245 #else 246 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 247 #endif 248 struct sk_buff *skb = rx_buffer->skb; 249 250 if (!skb) { 251 void *page_addr = page_address(rx_buffer->page) + 252 rx_buffer->page_offset; 253 254 /* prefetch first cache line of first page */ 255 net_prefetch(page_addr); 256 257 /* allocate a skb to store the frags */ 258 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256); 259 if (unlikely(!skb)) 260 return NULL; 261 262 /* we will be copying header into skb->data in 263 * pskb_may_pull so it is in our interest to prefetch 264 * it now to avoid a possible cache miss 265 */ 266 prefetchw(skb->data); 267 268 if (size <= WX_RXBUFFER_256) { 269 memcpy(__skb_put(skb, size), page_addr, 270 ALIGN(size, sizeof(long))); 271 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true); 272 return skb; 273 } 274 275 skb_mark_for_recycle(skb); 276 277 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) 278 WX_CB(skb)->dma = rx_buffer->dma; 279 280 skb_add_rx_frag(skb, 0, rx_buffer->page, 281 rx_buffer->page_offset, 282 size, truesize); 283 goto out; 284 285 } else { 286 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 287 rx_buffer->page_offset, size, truesize); 288 } 289 290 out: 291 #if (PAGE_SIZE < 8192) 292 /* flip page offset to other buffer */ 293 rx_buffer->page_offset ^= truesize; 294 #else 295 /* move offset up to the next cache line */ 296 rx_buffer->page_offset += truesize; 297 #endif 298 299 return skb; 300 } 301 302 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring, 303 struct wx_rx_buffer *bi) 304 { 305 struct page *page = bi->page; 306 dma_addr_t dma; 307 308 /* since we are recycling buffers we should seldom need to alloc */ 309 if (likely(page)) 310 return true; 311 312 page = page_pool_dev_alloc_pages(rx_ring->page_pool); 313 if (unlikely(!page)) 314 return false; 315 dma = page_pool_get_dma_addr(page); 316 317 bi->page_dma = dma; 318 bi->page = page; 319 bi->page_offset = 0; 320 321 return true; 322 } 323 324 /** 325 * wx_alloc_rx_buffers - Replace used receive buffers 326 * @rx_ring: ring to place buffers on 327 * @cleaned_count: number of buffers to replace 328 **/ 329 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count) 330 { 331 u16 i = rx_ring->next_to_use; 332 union wx_rx_desc *rx_desc; 333 struct wx_rx_buffer *bi; 334 335 /* nothing to do */ 336 if (!cleaned_count) 337 return; 338 339 rx_desc = WX_RX_DESC(rx_ring, i); 340 bi = &rx_ring->rx_buffer_info[i]; 341 i -= rx_ring->count; 342 343 do { 344 if (!wx_alloc_mapped_page(rx_ring, bi)) 345 break; 346 347 /* sync the buffer for use by the device */ 348 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 349 bi->page_offset, 350 WX_RX_BUFSZ, 351 DMA_FROM_DEVICE); 352 353 rx_desc->read.pkt_addr = 354 cpu_to_le64(bi->page_dma + bi->page_offset); 355 356 rx_desc++; 357 bi++; 358 i++; 359 if (unlikely(!i)) { 360 rx_desc = WX_RX_DESC(rx_ring, 0); 361 bi = rx_ring->rx_buffer_info; 362 i -= rx_ring->count; 363 } 364 365 /* clear the status bits for the next_to_use descriptor */ 366 rx_desc->wb.upper.status_error = 0; 367 368 cleaned_count--; 369 } while (cleaned_count); 370 371 i += rx_ring->count; 372 373 if (rx_ring->next_to_use != i) { 374 rx_ring->next_to_use = i; 375 /* update next to alloc since we have filled the ring */ 376 rx_ring->next_to_alloc = i; 377 378 /* Force memory writes to complete before letting h/w 379 * know there are new descriptors to fetch. (Only 380 * applicable for weak-ordered memory model archs, 381 * such as IA-64). 382 */ 383 wmb(); 384 writel(i, rx_ring->tail); 385 } 386 } 387 388 u16 wx_desc_unused(struct wx_ring *ring) 389 { 390 u16 ntc = ring->next_to_clean; 391 u16 ntu = ring->next_to_use; 392 393 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 394 } 395 396 /** 397 * wx_is_non_eop - process handling of non-EOP buffers 398 * @rx_ring: Rx ring being processed 399 * @rx_desc: Rx descriptor for current buffer 400 * @skb: Current socket buffer containing buffer in progress 401 * 402 * This function updates next to clean. If the buffer is an EOP buffer 403 * this function exits returning false, otherwise it will place the 404 * sk_buff in the next buffer to be chained and return true indicating 405 * that this is in fact a non-EOP buffer. 406 **/ 407 static bool wx_is_non_eop(struct wx_ring *rx_ring, 408 union wx_rx_desc *rx_desc, 409 struct sk_buff *skb) 410 { 411 u32 ntc = rx_ring->next_to_clean + 1; 412 413 /* fetch, update, and store next to clean */ 414 ntc = (ntc < rx_ring->count) ? ntc : 0; 415 rx_ring->next_to_clean = ntc; 416 417 prefetch(WX_RX_DESC(rx_ring, ntc)); 418 419 /* if we are the last buffer then there is nothing else to do */ 420 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))) 421 return false; 422 423 rx_ring->rx_buffer_info[ntc].skb = skb; 424 rx_ring->rx_stats.non_eop_descs++; 425 426 return true; 427 } 428 429 static void wx_pull_tail(struct sk_buff *skb) 430 { 431 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 432 unsigned int pull_len; 433 unsigned char *va; 434 435 /* it is valid to use page_address instead of kmap since we are 436 * working with pages allocated out of the lomem pool per 437 * alloc_page(GFP_ATOMIC) 438 */ 439 va = skb_frag_address(frag); 440 441 /* we need the header to contain the greater of either ETH_HLEN or 442 * 60 bytes if the skb->len is less than 60 for skb_pad. 443 */ 444 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256); 445 446 /* align pull length to size of long to optimize memcpy performance */ 447 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 448 449 /* update all of the pointers */ 450 skb_frag_size_sub(frag, pull_len); 451 skb_frag_off_add(frag, pull_len); 452 skb->data_len -= pull_len; 453 skb->tail += pull_len; 454 } 455 456 /** 457 * wx_cleanup_headers - Correct corrupted or empty headers 458 * @rx_ring: rx descriptor ring packet is being transacted on 459 * @rx_desc: pointer to the EOP Rx descriptor 460 * @skb: pointer to current skb being fixed 461 * 462 * Check for corrupted packet headers caused by senders on the local L2 463 * embedded NIC switch not setting up their Tx Descriptors right. These 464 * should be very rare. 465 * 466 * Also address the case where we are pulling data in on pages only 467 * and as such no data is present in the skb header. 468 * 469 * In addition if skb is not at least 60 bytes we need to pad it so that 470 * it is large enough to qualify as a valid Ethernet frame. 471 * 472 * Returns true if an error was encountered and skb was freed. 473 **/ 474 static bool wx_cleanup_headers(struct wx_ring *rx_ring, 475 union wx_rx_desc *rx_desc, 476 struct sk_buff *skb) 477 { 478 struct net_device *netdev = rx_ring->netdev; 479 480 /* verify that the packet does not have any known errors */ 481 if (!netdev || 482 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) && 483 !(netdev->features & NETIF_F_RXALL))) { 484 dev_kfree_skb_any(skb); 485 return true; 486 } 487 488 /* place header in linear portion of buffer */ 489 if (!skb_headlen(skb)) 490 wx_pull_tail(skb); 491 492 /* if eth_skb_pad returns an error the skb was freed */ 493 if (eth_skb_pad(skb)) 494 return true; 495 496 return false; 497 } 498 499 static void wx_rx_hash(struct wx_ring *ring, 500 union wx_rx_desc *rx_desc, 501 struct sk_buff *skb) 502 { 503 u16 rss_type; 504 505 if (!(ring->netdev->features & NETIF_F_RXHASH)) 506 return; 507 508 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 509 WX_RXD_RSSTYPE_MASK; 510 511 if (!rss_type) 512 return; 513 514 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 515 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 516 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 517 } 518 519 /** 520 * wx_rx_checksum - indicate in skb if hw indicated a good cksum 521 * @ring: structure containing ring specific data 522 * @rx_desc: current Rx descriptor being processed 523 * @skb: skb currently being received and modified 524 **/ 525 static void wx_rx_checksum(struct wx_ring *ring, 526 union wx_rx_desc *rx_desc, 527 struct sk_buff *skb) 528 { 529 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc)); 530 531 skb_checksum_none_assert(skb); 532 /* Rx csum disabled */ 533 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 534 return; 535 536 /* if IPv4 header checksum error */ 537 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) && 538 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) || 539 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) && 540 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) { 541 ring->rx_stats.csum_err++; 542 return; 543 } 544 545 /* L4 checksum offload flag must set for the below code to work */ 546 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS)) 547 return; 548 549 /* Hardware can't guarantee csum if IPv6 Dest Header found */ 550 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && 551 wx_test_staterr(rx_desc, WX_RXD_STAT_IPV6EX)) 552 return; 553 554 /* if L4 checksum error */ 555 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) { 556 ring->rx_stats.csum_err++; 557 return; 558 } 559 560 /* It must be a TCP or UDP or SCTP packet with a valid checksum */ 561 skb->ip_summed = CHECKSUM_UNNECESSARY; 562 563 /* If there is an outer header present that might contain a checksum 564 * we need to bump the checksum level by 1 to reflect the fact that 565 * we are indicating we validated the inner checksum. 566 */ 567 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG) 568 __skb_incr_checksum_unnecessary(skb); 569 ring->rx_stats.csum_good_cnt++; 570 } 571 572 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc, 573 struct sk_buff *skb) 574 { 575 u16 ethertype; 576 u8 idx = 0; 577 578 if ((ring->netdev->features & 579 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) && 580 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) { 581 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 582 0x1c0) >> 6; 583 ethertype = ring->q_vector->wx->tpid[idx]; 584 __vlan_hwaccel_put_tag(skb, htons(ethertype), 585 le16_to_cpu(rx_desc->wb.upper.vlan)); 586 } 587 } 588 589 /** 590 * wx_process_skb_fields - Populate skb header fields from Rx descriptor 591 * @rx_ring: rx descriptor ring packet is being transacted on 592 * @rx_desc: pointer to the EOP Rx descriptor 593 * @skb: pointer to current skb being populated 594 * 595 * This function checks the ring, descriptor, and packet information in 596 * order to populate the hash, checksum, protocol, and 597 * other fields within the skb. 598 **/ 599 static void wx_process_skb_fields(struct wx_ring *rx_ring, 600 union wx_rx_desc *rx_desc, 601 struct sk_buff *skb) 602 { 603 struct wx *wx = netdev_priv(rx_ring->netdev); 604 605 wx_rx_hash(rx_ring, rx_desc, skb); 606 wx_rx_checksum(rx_ring, rx_desc, skb); 607 608 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, wx->flags)) && 609 unlikely(wx_test_staterr(rx_desc, WX_RXD_STAT_TS))) { 610 wx_ptp_rx_hwtstamp(rx_ring->q_vector->wx, skb); 611 rx_ring->last_rx_timestamp = jiffies; 612 } 613 614 wx_rx_vlan(rx_ring, rx_desc, skb); 615 skb_record_rx_queue(skb, rx_ring->queue_index); 616 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 617 } 618 619 /** 620 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 621 * @q_vector: structure containing interrupt and ring information 622 * @rx_ring: rx descriptor ring to transact packets on 623 * @budget: Total limit on number of packets to process 624 * 625 * This function provides a "bounce buffer" approach to Rx interrupt 626 * processing. The advantage to this is that on systems that have 627 * expensive overhead for IOMMU access this provides a means of avoiding 628 * it by maintaining the mapping of the page to the system. 629 * 630 * Returns amount of work completed. 631 **/ 632 static int wx_clean_rx_irq(struct wx_q_vector *q_vector, 633 struct wx_ring *rx_ring, 634 int budget) 635 { 636 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 637 u16 cleaned_count = wx_desc_unused(rx_ring); 638 639 do { 640 struct wx_rx_buffer *rx_buffer; 641 union wx_rx_desc *rx_desc; 642 struct sk_buff *skb; 643 int rx_buffer_pgcnt; 644 645 /* return some buffers to hardware, one at a time is too slow */ 646 if (cleaned_count >= WX_RX_BUFFER_WRITE) { 647 wx_alloc_rx_buffers(rx_ring, cleaned_count); 648 cleaned_count = 0; 649 } 650 651 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean); 652 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD)) 653 break; 654 655 /* This memory barrier is needed to keep us from reading 656 * any other fields out of the rx_desc until we know the 657 * descriptor has been written back 658 */ 659 dma_rmb(); 660 661 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt); 662 663 /* retrieve a buffer from the ring */ 664 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc); 665 666 /* exit if we failed to retrieve a buffer */ 667 if (!skb) { 668 rx_ring->rx_stats.alloc_rx_buff_failed++; 669 break; 670 } 671 672 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 673 cleaned_count++; 674 675 /* place incomplete frames back on ring for completion */ 676 if (wx_is_non_eop(rx_ring, rx_desc, skb)) 677 continue; 678 679 /* verify the packet layout is correct */ 680 if (wx_cleanup_headers(rx_ring, rx_desc, skb)) 681 continue; 682 683 /* probably a little skewed due to removing CRC */ 684 total_rx_bytes += skb->len; 685 686 /* populate checksum, timestamp, VLAN, and protocol */ 687 wx_process_skb_fields(rx_ring, rx_desc, skb); 688 napi_gro_receive(&q_vector->napi, skb); 689 690 /* update budget accounting */ 691 total_rx_packets++; 692 } while (likely(total_rx_packets < budget)); 693 694 u64_stats_update_begin(&rx_ring->syncp); 695 rx_ring->stats.packets += total_rx_packets; 696 rx_ring->stats.bytes += total_rx_bytes; 697 u64_stats_update_end(&rx_ring->syncp); 698 q_vector->rx.total_packets += total_rx_packets; 699 q_vector->rx.total_bytes += total_rx_bytes; 700 701 return total_rx_packets; 702 } 703 704 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring) 705 { 706 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 707 } 708 709 /** 710 * wx_clean_tx_irq - Reclaim resources after transmit completes 711 * @q_vector: structure containing interrupt and ring information 712 * @tx_ring: tx ring to clean 713 * @napi_budget: Used to determine if we are in netpoll 714 **/ 715 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector, 716 struct wx_ring *tx_ring, int napi_budget) 717 { 718 unsigned int budget = q_vector->wx->tx_work_limit; 719 unsigned int total_bytes = 0, total_packets = 0; 720 struct wx *wx = netdev_priv(tx_ring->netdev); 721 unsigned int i = tx_ring->next_to_clean; 722 struct wx_tx_buffer *tx_buffer; 723 union wx_tx_desc *tx_desc; 724 725 if (!netif_carrier_ok(tx_ring->netdev)) 726 return true; 727 728 tx_buffer = &tx_ring->tx_buffer_info[i]; 729 tx_desc = WX_TX_DESC(tx_ring, i); 730 i -= tx_ring->count; 731 732 do { 733 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch; 734 735 /* if next_to_watch is not set then there is no work pending */ 736 if (!eop_desc) 737 break; 738 739 /* prevent any other reads prior to eop_desc */ 740 smp_rmb(); 741 742 /* if DD is not set pending work has not been completed */ 743 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) 744 break; 745 746 /* clear next_to_watch to prevent false hangs */ 747 tx_buffer->next_to_watch = NULL; 748 749 /* update the statistics for this packet */ 750 total_bytes += tx_buffer->bytecount; 751 total_packets += tx_buffer->gso_segs; 752 753 /* schedule check for Tx timestamp */ 754 if (unlikely(test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state)) && 755 skb_shinfo(tx_buffer->skb)->tx_flags & SKBTX_IN_PROGRESS) 756 ptp_schedule_worker(wx->ptp_clock, 0); 757 758 /* free the skb */ 759 napi_consume_skb(tx_buffer->skb, napi_budget); 760 761 /* unmap skb header data */ 762 dma_unmap_single(tx_ring->dev, 763 dma_unmap_addr(tx_buffer, dma), 764 dma_unmap_len(tx_buffer, len), 765 DMA_TO_DEVICE); 766 767 /* clear tx_buffer data */ 768 dma_unmap_len_set(tx_buffer, len, 0); 769 770 /* unmap remaining buffers */ 771 while (tx_desc != eop_desc) { 772 tx_buffer++; 773 tx_desc++; 774 i++; 775 if (unlikely(!i)) { 776 i -= tx_ring->count; 777 tx_buffer = tx_ring->tx_buffer_info; 778 tx_desc = WX_TX_DESC(tx_ring, 0); 779 } 780 781 /* unmap any remaining paged data */ 782 if (dma_unmap_len(tx_buffer, len)) { 783 dma_unmap_page(tx_ring->dev, 784 dma_unmap_addr(tx_buffer, dma), 785 dma_unmap_len(tx_buffer, len), 786 DMA_TO_DEVICE); 787 dma_unmap_len_set(tx_buffer, len, 0); 788 } 789 } 790 791 /* move us one more past the eop_desc for start of next pkt */ 792 tx_buffer++; 793 tx_desc++; 794 i++; 795 if (unlikely(!i)) { 796 i -= tx_ring->count; 797 tx_buffer = tx_ring->tx_buffer_info; 798 tx_desc = WX_TX_DESC(tx_ring, 0); 799 } 800 801 /* issue prefetch for next Tx descriptor */ 802 prefetch(tx_desc); 803 804 /* update budget accounting */ 805 budget--; 806 } while (likely(budget)); 807 808 i += tx_ring->count; 809 tx_ring->next_to_clean = i; 810 u64_stats_update_begin(&tx_ring->syncp); 811 tx_ring->stats.bytes += total_bytes; 812 tx_ring->stats.packets += total_packets; 813 u64_stats_update_end(&tx_ring->syncp); 814 q_vector->tx.total_bytes += total_bytes; 815 q_vector->tx.total_packets += total_packets; 816 817 netdev_tx_completed_queue(wx_txring_txq(tx_ring), 818 total_packets, total_bytes); 819 820 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 821 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 822 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 823 /* Make sure that anybody stopping the queue after this 824 * sees the new next_to_clean. 825 */ 826 smp_mb(); 827 828 if (__netif_subqueue_stopped(tx_ring->netdev, 829 tx_ring->queue_index) && 830 netif_running(tx_ring->netdev)) { 831 netif_wake_subqueue(tx_ring->netdev, 832 tx_ring->queue_index); 833 ++tx_ring->tx_stats.restart_queue; 834 } 835 } 836 837 return !!budget; 838 } 839 840 /** 841 * wx_poll - NAPI polling RX/TX cleanup routine 842 * @napi: napi struct with our devices info in it 843 * @budget: amount of work driver is allowed to do this pass, in packets 844 * 845 * This function will clean all queues associated with a q_vector. 846 **/ 847 static int wx_poll(struct napi_struct *napi, int budget) 848 { 849 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi); 850 int per_ring_budget, work_done = 0; 851 struct wx *wx = q_vector->wx; 852 bool clean_complete = true; 853 struct wx_ring *ring; 854 855 wx_for_each_ring(ring, q_vector->tx) { 856 if (!wx_clean_tx_irq(q_vector, ring, budget)) 857 clean_complete = false; 858 } 859 860 /* Exit if we are called by netpoll */ 861 if (budget <= 0) 862 return budget; 863 864 /* attempt to distribute budget to each queue fairly, but don't allow 865 * the budget to go below 1 because we'll exit polling 866 */ 867 if (q_vector->rx.count > 1) 868 per_ring_budget = max(budget / q_vector->rx.count, 1); 869 else 870 per_ring_budget = budget; 871 872 wx_for_each_ring(ring, q_vector->rx) { 873 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget); 874 875 work_done += cleaned; 876 if (cleaned >= per_ring_budget) 877 clean_complete = false; 878 } 879 880 /* If all work not completed, return budget and keep polling */ 881 if (!clean_complete) 882 return budget; 883 884 /* all work done, exit the polling mode */ 885 if (likely(napi_complete_done(napi, work_done))) { 886 if (netif_running(wx->netdev)) 887 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx)); 888 } 889 890 return min(work_done, budget - 1); 891 } 892 893 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size) 894 { 895 if (likely(wx_desc_unused(tx_ring) >= size)) 896 return 0; 897 898 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 899 900 /* For the next check */ 901 smp_mb(); 902 903 /* We need to check again in a case another CPU has just 904 * made room available. 905 */ 906 if (likely(wx_desc_unused(tx_ring) < size)) 907 return -EBUSY; 908 909 /* A reprieve! - use start_queue because it doesn't call schedule */ 910 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 911 ++tx_ring->tx_stats.restart_queue; 912 913 return 0; 914 } 915 916 static u32 wx_tx_cmd_type(u32 tx_flags) 917 { 918 /* set type for advanced descriptor with frame checksum insertion */ 919 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS; 920 921 /* set HW vlan bit if vlan is present */ 922 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE); 923 /* set segmentation enable bits for TSO/FSO */ 924 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE); 925 /* set timestamp bit if present */ 926 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP); 927 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC); 928 929 return cmd_type; 930 } 931 932 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc, 933 u32 tx_flags, unsigned int paylen) 934 { 935 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT; 936 937 /* enable L4 checksum for TSO and TX checksum offload */ 938 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS); 939 /* enable IPv4 checksum for TSO */ 940 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS); 941 /* enable outer IPv4 checksum for TSO */ 942 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4, 943 WX_TXD_EIPCS); 944 /* Check Context must be set if Tx switch is enabled, which it 945 * always is for case where virtual functions are running 946 */ 947 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC); 948 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC, 949 WX_TXD_IPSEC); 950 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 951 } 952 953 static int wx_tx_map(struct wx_ring *tx_ring, 954 struct wx_tx_buffer *first, 955 const u8 hdr_len) 956 { 957 struct sk_buff *skb = first->skb; 958 struct wx_tx_buffer *tx_buffer; 959 u32 tx_flags = first->tx_flags; 960 u16 i = tx_ring->next_to_use; 961 unsigned int data_len, size; 962 union wx_tx_desc *tx_desc; 963 skb_frag_t *frag; 964 dma_addr_t dma; 965 u32 cmd_type; 966 967 cmd_type = wx_tx_cmd_type(tx_flags); 968 tx_desc = WX_TX_DESC(tx_ring, i); 969 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 970 971 size = skb_headlen(skb); 972 data_len = skb->data_len; 973 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 974 975 tx_buffer = first; 976 977 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 978 if (dma_mapping_error(tx_ring->dev, dma)) 979 goto dma_error; 980 981 /* record length, and DMA address */ 982 dma_unmap_len_set(tx_buffer, len, size); 983 dma_unmap_addr_set(tx_buffer, dma, dma); 984 985 tx_desc->read.buffer_addr = cpu_to_le64(dma); 986 987 while (unlikely(size > WX_MAX_DATA_PER_TXD)) { 988 tx_desc->read.cmd_type_len = 989 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD); 990 991 i++; 992 tx_desc++; 993 if (i == tx_ring->count) { 994 tx_desc = WX_TX_DESC(tx_ring, 0); 995 i = 0; 996 } 997 tx_desc->read.olinfo_status = 0; 998 999 dma += WX_MAX_DATA_PER_TXD; 1000 size -= WX_MAX_DATA_PER_TXD; 1001 1002 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1003 } 1004 1005 if (likely(!data_len)) 1006 break; 1007 1008 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 1009 1010 i++; 1011 tx_desc++; 1012 if (i == tx_ring->count) { 1013 tx_desc = WX_TX_DESC(tx_ring, 0); 1014 i = 0; 1015 } 1016 tx_desc->read.olinfo_status = 0; 1017 1018 size = skb_frag_size(frag); 1019 1020 data_len -= size; 1021 1022 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1023 DMA_TO_DEVICE); 1024 1025 tx_buffer = &tx_ring->tx_buffer_info[i]; 1026 } 1027 1028 /* write last descriptor with RS and EOP bits */ 1029 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS; 1030 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1031 1032 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount); 1033 1034 /* set the timestamp */ 1035 first->time_stamp = jiffies; 1036 skb_tx_timestamp(skb); 1037 1038 /* Force memory writes to complete before letting h/w know there 1039 * are new descriptors to fetch. (Only applicable for weak-ordered 1040 * memory model archs, such as IA-64). 1041 * 1042 * We also need this memory barrier to make certain all of the 1043 * status bits have been updated before next_to_watch is written. 1044 */ 1045 wmb(); 1046 1047 /* set next_to_watch value indicating a packet is present */ 1048 first->next_to_watch = tx_desc; 1049 1050 i++; 1051 if (i == tx_ring->count) 1052 i = 0; 1053 1054 tx_ring->next_to_use = i; 1055 1056 wx_maybe_stop_tx(tx_ring, DESC_NEEDED); 1057 1058 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more()) 1059 writel(i, tx_ring->tail); 1060 1061 return 0; 1062 dma_error: 1063 dev_err(tx_ring->dev, "TX DMA map failed\n"); 1064 1065 /* clear dma mappings for failed tx_buffer_info map */ 1066 for (;;) { 1067 tx_buffer = &tx_ring->tx_buffer_info[i]; 1068 if (dma_unmap_len(tx_buffer, len)) 1069 dma_unmap_page(tx_ring->dev, 1070 dma_unmap_addr(tx_buffer, dma), 1071 dma_unmap_len(tx_buffer, len), 1072 DMA_TO_DEVICE); 1073 dma_unmap_len_set(tx_buffer, len, 0); 1074 if (tx_buffer == first) 1075 break; 1076 if (i == 0) 1077 i += tx_ring->count; 1078 i--; 1079 } 1080 1081 dev_kfree_skb_any(first->skb); 1082 first->skb = NULL; 1083 1084 tx_ring->next_to_use = i; 1085 1086 return -ENOMEM; 1087 } 1088 1089 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens, 1090 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1091 { 1092 struct wx_tx_context_desc *context_desc; 1093 u16 i = tx_ring->next_to_use; 1094 1095 context_desc = WX_TX_CTXTDESC(tx_ring, i); 1096 i++; 1097 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1098 1099 /* set bits to identify this as an advanced context descriptor */ 1100 type_tucmd |= WX_TXD_DTYP_CTXT; 1101 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1102 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1103 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1104 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1105 } 1106 1107 union network_header { 1108 struct iphdr *ipv4; 1109 struct ipv6hdr *ipv6; 1110 void *raw; 1111 }; 1112 1113 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first) 1114 { 1115 u8 tun_prot = 0, l4_prot = 0, ptype = 0; 1116 struct sk_buff *skb = first->skb; 1117 unsigned char *exthdr, *l4_hdr; 1118 __be16 frag_off; 1119 1120 if (skb->encapsulation) { 1121 union network_header hdr; 1122 1123 switch (first->protocol) { 1124 case htons(ETH_P_IP): 1125 tun_prot = ip_hdr(skb)->protocol; 1126 ptype = WX_PTYPE_TUN_IPV4; 1127 break; 1128 case htons(ETH_P_IPV6): 1129 l4_hdr = skb_transport_header(skb); 1130 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1131 tun_prot = ipv6_hdr(skb)->nexthdr; 1132 if (l4_hdr != exthdr) 1133 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off); 1134 ptype = WX_PTYPE_TUN_IPV6; 1135 break; 1136 default: 1137 return ptype; 1138 } 1139 1140 if (tun_prot == IPPROTO_IPIP || tun_prot == IPPROTO_IPV6) { 1141 hdr.raw = (void *)inner_ip_hdr(skb); 1142 ptype |= WX_PTYPE_PKT_IPIP; 1143 } else if (tun_prot == IPPROTO_UDP) { 1144 hdr.raw = (void *)inner_ip_hdr(skb); 1145 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1146 skb->inner_protocol != htons(ETH_P_TEB)) { 1147 ptype |= WX_PTYPE_PKT_IG; 1148 } else { 1149 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1150 == htons(ETH_P_8021Q)) 1151 ptype |= WX_PTYPE_PKT_IGMV; 1152 else 1153 ptype |= WX_PTYPE_PKT_IGM; 1154 } 1155 1156 } else if (tun_prot == IPPROTO_GRE) { 1157 hdr.raw = (void *)inner_ip_hdr(skb); 1158 if (skb->inner_protocol == htons(ETH_P_IP) || 1159 skb->inner_protocol == htons(ETH_P_IPV6)) { 1160 ptype |= WX_PTYPE_PKT_IG; 1161 } else { 1162 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1163 == htons(ETH_P_8021Q)) 1164 ptype |= WX_PTYPE_PKT_IGMV; 1165 else 1166 ptype |= WX_PTYPE_PKT_IGM; 1167 } 1168 } else { 1169 return ptype; 1170 } 1171 1172 switch (hdr.ipv4->version) { 1173 case IPVERSION: 1174 l4_prot = hdr.ipv4->protocol; 1175 break; 1176 case 6: 1177 l4_hdr = skb_inner_transport_header(skb); 1178 exthdr = skb_inner_network_header(skb) + sizeof(struct ipv6hdr); 1179 l4_prot = inner_ipv6_hdr(skb)->nexthdr; 1180 if (l4_hdr != exthdr) 1181 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1182 ptype |= WX_PTYPE_PKT_IPV6; 1183 break; 1184 default: 1185 return ptype; 1186 } 1187 } else { 1188 switch (first->protocol) { 1189 case htons(ETH_P_IP): 1190 l4_prot = ip_hdr(skb)->protocol; 1191 ptype = WX_PTYPE_PKT_IP; 1192 break; 1193 case htons(ETH_P_IPV6): 1194 l4_hdr = skb_transport_header(skb); 1195 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1196 l4_prot = ipv6_hdr(skb)->nexthdr; 1197 if (l4_hdr != exthdr) 1198 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1199 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6; 1200 break; 1201 default: 1202 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC; 1203 } 1204 } 1205 switch (l4_prot) { 1206 case IPPROTO_TCP: 1207 ptype |= WX_PTYPE_TYP_TCP; 1208 break; 1209 case IPPROTO_UDP: 1210 ptype |= WX_PTYPE_TYP_UDP; 1211 break; 1212 case IPPROTO_SCTP: 1213 ptype |= WX_PTYPE_TYP_SCTP; 1214 break; 1215 default: 1216 ptype |= WX_PTYPE_TYP_IP; 1217 break; 1218 } 1219 1220 return ptype; 1221 } 1222 1223 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1224 u8 *hdr_len, u8 ptype) 1225 { 1226 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1227 struct net_device *netdev = tx_ring->netdev; 1228 u32 l4len, tunhdr_eiplen_tunlen = 0; 1229 struct sk_buff *skb = first->skb; 1230 bool enc = skb->encapsulation; 1231 struct ipv6hdr *ipv6h; 1232 struct tcphdr *tcph; 1233 struct iphdr *iph; 1234 u8 tun_prot = 0; 1235 int err; 1236 1237 if (skb->ip_summed != CHECKSUM_PARTIAL) 1238 return 0; 1239 1240 if (!skb_is_gso(skb)) 1241 return 0; 1242 1243 err = skb_cow_head(skb, 0); 1244 if (err < 0) 1245 return err; 1246 1247 /* indicates the inner headers in the skbuff are valid. */ 1248 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb); 1249 if (iph->version == 4) { 1250 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1251 iph->tot_len = 0; 1252 iph->check = 0; 1253 tcph->check = ~csum_tcpudp_magic(iph->saddr, 1254 iph->daddr, 0, 1255 IPPROTO_TCP, 0); 1256 first->tx_flags |= WX_TX_FLAGS_TSO | 1257 WX_TX_FLAGS_CSUM | 1258 WX_TX_FLAGS_IPV4 | 1259 WX_TX_FLAGS_CC; 1260 } else if (iph->version == 6 && skb_is_gso_v6(skb)) { 1261 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 1262 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1263 ipv6h->payload_len = 0; 1264 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, 1265 &ipv6h->daddr, 0, 1266 IPPROTO_TCP, 0); 1267 first->tx_flags |= WX_TX_FLAGS_TSO | 1268 WX_TX_FLAGS_CSUM | 1269 WX_TX_FLAGS_CC; 1270 } 1271 1272 /* compute header lengths */ 1273 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 1274 *hdr_len = enc ? skb_inner_transport_offset(skb) : 1275 skb_transport_offset(skb); 1276 *hdr_len += l4len; 1277 1278 /* update gso size and bytecount with header size */ 1279 first->gso_segs = skb_shinfo(skb)->gso_segs; 1280 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1281 1282 /* mss_l4len_id: use 0 as index for TSO */ 1283 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT; 1284 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT; 1285 1286 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 1287 if (enc) { 1288 unsigned char *exthdr, *l4_hdr; 1289 __be16 frag_off; 1290 1291 switch (first->protocol) { 1292 case htons(ETH_P_IP): 1293 tun_prot = ip_hdr(skb)->protocol; 1294 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4; 1295 break; 1296 case htons(ETH_P_IPV6): 1297 l4_hdr = skb_transport_header(skb); 1298 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1299 tun_prot = ipv6_hdr(skb)->nexthdr; 1300 if (l4_hdr != exthdr) 1301 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off); 1302 break; 1303 default: 1304 break; 1305 } 1306 switch (tun_prot) { 1307 case IPPROTO_UDP: 1308 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1309 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1310 WX_TXD_OUTER_IPLEN_SHIFT) | 1311 (((skb_inner_mac_header(skb) - 1312 skb_transport_header(skb)) >> 1) << 1313 WX_TXD_TUNNEL_LEN_SHIFT); 1314 break; 1315 case IPPROTO_GRE: 1316 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1317 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1318 WX_TXD_OUTER_IPLEN_SHIFT) | 1319 (((skb_inner_mac_header(skb) - 1320 skb_transport_header(skb)) >> 1) << 1321 WX_TXD_TUNNEL_LEN_SHIFT); 1322 break; 1323 case IPPROTO_IPIP: 1324 case IPPROTO_IPV6: 1325 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1326 (char *)ip_hdr(skb)) >> 2) << 1327 WX_TXD_OUTER_IPLEN_SHIFT; 1328 break; 1329 default: 1330 break; 1331 } 1332 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1; 1333 } else { 1334 vlan_macip_lens = skb_network_header_len(skb) >> 1; 1335 } 1336 1337 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT; 1338 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1339 1340 type_tucmd = ptype << 24; 1341 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1342 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1343 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1344 WX_TX_FLAGS_HW_VLAN, 1345 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1346 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1347 type_tucmd, mss_l4len_idx); 1348 1349 return 1; 1350 } 1351 1352 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1353 u8 ptype) 1354 { 1355 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0; 1356 struct net_device *netdev = tx_ring->netdev; 1357 u32 mss_l4len_idx = 0, type_tucmd; 1358 struct sk_buff *skb = first->skb; 1359 u8 tun_prot = 0; 1360 1361 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1362 csum_failed: 1363 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) && 1364 !(first->tx_flags & WX_TX_FLAGS_CC)) 1365 return; 1366 vlan_macip_lens = skb_network_offset(skb) << 1367 WX_TXD_MACLEN_SHIFT; 1368 } else { 1369 unsigned char *exthdr, *l4_hdr; 1370 __be16 frag_off; 1371 u8 l4_prot = 0; 1372 union { 1373 struct iphdr *ipv4; 1374 struct ipv6hdr *ipv6; 1375 u8 *raw; 1376 } network_hdr; 1377 union { 1378 struct tcphdr *tcphdr; 1379 u8 *raw; 1380 } transport_hdr; 1381 1382 if (skb->encapsulation) { 1383 network_hdr.raw = skb_inner_network_header(skb); 1384 transport_hdr.raw = skb_inner_transport_header(skb); 1385 vlan_macip_lens = skb_network_offset(skb) << 1386 WX_TXD_MACLEN_SHIFT; 1387 switch (first->protocol) { 1388 case htons(ETH_P_IP): 1389 tun_prot = ip_hdr(skb)->protocol; 1390 break; 1391 case htons(ETH_P_IPV6): 1392 l4_hdr = skb_transport_header(skb); 1393 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1394 tun_prot = ipv6_hdr(skb)->nexthdr; 1395 if (l4_hdr != exthdr) 1396 ipv6_skip_exthdr(skb, exthdr - skb->data, 1397 &tun_prot, &frag_off); 1398 break; 1399 default: 1400 return; 1401 } 1402 switch (tun_prot) { 1403 case IPPROTO_UDP: 1404 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1405 tunhdr_eiplen_tunlen |= 1406 ((skb_network_header_len(skb) >> 2) << 1407 WX_TXD_OUTER_IPLEN_SHIFT) | 1408 (((skb_inner_mac_header(skb) - 1409 skb_transport_header(skb)) >> 1) << 1410 WX_TXD_TUNNEL_LEN_SHIFT); 1411 break; 1412 case IPPROTO_GRE: 1413 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1414 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1415 WX_TXD_OUTER_IPLEN_SHIFT) | 1416 (((skb_inner_mac_header(skb) - 1417 skb_transport_header(skb)) >> 1) << 1418 WX_TXD_TUNNEL_LEN_SHIFT); 1419 break; 1420 case IPPROTO_IPIP: 1421 case IPPROTO_IPV6: 1422 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1423 (char *)ip_hdr(skb)) >> 2) << 1424 WX_TXD_OUTER_IPLEN_SHIFT; 1425 break; 1426 default: 1427 break; 1428 } 1429 1430 } else { 1431 network_hdr.raw = skb_network_header(skb); 1432 transport_hdr.raw = skb_transport_header(skb); 1433 vlan_macip_lens = skb_network_offset(skb) << 1434 WX_TXD_MACLEN_SHIFT; 1435 } 1436 1437 switch (network_hdr.ipv4->version) { 1438 case IPVERSION: 1439 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1440 l4_prot = network_hdr.ipv4->protocol; 1441 break; 1442 case 6: 1443 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1444 exthdr = network_hdr.raw + sizeof(struct ipv6hdr); 1445 l4_prot = network_hdr.ipv6->nexthdr; 1446 if (transport_hdr.raw != exthdr) 1447 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1448 break; 1449 default: 1450 break; 1451 } 1452 1453 switch (l4_prot) { 1454 case IPPROTO_TCP: 1455 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 1456 WX_TXD_L4LEN_SHIFT; 1457 break; 1458 case IPPROTO_SCTP: 1459 mss_l4len_idx = sizeof(struct sctphdr) << 1460 WX_TXD_L4LEN_SHIFT; 1461 break; 1462 case IPPROTO_UDP: 1463 mss_l4len_idx = sizeof(struct udphdr) << 1464 WX_TXD_L4LEN_SHIFT; 1465 break; 1466 default: 1467 skb_checksum_help(skb); 1468 goto csum_failed; 1469 } 1470 1471 /* update TX checksum flag */ 1472 first->tx_flags |= WX_TX_FLAGS_CSUM; 1473 } 1474 first->tx_flags |= WX_TX_FLAGS_CC; 1475 /* vlan_macip_lens: MACLEN, VLAN tag */ 1476 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1477 1478 type_tucmd = ptype << 24; 1479 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1480 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1481 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1482 WX_TX_FLAGS_HW_VLAN, 1483 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1484 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1485 type_tucmd, mss_l4len_idx); 1486 } 1487 1488 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb, 1489 struct wx_ring *tx_ring) 1490 { 1491 struct wx *wx = netdev_priv(tx_ring->netdev); 1492 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1493 struct wx_tx_buffer *first; 1494 u8 hdr_len = 0, ptype; 1495 unsigned short f; 1496 u32 tx_flags = 0; 1497 int tso; 1498 1499 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD, 1500 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD, 1501 * + 2 desc gap to keep tail from touching head, 1502 * + 1 desc for context descriptor, 1503 * otherwise try next time 1504 */ 1505 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1506 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)-> 1507 frags[f])); 1508 1509 if (wx_maybe_stop_tx(tx_ring, count + 3)) { 1510 tx_ring->tx_stats.tx_busy++; 1511 return NETDEV_TX_BUSY; 1512 } 1513 1514 /* record the location of the first descriptor for this packet */ 1515 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1516 first->skb = skb; 1517 first->bytecount = skb->len; 1518 first->gso_segs = 1; 1519 1520 /* if we have a HW VLAN tag being added default to the HW one */ 1521 if (skb_vlan_tag_present(skb)) { 1522 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT; 1523 tx_flags |= WX_TX_FLAGS_HW_VLAN; 1524 } 1525 1526 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1527 wx->ptp_clock) { 1528 if (wx->tstamp_config.tx_type == HWTSTAMP_TX_ON && 1529 !test_and_set_bit_lock(WX_STATE_PTP_TX_IN_PROGRESS, 1530 wx->state)) { 1531 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1532 tx_flags |= WX_TX_FLAGS_TSTAMP; 1533 wx->ptp_tx_skb = skb_get(skb); 1534 wx->ptp_tx_start = jiffies; 1535 } else { 1536 wx->tx_hwtstamp_skipped++; 1537 } 1538 } 1539 1540 /* record initial flags and protocol */ 1541 first->tx_flags = tx_flags; 1542 first->protocol = vlan_get_protocol(skb); 1543 1544 ptype = wx_encode_tx_desc_ptype(first); 1545 1546 tso = wx_tso(tx_ring, first, &hdr_len, ptype); 1547 if (tso < 0) 1548 goto out_drop; 1549 else if (!tso) 1550 wx_tx_csum(tx_ring, first, ptype); 1551 1552 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate) 1553 wx->atr(tx_ring, first, ptype); 1554 1555 if (wx_tx_map(tx_ring, first, hdr_len)) 1556 goto cleanup_tx_tstamp; 1557 1558 return NETDEV_TX_OK; 1559 out_drop: 1560 dev_kfree_skb_any(first->skb); 1561 first->skb = NULL; 1562 cleanup_tx_tstamp: 1563 if (unlikely(tx_flags & WX_TX_FLAGS_TSTAMP)) { 1564 dev_kfree_skb_any(wx->ptp_tx_skb); 1565 wx->ptp_tx_skb = NULL; 1566 wx->tx_hwtstamp_errors++; 1567 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 1568 } 1569 1570 return NETDEV_TX_OK; 1571 } 1572 1573 netdev_tx_t wx_xmit_frame(struct sk_buff *skb, 1574 struct net_device *netdev) 1575 { 1576 unsigned int r_idx = skb->queue_mapping; 1577 struct wx *wx = netdev_priv(netdev); 1578 struct wx_ring *tx_ring; 1579 1580 if (!netif_carrier_ok(netdev)) { 1581 dev_kfree_skb_any(skb); 1582 return NETDEV_TX_OK; 1583 } 1584 1585 /* The minimum packet size for olinfo paylen is 17 so pad the skb 1586 * in order to meet this minimum size requirement. 1587 */ 1588 if (skb_put_padto(skb, 17)) 1589 return NETDEV_TX_OK; 1590 1591 if (r_idx >= wx->num_tx_queues) 1592 r_idx = r_idx % wx->num_tx_queues; 1593 tx_ring = wx->tx_ring[r_idx]; 1594 1595 return wx_xmit_frame_ring(skb, tx_ring); 1596 } 1597 EXPORT_SYMBOL(wx_xmit_frame); 1598 1599 void wx_napi_enable_all(struct wx *wx) 1600 { 1601 struct wx_q_vector *q_vector; 1602 int q_idx; 1603 1604 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1605 q_vector = wx->q_vector[q_idx]; 1606 napi_enable(&q_vector->napi); 1607 } 1608 } 1609 EXPORT_SYMBOL(wx_napi_enable_all); 1610 1611 void wx_napi_disable_all(struct wx *wx) 1612 { 1613 struct wx_q_vector *q_vector; 1614 int q_idx; 1615 1616 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1617 q_vector = wx->q_vector[q_idx]; 1618 napi_disable(&q_vector->napi); 1619 } 1620 } 1621 EXPORT_SYMBOL(wx_napi_disable_all); 1622 1623 static bool wx_set_vmdq_queues(struct wx *wx) 1624 { 1625 u16 vmdq_i = wx->ring_feature[RING_F_VMDQ].limit; 1626 u16 rss_i = wx->ring_feature[RING_F_RSS].limit; 1627 u16 rss_m = WX_RSS_DISABLED_MASK; 1628 u16 vmdq_m = 0; 1629 1630 /* only proceed if VMDq is enabled */ 1631 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 1632 return false; 1633 /* Add starting offset to total pool count */ 1634 vmdq_i += wx->ring_feature[RING_F_VMDQ].offset; 1635 1636 if (wx->mac.type == wx_mac_sp) { 1637 /* double check we are limited to maximum pools */ 1638 vmdq_i = min_t(u16, 64, vmdq_i); 1639 1640 /* 64 pool mode with 2 queues per pool, or 1641 * 16/32/64 pool mode with 1 queue per pool 1642 */ 1643 if (vmdq_i > 32 || rss_i < 4) { 1644 vmdq_m = WX_VMDQ_2Q_MASK; 1645 rss_m = WX_RSS_2Q_MASK; 1646 rss_i = min_t(u16, rss_i, 2); 1647 /* 32 pool mode with 4 queues per pool */ 1648 } else { 1649 vmdq_m = WX_VMDQ_4Q_MASK; 1650 rss_m = WX_RSS_4Q_MASK; 1651 rss_i = 4; 1652 } 1653 } else { 1654 /* double check we are limited to maximum pools */ 1655 vmdq_i = min_t(u16, 8, vmdq_i); 1656 1657 /* when VMDQ on, disable RSS */ 1658 rss_i = 1; 1659 } 1660 1661 /* remove the starting offset from the pool count */ 1662 vmdq_i -= wx->ring_feature[RING_F_VMDQ].offset; 1663 1664 /* save features for later use */ 1665 wx->ring_feature[RING_F_VMDQ].indices = vmdq_i; 1666 wx->ring_feature[RING_F_VMDQ].mask = vmdq_m; 1667 1668 /* limit RSS based on user input and save for later use */ 1669 wx->ring_feature[RING_F_RSS].indices = rss_i; 1670 wx->ring_feature[RING_F_RSS].mask = rss_m; 1671 1672 wx->queues_per_pool = rss_i;/*maybe same to num_rx_queues_per_pool*/ 1673 wx->num_rx_pools = vmdq_i; 1674 wx->num_rx_queues_per_pool = rss_i; 1675 1676 wx->num_rx_queues = vmdq_i * rss_i; 1677 wx->num_tx_queues = vmdq_i * rss_i; 1678 1679 return true; 1680 } 1681 1682 /** 1683 * wx_set_rss_queues: Allocate queues for RSS 1684 * @wx: board private structure to initialize 1685 * 1686 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1687 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1688 * 1689 **/ 1690 static void wx_set_rss_queues(struct wx *wx) 1691 { 1692 struct wx_ring_feature *f; 1693 1694 /* set mask for 16 queue limit of RSS */ 1695 f = &wx->ring_feature[RING_F_RSS]; 1696 if (wx->mac.type == wx_mac_sp) 1697 f->mask = WX_RSS_64Q_MASK; 1698 else 1699 f->mask = WX_RSS_8Q_MASK; 1700 f->indices = f->limit; 1701 1702 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 1703 goto out; 1704 1705 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 1706 1707 /* Use Flow Director in addition to RSS to ensure the best 1708 * distribution of flows across cores, even when an FDIR flow 1709 * isn't matched. 1710 */ 1711 if (f->indices > 1) { 1712 f = &wx->ring_feature[RING_F_FDIR]; 1713 1714 f->indices = f->limit; 1715 1716 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 1717 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 1718 } 1719 1720 out: 1721 wx->num_rx_queues = f->indices; 1722 wx->num_tx_queues = f->indices; 1723 } 1724 1725 static void wx_set_num_queues(struct wx *wx) 1726 { 1727 /* Start with base case */ 1728 wx->num_rx_queues = 1; 1729 wx->num_tx_queues = 1; 1730 wx->queues_per_pool = 1; 1731 1732 if (wx_set_vmdq_queues(wx)) 1733 return; 1734 1735 wx_set_rss_queues(wx); 1736 } 1737 1738 /** 1739 * wx_acquire_msix_vectors - acquire MSI-X vectors 1740 * @wx: board private structure 1741 * 1742 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will 1743 * return a negative error code if unable to acquire MSI-X vectors for any 1744 * reason. 1745 */ 1746 static int wx_acquire_msix_vectors(struct wx *wx) 1747 { 1748 struct irq_affinity affd = { .pre_vectors = 1 }; 1749 int nvecs, i; 1750 1751 /* We start by asking for one vector per queue pair */ 1752 nvecs = max(wx->num_rx_queues, wx->num_tx_queues); 1753 nvecs = min_t(int, nvecs, num_online_cpus()); 1754 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors); 1755 1756 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry), 1757 GFP_KERNEL); 1758 if (!wx->msix_q_entries) 1759 return -ENOMEM; 1760 1761 /* One for non-queue interrupts */ 1762 nvecs += 1; 1763 1764 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry), 1765 GFP_KERNEL); 1766 if (!wx->msix_entry) { 1767 kfree(wx->msix_q_entries); 1768 wx->msix_q_entries = NULL; 1769 return -ENOMEM; 1770 } 1771 1772 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs, 1773 nvecs, 1774 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, 1775 &affd); 1776 if (nvecs < 0) { 1777 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs); 1778 kfree(wx->msix_q_entries); 1779 wx->msix_q_entries = NULL; 1780 kfree(wx->msix_entry); 1781 wx->msix_entry = NULL; 1782 return nvecs; 1783 } 1784 1785 wx->msix_entry->entry = 0; 1786 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0); 1787 nvecs -= 1; 1788 for (i = 0; i < nvecs; i++) { 1789 wx->msix_q_entries[i].entry = i; 1790 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i + 1); 1791 } 1792 1793 wx->num_q_vectors = nvecs; 1794 1795 return 0; 1796 } 1797 1798 /** 1799 * wx_set_interrupt_capability - set MSI-X or MSI if supported 1800 * @wx: board private structure to initialize 1801 * 1802 * Attempt to configure the interrupts using the best available 1803 * capabilities of the hardware and the kernel. 1804 **/ 1805 static int wx_set_interrupt_capability(struct wx *wx) 1806 { 1807 struct pci_dev *pdev = wx->pdev; 1808 int nvecs, ret; 1809 1810 /* We will try to get MSI-X interrupts first */ 1811 ret = wx_acquire_msix_vectors(wx); 1812 if (ret == 0 || (ret == -ENOMEM)) 1813 return ret; 1814 1815 /* Disable VMDq support */ 1816 dev_warn(&wx->pdev->dev, "Disabling VMQQ support\n"); 1817 clear_bit(WX_FLAG_VMDQ_ENABLED, wx->flags); 1818 1819 /* Disable RSS */ 1820 dev_warn(&wx->pdev->dev, "Disabling RSS support\n"); 1821 wx->ring_feature[RING_F_RSS].limit = 1; 1822 1823 wx_set_num_queues(wx); 1824 1825 /* minmum one for queue, one for misc*/ 1826 nvecs = 1; 1827 nvecs = pci_alloc_irq_vectors(pdev, nvecs, 1828 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX); 1829 if (nvecs == 1) { 1830 if (pdev->msi_enabled) 1831 wx_err(wx, "Fallback to MSI.\n"); 1832 else 1833 wx_err(wx, "Fallback to INTx.\n"); 1834 } else { 1835 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs); 1836 return nvecs; 1837 } 1838 1839 pdev->irq = pci_irq_vector(pdev, 0); 1840 wx->num_q_vectors = 1; 1841 1842 return 0; 1843 } 1844 1845 static bool wx_cache_ring_vmdq(struct wx *wx) 1846 { 1847 struct wx_ring_feature *vmdq = &wx->ring_feature[RING_F_VMDQ]; 1848 struct wx_ring_feature *rss = &wx->ring_feature[RING_F_RSS]; 1849 u16 reg_idx; 1850 int i; 1851 1852 /* only proceed if VMDq is enabled */ 1853 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 1854 return false; 1855 1856 if (wx->mac.type == wx_mac_sp) { 1857 /* start at VMDq register offset for SR-IOV enabled setups */ 1858 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 1859 for (i = 0; i < wx->num_rx_queues; i++, reg_idx++) { 1860 /* If we are greater than indices move to next pool */ 1861 if ((reg_idx & ~vmdq->mask) >= rss->indices) 1862 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 1863 wx->rx_ring[i]->reg_idx = reg_idx; 1864 } 1865 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 1866 for (i = 0; i < wx->num_tx_queues; i++, reg_idx++) { 1867 /* If we are greater than indices move to next pool */ 1868 if ((reg_idx & rss->mask) >= rss->indices) 1869 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 1870 wx->tx_ring[i]->reg_idx = reg_idx; 1871 } 1872 } else { 1873 /* start at VMDq register offset for SR-IOV enabled setups */ 1874 reg_idx = vmdq->offset; 1875 for (i = 0; i < wx->num_rx_queues; i++) 1876 /* If we are greater than indices move to next pool */ 1877 wx->rx_ring[i]->reg_idx = reg_idx + i; 1878 1879 reg_idx = vmdq->offset; 1880 for (i = 0; i < wx->num_tx_queues; i++) 1881 /* If we are greater than indices move to next pool */ 1882 wx->tx_ring[i]->reg_idx = reg_idx + i; 1883 } 1884 1885 return true; 1886 } 1887 1888 /** 1889 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS 1890 * @wx: board private structure to initialize 1891 * 1892 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV. 1893 * 1894 **/ 1895 static void wx_cache_ring_rss(struct wx *wx) 1896 { 1897 u16 i; 1898 1899 if (wx_cache_ring_vmdq(wx)) 1900 return; 1901 1902 for (i = 0; i < wx->num_rx_queues; i++) 1903 wx->rx_ring[i]->reg_idx = i; 1904 1905 for (i = 0; i < wx->num_tx_queues; i++) 1906 wx->tx_ring[i]->reg_idx = i; 1907 } 1908 1909 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head) 1910 { 1911 ring->next = head->ring; 1912 head->ring = ring; 1913 head->count++; 1914 } 1915 1916 /** 1917 * wx_alloc_q_vector - Allocate memory for a single interrupt vector 1918 * @wx: board private structure to initialize 1919 * @v_count: q_vectors allocated on wx, used for ring interleaving 1920 * @v_idx: index of vector in wx struct 1921 * @txr_count: total number of Tx rings to allocate 1922 * @txr_idx: index of first Tx ring to allocate 1923 * @rxr_count: total number of Rx rings to allocate 1924 * @rxr_idx: index of first Rx ring to allocate 1925 * 1926 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1927 **/ 1928 static int wx_alloc_q_vector(struct wx *wx, 1929 unsigned int v_count, unsigned int v_idx, 1930 unsigned int txr_count, unsigned int txr_idx, 1931 unsigned int rxr_count, unsigned int rxr_idx) 1932 { 1933 struct wx_q_vector *q_vector; 1934 int ring_count, default_itr; 1935 struct wx_ring *ring; 1936 1937 /* note this will allocate space for the ring structure as well! */ 1938 ring_count = txr_count + rxr_count; 1939 1940 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 1941 GFP_KERNEL); 1942 if (!q_vector) 1943 return -ENOMEM; 1944 1945 /* initialize NAPI */ 1946 netif_napi_add(wx->netdev, &q_vector->napi, 1947 wx_poll); 1948 1949 /* tie q_vector and wx together */ 1950 wx->q_vector[v_idx] = q_vector; 1951 q_vector->wx = wx; 1952 q_vector->v_idx = v_idx; 1953 if (cpu_online(v_idx)) 1954 q_vector->numa_node = cpu_to_node(v_idx); 1955 1956 /* initialize pointer to rings */ 1957 ring = q_vector->ring; 1958 1959 switch (wx->mac.type) { 1960 case wx_mac_sp: 1961 case wx_mac_aml: 1962 default_itr = WX_12K_ITR; 1963 break; 1964 default: 1965 default_itr = WX_7K_ITR; 1966 break; 1967 } 1968 1969 /* initialize ITR */ 1970 if (txr_count && !rxr_count) 1971 /* tx only vector */ 1972 q_vector->itr = wx->tx_itr_setting ? 1973 default_itr : wx->tx_itr_setting; 1974 else 1975 /* rx or rx/tx vector */ 1976 q_vector->itr = wx->rx_itr_setting ? 1977 default_itr : wx->rx_itr_setting; 1978 1979 while (txr_count) { 1980 /* assign generic ring traits */ 1981 ring->dev = &wx->pdev->dev; 1982 ring->netdev = wx->netdev; 1983 1984 /* configure backlink on ring */ 1985 ring->q_vector = q_vector; 1986 1987 /* update q_vector Tx values */ 1988 wx_add_ring(ring, &q_vector->tx); 1989 1990 /* apply Tx specific ring traits */ 1991 ring->count = wx->tx_ring_count; 1992 1993 ring->queue_index = txr_idx; 1994 1995 /* assign ring to wx */ 1996 wx->tx_ring[txr_idx] = ring; 1997 1998 /* update count and index */ 1999 txr_count--; 2000 txr_idx += v_count; 2001 2002 /* push pointer to next ring */ 2003 ring++; 2004 } 2005 2006 while (rxr_count) { 2007 /* assign generic ring traits */ 2008 ring->dev = &wx->pdev->dev; 2009 ring->netdev = wx->netdev; 2010 2011 /* configure backlink on ring */ 2012 ring->q_vector = q_vector; 2013 2014 /* update q_vector Rx values */ 2015 wx_add_ring(ring, &q_vector->rx); 2016 2017 /* apply Rx specific ring traits */ 2018 ring->count = wx->rx_ring_count; 2019 ring->queue_index = rxr_idx; 2020 2021 /* assign ring to wx */ 2022 wx->rx_ring[rxr_idx] = ring; 2023 2024 /* update count and index */ 2025 rxr_count--; 2026 rxr_idx += v_count; 2027 2028 /* push pointer to next ring */ 2029 ring++; 2030 } 2031 2032 return 0; 2033 } 2034 2035 /** 2036 * wx_free_q_vector - Free memory allocated for specific interrupt vector 2037 * @wx: board private structure to initialize 2038 * @v_idx: Index of vector to be freed 2039 * 2040 * This function frees the memory allocated to the q_vector. In addition if 2041 * NAPI is enabled it will delete any references to the NAPI struct prior 2042 * to freeing the q_vector. 2043 **/ 2044 static void wx_free_q_vector(struct wx *wx, int v_idx) 2045 { 2046 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2047 struct wx_ring *ring; 2048 2049 wx_for_each_ring(ring, q_vector->tx) 2050 wx->tx_ring[ring->queue_index] = NULL; 2051 2052 wx_for_each_ring(ring, q_vector->rx) 2053 wx->rx_ring[ring->queue_index] = NULL; 2054 2055 wx->q_vector[v_idx] = NULL; 2056 netif_napi_del(&q_vector->napi); 2057 kfree_rcu(q_vector, rcu); 2058 } 2059 2060 /** 2061 * wx_alloc_q_vectors - Allocate memory for interrupt vectors 2062 * @wx: board private structure to initialize 2063 * 2064 * We allocate one q_vector per queue interrupt. If allocation fails we 2065 * return -ENOMEM. 2066 **/ 2067 static int wx_alloc_q_vectors(struct wx *wx) 2068 { 2069 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 2070 unsigned int rxr_remaining = wx->num_rx_queues; 2071 unsigned int txr_remaining = wx->num_tx_queues; 2072 unsigned int q_vectors = wx->num_q_vectors; 2073 int rqpv, tqpv; 2074 int err; 2075 2076 for (; v_idx < q_vectors; v_idx++) { 2077 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 2078 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 2079 err = wx_alloc_q_vector(wx, q_vectors, v_idx, 2080 tqpv, txr_idx, 2081 rqpv, rxr_idx); 2082 2083 if (err) 2084 goto err_out; 2085 2086 /* update counts and index */ 2087 rxr_remaining -= rqpv; 2088 txr_remaining -= tqpv; 2089 rxr_idx++; 2090 txr_idx++; 2091 } 2092 2093 return 0; 2094 2095 err_out: 2096 wx->num_tx_queues = 0; 2097 wx->num_rx_queues = 0; 2098 wx->num_q_vectors = 0; 2099 2100 while (v_idx--) 2101 wx_free_q_vector(wx, v_idx); 2102 2103 return -ENOMEM; 2104 } 2105 2106 /** 2107 * wx_free_q_vectors - Free memory allocated for interrupt vectors 2108 * @wx: board private structure to initialize 2109 * 2110 * This function frees the memory allocated to the q_vectors. In addition if 2111 * NAPI is enabled it will delete any references to the NAPI struct prior 2112 * to freeing the q_vector. 2113 **/ 2114 static void wx_free_q_vectors(struct wx *wx) 2115 { 2116 int v_idx = wx->num_q_vectors; 2117 2118 wx->num_tx_queues = 0; 2119 wx->num_rx_queues = 0; 2120 wx->num_q_vectors = 0; 2121 2122 while (v_idx--) 2123 wx_free_q_vector(wx, v_idx); 2124 } 2125 2126 void wx_reset_interrupt_capability(struct wx *wx) 2127 { 2128 struct pci_dev *pdev = wx->pdev; 2129 2130 if (!pdev->msi_enabled && !pdev->msix_enabled) 2131 return; 2132 2133 if (pdev->msix_enabled) { 2134 kfree(wx->msix_q_entries); 2135 wx->msix_q_entries = NULL; 2136 kfree(wx->msix_entry); 2137 wx->msix_entry = NULL; 2138 } 2139 pci_free_irq_vectors(wx->pdev); 2140 } 2141 EXPORT_SYMBOL(wx_reset_interrupt_capability); 2142 2143 /** 2144 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings 2145 * @wx: board private structure to clear interrupt scheme on 2146 * 2147 * We go through and clear interrupt specific resources and reset the structure 2148 * to pre-load conditions 2149 **/ 2150 void wx_clear_interrupt_scheme(struct wx *wx) 2151 { 2152 wx_free_q_vectors(wx); 2153 wx_reset_interrupt_capability(wx); 2154 } 2155 EXPORT_SYMBOL(wx_clear_interrupt_scheme); 2156 2157 int wx_init_interrupt_scheme(struct wx *wx) 2158 { 2159 int ret; 2160 2161 /* Number of supported queues */ 2162 wx_set_num_queues(wx); 2163 2164 /* Set interrupt mode */ 2165 ret = wx_set_interrupt_capability(wx); 2166 if (ret) { 2167 wx_err(wx, "Allocate irq vectors for failed.\n"); 2168 return ret; 2169 } 2170 2171 /* Allocate memory for queues */ 2172 ret = wx_alloc_q_vectors(wx); 2173 if (ret) { 2174 wx_err(wx, "Unable to allocate memory for queue vectors.\n"); 2175 wx_reset_interrupt_capability(wx); 2176 return ret; 2177 } 2178 2179 wx_cache_ring_rss(wx); 2180 2181 return 0; 2182 } 2183 EXPORT_SYMBOL(wx_init_interrupt_scheme); 2184 2185 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data) 2186 { 2187 struct wx_q_vector *q_vector = data; 2188 2189 /* EIAM disabled interrupts (on this vector) for us */ 2190 if (q_vector->rx.ring || q_vector->tx.ring) 2191 napi_schedule_irqoff(&q_vector->napi); 2192 2193 return IRQ_HANDLED; 2194 } 2195 EXPORT_SYMBOL(wx_msix_clean_rings); 2196 2197 void wx_free_irq(struct wx *wx) 2198 { 2199 struct pci_dev *pdev = wx->pdev; 2200 int vector; 2201 2202 if (!(pdev->msix_enabled)) { 2203 if (!wx->misc_irq_domain) 2204 free_irq(pdev->irq, wx); 2205 return; 2206 } 2207 2208 for (vector = 0; vector < wx->num_q_vectors; vector++) { 2209 struct wx_q_vector *q_vector = wx->q_vector[vector]; 2210 struct msix_entry *entry = &wx->msix_q_entries[vector]; 2211 2212 /* free only the irqs that were actually requested */ 2213 if (!q_vector->rx.ring && !q_vector->tx.ring) 2214 continue; 2215 2216 free_irq(entry->vector, q_vector); 2217 } 2218 2219 if (!wx->misc_irq_domain) 2220 free_irq(wx->msix_entry->vector, wx); 2221 } 2222 EXPORT_SYMBOL(wx_free_irq); 2223 2224 /** 2225 * wx_setup_isb_resources - allocate interrupt status resources 2226 * @wx: board private structure 2227 * 2228 * Return 0 on success, negative on failure 2229 **/ 2230 int wx_setup_isb_resources(struct wx *wx) 2231 { 2232 struct pci_dev *pdev = wx->pdev; 2233 2234 if (wx->isb_mem) 2235 return 0; 2236 2237 wx->isb_mem = dma_alloc_coherent(&pdev->dev, 2238 sizeof(u32) * 4, 2239 &wx->isb_dma, 2240 GFP_KERNEL); 2241 if (!wx->isb_mem) { 2242 wx_err(wx, "Alloc isb_mem failed\n"); 2243 return -ENOMEM; 2244 } 2245 2246 return 0; 2247 } 2248 EXPORT_SYMBOL(wx_setup_isb_resources); 2249 2250 /** 2251 * wx_free_isb_resources - allocate all queues Rx resources 2252 * @wx: board private structure 2253 * 2254 * Return 0 on success, negative on failure 2255 **/ 2256 void wx_free_isb_resources(struct wx *wx) 2257 { 2258 struct pci_dev *pdev = wx->pdev; 2259 2260 dma_free_coherent(&pdev->dev, sizeof(u32) * 4, 2261 wx->isb_mem, wx->isb_dma); 2262 wx->isb_mem = NULL; 2263 } 2264 EXPORT_SYMBOL(wx_free_isb_resources); 2265 2266 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx) 2267 { 2268 u32 cur_tag = 0; 2269 2270 cur_tag = wx->isb_mem[WX_ISB_HEADER]; 2271 wx->isb_tag[idx] = cur_tag; 2272 2273 return (__force u32)cpu_to_le32(wx->isb_mem[idx]); 2274 } 2275 EXPORT_SYMBOL(wx_misc_isb); 2276 2277 /** 2278 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 2279 * @wx: pointer to wx struct 2280 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 2281 * @queue: queue to map the corresponding interrupt to 2282 * @msix_vector: the vector to map to the corresponding queue 2283 * 2284 **/ 2285 static void wx_set_ivar(struct wx *wx, s8 direction, 2286 u16 queue, u16 msix_vector) 2287 { 2288 u32 ivar, index; 2289 2290 if (direction == -1) { 2291 /* other causes */ 2292 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2293 index = 0; 2294 ivar = rd32(wx, WX_PX_MISC_IVAR); 2295 ivar &= ~(0xFF << index); 2296 ivar |= (msix_vector << index); 2297 wr32(wx, WX_PX_MISC_IVAR, ivar); 2298 } else { 2299 /* tx or rx causes */ 2300 if (!(wx->mac.type == wx_mac_em && wx->num_vfs == 7)) 2301 msix_vector += 1; /* offset for queue vectors */ 2302 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2303 index = ((16 * (queue & 1)) + (8 * direction)); 2304 ivar = rd32(wx, WX_PX_IVAR(queue >> 1)); 2305 ivar &= ~(0xFF << index); 2306 ivar |= (msix_vector << index); 2307 wr32(wx, WX_PX_IVAR(queue >> 1), ivar); 2308 } 2309 } 2310 2311 /** 2312 * wx_write_eitr - write EITR register in hardware specific way 2313 * @q_vector: structure containing interrupt and ring information 2314 * 2315 * This function is made to be called by ethtool and by the driver 2316 * when it needs to update EITR registers at runtime. Hardware 2317 * specific quirks/differences are taken care of here. 2318 */ 2319 void wx_write_eitr(struct wx_q_vector *q_vector) 2320 { 2321 struct wx *wx = q_vector->wx; 2322 int v_idx = q_vector->v_idx; 2323 u32 itr_reg; 2324 2325 switch (wx->mac.type) { 2326 case wx_mac_sp: 2327 itr_reg = q_vector->itr & WX_SP_MAX_EITR; 2328 break; 2329 case wx_mac_aml: 2330 itr_reg = (q_vector->itr >> 3) & WX_AML_MAX_EITR; 2331 break; 2332 default: 2333 itr_reg = q_vector->itr & WX_EM_MAX_EITR; 2334 break; 2335 } 2336 2337 itr_reg |= WX_PX_ITR_CNT_WDIS; 2338 2339 wr32(wx, WX_PX_ITR(v_idx + 1), itr_reg); 2340 } 2341 2342 /** 2343 * wx_configure_vectors - Configure vectors for hardware 2344 * @wx: board private structure 2345 * 2346 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx 2347 * interrupts. 2348 **/ 2349 void wx_configure_vectors(struct wx *wx) 2350 { 2351 struct pci_dev *pdev = wx->pdev; 2352 u32 eitrsel = 0; 2353 u16 v_idx, i; 2354 2355 if (pdev->msix_enabled) { 2356 /* Populate MSIX to EITR Select */ 2357 if (wx->mac.type == wx_mac_sp) { 2358 if (wx->num_vfs >= 32) 2359 eitrsel = BIT(wx->num_vfs % 32) - 1; 2360 } else if (wx->mac.type == wx_mac_em) { 2361 for (i = 0; i < wx->num_vfs; i++) 2362 eitrsel |= BIT(i); 2363 } 2364 wr32(wx, WX_PX_ITRSEL, eitrsel); 2365 /* use EIAM to auto-mask when MSI-X interrupt is asserted 2366 * this saves a register write for every interrupt 2367 */ 2368 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL); 2369 } else { 2370 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 2371 * specifically only auto mask tx and rx interrupts. 2372 */ 2373 wr32(wx, WX_PX_GPIE, 0); 2374 } 2375 2376 /* Populate the IVAR table and set the ITR values to the 2377 * corresponding register. 2378 */ 2379 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) { 2380 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2381 struct wx_ring *ring; 2382 2383 wx_for_each_ring(ring, q_vector->rx) 2384 wx_set_ivar(wx, 0, ring->reg_idx, v_idx); 2385 2386 wx_for_each_ring(ring, q_vector->tx) 2387 wx_set_ivar(wx, 1, ring->reg_idx, v_idx); 2388 2389 wx_write_eitr(q_vector); 2390 } 2391 2392 wx_set_ivar(wx, -1, 0, 0); 2393 if (pdev->msix_enabled) 2394 wr32(wx, WX_PX_ITR(0), 1950); 2395 } 2396 EXPORT_SYMBOL(wx_configure_vectors); 2397 2398 /** 2399 * wx_clean_rx_ring - Free Rx Buffers per Queue 2400 * @rx_ring: ring to free buffers from 2401 **/ 2402 static void wx_clean_rx_ring(struct wx_ring *rx_ring) 2403 { 2404 struct wx_rx_buffer *rx_buffer; 2405 u16 i = rx_ring->next_to_clean; 2406 2407 rx_buffer = &rx_ring->rx_buffer_info[i]; 2408 2409 /* Free all the Rx ring sk_buffs */ 2410 while (i != rx_ring->next_to_alloc) { 2411 if (rx_buffer->skb) { 2412 struct sk_buff *skb = rx_buffer->skb; 2413 2414 if (WX_CB(skb)->page_released) 2415 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2416 2417 dev_kfree_skb(skb); 2418 } 2419 2420 /* Invalidate cache lines that may have been written to by 2421 * device so that we avoid corrupting memory. 2422 */ 2423 dma_sync_single_range_for_cpu(rx_ring->dev, 2424 rx_buffer->dma, 2425 rx_buffer->page_offset, 2426 WX_RX_BUFSZ, 2427 DMA_FROM_DEVICE); 2428 2429 /* free resources associated with mapping */ 2430 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2431 2432 i++; 2433 rx_buffer++; 2434 if (i == rx_ring->count) { 2435 i = 0; 2436 rx_buffer = rx_ring->rx_buffer_info; 2437 } 2438 } 2439 2440 rx_ring->next_to_alloc = 0; 2441 rx_ring->next_to_clean = 0; 2442 rx_ring->next_to_use = 0; 2443 } 2444 2445 /** 2446 * wx_clean_all_rx_rings - Free Rx Buffers for all queues 2447 * @wx: board private structure 2448 **/ 2449 void wx_clean_all_rx_rings(struct wx *wx) 2450 { 2451 int i; 2452 2453 for (i = 0; i < wx->num_rx_queues; i++) 2454 wx_clean_rx_ring(wx->rx_ring[i]); 2455 } 2456 EXPORT_SYMBOL(wx_clean_all_rx_rings); 2457 2458 /** 2459 * wx_free_rx_resources - Free Rx Resources 2460 * @rx_ring: ring to clean the resources from 2461 * 2462 * Free all receive software resources 2463 **/ 2464 static void wx_free_rx_resources(struct wx_ring *rx_ring) 2465 { 2466 wx_clean_rx_ring(rx_ring); 2467 kvfree(rx_ring->rx_buffer_info); 2468 rx_ring->rx_buffer_info = NULL; 2469 2470 /* if not set, then don't free */ 2471 if (!rx_ring->desc) 2472 return; 2473 2474 dma_free_coherent(rx_ring->dev, rx_ring->size, 2475 rx_ring->desc, rx_ring->dma); 2476 2477 rx_ring->desc = NULL; 2478 2479 if (rx_ring->page_pool) { 2480 page_pool_destroy(rx_ring->page_pool); 2481 rx_ring->page_pool = NULL; 2482 } 2483 } 2484 2485 /** 2486 * wx_free_all_rx_resources - Free Rx Resources for All Queues 2487 * @wx: pointer to hardware structure 2488 * 2489 * Free all receive software resources 2490 **/ 2491 static void wx_free_all_rx_resources(struct wx *wx) 2492 { 2493 int i; 2494 2495 for (i = 0; i < wx->num_rx_queues; i++) 2496 wx_free_rx_resources(wx->rx_ring[i]); 2497 } 2498 2499 /** 2500 * wx_clean_tx_ring - Free Tx Buffers 2501 * @tx_ring: ring to be cleaned 2502 **/ 2503 static void wx_clean_tx_ring(struct wx_ring *tx_ring) 2504 { 2505 struct wx_tx_buffer *tx_buffer; 2506 u16 i = tx_ring->next_to_clean; 2507 2508 tx_buffer = &tx_ring->tx_buffer_info[i]; 2509 2510 while (i != tx_ring->next_to_use) { 2511 union wx_tx_desc *eop_desc, *tx_desc; 2512 2513 /* Free all the Tx ring sk_buffs */ 2514 dev_kfree_skb_any(tx_buffer->skb); 2515 2516 /* unmap skb header data */ 2517 dma_unmap_single(tx_ring->dev, 2518 dma_unmap_addr(tx_buffer, dma), 2519 dma_unmap_len(tx_buffer, len), 2520 DMA_TO_DEVICE); 2521 2522 /* check for eop_desc to determine the end of the packet */ 2523 eop_desc = tx_buffer->next_to_watch; 2524 tx_desc = WX_TX_DESC(tx_ring, i); 2525 2526 /* unmap remaining buffers */ 2527 while (tx_desc != eop_desc) { 2528 tx_buffer++; 2529 tx_desc++; 2530 i++; 2531 if (unlikely(i == tx_ring->count)) { 2532 i = 0; 2533 tx_buffer = tx_ring->tx_buffer_info; 2534 tx_desc = WX_TX_DESC(tx_ring, 0); 2535 } 2536 2537 /* unmap any remaining paged data */ 2538 if (dma_unmap_len(tx_buffer, len)) 2539 dma_unmap_page(tx_ring->dev, 2540 dma_unmap_addr(tx_buffer, dma), 2541 dma_unmap_len(tx_buffer, len), 2542 DMA_TO_DEVICE); 2543 } 2544 2545 /* move us one more past the eop_desc for start of next pkt */ 2546 tx_buffer++; 2547 i++; 2548 if (unlikely(i == tx_ring->count)) { 2549 i = 0; 2550 tx_buffer = tx_ring->tx_buffer_info; 2551 } 2552 } 2553 2554 netdev_tx_reset_queue(wx_txring_txq(tx_ring)); 2555 2556 /* reset next_to_use and next_to_clean */ 2557 tx_ring->next_to_use = 0; 2558 tx_ring->next_to_clean = 0; 2559 } 2560 2561 /** 2562 * wx_clean_all_tx_rings - Free Tx Buffers for all queues 2563 * @wx: board private structure 2564 **/ 2565 void wx_clean_all_tx_rings(struct wx *wx) 2566 { 2567 int i; 2568 2569 for (i = 0; i < wx->num_tx_queues; i++) 2570 wx_clean_tx_ring(wx->tx_ring[i]); 2571 } 2572 EXPORT_SYMBOL(wx_clean_all_tx_rings); 2573 2574 /** 2575 * wx_free_tx_resources - Free Tx Resources per Queue 2576 * @tx_ring: Tx descriptor ring for a specific queue 2577 * 2578 * Free all transmit software resources 2579 **/ 2580 static void wx_free_tx_resources(struct wx_ring *tx_ring) 2581 { 2582 wx_clean_tx_ring(tx_ring); 2583 kvfree(tx_ring->tx_buffer_info); 2584 tx_ring->tx_buffer_info = NULL; 2585 2586 /* if not set, then don't free */ 2587 if (!tx_ring->desc) 2588 return; 2589 2590 dma_free_coherent(tx_ring->dev, tx_ring->size, 2591 tx_ring->desc, tx_ring->dma); 2592 tx_ring->desc = NULL; 2593 } 2594 2595 /** 2596 * wx_free_all_tx_resources - Free Tx Resources for All Queues 2597 * @wx: pointer to hardware structure 2598 * 2599 * Free all transmit software resources 2600 **/ 2601 static void wx_free_all_tx_resources(struct wx *wx) 2602 { 2603 int i; 2604 2605 for (i = 0; i < wx->num_tx_queues; i++) 2606 wx_free_tx_resources(wx->tx_ring[i]); 2607 } 2608 2609 void wx_free_resources(struct wx *wx) 2610 { 2611 wx_free_all_rx_resources(wx); 2612 wx_free_all_tx_resources(wx); 2613 } 2614 EXPORT_SYMBOL(wx_free_resources); 2615 2616 static int wx_alloc_page_pool(struct wx_ring *rx_ring) 2617 { 2618 int ret = 0; 2619 2620 struct page_pool_params pp_params = { 2621 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2622 .order = 0, 2623 .pool_size = rx_ring->size, 2624 .nid = dev_to_node(rx_ring->dev), 2625 .dev = rx_ring->dev, 2626 .dma_dir = DMA_FROM_DEVICE, 2627 .offset = 0, 2628 .max_len = PAGE_SIZE, 2629 }; 2630 2631 rx_ring->page_pool = page_pool_create(&pp_params); 2632 if (IS_ERR(rx_ring->page_pool)) { 2633 ret = PTR_ERR(rx_ring->page_pool); 2634 rx_ring->page_pool = NULL; 2635 } 2636 2637 return ret; 2638 } 2639 2640 /** 2641 * wx_setup_rx_resources - allocate Rx resources (Descriptors) 2642 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2643 * 2644 * Returns 0 on success, negative on failure 2645 **/ 2646 static int wx_setup_rx_resources(struct wx_ring *rx_ring) 2647 { 2648 struct device *dev = rx_ring->dev; 2649 int orig_node = dev_to_node(dev); 2650 int numa_node = NUMA_NO_NODE; 2651 int size, ret; 2652 2653 size = sizeof(struct wx_rx_buffer) * rx_ring->count; 2654 2655 if (rx_ring->q_vector) 2656 numa_node = rx_ring->q_vector->numa_node; 2657 2658 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2659 if (!rx_ring->rx_buffer_info) 2660 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL); 2661 if (!rx_ring->rx_buffer_info) 2662 goto err; 2663 2664 /* Round up to nearest 4K */ 2665 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc); 2666 rx_ring->size = ALIGN(rx_ring->size, 4096); 2667 2668 set_dev_node(dev, numa_node); 2669 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2670 &rx_ring->dma, GFP_KERNEL); 2671 if (!rx_ring->desc) { 2672 set_dev_node(dev, orig_node); 2673 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2674 &rx_ring->dma, GFP_KERNEL); 2675 } 2676 2677 if (!rx_ring->desc) 2678 goto err; 2679 2680 rx_ring->next_to_clean = 0; 2681 rx_ring->next_to_use = 0; 2682 2683 ret = wx_alloc_page_pool(rx_ring); 2684 if (ret < 0) { 2685 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret); 2686 goto err_desc; 2687 } 2688 2689 return 0; 2690 2691 err_desc: 2692 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2693 err: 2694 kvfree(rx_ring->rx_buffer_info); 2695 rx_ring->rx_buffer_info = NULL; 2696 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2697 return -ENOMEM; 2698 } 2699 2700 /** 2701 * wx_setup_all_rx_resources - allocate all queues Rx resources 2702 * @wx: pointer to hardware structure 2703 * 2704 * If this function returns with an error, then it's possible one or 2705 * more of the rings is populated (while the rest are not). It is the 2706 * callers duty to clean those orphaned rings. 2707 * 2708 * Return 0 on success, negative on failure 2709 **/ 2710 static int wx_setup_all_rx_resources(struct wx *wx) 2711 { 2712 int i, err = 0; 2713 2714 for (i = 0; i < wx->num_rx_queues; i++) { 2715 err = wx_setup_rx_resources(wx->rx_ring[i]); 2716 if (!err) 2717 continue; 2718 2719 wx_err(wx, "Allocation for Rx Queue %u failed\n", i); 2720 goto err_setup_rx; 2721 } 2722 2723 return 0; 2724 err_setup_rx: 2725 /* rewind the index freeing the rings as we go */ 2726 while (i--) 2727 wx_free_rx_resources(wx->rx_ring[i]); 2728 return err; 2729 } 2730 2731 /** 2732 * wx_setup_tx_resources - allocate Tx resources (Descriptors) 2733 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2734 * 2735 * Return 0 on success, negative on failure 2736 **/ 2737 static int wx_setup_tx_resources(struct wx_ring *tx_ring) 2738 { 2739 struct device *dev = tx_ring->dev; 2740 int orig_node = dev_to_node(dev); 2741 int numa_node = NUMA_NO_NODE; 2742 int size; 2743 2744 size = sizeof(struct wx_tx_buffer) * tx_ring->count; 2745 2746 if (tx_ring->q_vector) 2747 numa_node = tx_ring->q_vector->numa_node; 2748 2749 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2750 if (!tx_ring->tx_buffer_info) 2751 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL); 2752 if (!tx_ring->tx_buffer_info) 2753 goto err; 2754 2755 /* round up to nearest 4K */ 2756 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc); 2757 tx_ring->size = ALIGN(tx_ring->size, 4096); 2758 2759 set_dev_node(dev, numa_node); 2760 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2761 &tx_ring->dma, GFP_KERNEL); 2762 if (!tx_ring->desc) { 2763 set_dev_node(dev, orig_node); 2764 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2765 &tx_ring->dma, GFP_KERNEL); 2766 } 2767 2768 if (!tx_ring->desc) 2769 goto err; 2770 2771 tx_ring->next_to_use = 0; 2772 tx_ring->next_to_clean = 0; 2773 2774 return 0; 2775 2776 err: 2777 kvfree(tx_ring->tx_buffer_info); 2778 tx_ring->tx_buffer_info = NULL; 2779 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2780 return -ENOMEM; 2781 } 2782 2783 /** 2784 * wx_setup_all_tx_resources - allocate all queues Tx resources 2785 * @wx: pointer to private structure 2786 * 2787 * If this function returns with an error, then it's possible one or 2788 * more of the rings is populated (while the rest are not). It is the 2789 * callers duty to clean those orphaned rings. 2790 * 2791 * Return 0 on success, negative on failure 2792 **/ 2793 static int wx_setup_all_tx_resources(struct wx *wx) 2794 { 2795 int i, err = 0; 2796 2797 for (i = 0; i < wx->num_tx_queues; i++) { 2798 err = wx_setup_tx_resources(wx->tx_ring[i]); 2799 if (!err) 2800 continue; 2801 2802 wx_err(wx, "Allocation for Tx Queue %u failed\n", i); 2803 goto err_setup_tx; 2804 } 2805 2806 return 0; 2807 err_setup_tx: 2808 /* rewind the index freeing the rings as we go */ 2809 while (i--) 2810 wx_free_tx_resources(wx->tx_ring[i]); 2811 return err; 2812 } 2813 2814 int wx_setup_resources(struct wx *wx) 2815 { 2816 int err; 2817 2818 /* allocate transmit descriptors */ 2819 err = wx_setup_all_tx_resources(wx); 2820 if (err) 2821 return err; 2822 2823 /* allocate receive descriptors */ 2824 err = wx_setup_all_rx_resources(wx); 2825 if (err) 2826 goto err_free_tx; 2827 2828 err = wx_setup_isb_resources(wx); 2829 if (err) 2830 goto err_free_rx; 2831 2832 return 0; 2833 2834 err_free_rx: 2835 wx_free_all_rx_resources(wx); 2836 err_free_tx: 2837 wx_free_all_tx_resources(wx); 2838 2839 return err; 2840 } 2841 EXPORT_SYMBOL(wx_setup_resources); 2842 2843 /** 2844 * wx_get_stats64 - Get System Network Statistics 2845 * @netdev: network interface device structure 2846 * @stats: storage space for 64bit statistics 2847 */ 2848 void wx_get_stats64(struct net_device *netdev, 2849 struct rtnl_link_stats64 *stats) 2850 { 2851 struct wx *wx = netdev_priv(netdev); 2852 struct wx_hw_stats *hwstats; 2853 int i; 2854 2855 wx_update_stats(wx); 2856 2857 rcu_read_lock(); 2858 for (i = 0; i < wx->num_rx_queues; i++) { 2859 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]); 2860 u64 bytes, packets; 2861 unsigned int start; 2862 2863 if (ring) { 2864 do { 2865 start = u64_stats_fetch_begin(&ring->syncp); 2866 packets = ring->stats.packets; 2867 bytes = ring->stats.bytes; 2868 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2869 stats->rx_packets += packets; 2870 stats->rx_bytes += bytes; 2871 } 2872 } 2873 2874 for (i = 0; i < wx->num_tx_queues; i++) { 2875 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]); 2876 u64 bytes, packets; 2877 unsigned int start; 2878 2879 if (ring) { 2880 do { 2881 start = u64_stats_fetch_begin(&ring->syncp); 2882 packets = ring->stats.packets; 2883 bytes = ring->stats.bytes; 2884 } while (u64_stats_fetch_retry(&ring->syncp, 2885 start)); 2886 stats->tx_packets += packets; 2887 stats->tx_bytes += bytes; 2888 } 2889 } 2890 2891 rcu_read_unlock(); 2892 2893 hwstats = &wx->stats; 2894 stats->rx_errors = hwstats->crcerrs + hwstats->rlec; 2895 stats->multicast = hwstats->qmprc; 2896 stats->rx_length_errors = hwstats->rlec; 2897 stats->rx_crc_errors = hwstats->crcerrs; 2898 } 2899 EXPORT_SYMBOL(wx_get_stats64); 2900 2901 int wx_set_features(struct net_device *netdev, netdev_features_t features) 2902 { 2903 netdev_features_t changed = netdev->features ^ features; 2904 struct wx *wx = netdev_priv(netdev); 2905 bool need_reset = false; 2906 2907 if (features & NETIF_F_RXHASH) { 2908 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 2909 WX_RDB_RA_CTL_RSS_EN); 2910 wx->rss_enabled = true; 2911 } else { 2912 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0); 2913 wx->rss_enabled = false; 2914 } 2915 2916 netdev->features = features; 2917 2918 if (changed & NETIF_F_HW_VLAN_CTAG_RX && wx->do_reset) 2919 wx->do_reset(netdev); 2920 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER)) 2921 wx_set_rx_mode(netdev); 2922 2923 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 2924 return 0; 2925 2926 /* Check if Flow Director n-tuple support was enabled or disabled. If 2927 * the state changed, we need to reset. 2928 */ 2929 switch (features & NETIF_F_NTUPLE) { 2930 case NETIF_F_NTUPLE: 2931 /* turn off ATR, enable perfect filters and reset */ 2932 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 2933 need_reset = true; 2934 2935 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 2936 break; 2937 default: 2938 /* turn off perfect filters, enable ATR and reset */ 2939 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 2940 need_reset = true; 2941 2942 /* We cannot enable ATR if RSS is disabled */ 2943 if (wx->ring_feature[RING_F_RSS].limit <= 1) 2944 break; 2945 2946 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 2947 break; 2948 } 2949 2950 if (need_reset && wx->do_reset) 2951 wx->do_reset(netdev); 2952 2953 return 0; 2954 } 2955 EXPORT_SYMBOL(wx_set_features); 2956 2957 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \ 2958 NETIF_F_HW_VLAN_STAG_RX) 2959 2960 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \ 2961 NETIF_F_HW_VLAN_STAG_TX) 2962 2963 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \ 2964 NETIF_F_HW_VLAN_STAG_FILTER) 2965 2966 netdev_features_t wx_fix_features(struct net_device *netdev, 2967 netdev_features_t features) 2968 { 2969 netdev_features_t changed = netdev->features ^ features; 2970 struct wx *wx = netdev_priv(netdev); 2971 2972 if (changed & NETIF_VLAN_STRIPPING_FEATURES) { 2973 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES && 2974 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) { 2975 features &= ~NETIF_VLAN_STRIPPING_FEATURES; 2976 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES; 2977 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off."); 2978 } 2979 } 2980 2981 if (changed & NETIF_VLAN_INSERTION_FEATURES) { 2982 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES && 2983 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) { 2984 features &= ~NETIF_VLAN_INSERTION_FEATURES; 2985 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES; 2986 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off."); 2987 } 2988 } 2989 2990 if (changed & NETIF_VLAN_FILTERING_FEATURES) { 2991 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES && 2992 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) { 2993 features &= ~NETIF_VLAN_FILTERING_FEATURES; 2994 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES; 2995 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off."); 2996 } 2997 } 2998 2999 return features; 3000 } 3001 EXPORT_SYMBOL(wx_fix_features); 3002 3003 void wx_set_ring(struct wx *wx, u32 new_tx_count, 3004 u32 new_rx_count, struct wx_ring *temp_ring) 3005 { 3006 int i, err = 0; 3007 3008 /* Setup new Tx resources and free the old Tx resources in that order. 3009 * We can then assign the new resources to the rings via a memcpy. 3010 * The advantage to this approach is that we are guaranteed to still 3011 * have resources even in the case of an allocation failure. 3012 */ 3013 if (new_tx_count != wx->tx_ring_count) { 3014 for (i = 0; i < wx->num_tx_queues; i++) { 3015 memcpy(&temp_ring[i], wx->tx_ring[i], 3016 sizeof(struct wx_ring)); 3017 3018 temp_ring[i].count = new_tx_count; 3019 err = wx_setup_tx_resources(&temp_ring[i]); 3020 if (err) { 3021 wx_err(wx, "setup new tx resources failed, keep using the old config\n"); 3022 while (i) { 3023 i--; 3024 wx_free_tx_resources(&temp_ring[i]); 3025 } 3026 return; 3027 } 3028 } 3029 3030 for (i = 0; i < wx->num_tx_queues; i++) { 3031 wx_free_tx_resources(wx->tx_ring[i]); 3032 3033 memcpy(wx->tx_ring[i], &temp_ring[i], 3034 sizeof(struct wx_ring)); 3035 } 3036 3037 wx->tx_ring_count = new_tx_count; 3038 } 3039 3040 /* Repeat the process for the Rx rings if needed */ 3041 if (new_rx_count != wx->rx_ring_count) { 3042 for (i = 0; i < wx->num_rx_queues; i++) { 3043 memcpy(&temp_ring[i], wx->rx_ring[i], 3044 sizeof(struct wx_ring)); 3045 3046 temp_ring[i].count = new_rx_count; 3047 err = wx_setup_rx_resources(&temp_ring[i]); 3048 if (err) { 3049 wx_err(wx, "setup new rx resources failed, keep using the old config\n"); 3050 while (i) { 3051 i--; 3052 wx_free_rx_resources(&temp_ring[i]); 3053 } 3054 return; 3055 } 3056 } 3057 3058 for (i = 0; i < wx->num_rx_queues; i++) { 3059 wx_free_rx_resources(wx->rx_ring[i]); 3060 memcpy(wx->rx_ring[i], &temp_ring[i], 3061 sizeof(struct wx_ring)); 3062 } 3063 3064 wx->rx_ring_count = new_rx_count; 3065 } 3066 } 3067 EXPORT_SYMBOL(wx_set_ring); 3068 3069 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers."); 3070 MODULE_LICENSE("GPL"); 3071