1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <net/ip6_checksum.h> 6 #include <net/page_pool/helpers.h> 7 #include <net/inet_ecn.h> 8 #include <linux/workqueue.h> 9 #include <linux/iopoll.h> 10 #include <linux/sctp.h> 11 #include <linux/pci.h> 12 #include <net/tcp.h> 13 #include <net/ip.h> 14 15 #include "wx_type.h" 16 #include "wx_lib.h" 17 #include "wx_ptp.h" 18 #include "wx_hw.h" 19 #include "wx_vf_lib.h" 20 21 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 22 static struct wx_dec_ptype wx_ptype_lookup[256] = { 23 /* L2: mac */ 24 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 25 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2), 26 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 27 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 28 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 29 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 30 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 31 32 /* L2: ethertype filter */ 33 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 34 35 /* L3: ip non-tunnel */ 36 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3), 37 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3), 38 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4), 39 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4), 40 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4), 41 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3), 42 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3), 43 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3), 44 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4), 45 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4), 46 47 /* L2: fcoe */ 48 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 49 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 50 51 /* IPv4 --> IPv4/IPv6 */ 52 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3), 53 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3), 54 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4), 55 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4), 56 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4), 57 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3), 58 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3), 59 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4), 60 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4), 61 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4), 62 63 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */ 64 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3), 65 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3), 66 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3), 67 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4), 68 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4), 69 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4), 70 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3), 71 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3), 72 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4), 73 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4), 74 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4), 75 76 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */ 77 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3), 78 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3), 79 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3), 80 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4), 81 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4), 82 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4), 83 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3), 84 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3), 85 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4), 86 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4), 87 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4), 88 89 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */ 90 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3), 91 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3), 92 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3), 93 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4), 94 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4), 95 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4), 96 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3), 97 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3), 98 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4), 99 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4), 100 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4), 101 102 /* IPv6 --> IPv4/IPv6 */ 103 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3), 104 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3), 105 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4), 106 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4), 107 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4), 108 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3), 109 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3), 110 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4), 111 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4), 112 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4), 113 114 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */ 115 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3), 116 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3), 117 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3), 118 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4), 119 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4), 120 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4), 121 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3), 122 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3), 123 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4), 124 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4), 125 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4), 126 127 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */ 128 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3), 129 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3), 130 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3), 131 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4), 132 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4), 133 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4), 134 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3), 135 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3), 136 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4), 137 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4), 138 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4), 139 140 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */ 141 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3), 142 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3), 143 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3), 144 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4), 145 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4), 146 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4), 147 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3), 148 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3), 149 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4), 150 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4), 151 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4), 152 }; 153 154 struct wx_dec_ptype wx_decode_ptype(const u8 ptype) 155 { 156 return wx_ptype_lookup[ptype]; 157 } 158 EXPORT_SYMBOL(wx_decode_ptype); 159 160 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */ 161 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc, 162 const u32 stat_err_bits) 163 { 164 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 165 } 166 167 static void wx_dma_sync_frag(struct wx_ring *rx_ring, 168 struct wx_rx_buffer *rx_buffer) 169 { 170 struct sk_buff *skb = rx_buffer->skb; 171 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 172 173 dma_sync_single_range_for_cpu(rx_ring->dev, 174 WX_CB(skb)->dma, 175 skb_frag_off(frag), 176 skb_frag_size(frag), 177 DMA_FROM_DEVICE); 178 } 179 180 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring, 181 union wx_rx_desc *rx_desc, 182 struct sk_buff **skb) 183 { 184 struct wx_rx_buffer *rx_buffer; 185 unsigned int size; 186 187 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 188 size = le16_to_cpu(rx_desc->wb.upper.length); 189 190 prefetchw(rx_buffer->page); 191 *skb = rx_buffer->skb; 192 193 /* Delay unmapping of the first packet. It carries the header 194 * information, HW may still access the header after the writeback. 195 * Only unmap it when EOP is reached 196 */ 197 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) { 198 if (!*skb) 199 goto skip_sync; 200 } else { 201 if (*skb) 202 wx_dma_sync_frag(rx_ring, rx_buffer); 203 } 204 205 /* we are reusing so sync this buffer for CPU use */ 206 dma_sync_single_range_for_cpu(rx_ring->dev, 207 rx_buffer->dma, 208 rx_buffer->page_offset, 209 size, 210 DMA_FROM_DEVICE); 211 skip_sync: 212 return rx_buffer; 213 } 214 215 static void wx_put_rx_buffer(struct wx_ring *rx_ring, 216 struct wx_rx_buffer *rx_buffer, 217 struct sk_buff *skb) 218 { 219 /* clear contents of rx_buffer */ 220 rx_buffer->page = NULL; 221 rx_buffer->skb = NULL; 222 } 223 224 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring, 225 struct wx_rx_buffer *rx_buffer, 226 union wx_rx_desc *rx_desc) 227 { 228 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 229 #if (PAGE_SIZE < 8192) 230 unsigned int truesize = wx_rx_pg_size(rx_ring) / 2; 231 #else 232 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 233 #endif 234 struct sk_buff *skb = rx_buffer->skb; 235 236 if (!skb) { 237 void *page_addr = page_address(rx_buffer->page) + 238 rx_buffer->page_offset; 239 240 /* prefetch first cache line of first page */ 241 net_prefetch(page_addr); 242 243 /* allocate a skb to store the frags */ 244 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256); 245 if (unlikely(!skb)) 246 return NULL; 247 248 /* we will be copying header into skb->data in 249 * pskb_may_pull so it is in our interest to prefetch 250 * it now to avoid a possible cache miss 251 */ 252 prefetchw(skb->data); 253 254 if (size <= WX_RXBUFFER_256) { 255 memcpy(__skb_put(skb, size), page_addr, 256 ALIGN(size, sizeof(long))); 257 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true); 258 return skb; 259 } 260 261 skb_mark_for_recycle(skb); 262 263 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) 264 WX_CB(skb)->dma = rx_buffer->dma; 265 266 skb_add_rx_frag(skb, 0, rx_buffer->page, 267 rx_buffer->page_offset, 268 size, truesize); 269 goto out; 270 271 } else { 272 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 273 rx_buffer->page_offset, size, truesize); 274 } 275 276 out: 277 #if (PAGE_SIZE < 8192) 278 /* flip page offset to other buffer */ 279 rx_buffer->page_offset ^= truesize; 280 #else 281 /* move offset up to the next cache line */ 282 rx_buffer->page_offset += truesize; 283 #endif 284 285 return skb; 286 } 287 288 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring, 289 struct wx_rx_buffer *bi) 290 { 291 struct page *page = bi->page; 292 dma_addr_t dma; 293 294 /* since we are recycling buffers we should seldom need to alloc */ 295 if (likely(page)) 296 return true; 297 298 page = page_pool_dev_alloc_pages(rx_ring->page_pool); 299 if (unlikely(!page)) 300 return false; 301 dma = page_pool_get_dma_addr(page); 302 303 bi->dma = dma; 304 bi->page = page; 305 bi->page_offset = 0; 306 307 return true; 308 } 309 310 /** 311 * wx_alloc_rx_buffers - Replace used receive buffers 312 * @rx_ring: ring to place buffers on 313 * @cleaned_count: number of buffers to replace 314 **/ 315 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count) 316 { 317 u16 i = rx_ring->next_to_use; 318 union wx_rx_desc *rx_desc; 319 struct wx_rx_buffer *bi; 320 321 /* nothing to do */ 322 if (!cleaned_count) 323 return; 324 325 rx_desc = WX_RX_DESC(rx_ring, i); 326 bi = &rx_ring->rx_buffer_info[i]; 327 i -= rx_ring->count; 328 329 do { 330 if (!wx_alloc_mapped_page(rx_ring, bi)) 331 break; 332 333 /* sync the buffer for use by the device */ 334 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 335 bi->page_offset, 336 rx_ring->rx_buf_len, 337 DMA_FROM_DEVICE); 338 339 rx_desc->read.pkt_addr = 340 cpu_to_le64(bi->dma + bi->page_offset); 341 342 rx_desc++; 343 bi++; 344 i++; 345 if (unlikely(!i)) { 346 rx_desc = WX_RX_DESC(rx_ring, 0); 347 bi = rx_ring->rx_buffer_info; 348 i -= rx_ring->count; 349 } 350 351 /* clear the status bits for the next_to_use descriptor */ 352 rx_desc->wb.upper.status_error = 0; 353 /* clear the length for the next_to_use descriptor */ 354 rx_desc->wb.upper.length = 0; 355 356 cleaned_count--; 357 } while (cleaned_count); 358 359 i += rx_ring->count; 360 361 if (rx_ring->next_to_use != i) { 362 rx_ring->next_to_use = i; 363 /* update next to alloc since we have filled the ring */ 364 rx_ring->next_to_alloc = i; 365 366 /* Force memory writes to complete before letting h/w 367 * know there are new descriptors to fetch. (Only 368 * applicable for weak-ordered memory model archs, 369 * such as IA-64). 370 */ 371 wmb(); 372 writel(i, rx_ring->tail); 373 } 374 } 375 376 u16 wx_desc_unused(struct wx_ring *ring) 377 { 378 u16 ntc = ring->next_to_clean; 379 u16 ntu = ring->next_to_use; 380 381 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 382 } 383 384 /** 385 * wx_is_non_eop - process handling of non-EOP buffers 386 * @rx_ring: Rx ring being processed 387 * @rx_desc: Rx descriptor for current buffer 388 * @skb: Current socket buffer containing buffer in progress 389 * 390 * This function updates next to clean. If the buffer is an EOP buffer 391 * this function exits returning false, otherwise it will place the 392 * sk_buff in the next buffer to be chained and return true indicating 393 * that this is in fact a non-EOP buffer. 394 **/ 395 static bool wx_is_non_eop(struct wx_ring *rx_ring, 396 union wx_rx_desc *rx_desc, 397 struct sk_buff *skb) 398 { 399 struct wx *wx = rx_ring->q_vector->wx; 400 u32 ntc = rx_ring->next_to_clean + 1; 401 402 /* fetch, update, and store next to clean */ 403 ntc = (ntc < rx_ring->count) ? ntc : 0; 404 rx_ring->next_to_clean = ntc; 405 406 prefetch(WX_RX_DESC(rx_ring, ntc)); 407 408 /* update RSC append count if present */ 409 if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) { 410 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & 411 cpu_to_le32(WX_RXD_RSCCNT_MASK); 412 413 if (unlikely(rsc_enabled)) { 414 u32 rsc_cnt = le32_to_cpu(rsc_enabled); 415 416 rsc_cnt >>= WX_RXD_RSCCNT_SHIFT; 417 WX_CB(skb)->append_cnt += rsc_cnt - 1; 418 419 /* update ntc based on RSC value */ 420 ntc = le32_to_cpu(rx_desc->wb.upper.status_error); 421 ntc &= WX_RXD_NEXTP_MASK; 422 ntc >>= WX_RXD_NEXTP_SHIFT; 423 } 424 } 425 426 /* if we are the last buffer then there is nothing else to do */ 427 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))) 428 return false; 429 430 rx_ring->rx_buffer_info[ntc].skb = skb; 431 rx_ring->rx_stats.non_eop_descs++; 432 433 return true; 434 } 435 436 static void wx_pull_tail(struct sk_buff *skb) 437 { 438 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 439 unsigned int pull_len; 440 unsigned char *va; 441 442 /* it is valid to use page_address instead of kmap since we are 443 * working with pages allocated out of the lomem pool per 444 * alloc_page(GFP_ATOMIC) 445 */ 446 va = skb_frag_address(frag); 447 448 /* we need the header to contain the greater of either ETH_HLEN or 449 * 60 bytes if the skb->len is less than 60 for skb_pad. 450 */ 451 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256); 452 453 /* align pull length to size of long to optimize memcpy performance */ 454 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 455 456 /* update all of the pointers */ 457 skb_frag_size_sub(frag, pull_len); 458 skb_frag_off_add(frag, pull_len); 459 skb->data_len -= pull_len; 460 skb->tail += pull_len; 461 } 462 463 /** 464 * wx_cleanup_headers - Correct corrupted or empty headers 465 * @rx_ring: rx descriptor ring packet is being transacted on 466 * @rx_desc: pointer to the EOP Rx descriptor 467 * @skb: pointer to current skb being fixed 468 * 469 * Check for corrupted packet headers caused by senders on the local L2 470 * embedded NIC switch not setting up their Tx Descriptors right. These 471 * should be very rare. 472 * 473 * Also address the case where we are pulling data in on pages only 474 * and as such no data is present in the skb header. 475 * 476 * In addition if skb is not at least 60 bytes we need to pad it so that 477 * it is large enough to qualify as a valid Ethernet frame. 478 * 479 * Returns true if an error was encountered and skb was freed. 480 **/ 481 static bool wx_cleanup_headers(struct wx_ring *rx_ring, 482 union wx_rx_desc *rx_desc, 483 struct sk_buff *skb) 484 { 485 struct net_device *netdev = rx_ring->netdev; 486 487 /* verify that the packet does not have any known errors */ 488 if (!netdev || 489 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) && 490 !(netdev->features & NETIF_F_RXALL))) { 491 dev_kfree_skb_any(skb); 492 return true; 493 } 494 495 /* place header in linear portion of buffer */ 496 if (!skb_headlen(skb)) 497 wx_pull_tail(skb); 498 499 /* if eth_skb_pad returns an error the skb was freed */ 500 if (eth_skb_pad(skb)) 501 return true; 502 503 return false; 504 } 505 506 static void wx_rx_hash(struct wx_ring *ring, 507 union wx_rx_desc *rx_desc, 508 struct sk_buff *skb) 509 { 510 u16 rss_type; 511 512 if (!(ring->netdev->features & NETIF_F_RXHASH)) 513 return; 514 515 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 516 WX_RXD_RSSTYPE_MASK; 517 518 if (!rss_type) 519 return; 520 521 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 522 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 523 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 524 } 525 526 /** 527 * wx_rx_checksum - indicate in skb if hw indicated a good cksum 528 * @ring: structure containing ring specific data 529 * @rx_desc: current Rx descriptor being processed 530 * @skb: skb currently being received and modified 531 **/ 532 static void wx_rx_checksum(struct wx_ring *ring, 533 union wx_rx_desc *rx_desc, 534 struct sk_buff *skb) 535 { 536 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc)); 537 538 skb_checksum_none_assert(skb); 539 /* Rx csum disabled */ 540 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 541 return; 542 543 /* if IPv4 header checksum error */ 544 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) && 545 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) || 546 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) && 547 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) { 548 ring->rx_stats.csum_err++; 549 return; 550 } 551 552 /* L4 checksum offload flag must set for the below code to work */ 553 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS)) 554 return; 555 556 /* Hardware can't guarantee csum if IPv6 Dest Header found */ 557 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && 558 wx_test_staterr(rx_desc, WX_RXD_STAT_IPV6EX)) 559 return; 560 561 /* if L4 checksum error */ 562 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) { 563 ring->rx_stats.csum_err++; 564 return; 565 } 566 567 /* It must be a TCP or UDP or SCTP packet with a valid checksum */ 568 skb->ip_summed = CHECKSUM_UNNECESSARY; 569 570 /* If there is an outer header present that might contain a checksum 571 * we need to bump the checksum level by 1 to reflect the fact that 572 * we are indicating we validated the inner checksum. 573 */ 574 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG) 575 __skb_incr_checksum_unnecessary(skb); 576 ring->rx_stats.csum_good_cnt++; 577 } 578 579 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc, 580 struct sk_buff *skb) 581 { 582 u16 ethertype; 583 u8 idx = 0; 584 585 if ((ring->netdev->features & 586 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) && 587 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) { 588 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 589 0x1c0) >> 6; 590 ethertype = ring->q_vector->wx->tpid[idx]; 591 __vlan_hwaccel_put_tag(skb, htons(ethertype), 592 le16_to_cpu(rx_desc->wb.upper.vlan)); 593 } 594 } 595 596 static void wx_set_rsc_gso_size(struct wx_ring *ring, 597 struct sk_buff *skb) 598 { 599 u16 hdr_len = skb_headlen(skb); 600 601 /* set gso_size to avoid messing up TCP MSS */ 602 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), 603 WX_CB(skb)->append_cnt); 604 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; 605 } 606 607 static void wx_update_rsc_stats(struct wx_ring *rx_ring, 608 struct sk_buff *skb) 609 { 610 /* if append_cnt is 0 then frame is not RSC */ 611 if (!WX_CB(skb)->append_cnt) 612 return; 613 614 rx_ring->rx_stats.rsc_count += WX_CB(skb)->append_cnt; 615 rx_ring->rx_stats.rsc_flush++; 616 617 wx_set_rsc_gso_size(rx_ring, skb); 618 619 /* gso_size is computed using append_cnt so always clear it last */ 620 WX_CB(skb)->append_cnt = 0; 621 } 622 623 /** 624 * wx_process_skb_fields - Populate skb header fields from Rx descriptor 625 * @rx_ring: rx descriptor ring packet is being transacted on 626 * @rx_desc: pointer to the EOP Rx descriptor 627 * @skb: pointer to current skb being populated 628 * 629 * This function checks the ring, descriptor, and packet information in 630 * order to populate the hash, checksum, protocol, and 631 * other fields within the skb. 632 **/ 633 static void wx_process_skb_fields(struct wx_ring *rx_ring, 634 union wx_rx_desc *rx_desc, 635 struct sk_buff *skb) 636 { 637 struct wx *wx = netdev_priv(rx_ring->netdev); 638 639 if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) 640 wx_update_rsc_stats(rx_ring, skb); 641 642 wx_rx_hash(rx_ring, rx_desc, skb); 643 wx_rx_checksum(rx_ring, rx_desc, skb); 644 645 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, wx->flags)) && 646 unlikely(wx_test_staterr(rx_desc, WX_RXD_STAT_TS))) { 647 wx_ptp_rx_hwtstamp(rx_ring->q_vector->wx, skb); 648 rx_ring->last_rx_timestamp = jiffies; 649 } 650 651 wx_rx_vlan(rx_ring, rx_desc, skb); 652 skb_record_rx_queue(skb, rx_ring->queue_index); 653 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 654 } 655 656 /** 657 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 658 * @q_vector: structure containing interrupt and ring information 659 * @rx_ring: rx descriptor ring to transact packets on 660 * @budget: Total limit on number of packets to process 661 * 662 * This function provides a "bounce buffer" approach to Rx interrupt 663 * processing. The advantage to this is that on systems that have 664 * expensive overhead for IOMMU access this provides a means of avoiding 665 * it by maintaining the mapping of the page to the system. 666 * 667 * Returns amount of work completed. 668 **/ 669 static int wx_clean_rx_irq(struct wx_q_vector *q_vector, 670 struct wx_ring *rx_ring, 671 int budget) 672 { 673 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 674 u16 cleaned_count = wx_desc_unused(rx_ring); 675 676 do { 677 struct wx_rx_buffer *rx_buffer; 678 union wx_rx_desc *rx_desc; 679 struct sk_buff *skb; 680 681 /* return some buffers to hardware, one at a time is too slow */ 682 if (cleaned_count >= WX_RX_BUFFER_WRITE) { 683 wx_alloc_rx_buffers(rx_ring, cleaned_count); 684 cleaned_count = 0; 685 } 686 687 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean); 688 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD)) 689 break; 690 691 /* This memory barrier is needed to keep us from reading 692 * any other fields out of the rx_desc until we know the 693 * descriptor has been written back 694 */ 695 dma_rmb(); 696 697 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb); 698 699 /* retrieve a buffer from the ring */ 700 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc); 701 702 /* exit if we failed to retrieve a buffer */ 703 if (!skb) { 704 rx_ring->rx_stats.alloc_rx_buff_failed++; 705 break; 706 } 707 708 wx_put_rx_buffer(rx_ring, rx_buffer, skb); 709 cleaned_count++; 710 711 /* place incomplete frames back on ring for completion */ 712 if (wx_is_non_eop(rx_ring, rx_desc, skb)) 713 continue; 714 715 /* verify the packet layout is correct */ 716 if (wx_cleanup_headers(rx_ring, rx_desc, skb)) 717 continue; 718 719 /* probably a little skewed due to removing CRC */ 720 total_rx_bytes += skb->len; 721 722 /* populate checksum, timestamp, VLAN, and protocol */ 723 wx_process_skb_fields(rx_ring, rx_desc, skb); 724 napi_gro_receive(&q_vector->napi, skb); 725 726 /* update budget accounting */ 727 total_rx_packets++; 728 } while (likely(total_rx_packets < budget)); 729 730 u64_stats_update_begin(&rx_ring->syncp); 731 rx_ring->stats.packets += total_rx_packets; 732 rx_ring->stats.bytes += total_rx_bytes; 733 u64_stats_update_end(&rx_ring->syncp); 734 q_vector->rx.total_packets += total_rx_packets; 735 q_vector->rx.total_bytes += total_rx_bytes; 736 737 return total_rx_packets; 738 } 739 740 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring) 741 { 742 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 743 } 744 745 /** 746 * wx_clean_tx_irq - Reclaim resources after transmit completes 747 * @q_vector: structure containing interrupt and ring information 748 * @tx_ring: tx ring to clean 749 * @napi_budget: Used to determine if we are in netpoll 750 **/ 751 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector, 752 struct wx_ring *tx_ring, int napi_budget) 753 { 754 unsigned int budget = q_vector->wx->tx_work_limit; 755 unsigned int total_bytes = 0, total_packets = 0; 756 struct wx *wx = netdev_priv(tx_ring->netdev); 757 unsigned int i = tx_ring->next_to_clean; 758 struct wx_tx_buffer *tx_buffer; 759 union wx_tx_desc *tx_desc; 760 761 if (!netif_carrier_ok(tx_ring->netdev)) 762 return true; 763 764 tx_buffer = &tx_ring->tx_buffer_info[i]; 765 tx_desc = WX_TX_DESC(tx_ring, i); 766 i -= tx_ring->count; 767 768 do { 769 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch; 770 771 /* if next_to_watch is not set then there is no work pending */ 772 if (!eop_desc) 773 break; 774 775 /* prevent any other reads prior to eop_desc */ 776 smp_rmb(); 777 778 if (tx_ring->headwb_mem) { 779 u32 head = *tx_ring->headwb_mem; 780 781 if (head == tx_ring->next_to_clean) 782 break; 783 else if (head > tx_ring->next_to_clean && 784 !(tx_buffer->next_eop >= tx_ring->next_to_clean && 785 tx_buffer->next_eop < head)) 786 break; 787 else if (!(tx_buffer->next_eop >= tx_ring->next_to_clean || 788 tx_buffer->next_eop < head)) 789 break; 790 } else if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) { 791 /* if DD is not set pending work has not been completed */ 792 break; 793 } 794 795 /* clear next_to_watch to prevent false hangs */ 796 tx_buffer->next_to_watch = NULL; 797 798 /* update the statistics for this packet */ 799 total_bytes += tx_buffer->bytecount; 800 total_packets += tx_buffer->gso_segs; 801 802 /* schedule check for Tx timestamp */ 803 if (unlikely(test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state)) && 804 skb_shinfo(tx_buffer->skb)->tx_flags & SKBTX_IN_PROGRESS) 805 ptp_schedule_worker(wx->ptp_clock, 0); 806 807 /* free the skb */ 808 napi_consume_skb(tx_buffer->skb, napi_budget); 809 810 /* unmap skb header data */ 811 dma_unmap_single(tx_ring->dev, 812 dma_unmap_addr(tx_buffer, dma), 813 dma_unmap_len(tx_buffer, len), 814 DMA_TO_DEVICE); 815 816 /* clear tx_buffer data */ 817 dma_unmap_len_set(tx_buffer, len, 0); 818 819 /* unmap remaining buffers */ 820 while (tx_desc != eop_desc) { 821 tx_buffer++; 822 tx_desc++; 823 i++; 824 if (unlikely(!i)) { 825 i -= tx_ring->count; 826 tx_buffer = tx_ring->tx_buffer_info; 827 tx_desc = WX_TX_DESC(tx_ring, 0); 828 } 829 830 /* unmap any remaining paged data */ 831 if (dma_unmap_len(tx_buffer, len)) { 832 dma_unmap_page(tx_ring->dev, 833 dma_unmap_addr(tx_buffer, dma), 834 dma_unmap_len(tx_buffer, len), 835 DMA_TO_DEVICE); 836 dma_unmap_len_set(tx_buffer, len, 0); 837 } 838 } 839 840 /* move us one more past the eop_desc for start of next pkt */ 841 tx_buffer++; 842 tx_desc++; 843 i++; 844 if (unlikely(!i)) { 845 i -= tx_ring->count; 846 tx_buffer = tx_ring->tx_buffer_info; 847 tx_desc = WX_TX_DESC(tx_ring, 0); 848 } 849 850 /* issue prefetch for next Tx descriptor */ 851 prefetch(tx_desc); 852 853 /* update budget accounting */ 854 budget--; 855 } while (likely(budget)); 856 857 i += tx_ring->count; 858 tx_ring->next_to_clean = i; 859 u64_stats_update_begin(&tx_ring->syncp); 860 tx_ring->stats.bytes += total_bytes; 861 tx_ring->stats.packets += total_packets; 862 u64_stats_update_end(&tx_ring->syncp); 863 q_vector->tx.total_bytes += total_bytes; 864 q_vector->tx.total_packets += total_packets; 865 866 netdev_tx_completed_queue(wx_txring_txq(tx_ring), 867 total_packets, total_bytes); 868 869 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 870 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 871 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 872 /* Make sure that anybody stopping the queue after this 873 * sees the new next_to_clean. 874 */ 875 smp_mb(); 876 877 if (__netif_subqueue_stopped(tx_ring->netdev, 878 tx_ring->queue_index) && 879 netif_running(tx_ring->netdev)) { 880 netif_wake_subqueue(tx_ring->netdev, 881 tx_ring->queue_index); 882 ++tx_ring->tx_stats.restart_queue; 883 } 884 } 885 886 return !!budget; 887 } 888 889 static void wx_update_rx_dim_sample(struct wx_q_vector *q_vector) 890 { 891 struct dim_sample sample = {}; 892 893 dim_update_sample(q_vector->total_events, 894 q_vector->rx.total_packets, 895 q_vector->rx.total_bytes, 896 &sample); 897 898 net_dim(&q_vector->rx.dim, &sample); 899 } 900 901 static void wx_update_tx_dim_sample(struct wx_q_vector *q_vector) 902 { 903 struct dim_sample sample = {}; 904 905 dim_update_sample(q_vector->total_events, 906 q_vector->tx.total_packets, 907 q_vector->tx.total_bytes, 908 &sample); 909 910 net_dim(&q_vector->tx.dim, &sample); 911 } 912 913 static void wx_update_dim_sample(struct wx_q_vector *q_vector) 914 { 915 wx_update_rx_dim_sample(q_vector); 916 wx_update_tx_dim_sample(q_vector); 917 } 918 919 /** 920 * wx_poll - NAPI polling RX/TX cleanup routine 921 * @napi: napi struct with our devices info in it 922 * @budget: amount of work driver is allowed to do this pass, in packets 923 * 924 * This function will clean all queues associated with a q_vector. 925 **/ 926 static int wx_poll(struct napi_struct *napi, int budget) 927 { 928 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi); 929 int per_ring_budget, work_done = 0; 930 struct wx *wx = q_vector->wx; 931 bool clean_complete = true; 932 struct wx_ring *ring; 933 934 wx_for_each_ring(ring, q_vector->tx) { 935 if (!wx_clean_tx_irq(q_vector, ring, budget)) 936 clean_complete = false; 937 } 938 939 /* Exit if we are called by netpoll */ 940 if (budget <= 0) 941 return budget; 942 943 /* attempt to distribute budget to each queue fairly, but don't allow 944 * the budget to go below 1 because we'll exit polling 945 */ 946 if (q_vector->rx.count > 1) 947 per_ring_budget = max(budget / q_vector->rx.count, 1); 948 else 949 per_ring_budget = budget; 950 951 wx_for_each_ring(ring, q_vector->rx) { 952 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget); 953 954 work_done += cleaned; 955 if (cleaned >= per_ring_budget) 956 clean_complete = false; 957 } 958 959 /* If all work not completed, return budget and keep polling */ 960 if (!clean_complete) 961 return budget; 962 963 /* all work done, exit the polling mode */ 964 if (likely(napi_complete_done(napi, work_done))) { 965 if (wx->adaptive_itr) 966 wx_update_dim_sample(q_vector); 967 if (netif_running(wx->netdev)) 968 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx)); 969 } 970 971 return min(work_done, budget - 1); 972 } 973 974 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size) 975 { 976 if (likely(wx_desc_unused(tx_ring) >= size)) 977 return 0; 978 979 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 980 981 /* For the next check */ 982 smp_mb(); 983 984 /* We need to check again in a case another CPU has just 985 * made room available. 986 */ 987 if (likely(wx_desc_unused(tx_ring) < size)) 988 return -EBUSY; 989 990 /* A reprieve! - use start_queue because it doesn't call schedule */ 991 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 992 ++tx_ring->tx_stats.restart_queue; 993 994 return 0; 995 } 996 997 static u32 wx_tx_cmd_type(u32 tx_flags) 998 { 999 /* set type for advanced descriptor with frame checksum insertion */ 1000 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS; 1001 1002 /* set HW vlan bit if vlan is present */ 1003 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE); 1004 /* set segmentation enable bits for TSO/FSO */ 1005 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE); 1006 /* set timestamp bit if present */ 1007 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP); 1008 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC); 1009 1010 return cmd_type; 1011 } 1012 1013 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc, 1014 u32 tx_flags, unsigned int paylen) 1015 { 1016 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT; 1017 1018 /* enable L4 checksum for TSO and TX checksum offload */ 1019 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS); 1020 /* enable IPv4 checksum for TSO */ 1021 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS); 1022 /* enable outer IPv4 checksum for TSO */ 1023 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4, 1024 WX_TXD_EIPCS); 1025 /* Check Context must be set if Tx switch is enabled, which it 1026 * always is for case where virtual functions are running 1027 */ 1028 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC); 1029 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC, 1030 WX_TXD_IPSEC); 1031 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 1032 } 1033 1034 static int wx_tx_map(struct wx_ring *tx_ring, 1035 struct wx_tx_buffer *first, 1036 const u8 hdr_len) 1037 { 1038 struct sk_buff *skb = first->skb; 1039 struct wx_tx_buffer *tx_buffer; 1040 u32 tx_flags = first->tx_flags; 1041 u16 i = tx_ring->next_to_use; 1042 unsigned int data_len, size; 1043 union wx_tx_desc *tx_desc; 1044 skb_frag_t *frag; 1045 dma_addr_t dma; 1046 u32 cmd_type; 1047 1048 cmd_type = wx_tx_cmd_type(tx_flags); 1049 tx_desc = WX_TX_DESC(tx_ring, i); 1050 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 1051 1052 size = skb_headlen(skb); 1053 data_len = skb->data_len; 1054 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 1055 1056 tx_buffer = first; 1057 1058 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 1059 if (dma_mapping_error(tx_ring->dev, dma)) 1060 goto dma_error; 1061 1062 /* record length, and DMA address */ 1063 dma_unmap_len_set(tx_buffer, len, size); 1064 dma_unmap_addr_set(tx_buffer, dma, dma); 1065 1066 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1067 1068 while (unlikely(size > WX_MAX_DATA_PER_TXD)) { 1069 tx_desc->read.cmd_type_len = 1070 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD); 1071 1072 i++; 1073 tx_desc++; 1074 if (i == tx_ring->count) { 1075 tx_desc = WX_TX_DESC(tx_ring, 0); 1076 i = 0; 1077 } 1078 tx_desc->read.olinfo_status = 0; 1079 1080 dma += WX_MAX_DATA_PER_TXD; 1081 size -= WX_MAX_DATA_PER_TXD; 1082 1083 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1084 } 1085 1086 if (likely(!data_len)) 1087 break; 1088 1089 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 1090 1091 i++; 1092 tx_desc++; 1093 if (i == tx_ring->count) { 1094 tx_desc = WX_TX_DESC(tx_ring, 0); 1095 i = 0; 1096 } 1097 tx_desc->read.olinfo_status = 0; 1098 1099 size = skb_frag_size(frag); 1100 1101 data_len -= size; 1102 1103 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1104 DMA_TO_DEVICE); 1105 1106 tx_buffer = &tx_ring->tx_buffer_info[i]; 1107 } 1108 1109 /* write last descriptor with RS and EOP bits */ 1110 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS; 1111 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1112 1113 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount); 1114 1115 /* set the timestamp */ 1116 first->time_stamp = jiffies; 1117 skb_tx_timestamp(skb); 1118 1119 /* Force memory writes to complete before letting h/w know there 1120 * are new descriptors to fetch. (Only applicable for weak-ordered 1121 * memory model archs, such as IA-64). 1122 * 1123 * We also need this memory barrier to make certain all of the 1124 * status bits have been updated before next_to_watch is written. 1125 */ 1126 wmb(); 1127 1128 /* set next_to_watch value indicating a packet is present */ 1129 first->next_to_watch = tx_desc; 1130 1131 /* set next_eop for amlite tx head wb */ 1132 if (tx_ring->headwb_mem) 1133 first->next_eop = i; 1134 1135 i++; 1136 if (i == tx_ring->count) 1137 i = 0; 1138 1139 tx_ring->next_to_use = i; 1140 1141 wx_maybe_stop_tx(tx_ring, DESC_NEEDED); 1142 1143 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more()) 1144 writel(i, tx_ring->tail); 1145 1146 return 0; 1147 dma_error: 1148 dev_err(tx_ring->dev, "TX DMA map failed\n"); 1149 1150 /* clear dma mappings for failed tx_buffer_info map */ 1151 for (;;) { 1152 tx_buffer = &tx_ring->tx_buffer_info[i]; 1153 if (dma_unmap_len(tx_buffer, len)) 1154 dma_unmap_page(tx_ring->dev, 1155 dma_unmap_addr(tx_buffer, dma), 1156 dma_unmap_len(tx_buffer, len), 1157 DMA_TO_DEVICE); 1158 dma_unmap_len_set(tx_buffer, len, 0); 1159 if (tx_buffer == first) 1160 break; 1161 if (i == 0) 1162 i += tx_ring->count; 1163 i--; 1164 } 1165 1166 dev_kfree_skb_any(first->skb); 1167 first->skb = NULL; 1168 1169 tx_ring->next_to_use = i; 1170 1171 return -ENOMEM; 1172 } 1173 1174 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens, 1175 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1176 { 1177 struct wx_tx_context_desc *context_desc; 1178 u16 i = tx_ring->next_to_use; 1179 1180 context_desc = WX_TX_CTXTDESC(tx_ring, i); 1181 i++; 1182 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1183 1184 /* set bits to identify this as an advanced context descriptor */ 1185 type_tucmd |= WX_TXD_DTYP_CTXT; 1186 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1187 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1188 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1189 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1190 } 1191 1192 union network_header { 1193 struct iphdr *ipv4; 1194 struct ipv6hdr *ipv6; 1195 void *raw; 1196 }; 1197 1198 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first) 1199 { 1200 u8 tun_prot = 0, l4_prot = 0, ptype = 0; 1201 struct sk_buff *skb = first->skb; 1202 unsigned char *exthdr, *l4_hdr; 1203 __be16 frag_off; 1204 1205 if (skb->encapsulation) { 1206 union network_header hdr; 1207 1208 switch (first->protocol) { 1209 case htons(ETH_P_IP): 1210 tun_prot = ip_hdr(skb)->protocol; 1211 ptype = WX_PTYPE_TUN_IPV4; 1212 break; 1213 case htons(ETH_P_IPV6): 1214 l4_hdr = skb_transport_header(skb); 1215 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1216 tun_prot = ipv6_hdr(skb)->nexthdr; 1217 if (l4_hdr != exthdr) 1218 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off); 1219 ptype = WX_PTYPE_TUN_IPV6; 1220 break; 1221 default: 1222 return ptype; 1223 } 1224 1225 if (tun_prot == IPPROTO_IPIP || tun_prot == IPPROTO_IPV6) { 1226 hdr.raw = (void *)inner_ip_hdr(skb); 1227 ptype |= WX_PTYPE_PKT_IPIP; 1228 } else if (tun_prot == IPPROTO_UDP) { 1229 hdr.raw = (void *)inner_ip_hdr(skb); 1230 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1231 skb->inner_protocol != htons(ETH_P_TEB)) { 1232 ptype |= WX_PTYPE_PKT_IG; 1233 } else { 1234 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1235 == htons(ETH_P_8021Q)) 1236 ptype |= WX_PTYPE_PKT_IGMV; 1237 else 1238 ptype |= WX_PTYPE_PKT_IGM; 1239 } 1240 1241 } else if (tun_prot == IPPROTO_GRE) { 1242 hdr.raw = (void *)inner_ip_hdr(skb); 1243 if (skb->inner_protocol == htons(ETH_P_IP) || 1244 skb->inner_protocol == htons(ETH_P_IPV6)) { 1245 ptype |= WX_PTYPE_PKT_IG; 1246 } else { 1247 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1248 == htons(ETH_P_8021Q)) 1249 ptype |= WX_PTYPE_PKT_IGMV; 1250 else 1251 ptype |= WX_PTYPE_PKT_IGM; 1252 } 1253 } else { 1254 return ptype; 1255 } 1256 1257 switch (hdr.ipv4->version) { 1258 case IPVERSION: 1259 l4_prot = hdr.ipv4->protocol; 1260 break; 1261 case 6: 1262 l4_hdr = skb_inner_transport_header(skb); 1263 exthdr = skb_inner_network_header(skb) + sizeof(struct ipv6hdr); 1264 l4_prot = inner_ipv6_hdr(skb)->nexthdr; 1265 if (l4_hdr != exthdr) 1266 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1267 ptype |= WX_PTYPE_PKT_IPV6; 1268 break; 1269 default: 1270 return ptype; 1271 } 1272 } else { 1273 switch (first->protocol) { 1274 case htons(ETH_P_IP): 1275 l4_prot = ip_hdr(skb)->protocol; 1276 ptype = WX_PTYPE_PKT_IP; 1277 break; 1278 case htons(ETH_P_IPV6): 1279 l4_hdr = skb_transport_header(skb); 1280 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1281 l4_prot = ipv6_hdr(skb)->nexthdr; 1282 if (l4_hdr != exthdr) 1283 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1284 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6; 1285 break; 1286 default: 1287 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC; 1288 } 1289 } 1290 switch (l4_prot) { 1291 case IPPROTO_TCP: 1292 ptype |= WX_PTYPE_TYP_TCP; 1293 break; 1294 case IPPROTO_UDP: 1295 ptype |= WX_PTYPE_TYP_UDP; 1296 break; 1297 case IPPROTO_SCTP: 1298 ptype |= WX_PTYPE_TYP_SCTP; 1299 break; 1300 default: 1301 ptype |= WX_PTYPE_TYP_IP; 1302 break; 1303 } 1304 1305 return ptype; 1306 } 1307 1308 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1309 u8 *hdr_len, u8 ptype) 1310 { 1311 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1312 struct net_device *netdev = tx_ring->netdev; 1313 u32 l4len, tunhdr_eiplen_tunlen = 0; 1314 struct sk_buff *skb = first->skb; 1315 bool enc = skb->encapsulation; 1316 struct ipv6hdr *ipv6h; 1317 struct tcphdr *tcph; 1318 struct iphdr *iph; 1319 u8 tun_prot = 0; 1320 int err; 1321 1322 if (skb->ip_summed != CHECKSUM_PARTIAL) 1323 return 0; 1324 1325 if (!skb_is_gso(skb)) 1326 return 0; 1327 1328 err = skb_cow_head(skb, 0); 1329 if (err < 0) 1330 return err; 1331 1332 /* indicates the inner headers in the skbuff are valid. */ 1333 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb); 1334 if (iph->version == 4) { 1335 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1336 iph->tot_len = 0; 1337 iph->check = 0; 1338 tcph->check = ~csum_tcpudp_magic(iph->saddr, 1339 iph->daddr, 0, 1340 IPPROTO_TCP, 0); 1341 first->tx_flags |= WX_TX_FLAGS_TSO | 1342 WX_TX_FLAGS_CSUM | 1343 WX_TX_FLAGS_IPV4 | 1344 WX_TX_FLAGS_CC; 1345 } else if (iph->version == 6 && skb_is_gso_v6(skb)) { 1346 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 1347 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1348 ipv6h->payload_len = 0; 1349 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, 1350 &ipv6h->daddr, 0, 1351 IPPROTO_TCP, 0); 1352 first->tx_flags |= WX_TX_FLAGS_TSO | 1353 WX_TX_FLAGS_CSUM | 1354 WX_TX_FLAGS_CC; 1355 } 1356 1357 /* compute header lengths */ 1358 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 1359 *hdr_len = enc ? skb_inner_transport_offset(skb) : 1360 skb_transport_offset(skb); 1361 *hdr_len += l4len; 1362 1363 /* update gso size and bytecount with header size */ 1364 first->gso_segs = skb_shinfo(skb)->gso_segs; 1365 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1366 1367 /* mss_l4len_id: use 0 as index for TSO */ 1368 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT; 1369 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT; 1370 1371 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 1372 if (enc) { 1373 unsigned char *exthdr, *l4_hdr; 1374 __be16 frag_off; 1375 1376 switch (first->protocol) { 1377 case htons(ETH_P_IP): 1378 tun_prot = ip_hdr(skb)->protocol; 1379 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4; 1380 break; 1381 case htons(ETH_P_IPV6): 1382 l4_hdr = skb_transport_header(skb); 1383 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1384 tun_prot = ipv6_hdr(skb)->nexthdr; 1385 if (l4_hdr != exthdr) 1386 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off); 1387 break; 1388 default: 1389 break; 1390 } 1391 switch (tun_prot) { 1392 case IPPROTO_UDP: 1393 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1394 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1395 WX_TXD_OUTER_IPLEN_SHIFT) | 1396 (((skb_inner_mac_header(skb) - 1397 skb_transport_header(skb)) >> 1) << 1398 WX_TXD_TUNNEL_LEN_SHIFT); 1399 break; 1400 case IPPROTO_GRE: 1401 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1402 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1403 WX_TXD_OUTER_IPLEN_SHIFT) | 1404 (((skb_inner_mac_header(skb) - 1405 skb_transport_header(skb)) >> 1) << 1406 WX_TXD_TUNNEL_LEN_SHIFT); 1407 break; 1408 case IPPROTO_IPIP: 1409 case IPPROTO_IPV6: 1410 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1411 (char *)ip_hdr(skb)) >> 2) << 1412 WX_TXD_OUTER_IPLEN_SHIFT; 1413 break; 1414 default: 1415 break; 1416 } 1417 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1; 1418 } else { 1419 vlan_macip_lens = skb_network_header_len(skb) >> 1; 1420 } 1421 1422 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT; 1423 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1424 1425 type_tucmd = ptype << 24; 1426 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1427 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1428 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1429 WX_TX_FLAGS_HW_VLAN, 1430 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1431 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1432 type_tucmd, mss_l4len_idx); 1433 1434 return 1; 1435 } 1436 1437 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1438 u8 ptype) 1439 { 1440 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0; 1441 struct net_device *netdev = tx_ring->netdev; 1442 u32 mss_l4len_idx = 0, type_tucmd; 1443 struct sk_buff *skb = first->skb; 1444 u8 tun_prot = 0; 1445 1446 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1447 csum_failed: 1448 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) && 1449 !(first->tx_flags & WX_TX_FLAGS_CC)) 1450 return; 1451 vlan_macip_lens = skb_network_offset(skb) << 1452 WX_TXD_MACLEN_SHIFT; 1453 } else { 1454 unsigned char *exthdr, *l4_hdr; 1455 __be16 frag_off; 1456 u8 l4_prot = 0; 1457 union { 1458 struct iphdr *ipv4; 1459 struct ipv6hdr *ipv6; 1460 u8 *raw; 1461 } network_hdr; 1462 union { 1463 struct tcphdr *tcphdr; 1464 u8 *raw; 1465 } transport_hdr; 1466 1467 if (skb->encapsulation) { 1468 network_hdr.raw = skb_inner_network_header(skb); 1469 transport_hdr.raw = skb_inner_transport_header(skb); 1470 vlan_macip_lens = skb_network_offset(skb) << 1471 WX_TXD_MACLEN_SHIFT; 1472 switch (first->protocol) { 1473 case htons(ETH_P_IP): 1474 tun_prot = ip_hdr(skb)->protocol; 1475 break; 1476 case htons(ETH_P_IPV6): 1477 l4_hdr = skb_transport_header(skb); 1478 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1479 tun_prot = ipv6_hdr(skb)->nexthdr; 1480 if (l4_hdr != exthdr) 1481 ipv6_skip_exthdr(skb, exthdr - skb->data, 1482 &tun_prot, &frag_off); 1483 break; 1484 default: 1485 return; 1486 } 1487 switch (tun_prot) { 1488 case IPPROTO_UDP: 1489 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1490 tunhdr_eiplen_tunlen |= 1491 ((skb_network_header_len(skb) >> 2) << 1492 WX_TXD_OUTER_IPLEN_SHIFT) | 1493 (((skb_inner_mac_header(skb) - 1494 skb_transport_header(skb)) >> 1) << 1495 WX_TXD_TUNNEL_LEN_SHIFT); 1496 break; 1497 case IPPROTO_GRE: 1498 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1499 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1500 WX_TXD_OUTER_IPLEN_SHIFT) | 1501 (((skb_inner_mac_header(skb) - 1502 skb_transport_header(skb)) >> 1) << 1503 WX_TXD_TUNNEL_LEN_SHIFT); 1504 break; 1505 case IPPROTO_IPIP: 1506 case IPPROTO_IPV6: 1507 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1508 (char *)ip_hdr(skb)) >> 2) << 1509 WX_TXD_OUTER_IPLEN_SHIFT; 1510 break; 1511 default: 1512 break; 1513 } 1514 1515 } else { 1516 network_hdr.raw = skb_network_header(skb); 1517 transport_hdr.raw = skb_transport_header(skb); 1518 vlan_macip_lens = skb_network_offset(skb) << 1519 WX_TXD_MACLEN_SHIFT; 1520 } 1521 1522 switch (network_hdr.ipv4->version) { 1523 case IPVERSION: 1524 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1525 l4_prot = network_hdr.ipv4->protocol; 1526 break; 1527 case 6: 1528 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1529 exthdr = network_hdr.raw + sizeof(struct ipv6hdr); 1530 l4_prot = network_hdr.ipv6->nexthdr; 1531 if (transport_hdr.raw != exthdr) 1532 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1533 break; 1534 default: 1535 break; 1536 } 1537 1538 switch (l4_prot) { 1539 case IPPROTO_TCP: 1540 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 1541 WX_TXD_L4LEN_SHIFT; 1542 break; 1543 case IPPROTO_SCTP: 1544 mss_l4len_idx = sizeof(struct sctphdr) << 1545 WX_TXD_L4LEN_SHIFT; 1546 break; 1547 case IPPROTO_UDP: 1548 mss_l4len_idx = sizeof(struct udphdr) << 1549 WX_TXD_L4LEN_SHIFT; 1550 break; 1551 default: 1552 skb_checksum_help(skb); 1553 goto csum_failed; 1554 } 1555 1556 /* update TX checksum flag */ 1557 first->tx_flags |= WX_TX_FLAGS_CSUM; 1558 } 1559 first->tx_flags |= WX_TX_FLAGS_CC; 1560 /* vlan_macip_lens: MACLEN, VLAN tag */ 1561 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1562 1563 type_tucmd = ptype << 24; 1564 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1565 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1566 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1567 WX_TX_FLAGS_HW_VLAN, 1568 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1569 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1570 type_tucmd, mss_l4len_idx); 1571 } 1572 1573 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb, 1574 struct wx_ring *tx_ring) 1575 { 1576 struct wx *wx = netdev_priv(tx_ring->netdev); 1577 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1578 struct wx_tx_buffer *first; 1579 u8 hdr_len = 0, ptype; 1580 unsigned short f; 1581 u32 tx_flags = 0; 1582 int tso; 1583 1584 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD, 1585 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD, 1586 * + 2 desc gap to keep tail from touching head, 1587 * + 1 desc for context descriptor, 1588 * otherwise try next time 1589 */ 1590 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1591 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)-> 1592 frags[f])); 1593 1594 if (wx_maybe_stop_tx(tx_ring, count + 3)) { 1595 tx_ring->tx_stats.tx_busy++; 1596 return NETDEV_TX_BUSY; 1597 } 1598 1599 /* record the location of the first descriptor for this packet */ 1600 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1601 first->skb = skb; 1602 first->bytecount = skb->len; 1603 first->gso_segs = 1; 1604 1605 /* if we have a HW VLAN tag being added default to the HW one */ 1606 if (skb_vlan_tag_present(skb)) { 1607 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT; 1608 tx_flags |= WX_TX_FLAGS_HW_VLAN; 1609 } 1610 1611 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1612 wx->ptp_clock) { 1613 if (wx->tstamp_config.tx_type == HWTSTAMP_TX_ON && 1614 !test_and_set_bit_lock(WX_STATE_PTP_TX_IN_PROGRESS, 1615 wx->state)) { 1616 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1617 tx_flags |= WX_TX_FLAGS_TSTAMP; 1618 wx->ptp_tx_skb = skb_get(skb); 1619 wx->ptp_tx_start = jiffies; 1620 } else { 1621 wx->tx_hwtstamp_skipped++; 1622 } 1623 } 1624 1625 /* record initial flags and protocol */ 1626 first->tx_flags = tx_flags; 1627 first->protocol = vlan_get_protocol(skb); 1628 1629 ptype = wx_encode_tx_desc_ptype(first); 1630 1631 tso = wx_tso(tx_ring, first, &hdr_len, ptype); 1632 if (tso < 0) 1633 goto out_drop; 1634 else if (!tso) 1635 wx_tx_csum(tx_ring, first, ptype); 1636 1637 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate) 1638 wx->atr(tx_ring, first, ptype); 1639 1640 if (wx_tx_map(tx_ring, first, hdr_len)) 1641 goto cleanup_tx_tstamp; 1642 1643 return NETDEV_TX_OK; 1644 out_drop: 1645 dev_kfree_skb_any(first->skb); 1646 first->skb = NULL; 1647 cleanup_tx_tstamp: 1648 if (unlikely(tx_flags & WX_TX_FLAGS_TSTAMP)) { 1649 dev_kfree_skb_any(wx->ptp_tx_skb); 1650 wx->ptp_tx_skb = NULL; 1651 wx->tx_hwtstamp_errors++; 1652 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 1653 } 1654 1655 return NETDEV_TX_OK; 1656 } 1657 1658 netdev_tx_t wx_xmit_frame(struct sk_buff *skb, 1659 struct net_device *netdev) 1660 { 1661 unsigned int r_idx = skb->queue_mapping; 1662 struct wx *wx = netdev_priv(netdev); 1663 struct wx_ring *tx_ring; 1664 1665 if (!netif_carrier_ok(netdev)) { 1666 dev_kfree_skb_any(skb); 1667 return NETDEV_TX_OK; 1668 } 1669 1670 /* The minimum packet size for olinfo paylen is 17 so pad the skb 1671 * in order to meet this minimum size requirement. 1672 */ 1673 if (skb_put_padto(skb, 17)) 1674 return NETDEV_TX_OK; 1675 1676 if (r_idx >= wx->num_tx_queues) 1677 r_idx = r_idx % wx->num_tx_queues; 1678 tx_ring = wx->tx_ring[r_idx]; 1679 1680 return wx_xmit_frame_ring(skb, tx_ring); 1681 } 1682 EXPORT_SYMBOL(wx_xmit_frame); 1683 1684 static void wx_set_itr(struct wx_q_vector *q_vector) 1685 { 1686 struct wx *wx = q_vector->wx; 1687 u32 new_itr; 1688 1689 if (!wx->adaptive_itr) 1690 return; 1691 1692 /* use the smallest value of new ITR delay calculations */ 1693 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 1694 new_itr <<= 2; 1695 1696 if (new_itr != q_vector->itr) { 1697 /* save the algorithm value here */ 1698 q_vector->itr = new_itr; 1699 1700 if (wx->pdev->is_virtfn) 1701 wx_write_eitr_vf(q_vector); 1702 else 1703 wx_write_eitr(q_vector); 1704 } 1705 } 1706 1707 static void wx_rx_dim_work(struct work_struct *work) 1708 { 1709 struct dim *dim = container_of(work, struct dim, work); 1710 struct dim_cq_moder rx_moder; 1711 struct wx_ring_container *rx; 1712 struct wx_q_vector *q_vector; 1713 1714 rx = container_of(dim, struct wx_ring_container, dim); 1715 1716 rx_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1717 rx->itr = rx_moder.usec; 1718 1719 q_vector = container_of(rx, struct wx_q_vector, rx); 1720 wx_set_itr(q_vector); 1721 1722 dim->state = DIM_START_MEASURE; 1723 } 1724 1725 static void wx_tx_dim_work(struct work_struct *work) 1726 { 1727 struct dim *dim = container_of(work, struct dim, work); 1728 struct dim_cq_moder tx_moder; 1729 struct wx_ring_container *tx; 1730 struct wx_q_vector *q_vector; 1731 1732 tx = container_of(dim, struct wx_ring_container, dim); 1733 1734 tx_moder = net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 1735 tx->itr = tx_moder.usec; 1736 1737 q_vector = container_of(tx, struct wx_q_vector, tx); 1738 wx_set_itr(q_vector); 1739 1740 dim->state = DIM_START_MEASURE; 1741 } 1742 1743 void wx_napi_enable_all(struct wx *wx) 1744 { 1745 struct wx_q_vector *q_vector; 1746 int q_idx; 1747 1748 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1749 q_vector = wx->q_vector[q_idx]; 1750 1751 INIT_WORK(&q_vector->rx.dim.work, wx_rx_dim_work); 1752 INIT_WORK(&q_vector->tx.dim.work, wx_tx_dim_work); 1753 q_vector->rx.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1754 q_vector->tx.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1755 napi_enable(&q_vector->napi); 1756 } 1757 } 1758 EXPORT_SYMBOL(wx_napi_enable_all); 1759 1760 void wx_napi_disable_all(struct wx *wx) 1761 { 1762 struct wx_q_vector *q_vector; 1763 int q_idx; 1764 1765 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1766 q_vector = wx->q_vector[q_idx]; 1767 napi_disable(&q_vector->napi); 1768 disable_work_sync(&q_vector->rx.dim.work); 1769 disable_work_sync(&q_vector->tx.dim.work); 1770 } 1771 } 1772 EXPORT_SYMBOL(wx_napi_disable_all); 1773 1774 static bool wx_set_vmdq_queues(struct wx *wx) 1775 { 1776 u16 vmdq_i = wx->ring_feature[RING_F_VMDQ].limit; 1777 u16 rss_i = wx->ring_feature[RING_F_RSS].limit; 1778 u16 rss_m = WX_RSS_DISABLED_MASK; 1779 u16 vmdq_m = 0; 1780 1781 /* only proceed if VMDq is enabled */ 1782 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 1783 return false; 1784 /* Add starting offset to total pool count */ 1785 vmdq_i += wx->ring_feature[RING_F_VMDQ].offset; 1786 1787 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1788 /* double check we are limited to maximum pools */ 1789 vmdq_i = min_t(u16, 64, vmdq_i); 1790 1791 /* 64 pool mode with 2 queues per pool, or 1792 * 16/32/64 pool mode with 1 queue per pool 1793 */ 1794 if (vmdq_i > 32 || rss_i < 4) { 1795 vmdq_m = WX_VMDQ_2Q_MASK; 1796 rss_m = WX_RSS_2Q_MASK; 1797 rss_i = min_t(u16, rss_i, 2); 1798 /* 32 pool mode with 4 queues per pool */ 1799 } else { 1800 vmdq_m = WX_VMDQ_4Q_MASK; 1801 rss_m = WX_RSS_4Q_MASK; 1802 rss_i = 4; 1803 } 1804 } else { 1805 /* double check we are limited to maximum pools */ 1806 vmdq_i = min_t(u16, 8, vmdq_i); 1807 1808 /* when VMDQ on, disable RSS */ 1809 rss_i = 1; 1810 } 1811 1812 /* remove the starting offset from the pool count */ 1813 vmdq_i -= wx->ring_feature[RING_F_VMDQ].offset; 1814 1815 /* save features for later use */ 1816 wx->ring_feature[RING_F_VMDQ].indices = vmdq_i; 1817 wx->ring_feature[RING_F_VMDQ].mask = vmdq_m; 1818 1819 /* limit RSS based on user input and save for later use */ 1820 wx->ring_feature[RING_F_RSS].indices = rss_i; 1821 wx->ring_feature[RING_F_RSS].mask = rss_m; 1822 1823 wx->queues_per_pool = rss_i;/*maybe same to num_rx_queues_per_pool*/ 1824 wx->num_rx_pools = vmdq_i; 1825 wx->num_rx_queues_per_pool = rss_i; 1826 1827 wx->num_rx_queues = vmdq_i * rss_i; 1828 wx->num_tx_queues = vmdq_i * rss_i; 1829 1830 return true; 1831 } 1832 1833 /** 1834 * wx_set_rss_queues: Allocate queues for RSS 1835 * @wx: board private structure to initialize 1836 * 1837 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1838 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1839 * 1840 **/ 1841 static void wx_set_rss_queues(struct wx *wx) 1842 { 1843 struct wx_ring_feature *f; 1844 1845 /* set mask for 16 queue limit of RSS */ 1846 f = &wx->ring_feature[RING_F_RSS]; 1847 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) 1848 f->mask = WX_RSS_64Q_MASK; 1849 else 1850 f->mask = WX_RSS_8Q_MASK; 1851 f->indices = f->limit; 1852 1853 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 1854 goto out; 1855 1856 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 1857 1858 wx->ring_feature[RING_F_FDIR].indices = 1; 1859 /* Use Flow Director in addition to RSS to ensure the best 1860 * distribution of flows across cores, even when an FDIR flow 1861 * isn't matched. 1862 */ 1863 if (f->indices > 1) { 1864 f = &wx->ring_feature[RING_F_FDIR]; 1865 1866 f->indices = f->limit; 1867 1868 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 1869 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 1870 } 1871 1872 out: 1873 wx->num_rx_queues = f->indices; 1874 wx->num_tx_queues = f->indices; 1875 } 1876 1877 static void wx_set_num_queues(struct wx *wx) 1878 { 1879 /* Start with base case */ 1880 wx->num_rx_queues = 1; 1881 wx->num_tx_queues = 1; 1882 wx->queues_per_pool = 1; 1883 1884 if (wx_set_vmdq_queues(wx)) 1885 return; 1886 1887 wx_set_rss_queues(wx); 1888 } 1889 1890 /** 1891 * wx_acquire_msix_vectors - acquire MSI-X vectors 1892 * @wx: board private structure 1893 * 1894 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will 1895 * return a negative error code if unable to acquire MSI-X vectors for any 1896 * reason. 1897 */ 1898 static int wx_acquire_msix_vectors(struct wx *wx) 1899 { 1900 struct irq_affinity affd = { .post_vectors = 1 }; 1901 int nvecs, i; 1902 1903 /* We start by asking for one vector per queue pair */ 1904 nvecs = max(wx->num_rx_queues, wx->num_tx_queues); 1905 nvecs = min_t(int, nvecs, num_online_cpus()); 1906 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors); 1907 1908 wx->msix_q_entries = kzalloc_objs(struct msix_entry, nvecs); 1909 if (!wx->msix_q_entries) 1910 return -ENOMEM; 1911 1912 /* One for non-queue interrupts */ 1913 nvecs += 1; 1914 1915 wx->msix_entry = kzalloc_objs(struct msix_entry, 1); 1916 if (!wx->msix_entry) { 1917 kfree(wx->msix_q_entries); 1918 wx->msix_q_entries = NULL; 1919 return -ENOMEM; 1920 } 1921 1922 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs, 1923 nvecs, 1924 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, 1925 &affd); 1926 if (nvecs < 0) { 1927 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs); 1928 kfree(wx->msix_q_entries); 1929 wx->msix_q_entries = NULL; 1930 kfree(wx->msix_entry); 1931 wx->msix_entry = NULL; 1932 return nvecs; 1933 } 1934 1935 nvecs -= 1; 1936 for (i = 0; i < nvecs; i++) { 1937 wx->msix_q_entries[i].entry = i; 1938 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i); 1939 } 1940 1941 wx->num_q_vectors = nvecs; 1942 1943 wx->msix_entry->entry = nvecs; 1944 wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs); 1945 1946 if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) { 1947 wx->msix_entry->entry = 0; 1948 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0); 1949 wx->msix_q_entries[0].entry = 0; 1950 wx->msix_q_entries[0].vector = pci_irq_vector(wx->pdev, 1); 1951 } 1952 1953 return 0; 1954 } 1955 1956 /** 1957 * wx_set_interrupt_capability - set MSI-X or MSI if supported 1958 * @wx: board private structure to initialize 1959 * 1960 * Attempt to configure the interrupts using the best available 1961 * capabilities of the hardware and the kernel. 1962 **/ 1963 static int wx_set_interrupt_capability(struct wx *wx) 1964 { 1965 struct pci_dev *pdev = wx->pdev; 1966 int nvecs, ret; 1967 1968 /* We will try to get MSI-X interrupts first */ 1969 ret = wx_acquire_msix_vectors(wx); 1970 if (ret == 0 || (ret == -ENOMEM) || pdev->is_virtfn) 1971 return ret; 1972 1973 /* Disable VMDq support */ 1974 dev_warn(&wx->pdev->dev, "Disabling VMQQ support\n"); 1975 clear_bit(WX_FLAG_VMDQ_ENABLED, wx->flags); 1976 1977 /* Disable RSS */ 1978 dev_warn(&wx->pdev->dev, "Disabling RSS support\n"); 1979 wx->ring_feature[RING_F_RSS].limit = 1; 1980 1981 wx_set_num_queues(wx); 1982 1983 /* minmum one for queue, one for misc*/ 1984 nvecs = 1; 1985 nvecs = pci_alloc_irq_vectors(pdev, nvecs, 1986 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX); 1987 if (nvecs == 1) { 1988 if (pdev->msi_enabled) 1989 wx_err(wx, "Fallback to MSI.\n"); 1990 else 1991 wx_err(wx, "Fallback to INTx.\n"); 1992 } else { 1993 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs); 1994 return nvecs; 1995 } 1996 1997 pdev->irq = pci_irq_vector(pdev, 0); 1998 wx->num_q_vectors = 1; 1999 2000 return 0; 2001 } 2002 2003 static bool wx_cache_ring_vmdq(struct wx *wx) 2004 { 2005 struct wx_ring_feature *vmdq = &wx->ring_feature[RING_F_VMDQ]; 2006 struct wx_ring_feature *rss = &wx->ring_feature[RING_F_RSS]; 2007 u16 reg_idx; 2008 int i; 2009 2010 /* only proceed if VMDq is enabled */ 2011 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 2012 return false; 2013 2014 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2015 /* start at VMDq register offset for SR-IOV enabled setups */ 2016 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 2017 for (i = 0; i < wx->num_rx_queues; i++, reg_idx++) { 2018 /* If we are greater than indices move to next pool */ 2019 if ((reg_idx & ~vmdq->mask) >= rss->indices) 2020 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 2021 wx->rx_ring[i]->reg_idx = reg_idx; 2022 } 2023 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 2024 for (i = 0; i < wx->num_tx_queues; i++, reg_idx++) { 2025 /* If we are greater than indices move to next pool */ 2026 if ((reg_idx & rss->mask) >= rss->indices) 2027 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 2028 wx->tx_ring[i]->reg_idx = reg_idx; 2029 } 2030 } else { 2031 /* start at VMDq register offset for SR-IOV enabled setups */ 2032 reg_idx = vmdq->offset; 2033 for (i = 0; i < wx->num_rx_queues; i++) 2034 /* If we are greater than indices move to next pool */ 2035 wx->rx_ring[i]->reg_idx = reg_idx + i; 2036 2037 reg_idx = vmdq->offset; 2038 for (i = 0; i < wx->num_tx_queues; i++) 2039 /* If we are greater than indices move to next pool */ 2040 wx->tx_ring[i]->reg_idx = reg_idx + i; 2041 } 2042 2043 return true; 2044 } 2045 2046 /** 2047 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS 2048 * @wx: board private structure to initialize 2049 * 2050 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV. 2051 * 2052 **/ 2053 static void wx_cache_ring_rss(struct wx *wx) 2054 { 2055 u16 i; 2056 2057 if (wx_cache_ring_vmdq(wx)) 2058 return; 2059 2060 for (i = 0; i < wx->num_rx_queues; i++) 2061 wx->rx_ring[i]->reg_idx = i; 2062 2063 for (i = 0; i < wx->num_tx_queues; i++) 2064 wx->tx_ring[i]->reg_idx = i; 2065 } 2066 2067 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head) 2068 { 2069 ring->next = head->ring; 2070 head->ring = ring; 2071 head->count++; 2072 } 2073 2074 /** 2075 * wx_alloc_q_vector - Allocate memory for a single interrupt vector 2076 * @wx: board private structure to initialize 2077 * @v_count: q_vectors allocated on wx, used for ring interleaving 2078 * @v_idx: index of vector in wx struct 2079 * @txr_count: total number of Tx rings to allocate 2080 * @txr_idx: index of first Tx ring to allocate 2081 * @rxr_count: total number of Rx rings to allocate 2082 * @rxr_idx: index of first Rx ring to allocate 2083 * 2084 * We allocate one q_vector. If allocation fails we return -ENOMEM. 2085 **/ 2086 static int wx_alloc_q_vector(struct wx *wx, 2087 unsigned int v_count, unsigned int v_idx, 2088 unsigned int txr_count, unsigned int txr_idx, 2089 unsigned int rxr_count, unsigned int rxr_idx) 2090 { 2091 struct wx_q_vector *q_vector; 2092 int ring_count, default_itr; 2093 struct wx_ring *ring; 2094 2095 /* note this will allocate space for the ring structure as well! */ 2096 ring_count = txr_count + rxr_count; 2097 2098 q_vector = kzalloc_flex(*q_vector, ring, ring_count); 2099 if (!q_vector) 2100 return -ENOMEM; 2101 2102 /* initialize NAPI */ 2103 netif_napi_add(wx->netdev, &q_vector->napi, 2104 wx_poll); 2105 2106 /* tie q_vector and wx together */ 2107 wx->q_vector[v_idx] = q_vector; 2108 q_vector->wx = wx; 2109 q_vector->v_idx = v_idx; 2110 if (cpu_online(v_idx)) 2111 q_vector->numa_node = cpu_to_node(v_idx); 2112 2113 /* initialize pointer to rings */ 2114 ring = q_vector->ring; 2115 2116 switch (wx->mac.type) { 2117 case wx_mac_sp: 2118 case wx_mac_aml: 2119 case wx_mac_aml40: 2120 default_itr = WX_12K_ITR; 2121 break; 2122 default: 2123 default_itr = WX_7K_ITR; 2124 break; 2125 } 2126 2127 /* initialize ITR */ 2128 if (txr_count && !rxr_count) 2129 /* tx only vector */ 2130 q_vector->itr = wx->tx_itr_setting ? 2131 default_itr : wx->tx_itr_setting; 2132 else 2133 /* rx or rx/tx vector */ 2134 q_vector->itr = wx->rx_itr_setting ? 2135 default_itr : wx->rx_itr_setting; 2136 2137 while (txr_count) { 2138 /* assign generic ring traits */ 2139 ring->dev = &wx->pdev->dev; 2140 ring->netdev = wx->netdev; 2141 2142 /* configure backlink on ring */ 2143 ring->q_vector = q_vector; 2144 2145 /* update q_vector Tx values */ 2146 wx_add_ring(ring, &q_vector->tx); 2147 2148 /* apply Tx specific ring traits */ 2149 ring->count = wx->tx_ring_count; 2150 2151 ring->queue_index = txr_idx; 2152 2153 /* assign ring to wx */ 2154 wx->tx_ring[txr_idx] = ring; 2155 2156 /* update count and index */ 2157 txr_count--; 2158 txr_idx += v_count; 2159 2160 /* push pointer to next ring */ 2161 ring++; 2162 } 2163 2164 while (rxr_count) { 2165 /* assign generic ring traits */ 2166 ring->dev = &wx->pdev->dev; 2167 ring->netdev = wx->netdev; 2168 2169 /* configure backlink on ring */ 2170 ring->q_vector = q_vector; 2171 2172 /* update q_vector Rx values */ 2173 wx_add_ring(ring, &q_vector->rx); 2174 2175 /* apply Rx specific ring traits */ 2176 ring->count = wx->rx_ring_count; 2177 ring->queue_index = rxr_idx; 2178 2179 /* assign ring to wx */ 2180 wx->rx_ring[rxr_idx] = ring; 2181 2182 /* update count and index */ 2183 rxr_count--; 2184 rxr_idx += v_count; 2185 2186 /* push pointer to next ring */ 2187 ring++; 2188 } 2189 2190 return 0; 2191 } 2192 2193 /** 2194 * wx_free_q_vector - Free memory allocated for specific interrupt vector 2195 * @wx: board private structure to initialize 2196 * @v_idx: Index of vector to be freed 2197 * 2198 * This function frees the memory allocated to the q_vector. In addition if 2199 * NAPI is enabled it will delete any references to the NAPI struct prior 2200 * to freeing the q_vector. 2201 **/ 2202 static void wx_free_q_vector(struct wx *wx, int v_idx) 2203 { 2204 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2205 struct wx_ring *ring; 2206 2207 wx_for_each_ring(ring, q_vector->tx) 2208 wx->tx_ring[ring->queue_index] = NULL; 2209 2210 wx_for_each_ring(ring, q_vector->rx) 2211 wx->rx_ring[ring->queue_index] = NULL; 2212 2213 wx->q_vector[v_idx] = NULL; 2214 netif_napi_del(&q_vector->napi); 2215 kfree_rcu(q_vector, rcu); 2216 } 2217 2218 /** 2219 * wx_alloc_q_vectors - Allocate memory for interrupt vectors 2220 * @wx: board private structure to initialize 2221 * 2222 * We allocate one q_vector per queue interrupt. If allocation fails we 2223 * return -ENOMEM. 2224 **/ 2225 static int wx_alloc_q_vectors(struct wx *wx) 2226 { 2227 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 2228 unsigned int rxr_remaining = wx->num_rx_queues; 2229 unsigned int txr_remaining = wx->num_tx_queues; 2230 unsigned int q_vectors = wx->num_q_vectors; 2231 int rqpv, tqpv; 2232 int err; 2233 2234 for (; v_idx < q_vectors; v_idx++) { 2235 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 2236 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 2237 err = wx_alloc_q_vector(wx, q_vectors, v_idx, 2238 tqpv, txr_idx, 2239 rqpv, rxr_idx); 2240 2241 if (err) 2242 goto err_out; 2243 2244 /* update counts and index */ 2245 rxr_remaining -= rqpv; 2246 txr_remaining -= tqpv; 2247 rxr_idx++; 2248 txr_idx++; 2249 } 2250 2251 return 0; 2252 2253 err_out: 2254 wx->num_tx_queues = 0; 2255 wx->num_rx_queues = 0; 2256 wx->num_q_vectors = 0; 2257 2258 while (v_idx--) 2259 wx_free_q_vector(wx, v_idx); 2260 2261 return -ENOMEM; 2262 } 2263 2264 /** 2265 * wx_free_q_vectors - Free memory allocated for interrupt vectors 2266 * @wx: board private structure to initialize 2267 * 2268 * This function frees the memory allocated to the q_vectors. In addition if 2269 * NAPI is enabled it will delete any references to the NAPI struct prior 2270 * to freeing the q_vector. 2271 **/ 2272 static void wx_free_q_vectors(struct wx *wx) 2273 { 2274 int v_idx = wx->num_q_vectors; 2275 2276 wx->num_tx_queues = 0; 2277 wx->num_rx_queues = 0; 2278 wx->num_q_vectors = 0; 2279 2280 while (v_idx--) 2281 wx_free_q_vector(wx, v_idx); 2282 } 2283 2284 void wx_reset_interrupt_capability(struct wx *wx) 2285 { 2286 struct pci_dev *pdev = wx->pdev; 2287 2288 if (!pdev->msi_enabled && !pdev->msix_enabled) 2289 return; 2290 2291 if (pdev->msix_enabled) { 2292 kfree(wx->msix_q_entries); 2293 wx->msix_q_entries = NULL; 2294 kfree(wx->msix_entry); 2295 wx->msix_entry = NULL; 2296 } 2297 pci_free_irq_vectors(wx->pdev); 2298 } 2299 EXPORT_SYMBOL(wx_reset_interrupt_capability); 2300 2301 /** 2302 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings 2303 * @wx: board private structure to clear interrupt scheme on 2304 * 2305 * We go through and clear interrupt specific resources and reset the structure 2306 * to pre-load conditions 2307 **/ 2308 void wx_clear_interrupt_scheme(struct wx *wx) 2309 { 2310 wx_free_q_vectors(wx); 2311 wx_reset_interrupt_capability(wx); 2312 } 2313 EXPORT_SYMBOL(wx_clear_interrupt_scheme); 2314 2315 int wx_init_interrupt_scheme(struct wx *wx) 2316 { 2317 int ret; 2318 2319 /* Number of supported queues */ 2320 if (wx->pdev->is_virtfn) { 2321 if (wx->set_num_queues) 2322 wx->set_num_queues(wx); 2323 } else { 2324 wx_set_num_queues(wx); 2325 } 2326 2327 /* Set interrupt mode */ 2328 ret = wx_set_interrupt_capability(wx); 2329 if (ret) { 2330 wx_err(wx, "Allocate irq vectors for failed.\n"); 2331 return ret; 2332 } 2333 2334 /* Allocate memory for queues */ 2335 ret = wx_alloc_q_vectors(wx); 2336 if (ret) { 2337 wx_err(wx, "Unable to allocate memory for queue vectors.\n"); 2338 wx_reset_interrupt_capability(wx); 2339 return ret; 2340 } 2341 2342 wx_cache_ring_rss(wx); 2343 2344 return 0; 2345 } 2346 EXPORT_SYMBOL(wx_init_interrupt_scheme); 2347 2348 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data) 2349 { 2350 struct wx_q_vector *q_vector = data; 2351 2352 /* EIAM disabled interrupts (on this vector) for us */ 2353 if (q_vector->rx.ring || q_vector->tx.ring) { 2354 napi_schedule_irqoff(&q_vector->napi); 2355 q_vector->total_events++; 2356 } 2357 2358 return IRQ_HANDLED; 2359 } 2360 EXPORT_SYMBOL(wx_msix_clean_rings); 2361 2362 void wx_free_irq(struct wx *wx) 2363 { 2364 struct pci_dev *pdev = wx->pdev; 2365 int vector; 2366 2367 if (!(pdev->msix_enabled)) { 2368 if (!wx->misc_irq_domain) 2369 free_irq(pdev->irq, wx); 2370 return; 2371 } 2372 2373 for (vector = 0; vector < wx->num_q_vectors; vector++) { 2374 struct wx_q_vector *q_vector = wx->q_vector[vector]; 2375 struct msix_entry *entry = &wx->msix_q_entries[vector]; 2376 2377 /* free only the irqs that were actually requested */ 2378 if (!q_vector->rx.ring && !q_vector->tx.ring) 2379 continue; 2380 2381 free_irq(entry->vector, q_vector); 2382 } 2383 2384 if (!wx->misc_irq_domain) 2385 free_irq(wx->msix_entry->vector, wx); 2386 } 2387 EXPORT_SYMBOL(wx_free_irq); 2388 2389 /** 2390 * wx_setup_isb_resources - allocate interrupt status resources 2391 * @wx: board private structure 2392 * 2393 * Return 0 on success, negative on failure 2394 **/ 2395 int wx_setup_isb_resources(struct wx *wx) 2396 { 2397 struct pci_dev *pdev = wx->pdev; 2398 2399 if (wx->isb_mem) 2400 return 0; 2401 2402 wx->isb_mem = dma_alloc_coherent(&pdev->dev, 2403 sizeof(u32) * 4, 2404 &wx->isb_dma, 2405 GFP_KERNEL); 2406 if (!wx->isb_mem) { 2407 wx_err(wx, "Alloc isb_mem failed\n"); 2408 return -ENOMEM; 2409 } 2410 2411 return 0; 2412 } 2413 EXPORT_SYMBOL(wx_setup_isb_resources); 2414 2415 /** 2416 * wx_free_isb_resources - allocate all queues Rx resources 2417 * @wx: board private structure 2418 * 2419 * Return 0 on success, negative on failure 2420 **/ 2421 void wx_free_isb_resources(struct wx *wx) 2422 { 2423 struct pci_dev *pdev = wx->pdev; 2424 2425 dma_free_coherent(&pdev->dev, sizeof(u32) * 4, 2426 wx->isb_mem, wx->isb_dma); 2427 wx->isb_mem = NULL; 2428 } 2429 EXPORT_SYMBOL(wx_free_isb_resources); 2430 2431 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx) 2432 { 2433 u32 cur_tag = 0; 2434 2435 cur_tag = wx->isb_mem[WX_ISB_HEADER]; 2436 wx->isb_tag[idx] = cur_tag; 2437 2438 return (__force u32)cpu_to_le32(wx->isb_mem[idx]); 2439 } 2440 EXPORT_SYMBOL(wx_misc_isb); 2441 2442 /** 2443 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 2444 * @wx: pointer to wx struct 2445 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 2446 * @queue: queue to map the corresponding interrupt to 2447 * @msix_vector: the vector to map to the corresponding queue 2448 * 2449 **/ 2450 static void wx_set_ivar(struct wx *wx, s8 direction, 2451 u16 queue, u16 msix_vector) 2452 { 2453 u32 ivar, index; 2454 2455 if (direction == -1) { 2456 /* other causes */ 2457 if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) 2458 msix_vector = 0; 2459 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2460 index = 0; 2461 ivar = rd32(wx, WX_PX_MISC_IVAR); 2462 ivar &= ~(0xFF << index); 2463 ivar |= (msix_vector << index); 2464 wr32(wx, WX_PX_MISC_IVAR, ivar); 2465 } else { 2466 /* tx or rx causes */ 2467 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2468 index = ((16 * (queue & 1)) + (8 * direction)); 2469 ivar = rd32(wx, WX_PX_IVAR(queue >> 1)); 2470 ivar &= ~(0xFF << index); 2471 ivar |= (msix_vector << index); 2472 wr32(wx, WX_PX_IVAR(queue >> 1), ivar); 2473 } 2474 } 2475 2476 /** 2477 * wx_write_eitr - write EITR register in hardware specific way 2478 * @q_vector: structure containing interrupt and ring information 2479 * 2480 * This function is made to be called by ethtool and by the driver 2481 * when it needs to update EITR registers at runtime. Hardware 2482 * specific quirks/differences are taken care of here. 2483 */ 2484 void wx_write_eitr(struct wx_q_vector *q_vector) 2485 { 2486 struct wx *wx = q_vector->wx; 2487 int v_idx = q_vector->v_idx; 2488 u32 itr_reg; 2489 2490 switch (wx->mac.type) { 2491 case wx_mac_sp: 2492 itr_reg = q_vector->itr & WX_SP_MAX_EITR; 2493 break; 2494 case wx_mac_aml: 2495 case wx_mac_aml40: 2496 itr_reg = (q_vector->itr >> 3) & WX_AML_MAX_EITR; 2497 break; 2498 default: 2499 itr_reg = q_vector->itr & WX_EM_MAX_EITR; 2500 break; 2501 } 2502 2503 itr_reg |= WX_PX_ITR_CNT_WDIS; 2504 2505 wr32(wx, WX_PX_ITR(v_idx), itr_reg); 2506 } 2507 2508 /** 2509 * wx_configure_vectors - Configure vectors for hardware 2510 * @wx: board private structure 2511 * 2512 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx 2513 * interrupts. 2514 **/ 2515 void wx_configure_vectors(struct wx *wx) 2516 { 2517 struct pci_dev *pdev = wx->pdev; 2518 u32 eitrsel = 0; 2519 u16 v_idx, i; 2520 2521 if (pdev->msix_enabled) { 2522 /* Populate MSIX to EITR Select */ 2523 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2524 if (wx->num_vfs >= 32) 2525 eitrsel = BIT(wx->num_vfs % 32) - 1; 2526 } else { 2527 for (i = 0; i < wx->num_vfs; i++) 2528 eitrsel |= BIT(i); 2529 } 2530 wr32(wx, WX_PX_ITRSEL, eitrsel); 2531 /* use EIAM to auto-mask when MSI-X interrupt is asserted 2532 * this saves a register write for every interrupt 2533 */ 2534 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL); 2535 } else { 2536 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 2537 * specifically only auto mask tx and rx interrupts. 2538 */ 2539 wr32(wx, WX_PX_GPIE, 0); 2540 } 2541 2542 /* Populate the IVAR table and set the ITR values to the 2543 * corresponding register. 2544 */ 2545 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) { 2546 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2547 struct wx_ring *ring; 2548 2549 wx_for_each_ring(ring, q_vector->rx) 2550 wx_set_ivar(wx, 0, ring->reg_idx, v_idx); 2551 2552 wx_for_each_ring(ring, q_vector->tx) 2553 wx_set_ivar(wx, 1, ring->reg_idx, v_idx); 2554 2555 wx_write_eitr(q_vector); 2556 } 2557 2558 wx_set_ivar(wx, -1, 0, v_idx); 2559 if (pdev->msix_enabled) 2560 wr32(wx, WX_PX_ITR(v_idx), 1950); 2561 } 2562 EXPORT_SYMBOL(wx_configure_vectors); 2563 2564 /** 2565 * wx_clean_rx_ring - Free Rx Buffers per Queue 2566 * @rx_ring: ring to free buffers from 2567 **/ 2568 static void wx_clean_rx_ring(struct wx_ring *rx_ring) 2569 { 2570 struct wx_rx_buffer *rx_buffer; 2571 u16 i = rx_ring->next_to_clean; 2572 2573 rx_buffer = &rx_ring->rx_buffer_info[i]; 2574 2575 /* Free all the Rx ring sk_buffs */ 2576 while (i != rx_ring->next_to_alloc) { 2577 if (rx_buffer->skb) { 2578 struct sk_buff *skb = rx_buffer->skb; 2579 2580 dev_kfree_skb(skb); 2581 } 2582 2583 /* Invalidate cache lines that may have been written to by 2584 * device so that we avoid corrupting memory. 2585 */ 2586 dma_sync_single_range_for_cpu(rx_ring->dev, 2587 rx_buffer->dma, 2588 rx_buffer->page_offset, 2589 rx_ring->rx_buf_len, 2590 DMA_FROM_DEVICE); 2591 2592 /* free resources associated with mapping */ 2593 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2594 2595 i++; 2596 rx_buffer++; 2597 if (i == rx_ring->count) { 2598 i = 0; 2599 rx_buffer = rx_ring->rx_buffer_info; 2600 } 2601 } 2602 2603 /* Zero out the descriptor ring */ 2604 memset(rx_ring->desc, 0, rx_ring->size); 2605 2606 rx_ring->next_to_alloc = 0; 2607 rx_ring->next_to_clean = 0; 2608 rx_ring->next_to_use = 0; 2609 } 2610 2611 /** 2612 * wx_clean_all_rx_rings - Free Rx Buffers for all queues 2613 * @wx: board private structure 2614 **/ 2615 void wx_clean_all_rx_rings(struct wx *wx) 2616 { 2617 int i; 2618 2619 for (i = 0; i < wx->num_rx_queues; i++) 2620 wx_clean_rx_ring(wx->rx_ring[i]); 2621 } 2622 EXPORT_SYMBOL(wx_clean_all_rx_rings); 2623 2624 /** 2625 * wx_free_rx_resources - Free Rx Resources 2626 * @rx_ring: ring to clean the resources from 2627 * 2628 * Free all receive software resources 2629 **/ 2630 static void wx_free_rx_resources(struct wx_ring *rx_ring) 2631 { 2632 wx_clean_rx_ring(rx_ring); 2633 kvfree(rx_ring->rx_buffer_info); 2634 rx_ring->rx_buffer_info = NULL; 2635 2636 /* if not set, then don't free */ 2637 if (!rx_ring->desc) 2638 return; 2639 2640 dma_free_coherent(rx_ring->dev, rx_ring->size, 2641 rx_ring->desc, rx_ring->dma); 2642 2643 rx_ring->desc = NULL; 2644 2645 if (rx_ring->page_pool) { 2646 page_pool_destroy(rx_ring->page_pool); 2647 rx_ring->page_pool = NULL; 2648 } 2649 } 2650 2651 /** 2652 * wx_free_all_rx_resources - Free Rx Resources for All Queues 2653 * @wx: pointer to hardware structure 2654 * 2655 * Free all receive software resources 2656 **/ 2657 static void wx_free_all_rx_resources(struct wx *wx) 2658 { 2659 int i; 2660 2661 for (i = 0; i < wx->num_rx_queues; i++) 2662 wx_free_rx_resources(wx->rx_ring[i]); 2663 } 2664 2665 /** 2666 * wx_clean_tx_ring - Free Tx Buffers 2667 * @tx_ring: ring to be cleaned 2668 **/ 2669 static void wx_clean_tx_ring(struct wx_ring *tx_ring) 2670 { 2671 struct wx_tx_buffer *tx_buffer; 2672 u16 i = tx_ring->next_to_clean; 2673 2674 tx_buffer = &tx_ring->tx_buffer_info[i]; 2675 2676 while (i != tx_ring->next_to_use) { 2677 union wx_tx_desc *eop_desc, *tx_desc; 2678 2679 /* Free all the Tx ring sk_buffs */ 2680 dev_kfree_skb_any(tx_buffer->skb); 2681 2682 /* unmap skb header data */ 2683 dma_unmap_single(tx_ring->dev, 2684 dma_unmap_addr(tx_buffer, dma), 2685 dma_unmap_len(tx_buffer, len), 2686 DMA_TO_DEVICE); 2687 2688 /* check for eop_desc to determine the end of the packet */ 2689 eop_desc = tx_buffer->next_to_watch; 2690 tx_desc = WX_TX_DESC(tx_ring, i); 2691 2692 /* unmap remaining buffers */ 2693 while (tx_desc != eop_desc) { 2694 tx_buffer++; 2695 tx_desc++; 2696 i++; 2697 if (unlikely(i == tx_ring->count)) { 2698 i = 0; 2699 tx_buffer = tx_ring->tx_buffer_info; 2700 tx_desc = WX_TX_DESC(tx_ring, 0); 2701 } 2702 2703 /* unmap any remaining paged data */ 2704 if (dma_unmap_len(tx_buffer, len)) 2705 dma_unmap_page(tx_ring->dev, 2706 dma_unmap_addr(tx_buffer, dma), 2707 dma_unmap_len(tx_buffer, len), 2708 DMA_TO_DEVICE); 2709 } 2710 2711 /* move us one more past the eop_desc for start of next pkt */ 2712 tx_buffer++; 2713 i++; 2714 if (unlikely(i == tx_ring->count)) { 2715 i = 0; 2716 tx_buffer = tx_ring->tx_buffer_info; 2717 } 2718 } 2719 2720 netdev_tx_reset_queue(wx_txring_txq(tx_ring)); 2721 2722 /* reset next_to_use and next_to_clean */ 2723 tx_ring->next_to_use = 0; 2724 tx_ring->next_to_clean = 0; 2725 } 2726 2727 /** 2728 * wx_clean_all_tx_rings - Free Tx Buffers for all queues 2729 * @wx: board private structure 2730 **/ 2731 void wx_clean_all_tx_rings(struct wx *wx) 2732 { 2733 int i; 2734 2735 for (i = 0; i < wx->num_tx_queues; i++) 2736 wx_clean_tx_ring(wx->tx_ring[i]); 2737 } 2738 EXPORT_SYMBOL(wx_clean_all_tx_rings); 2739 2740 static void wx_free_headwb_resources(struct wx_ring *tx_ring) 2741 { 2742 if (!tx_ring->headwb_mem) 2743 return; 2744 2745 dma_free_coherent(tx_ring->dev, sizeof(u32), 2746 tx_ring->headwb_mem, tx_ring->headwb_dma); 2747 tx_ring->headwb_mem = NULL; 2748 } 2749 2750 /** 2751 * wx_free_tx_resources - Free Tx Resources per Queue 2752 * @tx_ring: Tx descriptor ring for a specific queue 2753 * 2754 * Free all transmit software resources 2755 **/ 2756 static void wx_free_tx_resources(struct wx_ring *tx_ring) 2757 { 2758 wx_clean_tx_ring(tx_ring); 2759 kvfree(tx_ring->tx_buffer_info); 2760 tx_ring->tx_buffer_info = NULL; 2761 2762 /* if not set, then don't free */ 2763 if (!tx_ring->desc) 2764 return; 2765 2766 dma_free_coherent(tx_ring->dev, tx_ring->size, 2767 tx_ring->desc, tx_ring->dma); 2768 tx_ring->desc = NULL; 2769 2770 wx_free_headwb_resources(tx_ring); 2771 } 2772 2773 /** 2774 * wx_free_all_tx_resources - Free Tx Resources for All Queues 2775 * @wx: pointer to hardware structure 2776 * 2777 * Free all transmit software resources 2778 **/ 2779 static void wx_free_all_tx_resources(struct wx *wx) 2780 { 2781 int i; 2782 2783 for (i = 0; i < wx->num_tx_queues; i++) 2784 wx_free_tx_resources(wx->tx_ring[i]); 2785 } 2786 2787 void wx_free_resources(struct wx *wx) 2788 { 2789 wx_free_all_rx_resources(wx); 2790 wx_free_all_tx_resources(wx); 2791 } 2792 EXPORT_SYMBOL(wx_free_resources); 2793 2794 static int wx_alloc_page_pool(struct wx_ring *rx_ring) 2795 { 2796 int ret = 0; 2797 2798 struct page_pool_params pp_params = { 2799 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2800 .order = wx_rx_pg_order(rx_ring), 2801 .pool_size = rx_ring->count * rx_ring->rx_buf_len / 2802 wx_rx_pg_size(rx_ring), 2803 .nid = dev_to_node(rx_ring->dev), 2804 .dev = rx_ring->dev, 2805 .dma_dir = DMA_FROM_DEVICE, 2806 .offset = 0, 2807 .max_len = wx_rx_pg_size(rx_ring), 2808 }; 2809 2810 rx_ring->page_pool = page_pool_create(&pp_params); 2811 if (IS_ERR(rx_ring->page_pool)) { 2812 ret = PTR_ERR(rx_ring->page_pool); 2813 rx_ring->page_pool = NULL; 2814 } 2815 2816 return ret; 2817 } 2818 2819 /** 2820 * wx_setup_rx_resources - allocate Rx resources (Descriptors) 2821 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2822 * 2823 * Returns 0 on success, negative on failure 2824 **/ 2825 static int wx_setup_rx_resources(struct wx_ring *rx_ring) 2826 { 2827 struct device *dev = rx_ring->dev; 2828 int orig_node = dev_to_node(dev); 2829 int numa_node = NUMA_NO_NODE; 2830 int size, ret; 2831 2832 size = sizeof(struct wx_rx_buffer) * rx_ring->count; 2833 2834 if (rx_ring->q_vector) 2835 numa_node = rx_ring->q_vector->numa_node; 2836 2837 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2838 if (!rx_ring->rx_buffer_info) 2839 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL); 2840 if (!rx_ring->rx_buffer_info) 2841 goto err; 2842 2843 /* Round up to nearest 4K */ 2844 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc); 2845 rx_ring->size = ALIGN(rx_ring->size, 4096); 2846 2847 set_dev_node(dev, numa_node); 2848 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2849 &rx_ring->dma, GFP_KERNEL); 2850 if (!rx_ring->desc) { 2851 set_dev_node(dev, orig_node); 2852 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2853 &rx_ring->dma, GFP_KERNEL); 2854 } 2855 2856 if (!rx_ring->desc) 2857 goto err; 2858 2859 rx_ring->next_to_clean = 0; 2860 rx_ring->next_to_use = 0; 2861 2862 ret = wx_alloc_page_pool(rx_ring); 2863 if (ret < 0) { 2864 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret); 2865 goto err_desc; 2866 } 2867 2868 return 0; 2869 2870 err_desc: 2871 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2872 err: 2873 kvfree(rx_ring->rx_buffer_info); 2874 rx_ring->rx_buffer_info = NULL; 2875 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2876 return -ENOMEM; 2877 } 2878 2879 /** 2880 * wx_setup_all_rx_resources - allocate all queues Rx resources 2881 * @wx: pointer to hardware structure 2882 * 2883 * If this function returns with an error, then it's possible one or 2884 * more of the rings is populated (while the rest are not). It is the 2885 * callers duty to clean those orphaned rings. 2886 * 2887 * Return 0 on success, negative on failure 2888 **/ 2889 static int wx_setup_all_rx_resources(struct wx *wx) 2890 { 2891 int i, err = 0; 2892 2893 for (i = 0; i < wx->num_rx_queues; i++) { 2894 err = wx_setup_rx_resources(wx->rx_ring[i]); 2895 if (!err) 2896 continue; 2897 2898 wx_err(wx, "Allocation for Rx Queue %u failed\n", i); 2899 goto err_setup_rx; 2900 } 2901 2902 return 0; 2903 err_setup_rx: 2904 /* rewind the index freeing the rings as we go */ 2905 while (i--) 2906 wx_free_rx_resources(wx->rx_ring[i]); 2907 return err; 2908 } 2909 2910 static void wx_setup_headwb_resources(struct wx_ring *tx_ring) 2911 { 2912 struct wx *wx = netdev_priv(tx_ring->netdev); 2913 2914 if (!test_bit(WX_FLAG_TXHEAD_WB_ENABLED, wx->flags)) 2915 return; 2916 2917 if (!tx_ring->q_vector) 2918 return; 2919 2920 tx_ring->headwb_mem = dma_alloc_coherent(tx_ring->dev, 2921 sizeof(u32), 2922 &tx_ring->headwb_dma, 2923 GFP_KERNEL); 2924 if (!tx_ring->headwb_mem) 2925 dev_info(tx_ring->dev, "Allocate headwb memory failed, disable it\n"); 2926 } 2927 2928 /** 2929 * wx_setup_tx_resources - allocate Tx resources (Descriptors) 2930 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2931 * 2932 * Return 0 on success, negative on failure 2933 **/ 2934 static int wx_setup_tx_resources(struct wx_ring *tx_ring) 2935 { 2936 struct device *dev = tx_ring->dev; 2937 int orig_node = dev_to_node(dev); 2938 int numa_node = NUMA_NO_NODE; 2939 int size; 2940 2941 size = sizeof(struct wx_tx_buffer) * tx_ring->count; 2942 2943 if (tx_ring->q_vector) 2944 numa_node = tx_ring->q_vector->numa_node; 2945 2946 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2947 if (!tx_ring->tx_buffer_info) 2948 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL); 2949 if (!tx_ring->tx_buffer_info) 2950 goto err; 2951 2952 /* round up to nearest 4K */ 2953 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc); 2954 tx_ring->size = ALIGN(tx_ring->size, 4096); 2955 2956 set_dev_node(dev, numa_node); 2957 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2958 &tx_ring->dma, GFP_KERNEL); 2959 if (!tx_ring->desc) { 2960 set_dev_node(dev, orig_node); 2961 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2962 &tx_ring->dma, GFP_KERNEL); 2963 } 2964 2965 if (!tx_ring->desc) 2966 goto err; 2967 2968 wx_setup_headwb_resources(tx_ring); 2969 2970 tx_ring->next_to_use = 0; 2971 tx_ring->next_to_clean = 0; 2972 2973 return 0; 2974 2975 err: 2976 kvfree(tx_ring->tx_buffer_info); 2977 tx_ring->tx_buffer_info = NULL; 2978 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2979 return -ENOMEM; 2980 } 2981 2982 /** 2983 * wx_setup_all_tx_resources - allocate all queues Tx resources 2984 * @wx: pointer to private structure 2985 * 2986 * If this function returns with an error, then it's possible one or 2987 * more of the rings is populated (while the rest are not). It is the 2988 * callers duty to clean those orphaned rings. 2989 * 2990 * Return 0 on success, negative on failure 2991 **/ 2992 static int wx_setup_all_tx_resources(struct wx *wx) 2993 { 2994 int i, err = 0; 2995 2996 for (i = 0; i < wx->num_tx_queues; i++) { 2997 err = wx_setup_tx_resources(wx->tx_ring[i]); 2998 if (!err) 2999 continue; 3000 3001 wx_err(wx, "Allocation for Tx Queue %u failed\n", i); 3002 goto err_setup_tx; 3003 } 3004 3005 return 0; 3006 err_setup_tx: 3007 /* rewind the index freeing the rings as we go */ 3008 while (i--) 3009 wx_free_tx_resources(wx->tx_ring[i]); 3010 return err; 3011 } 3012 3013 int wx_setup_resources(struct wx *wx) 3014 { 3015 int err; 3016 3017 /* allocate transmit descriptors */ 3018 err = wx_setup_all_tx_resources(wx); 3019 if (err) 3020 return err; 3021 3022 /* allocate receive descriptors */ 3023 err = wx_setup_all_rx_resources(wx); 3024 if (err) 3025 goto err_free_tx; 3026 3027 err = wx_setup_isb_resources(wx); 3028 if (err) 3029 goto err_free_rx; 3030 3031 return 0; 3032 3033 err_free_rx: 3034 wx_free_all_rx_resources(wx); 3035 err_free_tx: 3036 wx_free_all_tx_resources(wx); 3037 3038 return err; 3039 } 3040 EXPORT_SYMBOL(wx_setup_resources); 3041 3042 /** 3043 * wx_get_stats64 - Get System Network Statistics 3044 * @netdev: network interface device structure 3045 * @stats: storage space for 64bit statistics 3046 */ 3047 void wx_get_stats64(struct net_device *netdev, 3048 struct rtnl_link_stats64 *stats) 3049 { 3050 struct wx *wx = netdev_priv(netdev); 3051 struct wx_hw_stats *hwstats; 3052 int i; 3053 3054 wx_update_stats(wx); 3055 3056 rcu_read_lock(); 3057 for (i = 0; i < wx->num_rx_queues; i++) { 3058 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]); 3059 u64 bytes, packets; 3060 unsigned int start; 3061 3062 if (ring) { 3063 do { 3064 start = u64_stats_fetch_begin(&ring->syncp); 3065 packets = ring->stats.packets; 3066 bytes = ring->stats.bytes; 3067 } while (u64_stats_fetch_retry(&ring->syncp, start)); 3068 stats->rx_packets += packets; 3069 stats->rx_bytes += bytes; 3070 } 3071 } 3072 3073 for (i = 0; i < wx->num_tx_queues; i++) { 3074 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]); 3075 u64 bytes, packets; 3076 unsigned int start; 3077 3078 if (ring) { 3079 do { 3080 start = u64_stats_fetch_begin(&ring->syncp); 3081 packets = ring->stats.packets; 3082 bytes = ring->stats.bytes; 3083 } while (u64_stats_fetch_retry(&ring->syncp, 3084 start)); 3085 stats->tx_packets += packets; 3086 stats->tx_bytes += bytes; 3087 } 3088 } 3089 3090 rcu_read_unlock(); 3091 3092 hwstats = &wx->stats; 3093 stats->rx_errors = hwstats->crcerrs + hwstats->rlec; 3094 stats->multicast = hwstats->qmprc; 3095 stats->rx_length_errors = hwstats->rlec; 3096 stats->rx_crc_errors = hwstats->crcerrs; 3097 } 3098 EXPORT_SYMBOL(wx_get_stats64); 3099 3100 int wx_set_features(struct net_device *netdev, netdev_features_t features) 3101 { 3102 netdev_features_t changed = netdev->features ^ features; 3103 struct wx *wx = netdev_priv(netdev); 3104 bool need_reset = false; 3105 3106 wx->rss_enabled = !!(features & NETIF_F_RXHASH); 3107 wx_enable_rss(wx, wx->rss_enabled); 3108 3109 netdev->features = features; 3110 3111 if (changed & NETIF_F_HW_VLAN_CTAG_RX && wx->do_reset) 3112 wx->do_reset(netdev); 3113 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER)) 3114 wx_set_rx_mode(netdev); 3115 3116 if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) { 3117 if (!(features & NETIF_F_LRO)) { 3118 if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) 3119 need_reset = true; 3120 clear_bit(WX_FLAG_RSC_ENABLED, wx->flags); 3121 } else if (!(test_bit(WX_FLAG_RSC_ENABLED, wx->flags))) { 3122 if (wx->rx_itr_setting == 1 || 3123 wx->rx_itr_setting > WX_MIN_RSC_ITR) { 3124 set_bit(WX_FLAG_RSC_ENABLED, wx->flags); 3125 need_reset = true; 3126 } else if (changed & NETIF_F_LRO) { 3127 dev_info(&wx->pdev->dev, 3128 "rx-usecs set too low, disable RSC\n"); 3129 } 3130 } 3131 } 3132 3133 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 3134 goto out; 3135 3136 /* Check if Flow Director n-tuple support was enabled or disabled. If 3137 * the state changed, we need to reset. 3138 */ 3139 switch (features & NETIF_F_NTUPLE) { 3140 case NETIF_F_NTUPLE: 3141 /* turn off ATR, enable perfect filters and reset */ 3142 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 3143 need_reset = true; 3144 3145 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 3146 break; 3147 default: 3148 /* turn off perfect filters, enable ATR and reset */ 3149 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 3150 need_reset = true; 3151 3152 /* We cannot enable ATR if RSS is disabled */ 3153 if (wx->ring_feature[RING_F_RSS].limit <= 1) 3154 break; 3155 3156 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 3157 break; 3158 } 3159 3160 out: 3161 if (need_reset && wx->do_reset) 3162 wx->do_reset(netdev); 3163 3164 return 0; 3165 } 3166 EXPORT_SYMBOL(wx_set_features); 3167 3168 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \ 3169 NETIF_F_HW_VLAN_STAG_RX) 3170 3171 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \ 3172 NETIF_F_HW_VLAN_STAG_TX) 3173 3174 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \ 3175 NETIF_F_HW_VLAN_STAG_FILTER) 3176 3177 netdev_features_t wx_fix_features(struct net_device *netdev, 3178 netdev_features_t features) 3179 { 3180 netdev_features_t changed = netdev->features ^ features; 3181 struct wx *wx = netdev_priv(netdev); 3182 3183 if (changed & NETIF_VLAN_STRIPPING_FEATURES) { 3184 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES && 3185 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) { 3186 features &= ~NETIF_VLAN_STRIPPING_FEATURES; 3187 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES; 3188 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off."); 3189 } 3190 } 3191 3192 if (changed & NETIF_VLAN_INSERTION_FEATURES) { 3193 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES && 3194 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) { 3195 features &= ~NETIF_VLAN_INSERTION_FEATURES; 3196 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES; 3197 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off."); 3198 } 3199 } 3200 3201 if (changed & NETIF_VLAN_FILTERING_FEATURES) { 3202 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES && 3203 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) { 3204 features &= ~NETIF_VLAN_FILTERING_FEATURES; 3205 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES; 3206 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off."); 3207 } 3208 } 3209 3210 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ 3211 if (!(features & NETIF_F_RXCSUM)) 3212 features &= ~NETIF_F_LRO; 3213 3214 /* Turn off LRO if not RSC capable */ 3215 if (!test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) 3216 features &= ~NETIF_F_LRO; 3217 3218 return features; 3219 } 3220 EXPORT_SYMBOL(wx_fix_features); 3221 3222 #define WX_MAX_TUNNEL_HDR_LEN 80 3223 netdev_features_t wx_features_check(struct sk_buff *skb, 3224 struct net_device *netdev, 3225 netdev_features_t features) 3226 { 3227 struct wx *wx = netdev_priv(netdev); 3228 3229 if (!skb->encapsulation) 3230 return features; 3231 3232 if (wx->mac.type == wx_mac_em) 3233 return features & ~NETIF_F_CSUM_MASK; 3234 3235 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) > 3236 WX_MAX_TUNNEL_HDR_LEN)) 3237 return features & ~NETIF_F_CSUM_MASK; 3238 3239 if (skb->inner_protocol_type == ENCAP_TYPE_ETHER && 3240 skb->inner_protocol != htons(ETH_P_IP) && 3241 skb->inner_protocol != htons(ETH_P_IPV6) && 3242 skb->inner_protocol != htons(ETH_P_TEB)) 3243 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 3244 3245 return features; 3246 } 3247 EXPORT_SYMBOL(wx_features_check); 3248 3249 void wx_set_ring(struct wx *wx, u32 new_tx_count, 3250 u32 new_rx_count, struct wx_ring *temp_ring) 3251 { 3252 int i, err = 0; 3253 3254 /* Setup new Tx resources and free the old Tx resources in that order. 3255 * We can then assign the new resources to the rings via a memcpy. 3256 * The advantage to this approach is that we are guaranteed to still 3257 * have resources even in the case of an allocation failure. 3258 */ 3259 if (new_tx_count != wx->tx_ring_count) { 3260 for (i = 0; i < wx->num_tx_queues; i++) { 3261 memcpy(&temp_ring[i], wx->tx_ring[i], 3262 sizeof(struct wx_ring)); 3263 3264 temp_ring[i].count = new_tx_count; 3265 err = wx_setup_tx_resources(&temp_ring[i]); 3266 if (err) { 3267 wx_err(wx, "setup new tx resources failed, keep using the old config\n"); 3268 while (i) { 3269 i--; 3270 wx_free_tx_resources(&temp_ring[i]); 3271 } 3272 return; 3273 } 3274 } 3275 3276 for (i = 0; i < wx->num_tx_queues; i++) { 3277 wx_free_tx_resources(wx->tx_ring[i]); 3278 3279 memcpy(wx->tx_ring[i], &temp_ring[i], 3280 sizeof(struct wx_ring)); 3281 } 3282 3283 wx->tx_ring_count = new_tx_count; 3284 } 3285 3286 /* Repeat the process for the Rx rings if needed */ 3287 if (new_rx_count != wx->rx_ring_count) { 3288 for (i = 0; i < wx->num_rx_queues; i++) { 3289 memcpy(&temp_ring[i], wx->rx_ring[i], 3290 sizeof(struct wx_ring)); 3291 3292 temp_ring[i].count = new_rx_count; 3293 err = wx_setup_rx_resources(&temp_ring[i]); 3294 if (err) { 3295 wx_err(wx, "setup new rx resources failed, keep using the old config\n"); 3296 while (i) { 3297 i--; 3298 wx_free_rx_resources(&temp_ring[i]); 3299 } 3300 return; 3301 } 3302 } 3303 3304 for (i = 0; i < wx->num_rx_queues; i++) { 3305 wx_free_rx_resources(wx->rx_ring[i]); 3306 memcpy(wx->rx_ring[i], &temp_ring[i], 3307 sizeof(struct wx_ring)); 3308 } 3309 3310 wx->rx_ring_count = new_rx_count; 3311 } 3312 } 3313 EXPORT_SYMBOL(wx_set_ring); 3314 3315 void wx_service_event_schedule(struct wx *wx) 3316 { 3317 if (!test_and_set_bit(WX_STATE_SERVICE_SCHED, wx->state)) 3318 queue_work(system_power_efficient_wq, &wx->service_task); 3319 } 3320 EXPORT_SYMBOL(wx_service_event_schedule); 3321 3322 void wx_service_event_complete(struct wx *wx) 3323 { 3324 if (WARN_ON(!test_bit(WX_STATE_SERVICE_SCHED, wx->state))) 3325 return; 3326 3327 /* flush memory to make sure state is correct before next watchdog */ 3328 smp_mb__before_atomic(); 3329 clear_bit(WX_STATE_SERVICE_SCHED, wx->state); 3330 } 3331 EXPORT_SYMBOL(wx_service_event_complete); 3332 3333 void wx_service_timer(struct timer_list *t) 3334 { 3335 struct wx *wx = timer_container_of(wx, t, service_timer); 3336 unsigned long next_event_offset = HZ * 2; 3337 3338 /* Reset the timer */ 3339 mod_timer(&wx->service_timer, next_event_offset + jiffies); 3340 3341 wx_service_event_schedule(wx); 3342 } 3343 EXPORT_SYMBOL(wx_service_timer); 3344 3345 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers."); 3346 MODULE_LICENSE("GPL"); 3347