1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <net/ip6_checksum.h> 6 #include <net/page_pool/helpers.h> 7 #include <net/inet_ecn.h> 8 #include <linux/workqueue.h> 9 #include <linux/iopoll.h> 10 #include <linux/sctp.h> 11 #include <linux/pci.h> 12 #include <net/tcp.h> 13 #include <net/ip.h> 14 15 #include "wx_type.h" 16 #include "wx_lib.h" 17 #include "wx_ptp.h" 18 #include "wx_hw.h" 19 20 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 21 static struct wx_dec_ptype wx_ptype_lookup[256] = { 22 /* L2: mac */ 23 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 24 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2), 25 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 26 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 27 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 28 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 29 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 30 31 /* L2: ethertype filter */ 32 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 33 34 /* L3: ip non-tunnel */ 35 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3), 36 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3), 37 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4), 38 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4), 39 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4), 40 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3), 41 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3), 42 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3), 43 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4), 44 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4), 45 46 /* L2: fcoe */ 47 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 48 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 49 50 /* IPv4 --> IPv4/IPv6 */ 51 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3), 52 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3), 53 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4), 54 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4), 55 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4), 56 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3), 57 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3), 58 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4), 59 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4), 60 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4), 61 62 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */ 63 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3), 64 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3), 65 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3), 66 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4), 67 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4), 68 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4), 69 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3), 70 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3), 71 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4), 72 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4), 73 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4), 74 75 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */ 76 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3), 77 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3), 78 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3), 79 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4), 80 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4), 81 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4), 82 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3), 83 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3), 84 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4), 85 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4), 86 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4), 87 88 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */ 89 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3), 90 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3), 91 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3), 92 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4), 93 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4), 94 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4), 95 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3), 96 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3), 97 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4), 98 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4), 99 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4), 100 101 /* IPv6 --> IPv4/IPv6 */ 102 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3), 103 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3), 104 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4), 105 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4), 106 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4), 107 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3), 108 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3), 109 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4), 110 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4), 111 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4), 112 113 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */ 114 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3), 115 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3), 116 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3), 117 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4), 118 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4), 119 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4), 120 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3), 121 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3), 122 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4), 123 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4), 124 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4), 125 126 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */ 127 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3), 128 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3), 129 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3), 130 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4), 131 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4), 132 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4), 133 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3), 134 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3), 135 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4), 136 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4), 137 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4), 138 139 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */ 140 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3), 141 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3), 142 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3), 143 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4), 144 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4), 145 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4), 146 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3), 147 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3), 148 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4), 149 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4), 150 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4), 151 }; 152 153 struct wx_dec_ptype wx_decode_ptype(const u8 ptype) 154 { 155 return wx_ptype_lookup[ptype]; 156 } 157 EXPORT_SYMBOL(wx_decode_ptype); 158 159 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */ 160 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc, 161 const u32 stat_err_bits) 162 { 163 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 164 } 165 166 static void wx_dma_sync_frag(struct wx_ring *rx_ring, 167 struct wx_rx_buffer *rx_buffer) 168 { 169 struct sk_buff *skb = rx_buffer->skb; 170 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 171 172 dma_sync_single_range_for_cpu(rx_ring->dev, 173 WX_CB(skb)->dma, 174 skb_frag_off(frag), 175 skb_frag_size(frag), 176 DMA_FROM_DEVICE); 177 } 178 179 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring, 180 union wx_rx_desc *rx_desc, 181 struct sk_buff **skb, 182 int *rx_buffer_pgcnt) 183 { 184 struct wx_rx_buffer *rx_buffer; 185 unsigned int size; 186 187 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 188 size = le16_to_cpu(rx_desc->wb.upper.length); 189 190 #if (PAGE_SIZE < 8192) 191 *rx_buffer_pgcnt = page_count(rx_buffer->page); 192 #else 193 *rx_buffer_pgcnt = 0; 194 #endif 195 196 prefetchw(rx_buffer->page); 197 *skb = rx_buffer->skb; 198 199 /* Delay unmapping of the first packet. It carries the header 200 * information, HW may still access the header after the writeback. 201 * Only unmap it when EOP is reached 202 */ 203 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) { 204 if (!*skb) 205 goto skip_sync; 206 } else { 207 if (*skb) 208 wx_dma_sync_frag(rx_ring, rx_buffer); 209 } 210 211 /* we are reusing so sync this buffer for CPU use */ 212 dma_sync_single_range_for_cpu(rx_ring->dev, 213 rx_buffer->dma, 214 rx_buffer->page_offset, 215 size, 216 DMA_FROM_DEVICE); 217 skip_sync: 218 return rx_buffer; 219 } 220 221 static void wx_put_rx_buffer(struct wx_ring *rx_ring, 222 struct wx_rx_buffer *rx_buffer, 223 struct sk_buff *skb, 224 int rx_buffer_pgcnt) 225 { 226 /* clear contents of rx_buffer */ 227 rx_buffer->page = NULL; 228 rx_buffer->skb = NULL; 229 } 230 231 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring, 232 struct wx_rx_buffer *rx_buffer, 233 union wx_rx_desc *rx_desc) 234 { 235 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 236 #if (PAGE_SIZE < 8192) 237 unsigned int truesize = WX_RX_BUFSZ; 238 #else 239 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 240 #endif 241 struct sk_buff *skb = rx_buffer->skb; 242 243 if (!skb) { 244 void *page_addr = page_address(rx_buffer->page) + 245 rx_buffer->page_offset; 246 247 /* prefetch first cache line of first page */ 248 net_prefetch(page_addr); 249 250 /* allocate a skb to store the frags */ 251 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256); 252 if (unlikely(!skb)) 253 return NULL; 254 255 /* we will be copying header into skb->data in 256 * pskb_may_pull so it is in our interest to prefetch 257 * it now to avoid a possible cache miss 258 */ 259 prefetchw(skb->data); 260 261 if (size <= WX_RXBUFFER_256) { 262 memcpy(__skb_put(skb, size), page_addr, 263 ALIGN(size, sizeof(long))); 264 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true); 265 return skb; 266 } 267 268 skb_mark_for_recycle(skb); 269 270 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) 271 WX_CB(skb)->dma = rx_buffer->dma; 272 273 skb_add_rx_frag(skb, 0, rx_buffer->page, 274 rx_buffer->page_offset, 275 size, truesize); 276 goto out; 277 278 } else { 279 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 280 rx_buffer->page_offset, size, truesize); 281 } 282 283 out: 284 #if (PAGE_SIZE < 8192) 285 /* flip page offset to other buffer */ 286 rx_buffer->page_offset ^= truesize; 287 #else 288 /* move offset up to the next cache line */ 289 rx_buffer->page_offset += truesize; 290 #endif 291 292 return skb; 293 } 294 295 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring, 296 struct wx_rx_buffer *bi) 297 { 298 struct page *page = bi->page; 299 dma_addr_t dma; 300 301 /* since we are recycling buffers we should seldom need to alloc */ 302 if (likely(page)) 303 return true; 304 305 page = page_pool_dev_alloc_pages(rx_ring->page_pool); 306 if (unlikely(!page)) 307 return false; 308 dma = page_pool_get_dma_addr(page); 309 310 bi->dma = dma; 311 bi->page = page; 312 bi->page_offset = 0; 313 314 return true; 315 } 316 317 /** 318 * wx_alloc_rx_buffers - Replace used receive buffers 319 * @rx_ring: ring to place buffers on 320 * @cleaned_count: number of buffers to replace 321 **/ 322 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count) 323 { 324 u16 i = rx_ring->next_to_use; 325 union wx_rx_desc *rx_desc; 326 struct wx_rx_buffer *bi; 327 328 /* nothing to do */ 329 if (!cleaned_count) 330 return; 331 332 rx_desc = WX_RX_DESC(rx_ring, i); 333 bi = &rx_ring->rx_buffer_info[i]; 334 i -= rx_ring->count; 335 336 do { 337 if (!wx_alloc_mapped_page(rx_ring, bi)) 338 break; 339 340 /* sync the buffer for use by the device */ 341 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 342 bi->page_offset, 343 WX_RX_BUFSZ, 344 DMA_FROM_DEVICE); 345 346 rx_desc->read.pkt_addr = 347 cpu_to_le64(bi->dma + bi->page_offset); 348 349 rx_desc++; 350 bi++; 351 i++; 352 if (unlikely(!i)) { 353 rx_desc = WX_RX_DESC(rx_ring, 0); 354 bi = rx_ring->rx_buffer_info; 355 i -= rx_ring->count; 356 } 357 358 /* clear the status bits for the next_to_use descriptor */ 359 rx_desc->wb.upper.status_error = 0; 360 /* clear the length for the next_to_use descriptor */ 361 rx_desc->wb.upper.length = 0; 362 363 cleaned_count--; 364 } while (cleaned_count); 365 366 i += rx_ring->count; 367 368 if (rx_ring->next_to_use != i) { 369 rx_ring->next_to_use = i; 370 /* update next to alloc since we have filled the ring */ 371 rx_ring->next_to_alloc = i; 372 373 /* Force memory writes to complete before letting h/w 374 * know there are new descriptors to fetch. (Only 375 * applicable for weak-ordered memory model archs, 376 * such as IA-64). 377 */ 378 wmb(); 379 writel(i, rx_ring->tail); 380 } 381 } 382 383 u16 wx_desc_unused(struct wx_ring *ring) 384 { 385 u16 ntc = ring->next_to_clean; 386 u16 ntu = ring->next_to_use; 387 388 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 389 } 390 391 /** 392 * wx_is_non_eop - process handling of non-EOP buffers 393 * @rx_ring: Rx ring being processed 394 * @rx_desc: Rx descriptor for current buffer 395 * @skb: Current socket buffer containing buffer in progress 396 * 397 * This function updates next to clean. If the buffer is an EOP buffer 398 * this function exits returning false, otherwise it will place the 399 * sk_buff in the next buffer to be chained and return true indicating 400 * that this is in fact a non-EOP buffer. 401 **/ 402 static bool wx_is_non_eop(struct wx_ring *rx_ring, 403 union wx_rx_desc *rx_desc, 404 struct sk_buff *skb) 405 { 406 u32 ntc = rx_ring->next_to_clean + 1; 407 408 /* fetch, update, and store next to clean */ 409 ntc = (ntc < rx_ring->count) ? ntc : 0; 410 rx_ring->next_to_clean = ntc; 411 412 prefetch(WX_RX_DESC(rx_ring, ntc)); 413 414 /* if we are the last buffer then there is nothing else to do */ 415 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))) 416 return false; 417 418 rx_ring->rx_buffer_info[ntc].skb = skb; 419 rx_ring->rx_stats.non_eop_descs++; 420 421 return true; 422 } 423 424 static void wx_pull_tail(struct sk_buff *skb) 425 { 426 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 427 unsigned int pull_len; 428 unsigned char *va; 429 430 /* it is valid to use page_address instead of kmap since we are 431 * working with pages allocated out of the lomem pool per 432 * alloc_page(GFP_ATOMIC) 433 */ 434 va = skb_frag_address(frag); 435 436 /* we need the header to contain the greater of either ETH_HLEN or 437 * 60 bytes if the skb->len is less than 60 for skb_pad. 438 */ 439 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256); 440 441 /* align pull length to size of long to optimize memcpy performance */ 442 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 443 444 /* update all of the pointers */ 445 skb_frag_size_sub(frag, pull_len); 446 skb_frag_off_add(frag, pull_len); 447 skb->data_len -= pull_len; 448 skb->tail += pull_len; 449 } 450 451 /** 452 * wx_cleanup_headers - Correct corrupted or empty headers 453 * @rx_ring: rx descriptor ring packet is being transacted on 454 * @rx_desc: pointer to the EOP Rx descriptor 455 * @skb: pointer to current skb being fixed 456 * 457 * Check for corrupted packet headers caused by senders on the local L2 458 * embedded NIC switch not setting up their Tx Descriptors right. These 459 * should be very rare. 460 * 461 * Also address the case where we are pulling data in on pages only 462 * and as such no data is present in the skb header. 463 * 464 * In addition if skb is not at least 60 bytes we need to pad it so that 465 * it is large enough to qualify as a valid Ethernet frame. 466 * 467 * Returns true if an error was encountered and skb was freed. 468 **/ 469 static bool wx_cleanup_headers(struct wx_ring *rx_ring, 470 union wx_rx_desc *rx_desc, 471 struct sk_buff *skb) 472 { 473 struct net_device *netdev = rx_ring->netdev; 474 475 /* verify that the packet does not have any known errors */ 476 if (!netdev || 477 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) && 478 !(netdev->features & NETIF_F_RXALL))) { 479 dev_kfree_skb_any(skb); 480 return true; 481 } 482 483 /* place header in linear portion of buffer */ 484 if (!skb_headlen(skb)) 485 wx_pull_tail(skb); 486 487 /* if eth_skb_pad returns an error the skb was freed */ 488 if (eth_skb_pad(skb)) 489 return true; 490 491 return false; 492 } 493 494 static void wx_rx_hash(struct wx_ring *ring, 495 union wx_rx_desc *rx_desc, 496 struct sk_buff *skb) 497 { 498 u16 rss_type; 499 500 if (!(ring->netdev->features & NETIF_F_RXHASH)) 501 return; 502 503 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 504 WX_RXD_RSSTYPE_MASK; 505 506 if (!rss_type) 507 return; 508 509 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 510 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 511 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 512 } 513 514 /** 515 * wx_rx_checksum - indicate in skb if hw indicated a good cksum 516 * @ring: structure containing ring specific data 517 * @rx_desc: current Rx descriptor being processed 518 * @skb: skb currently being received and modified 519 **/ 520 static void wx_rx_checksum(struct wx_ring *ring, 521 union wx_rx_desc *rx_desc, 522 struct sk_buff *skb) 523 { 524 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc)); 525 526 skb_checksum_none_assert(skb); 527 /* Rx csum disabled */ 528 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 529 return; 530 531 /* if IPv4 header checksum error */ 532 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) && 533 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) || 534 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) && 535 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) { 536 ring->rx_stats.csum_err++; 537 return; 538 } 539 540 /* L4 checksum offload flag must set for the below code to work */ 541 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS)) 542 return; 543 544 /* Hardware can't guarantee csum if IPv6 Dest Header found */ 545 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && 546 wx_test_staterr(rx_desc, WX_RXD_STAT_IPV6EX)) 547 return; 548 549 /* if L4 checksum error */ 550 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) { 551 ring->rx_stats.csum_err++; 552 return; 553 } 554 555 /* It must be a TCP or UDP or SCTP packet with a valid checksum */ 556 skb->ip_summed = CHECKSUM_UNNECESSARY; 557 558 /* If there is an outer header present that might contain a checksum 559 * we need to bump the checksum level by 1 to reflect the fact that 560 * we are indicating we validated the inner checksum. 561 */ 562 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG) 563 __skb_incr_checksum_unnecessary(skb); 564 ring->rx_stats.csum_good_cnt++; 565 } 566 567 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc, 568 struct sk_buff *skb) 569 { 570 u16 ethertype; 571 u8 idx = 0; 572 573 if ((ring->netdev->features & 574 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) && 575 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) { 576 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 577 0x1c0) >> 6; 578 ethertype = ring->q_vector->wx->tpid[idx]; 579 __vlan_hwaccel_put_tag(skb, htons(ethertype), 580 le16_to_cpu(rx_desc->wb.upper.vlan)); 581 } 582 } 583 584 /** 585 * wx_process_skb_fields - Populate skb header fields from Rx descriptor 586 * @rx_ring: rx descriptor ring packet is being transacted on 587 * @rx_desc: pointer to the EOP Rx descriptor 588 * @skb: pointer to current skb being populated 589 * 590 * This function checks the ring, descriptor, and packet information in 591 * order to populate the hash, checksum, protocol, and 592 * other fields within the skb. 593 **/ 594 static void wx_process_skb_fields(struct wx_ring *rx_ring, 595 union wx_rx_desc *rx_desc, 596 struct sk_buff *skb) 597 { 598 struct wx *wx = netdev_priv(rx_ring->netdev); 599 600 wx_rx_hash(rx_ring, rx_desc, skb); 601 wx_rx_checksum(rx_ring, rx_desc, skb); 602 603 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, wx->flags)) && 604 unlikely(wx_test_staterr(rx_desc, WX_RXD_STAT_TS))) { 605 wx_ptp_rx_hwtstamp(rx_ring->q_vector->wx, skb); 606 rx_ring->last_rx_timestamp = jiffies; 607 } 608 609 wx_rx_vlan(rx_ring, rx_desc, skb); 610 skb_record_rx_queue(skb, rx_ring->queue_index); 611 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 612 } 613 614 /** 615 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 616 * @q_vector: structure containing interrupt and ring information 617 * @rx_ring: rx descriptor ring to transact packets on 618 * @budget: Total limit on number of packets to process 619 * 620 * This function provides a "bounce buffer" approach to Rx interrupt 621 * processing. The advantage to this is that on systems that have 622 * expensive overhead for IOMMU access this provides a means of avoiding 623 * it by maintaining the mapping of the page to the system. 624 * 625 * Returns amount of work completed. 626 **/ 627 static int wx_clean_rx_irq(struct wx_q_vector *q_vector, 628 struct wx_ring *rx_ring, 629 int budget) 630 { 631 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 632 u16 cleaned_count = wx_desc_unused(rx_ring); 633 634 do { 635 struct wx_rx_buffer *rx_buffer; 636 union wx_rx_desc *rx_desc; 637 struct sk_buff *skb; 638 int rx_buffer_pgcnt; 639 640 /* return some buffers to hardware, one at a time is too slow */ 641 if (cleaned_count >= WX_RX_BUFFER_WRITE) { 642 wx_alloc_rx_buffers(rx_ring, cleaned_count); 643 cleaned_count = 0; 644 } 645 646 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean); 647 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD)) 648 break; 649 650 /* This memory barrier is needed to keep us from reading 651 * any other fields out of the rx_desc until we know the 652 * descriptor has been written back 653 */ 654 dma_rmb(); 655 656 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt); 657 658 /* retrieve a buffer from the ring */ 659 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc); 660 661 /* exit if we failed to retrieve a buffer */ 662 if (!skb) { 663 rx_ring->rx_stats.alloc_rx_buff_failed++; 664 break; 665 } 666 667 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 668 cleaned_count++; 669 670 /* place incomplete frames back on ring for completion */ 671 if (wx_is_non_eop(rx_ring, rx_desc, skb)) 672 continue; 673 674 /* verify the packet layout is correct */ 675 if (wx_cleanup_headers(rx_ring, rx_desc, skb)) 676 continue; 677 678 /* probably a little skewed due to removing CRC */ 679 total_rx_bytes += skb->len; 680 681 /* populate checksum, timestamp, VLAN, and protocol */ 682 wx_process_skb_fields(rx_ring, rx_desc, skb); 683 napi_gro_receive(&q_vector->napi, skb); 684 685 /* update budget accounting */ 686 total_rx_packets++; 687 } while (likely(total_rx_packets < budget)); 688 689 u64_stats_update_begin(&rx_ring->syncp); 690 rx_ring->stats.packets += total_rx_packets; 691 rx_ring->stats.bytes += total_rx_bytes; 692 u64_stats_update_end(&rx_ring->syncp); 693 q_vector->rx.total_packets += total_rx_packets; 694 q_vector->rx.total_bytes += total_rx_bytes; 695 696 return total_rx_packets; 697 } 698 699 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring) 700 { 701 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 702 } 703 704 /** 705 * wx_clean_tx_irq - Reclaim resources after transmit completes 706 * @q_vector: structure containing interrupt and ring information 707 * @tx_ring: tx ring to clean 708 * @napi_budget: Used to determine if we are in netpoll 709 **/ 710 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector, 711 struct wx_ring *tx_ring, int napi_budget) 712 { 713 unsigned int budget = q_vector->wx->tx_work_limit; 714 unsigned int total_bytes = 0, total_packets = 0; 715 struct wx *wx = netdev_priv(tx_ring->netdev); 716 unsigned int i = tx_ring->next_to_clean; 717 struct wx_tx_buffer *tx_buffer; 718 union wx_tx_desc *tx_desc; 719 720 if (!netif_carrier_ok(tx_ring->netdev)) 721 return true; 722 723 tx_buffer = &tx_ring->tx_buffer_info[i]; 724 tx_desc = WX_TX_DESC(tx_ring, i); 725 i -= tx_ring->count; 726 727 do { 728 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch; 729 730 /* if next_to_watch is not set then there is no work pending */ 731 if (!eop_desc) 732 break; 733 734 /* prevent any other reads prior to eop_desc */ 735 smp_rmb(); 736 737 /* if DD is not set pending work has not been completed */ 738 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) 739 break; 740 741 /* clear next_to_watch to prevent false hangs */ 742 tx_buffer->next_to_watch = NULL; 743 744 /* update the statistics for this packet */ 745 total_bytes += tx_buffer->bytecount; 746 total_packets += tx_buffer->gso_segs; 747 748 /* schedule check for Tx timestamp */ 749 if (unlikely(test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state)) && 750 skb_shinfo(tx_buffer->skb)->tx_flags & SKBTX_IN_PROGRESS) 751 ptp_schedule_worker(wx->ptp_clock, 0); 752 753 /* free the skb */ 754 napi_consume_skb(tx_buffer->skb, napi_budget); 755 756 /* unmap skb header data */ 757 dma_unmap_single(tx_ring->dev, 758 dma_unmap_addr(tx_buffer, dma), 759 dma_unmap_len(tx_buffer, len), 760 DMA_TO_DEVICE); 761 762 /* clear tx_buffer data */ 763 dma_unmap_len_set(tx_buffer, len, 0); 764 765 /* unmap remaining buffers */ 766 while (tx_desc != eop_desc) { 767 tx_buffer++; 768 tx_desc++; 769 i++; 770 if (unlikely(!i)) { 771 i -= tx_ring->count; 772 tx_buffer = tx_ring->tx_buffer_info; 773 tx_desc = WX_TX_DESC(tx_ring, 0); 774 } 775 776 /* unmap any remaining paged data */ 777 if (dma_unmap_len(tx_buffer, len)) { 778 dma_unmap_page(tx_ring->dev, 779 dma_unmap_addr(tx_buffer, dma), 780 dma_unmap_len(tx_buffer, len), 781 DMA_TO_DEVICE); 782 dma_unmap_len_set(tx_buffer, len, 0); 783 } 784 } 785 786 /* move us one more past the eop_desc for start of next pkt */ 787 tx_buffer++; 788 tx_desc++; 789 i++; 790 if (unlikely(!i)) { 791 i -= tx_ring->count; 792 tx_buffer = tx_ring->tx_buffer_info; 793 tx_desc = WX_TX_DESC(tx_ring, 0); 794 } 795 796 /* issue prefetch for next Tx descriptor */ 797 prefetch(tx_desc); 798 799 /* update budget accounting */ 800 budget--; 801 } while (likely(budget)); 802 803 i += tx_ring->count; 804 tx_ring->next_to_clean = i; 805 u64_stats_update_begin(&tx_ring->syncp); 806 tx_ring->stats.bytes += total_bytes; 807 tx_ring->stats.packets += total_packets; 808 u64_stats_update_end(&tx_ring->syncp); 809 q_vector->tx.total_bytes += total_bytes; 810 q_vector->tx.total_packets += total_packets; 811 812 netdev_tx_completed_queue(wx_txring_txq(tx_ring), 813 total_packets, total_bytes); 814 815 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 816 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 817 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 818 /* Make sure that anybody stopping the queue after this 819 * sees the new next_to_clean. 820 */ 821 smp_mb(); 822 823 if (__netif_subqueue_stopped(tx_ring->netdev, 824 tx_ring->queue_index) && 825 netif_running(tx_ring->netdev)) { 826 netif_wake_subqueue(tx_ring->netdev, 827 tx_ring->queue_index); 828 ++tx_ring->tx_stats.restart_queue; 829 } 830 } 831 832 return !!budget; 833 } 834 835 /** 836 * wx_poll - NAPI polling RX/TX cleanup routine 837 * @napi: napi struct with our devices info in it 838 * @budget: amount of work driver is allowed to do this pass, in packets 839 * 840 * This function will clean all queues associated with a q_vector. 841 **/ 842 static int wx_poll(struct napi_struct *napi, int budget) 843 { 844 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi); 845 int per_ring_budget, work_done = 0; 846 struct wx *wx = q_vector->wx; 847 bool clean_complete = true; 848 struct wx_ring *ring; 849 850 wx_for_each_ring(ring, q_vector->tx) { 851 if (!wx_clean_tx_irq(q_vector, ring, budget)) 852 clean_complete = false; 853 } 854 855 /* Exit if we are called by netpoll */ 856 if (budget <= 0) 857 return budget; 858 859 /* attempt to distribute budget to each queue fairly, but don't allow 860 * the budget to go below 1 because we'll exit polling 861 */ 862 if (q_vector->rx.count > 1) 863 per_ring_budget = max(budget / q_vector->rx.count, 1); 864 else 865 per_ring_budget = budget; 866 867 wx_for_each_ring(ring, q_vector->rx) { 868 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget); 869 870 work_done += cleaned; 871 if (cleaned >= per_ring_budget) 872 clean_complete = false; 873 } 874 875 /* If all work not completed, return budget and keep polling */ 876 if (!clean_complete) 877 return budget; 878 879 /* all work done, exit the polling mode */ 880 if (likely(napi_complete_done(napi, work_done))) { 881 if (netif_running(wx->netdev)) 882 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx)); 883 } 884 885 return min(work_done, budget - 1); 886 } 887 888 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size) 889 { 890 if (likely(wx_desc_unused(tx_ring) >= size)) 891 return 0; 892 893 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 894 895 /* For the next check */ 896 smp_mb(); 897 898 /* We need to check again in a case another CPU has just 899 * made room available. 900 */ 901 if (likely(wx_desc_unused(tx_ring) < size)) 902 return -EBUSY; 903 904 /* A reprieve! - use start_queue because it doesn't call schedule */ 905 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 906 ++tx_ring->tx_stats.restart_queue; 907 908 return 0; 909 } 910 911 static u32 wx_tx_cmd_type(u32 tx_flags) 912 { 913 /* set type for advanced descriptor with frame checksum insertion */ 914 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS; 915 916 /* set HW vlan bit if vlan is present */ 917 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE); 918 /* set segmentation enable bits for TSO/FSO */ 919 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE); 920 /* set timestamp bit if present */ 921 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP); 922 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC); 923 924 return cmd_type; 925 } 926 927 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc, 928 u32 tx_flags, unsigned int paylen) 929 { 930 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT; 931 932 /* enable L4 checksum for TSO and TX checksum offload */ 933 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS); 934 /* enable IPv4 checksum for TSO */ 935 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS); 936 /* enable outer IPv4 checksum for TSO */ 937 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4, 938 WX_TXD_EIPCS); 939 /* Check Context must be set if Tx switch is enabled, which it 940 * always is for case where virtual functions are running 941 */ 942 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC); 943 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC, 944 WX_TXD_IPSEC); 945 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 946 } 947 948 static int wx_tx_map(struct wx_ring *tx_ring, 949 struct wx_tx_buffer *first, 950 const u8 hdr_len) 951 { 952 struct sk_buff *skb = first->skb; 953 struct wx_tx_buffer *tx_buffer; 954 u32 tx_flags = first->tx_flags; 955 u16 i = tx_ring->next_to_use; 956 unsigned int data_len, size; 957 union wx_tx_desc *tx_desc; 958 skb_frag_t *frag; 959 dma_addr_t dma; 960 u32 cmd_type; 961 962 cmd_type = wx_tx_cmd_type(tx_flags); 963 tx_desc = WX_TX_DESC(tx_ring, i); 964 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 965 966 size = skb_headlen(skb); 967 data_len = skb->data_len; 968 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 969 970 tx_buffer = first; 971 972 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 973 if (dma_mapping_error(tx_ring->dev, dma)) 974 goto dma_error; 975 976 /* record length, and DMA address */ 977 dma_unmap_len_set(tx_buffer, len, size); 978 dma_unmap_addr_set(tx_buffer, dma, dma); 979 980 tx_desc->read.buffer_addr = cpu_to_le64(dma); 981 982 while (unlikely(size > WX_MAX_DATA_PER_TXD)) { 983 tx_desc->read.cmd_type_len = 984 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD); 985 986 i++; 987 tx_desc++; 988 if (i == tx_ring->count) { 989 tx_desc = WX_TX_DESC(tx_ring, 0); 990 i = 0; 991 } 992 tx_desc->read.olinfo_status = 0; 993 994 dma += WX_MAX_DATA_PER_TXD; 995 size -= WX_MAX_DATA_PER_TXD; 996 997 tx_desc->read.buffer_addr = cpu_to_le64(dma); 998 } 999 1000 if (likely(!data_len)) 1001 break; 1002 1003 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 1004 1005 i++; 1006 tx_desc++; 1007 if (i == tx_ring->count) { 1008 tx_desc = WX_TX_DESC(tx_ring, 0); 1009 i = 0; 1010 } 1011 tx_desc->read.olinfo_status = 0; 1012 1013 size = skb_frag_size(frag); 1014 1015 data_len -= size; 1016 1017 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1018 DMA_TO_DEVICE); 1019 1020 tx_buffer = &tx_ring->tx_buffer_info[i]; 1021 } 1022 1023 /* write last descriptor with RS and EOP bits */ 1024 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS; 1025 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1026 1027 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount); 1028 1029 /* set the timestamp */ 1030 first->time_stamp = jiffies; 1031 skb_tx_timestamp(skb); 1032 1033 /* Force memory writes to complete before letting h/w know there 1034 * are new descriptors to fetch. (Only applicable for weak-ordered 1035 * memory model archs, such as IA-64). 1036 * 1037 * We also need this memory barrier to make certain all of the 1038 * status bits have been updated before next_to_watch is written. 1039 */ 1040 wmb(); 1041 1042 /* set next_to_watch value indicating a packet is present */ 1043 first->next_to_watch = tx_desc; 1044 1045 i++; 1046 if (i == tx_ring->count) 1047 i = 0; 1048 1049 tx_ring->next_to_use = i; 1050 1051 wx_maybe_stop_tx(tx_ring, DESC_NEEDED); 1052 1053 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more()) 1054 writel(i, tx_ring->tail); 1055 1056 return 0; 1057 dma_error: 1058 dev_err(tx_ring->dev, "TX DMA map failed\n"); 1059 1060 /* clear dma mappings for failed tx_buffer_info map */ 1061 for (;;) { 1062 tx_buffer = &tx_ring->tx_buffer_info[i]; 1063 if (dma_unmap_len(tx_buffer, len)) 1064 dma_unmap_page(tx_ring->dev, 1065 dma_unmap_addr(tx_buffer, dma), 1066 dma_unmap_len(tx_buffer, len), 1067 DMA_TO_DEVICE); 1068 dma_unmap_len_set(tx_buffer, len, 0); 1069 if (tx_buffer == first) 1070 break; 1071 if (i == 0) 1072 i += tx_ring->count; 1073 i--; 1074 } 1075 1076 dev_kfree_skb_any(first->skb); 1077 first->skb = NULL; 1078 1079 tx_ring->next_to_use = i; 1080 1081 return -ENOMEM; 1082 } 1083 1084 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens, 1085 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1086 { 1087 struct wx_tx_context_desc *context_desc; 1088 u16 i = tx_ring->next_to_use; 1089 1090 context_desc = WX_TX_CTXTDESC(tx_ring, i); 1091 i++; 1092 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1093 1094 /* set bits to identify this as an advanced context descriptor */ 1095 type_tucmd |= WX_TXD_DTYP_CTXT; 1096 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1097 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1098 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1099 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1100 } 1101 1102 union network_header { 1103 struct iphdr *ipv4; 1104 struct ipv6hdr *ipv6; 1105 void *raw; 1106 }; 1107 1108 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first) 1109 { 1110 u8 tun_prot = 0, l4_prot = 0, ptype = 0; 1111 struct sk_buff *skb = first->skb; 1112 unsigned char *exthdr, *l4_hdr; 1113 __be16 frag_off; 1114 1115 if (skb->encapsulation) { 1116 union network_header hdr; 1117 1118 switch (first->protocol) { 1119 case htons(ETH_P_IP): 1120 tun_prot = ip_hdr(skb)->protocol; 1121 ptype = WX_PTYPE_TUN_IPV4; 1122 break; 1123 case htons(ETH_P_IPV6): 1124 l4_hdr = skb_transport_header(skb); 1125 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1126 tun_prot = ipv6_hdr(skb)->nexthdr; 1127 if (l4_hdr != exthdr) 1128 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off); 1129 ptype = WX_PTYPE_TUN_IPV6; 1130 break; 1131 default: 1132 return ptype; 1133 } 1134 1135 if (tun_prot == IPPROTO_IPIP || tun_prot == IPPROTO_IPV6) { 1136 hdr.raw = (void *)inner_ip_hdr(skb); 1137 ptype |= WX_PTYPE_PKT_IPIP; 1138 } else if (tun_prot == IPPROTO_UDP) { 1139 hdr.raw = (void *)inner_ip_hdr(skb); 1140 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1141 skb->inner_protocol != htons(ETH_P_TEB)) { 1142 ptype |= WX_PTYPE_PKT_IG; 1143 } else { 1144 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1145 == htons(ETH_P_8021Q)) 1146 ptype |= WX_PTYPE_PKT_IGMV; 1147 else 1148 ptype |= WX_PTYPE_PKT_IGM; 1149 } 1150 1151 } else if (tun_prot == IPPROTO_GRE) { 1152 hdr.raw = (void *)inner_ip_hdr(skb); 1153 if (skb->inner_protocol == htons(ETH_P_IP) || 1154 skb->inner_protocol == htons(ETH_P_IPV6)) { 1155 ptype |= WX_PTYPE_PKT_IG; 1156 } else { 1157 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1158 == htons(ETH_P_8021Q)) 1159 ptype |= WX_PTYPE_PKT_IGMV; 1160 else 1161 ptype |= WX_PTYPE_PKT_IGM; 1162 } 1163 } else { 1164 return ptype; 1165 } 1166 1167 switch (hdr.ipv4->version) { 1168 case IPVERSION: 1169 l4_prot = hdr.ipv4->protocol; 1170 break; 1171 case 6: 1172 l4_hdr = skb_inner_transport_header(skb); 1173 exthdr = skb_inner_network_header(skb) + sizeof(struct ipv6hdr); 1174 l4_prot = inner_ipv6_hdr(skb)->nexthdr; 1175 if (l4_hdr != exthdr) 1176 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1177 ptype |= WX_PTYPE_PKT_IPV6; 1178 break; 1179 default: 1180 return ptype; 1181 } 1182 } else { 1183 switch (first->protocol) { 1184 case htons(ETH_P_IP): 1185 l4_prot = ip_hdr(skb)->protocol; 1186 ptype = WX_PTYPE_PKT_IP; 1187 break; 1188 case htons(ETH_P_IPV6): 1189 l4_hdr = skb_transport_header(skb); 1190 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1191 l4_prot = ipv6_hdr(skb)->nexthdr; 1192 if (l4_hdr != exthdr) 1193 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1194 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6; 1195 break; 1196 default: 1197 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC; 1198 } 1199 } 1200 switch (l4_prot) { 1201 case IPPROTO_TCP: 1202 ptype |= WX_PTYPE_TYP_TCP; 1203 break; 1204 case IPPROTO_UDP: 1205 ptype |= WX_PTYPE_TYP_UDP; 1206 break; 1207 case IPPROTO_SCTP: 1208 ptype |= WX_PTYPE_TYP_SCTP; 1209 break; 1210 default: 1211 ptype |= WX_PTYPE_TYP_IP; 1212 break; 1213 } 1214 1215 return ptype; 1216 } 1217 1218 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1219 u8 *hdr_len, u8 ptype) 1220 { 1221 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1222 struct net_device *netdev = tx_ring->netdev; 1223 u32 l4len, tunhdr_eiplen_tunlen = 0; 1224 struct sk_buff *skb = first->skb; 1225 bool enc = skb->encapsulation; 1226 struct ipv6hdr *ipv6h; 1227 struct tcphdr *tcph; 1228 struct iphdr *iph; 1229 u8 tun_prot = 0; 1230 int err; 1231 1232 if (skb->ip_summed != CHECKSUM_PARTIAL) 1233 return 0; 1234 1235 if (!skb_is_gso(skb)) 1236 return 0; 1237 1238 err = skb_cow_head(skb, 0); 1239 if (err < 0) 1240 return err; 1241 1242 /* indicates the inner headers in the skbuff are valid. */ 1243 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb); 1244 if (iph->version == 4) { 1245 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1246 iph->tot_len = 0; 1247 iph->check = 0; 1248 tcph->check = ~csum_tcpudp_magic(iph->saddr, 1249 iph->daddr, 0, 1250 IPPROTO_TCP, 0); 1251 first->tx_flags |= WX_TX_FLAGS_TSO | 1252 WX_TX_FLAGS_CSUM | 1253 WX_TX_FLAGS_IPV4 | 1254 WX_TX_FLAGS_CC; 1255 } else if (iph->version == 6 && skb_is_gso_v6(skb)) { 1256 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 1257 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1258 ipv6h->payload_len = 0; 1259 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, 1260 &ipv6h->daddr, 0, 1261 IPPROTO_TCP, 0); 1262 first->tx_flags |= WX_TX_FLAGS_TSO | 1263 WX_TX_FLAGS_CSUM | 1264 WX_TX_FLAGS_CC; 1265 } 1266 1267 /* compute header lengths */ 1268 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 1269 *hdr_len = enc ? skb_inner_transport_offset(skb) : 1270 skb_transport_offset(skb); 1271 *hdr_len += l4len; 1272 1273 /* update gso size and bytecount with header size */ 1274 first->gso_segs = skb_shinfo(skb)->gso_segs; 1275 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1276 1277 /* mss_l4len_id: use 0 as index for TSO */ 1278 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT; 1279 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT; 1280 1281 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 1282 if (enc) { 1283 unsigned char *exthdr, *l4_hdr; 1284 __be16 frag_off; 1285 1286 switch (first->protocol) { 1287 case htons(ETH_P_IP): 1288 tun_prot = ip_hdr(skb)->protocol; 1289 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4; 1290 break; 1291 case htons(ETH_P_IPV6): 1292 l4_hdr = skb_transport_header(skb); 1293 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1294 tun_prot = ipv6_hdr(skb)->nexthdr; 1295 if (l4_hdr != exthdr) 1296 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off); 1297 break; 1298 default: 1299 break; 1300 } 1301 switch (tun_prot) { 1302 case IPPROTO_UDP: 1303 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1304 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1305 WX_TXD_OUTER_IPLEN_SHIFT) | 1306 (((skb_inner_mac_header(skb) - 1307 skb_transport_header(skb)) >> 1) << 1308 WX_TXD_TUNNEL_LEN_SHIFT); 1309 break; 1310 case IPPROTO_GRE: 1311 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1312 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1313 WX_TXD_OUTER_IPLEN_SHIFT) | 1314 (((skb_inner_mac_header(skb) - 1315 skb_transport_header(skb)) >> 1) << 1316 WX_TXD_TUNNEL_LEN_SHIFT); 1317 break; 1318 case IPPROTO_IPIP: 1319 case IPPROTO_IPV6: 1320 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1321 (char *)ip_hdr(skb)) >> 2) << 1322 WX_TXD_OUTER_IPLEN_SHIFT; 1323 break; 1324 default: 1325 break; 1326 } 1327 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1; 1328 } else { 1329 vlan_macip_lens = skb_network_header_len(skb) >> 1; 1330 } 1331 1332 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT; 1333 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1334 1335 type_tucmd = ptype << 24; 1336 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1337 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1338 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1339 WX_TX_FLAGS_HW_VLAN, 1340 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1341 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1342 type_tucmd, mss_l4len_idx); 1343 1344 return 1; 1345 } 1346 1347 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1348 u8 ptype) 1349 { 1350 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0; 1351 struct net_device *netdev = tx_ring->netdev; 1352 u32 mss_l4len_idx = 0, type_tucmd; 1353 struct sk_buff *skb = first->skb; 1354 u8 tun_prot = 0; 1355 1356 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1357 csum_failed: 1358 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) && 1359 !(first->tx_flags & WX_TX_FLAGS_CC)) 1360 return; 1361 vlan_macip_lens = skb_network_offset(skb) << 1362 WX_TXD_MACLEN_SHIFT; 1363 } else { 1364 unsigned char *exthdr, *l4_hdr; 1365 __be16 frag_off; 1366 u8 l4_prot = 0; 1367 union { 1368 struct iphdr *ipv4; 1369 struct ipv6hdr *ipv6; 1370 u8 *raw; 1371 } network_hdr; 1372 union { 1373 struct tcphdr *tcphdr; 1374 u8 *raw; 1375 } transport_hdr; 1376 1377 if (skb->encapsulation) { 1378 network_hdr.raw = skb_inner_network_header(skb); 1379 transport_hdr.raw = skb_inner_transport_header(skb); 1380 vlan_macip_lens = skb_network_offset(skb) << 1381 WX_TXD_MACLEN_SHIFT; 1382 switch (first->protocol) { 1383 case htons(ETH_P_IP): 1384 tun_prot = ip_hdr(skb)->protocol; 1385 break; 1386 case htons(ETH_P_IPV6): 1387 l4_hdr = skb_transport_header(skb); 1388 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1389 tun_prot = ipv6_hdr(skb)->nexthdr; 1390 if (l4_hdr != exthdr) 1391 ipv6_skip_exthdr(skb, exthdr - skb->data, 1392 &tun_prot, &frag_off); 1393 break; 1394 default: 1395 return; 1396 } 1397 switch (tun_prot) { 1398 case IPPROTO_UDP: 1399 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1400 tunhdr_eiplen_tunlen |= 1401 ((skb_network_header_len(skb) >> 2) << 1402 WX_TXD_OUTER_IPLEN_SHIFT) | 1403 (((skb_inner_mac_header(skb) - 1404 skb_transport_header(skb)) >> 1) << 1405 WX_TXD_TUNNEL_LEN_SHIFT); 1406 break; 1407 case IPPROTO_GRE: 1408 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1409 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1410 WX_TXD_OUTER_IPLEN_SHIFT) | 1411 (((skb_inner_mac_header(skb) - 1412 skb_transport_header(skb)) >> 1) << 1413 WX_TXD_TUNNEL_LEN_SHIFT); 1414 break; 1415 case IPPROTO_IPIP: 1416 case IPPROTO_IPV6: 1417 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1418 (char *)ip_hdr(skb)) >> 2) << 1419 WX_TXD_OUTER_IPLEN_SHIFT; 1420 break; 1421 default: 1422 break; 1423 } 1424 1425 } else { 1426 network_hdr.raw = skb_network_header(skb); 1427 transport_hdr.raw = skb_transport_header(skb); 1428 vlan_macip_lens = skb_network_offset(skb) << 1429 WX_TXD_MACLEN_SHIFT; 1430 } 1431 1432 switch (network_hdr.ipv4->version) { 1433 case IPVERSION: 1434 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1435 l4_prot = network_hdr.ipv4->protocol; 1436 break; 1437 case 6: 1438 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1439 exthdr = network_hdr.raw + sizeof(struct ipv6hdr); 1440 l4_prot = network_hdr.ipv6->nexthdr; 1441 if (transport_hdr.raw != exthdr) 1442 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1443 break; 1444 default: 1445 break; 1446 } 1447 1448 switch (l4_prot) { 1449 case IPPROTO_TCP: 1450 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 1451 WX_TXD_L4LEN_SHIFT; 1452 break; 1453 case IPPROTO_SCTP: 1454 mss_l4len_idx = sizeof(struct sctphdr) << 1455 WX_TXD_L4LEN_SHIFT; 1456 break; 1457 case IPPROTO_UDP: 1458 mss_l4len_idx = sizeof(struct udphdr) << 1459 WX_TXD_L4LEN_SHIFT; 1460 break; 1461 default: 1462 skb_checksum_help(skb); 1463 goto csum_failed; 1464 } 1465 1466 /* update TX checksum flag */ 1467 first->tx_flags |= WX_TX_FLAGS_CSUM; 1468 } 1469 first->tx_flags |= WX_TX_FLAGS_CC; 1470 /* vlan_macip_lens: MACLEN, VLAN tag */ 1471 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1472 1473 type_tucmd = ptype << 24; 1474 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1475 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1476 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1477 WX_TX_FLAGS_HW_VLAN, 1478 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1479 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1480 type_tucmd, mss_l4len_idx); 1481 } 1482 1483 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb, 1484 struct wx_ring *tx_ring) 1485 { 1486 struct wx *wx = netdev_priv(tx_ring->netdev); 1487 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1488 struct wx_tx_buffer *first; 1489 u8 hdr_len = 0, ptype; 1490 unsigned short f; 1491 u32 tx_flags = 0; 1492 int tso; 1493 1494 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD, 1495 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD, 1496 * + 2 desc gap to keep tail from touching head, 1497 * + 1 desc for context descriptor, 1498 * otherwise try next time 1499 */ 1500 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1501 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)-> 1502 frags[f])); 1503 1504 if (wx_maybe_stop_tx(tx_ring, count + 3)) { 1505 tx_ring->tx_stats.tx_busy++; 1506 return NETDEV_TX_BUSY; 1507 } 1508 1509 /* record the location of the first descriptor for this packet */ 1510 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1511 first->skb = skb; 1512 first->bytecount = skb->len; 1513 first->gso_segs = 1; 1514 1515 /* if we have a HW VLAN tag being added default to the HW one */ 1516 if (skb_vlan_tag_present(skb)) { 1517 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT; 1518 tx_flags |= WX_TX_FLAGS_HW_VLAN; 1519 } 1520 1521 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1522 wx->ptp_clock) { 1523 if (wx->tstamp_config.tx_type == HWTSTAMP_TX_ON && 1524 !test_and_set_bit_lock(WX_STATE_PTP_TX_IN_PROGRESS, 1525 wx->state)) { 1526 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1527 tx_flags |= WX_TX_FLAGS_TSTAMP; 1528 wx->ptp_tx_skb = skb_get(skb); 1529 wx->ptp_tx_start = jiffies; 1530 } else { 1531 wx->tx_hwtstamp_skipped++; 1532 } 1533 } 1534 1535 /* record initial flags and protocol */ 1536 first->tx_flags = tx_flags; 1537 first->protocol = vlan_get_protocol(skb); 1538 1539 ptype = wx_encode_tx_desc_ptype(first); 1540 1541 tso = wx_tso(tx_ring, first, &hdr_len, ptype); 1542 if (tso < 0) 1543 goto out_drop; 1544 else if (!tso) 1545 wx_tx_csum(tx_ring, first, ptype); 1546 1547 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate) 1548 wx->atr(tx_ring, first, ptype); 1549 1550 if (wx_tx_map(tx_ring, first, hdr_len)) 1551 goto cleanup_tx_tstamp; 1552 1553 return NETDEV_TX_OK; 1554 out_drop: 1555 dev_kfree_skb_any(first->skb); 1556 first->skb = NULL; 1557 cleanup_tx_tstamp: 1558 if (unlikely(tx_flags & WX_TX_FLAGS_TSTAMP)) { 1559 dev_kfree_skb_any(wx->ptp_tx_skb); 1560 wx->ptp_tx_skb = NULL; 1561 wx->tx_hwtstamp_errors++; 1562 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 1563 } 1564 1565 return NETDEV_TX_OK; 1566 } 1567 1568 netdev_tx_t wx_xmit_frame(struct sk_buff *skb, 1569 struct net_device *netdev) 1570 { 1571 unsigned int r_idx = skb->queue_mapping; 1572 struct wx *wx = netdev_priv(netdev); 1573 struct wx_ring *tx_ring; 1574 1575 if (!netif_carrier_ok(netdev)) { 1576 dev_kfree_skb_any(skb); 1577 return NETDEV_TX_OK; 1578 } 1579 1580 /* The minimum packet size for olinfo paylen is 17 so pad the skb 1581 * in order to meet this minimum size requirement. 1582 */ 1583 if (skb_put_padto(skb, 17)) 1584 return NETDEV_TX_OK; 1585 1586 if (r_idx >= wx->num_tx_queues) 1587 r_idx = r_idx % wx->num_tx_queues; 1588 tx_ring = wx->tx_ring[r_idx]; 1589 1590 return wx_xmit_frame_ring(skb, tx_ring); 1591 } 1592 EXPORT_SYMBOL(wx_xmit_frame); 1593 1594 void wx_napi_enable_all(struct wx *wx) 1595 { 1596 struct wx_q_vector *q_vector; 1597 int q_idx; 1598 1599 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1600 q_vector = wx->q_vector[q_idx]; 1601 napi_enable(&q_vector->napi); 1602 } 1603 } 1604 EXPORT_SYMBOL(wx_napi_enable_all); 1605 1606 void wx_napi_disable_all(struct wx *wx) 1607 { 1608 struct wx_q_vector *q_vector; 1609 int q_idx; 1610 1611 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1612 q_vector = wx->q_vector[q_idx]; 1613 napi_disable(&q_vector->napi); 1614 } 1615 } 1616 EXPORT_SYMBOL(wx_napi_disable_all); 1617 1618 static bool wx_set_vmdq_queues(struct wx *wx) 1619 { 1620 u16 vmdq_i = wx->ring_feature[RING_F_VMDQ].limit; 1621 u16 rss_i = wx->ring_feature[RING_F_RSS].limit; 1622 u16 rss_m = WX_RSS_DISABLED_MASK; 1623 u16 vmdq_m = 0; 1624 1625 /* only proceed if VMDq is enabled */ 1626 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 1627 return false; 1628 /* Add starting offset to total pool count */ 1629 vmdq_i += wx->ring_feature[RING_F_VMDQ].offset; 1630 1631 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1632 /* double check we are limited to maximum pools */ 1633 vmdq_i = min_t(u16, 64, vmdq_i); 1634 1635 /* 64 pool mode with 2 queues per pool, or 1636 * 16/32/64 pool mode with 1 queue per pool 1637 */ 1638 if (vmdq_i > 32 || rss_i < 4) { 1639 vmdq_m = WX_VMDQ_2Q_MASK; 1640 rss_m = WX_RSS_2Q_MASK; 1641 rss_i = min_t(u16, rss_i, 2); 1642 /* 32 pool mode with 4 queues per pool */ 1643 } else { 1644 vmdq_m = WX_VMDQ_4Q_MASK; 1645 rss_m = WX_RSS_4Q_MASK; 1646 rss_i = 4; 1647 } 1648 } else { 1649 /* double check we are limited to maximum pools */ 1650 vmdq_i = min_t(u16, 8, vmdq_i); 1651 1652 /* when VMDQ on, disable RSS */ 1653 rss_i = 1; 1654 } 1655 1656 /* remove the starting offset from the pool count */ 1657 vmdq_i -= wx->ring_feature[RING_F_VMDQ].offset; 1658 1659 /* save features for later use */ 1660 wx->ring_feature[RING_F_VMDQ].indices = vmdq_i; 1661 wx->ring_feature[RING_F_VMDQ].mask = vmdq_m; 1662 1663 /* limit RSS based on user input and save for later use */ 1664 wx->ring_feature[RING_F_RSS].indices = rss_i; 1665 wx->ring_feature[RING_F_RSS].mask = rss_m; 1666 1667 wx->queues_per_pool = rss_i;/*maybe same to num_rx_queues_per_pool*/ 1668 wx->num_rx_pools = vmdq_i; 1669 wx->num_rx_queues_per_pool = rss_i; 1670 1671 wx->num_rx_queues = vmdq_i * rss_i; 1672 wx->num_tx_queues = vmdq_i * rss_i; 1673 1674 return true; 1675 } 1676 1677 /** 1678 * wx_set_rss_queues: Allocate queues for RSS 1679 * @wx: board private structure to initialize 1680 * 1681 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1682 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1683 * 1684 **/ 1685 static void wx_set_rss_queues(struct wx *wx) 1686 { 1687 struct wx_ring_feature *f; 1688 1689 /* set mask for 16 queue limit of RSS */ 1690 f = &wx->ring_feature[RING_F_RSS]; 1691 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) 1692 f->mask = WX_RSS_64Q_MASK; 1693 else 1694 f->mask = WX_RSS_8Q_MASK; 1695 f->indices = f->limit; 1696 1697 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 1698 goto out; 1699 1700 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 1701 1702 wx->ring_feature[RING_F_FDIR].indices = 1; 1703 /* Use Flow Director in addition to RSS to ensure the best 1704 * distribution of flows across cores, even when an FDIR flow 1705 * isn't matched. 1706 */ 1707 if (f->indices > 1) { 1708 f = &wx->ring_feature[RING_F_FDIR]; 1709 1710 f->indices = f->limit; 1711 1712 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 1713 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 1714 } 1715 1716 out: 1717 wx->num_rx_queues = f->indices; 1718 wx->num_tx_queues = f->indices; 1719 } 1720 1721 static void wx_set_num_queues(struct wx *wx) 1722 { 1723 /* Start with base case */ 1724 wx->num_rx_queues = 1; 1725 wx->num_tx_queues = 1; 1726 wx->queues_per_pool = 1; 1727 1728 if (wx_set_vmdq_queues(wx)) 1729 return; 1730 1731 wx_set_rss_queues(wx); 1732 } 1733 1734 /** 1735 * wx_acquire_msix_vectors - acquire MSI-X vectors 1736 * @wx: board private structure 1737 * 1738 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will 1739 * return a negative error code if unable to acquire MSI-X vectors for any 1740 * reason. 1741 */ 1742 static int wx_acquire_msix_vectors(struct wx *wx) 1743 { 1744 struct irq_affinity affd = { .post_vectors = 1 }; 1745 int nvecs, i; 1746 1747 /* We start by asking for one vector per queue pair */ 1748 nvecs = max(wx->num_rx_queues, wx->num_tx_queues); 1749 nvecs = min_t(int, nvecs, num_online_cpus()); 1750 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors); 1751 1752 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry), 1753 GFP_KERNEL); 1754 if (!wx->msix_q_entries) 1755 return -ENOMEM; 1756 1757 /* One for non-queue interrupts */ 1758 nvecs += 1; 1759 1760 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry), 1761 GFP_KERNEL); 1762 if (!wx->msix_entry) { 1763 kfree(wx->msix_q_entries); 1764 wx->msix_q_entries = NULL; 1765 return -ENOMEM; 1766 } 1767 1768 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs, 1769 nvecs, 1770 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, 1771 &affd); 1772 if (nvecs < 0) { 1773 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs); 1774 kfree(wx->msix_q_entries); 1775 wx->msix_q_entries = NULL; 1776 kfree(wx->msix_entry); 1777 wx->msix_entry = NULL; 1778 return nvecs; 1779 } 1780 1781 nvecs -= 1; 1782 for (i = 0; i < nvecs; i++) { 1783 wx->msix_q_entries[i].entry = i; 1784 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i); 1785 } 1786 1787 wx->num_q_vectors = nvecs; 1788 1789 wx->msix_entry->entry = nvecs; 1790 wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs); 1791 1792 if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) { 1793 wx->msix_entry->entry = 0; 1794 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0); 1795 wx->msix_q_entries[0].entry = 0; 1796 wx->msix_q_entries[0].vector = pci_irq_vector(wx->pdev, 1); 1797 } 1798 1799 return 0; 1800 } 1801 1802 /** 1803 * wx_set_interrupt_capability - set MSI-X or MSI if supported 1804 * @wx: board private structure to initialize 1805 * 1806 * Attempt to configure the interrupts using the best available 1807 * capabilities of the hardware and the kernel. 1808 **/ 1809 static int wx_set_interrupt_capability(struct wx *wx) 1810 { 1811 struct pci_dev *pdev = wx->pdev; 1812 int nvecs, ret; 1813 1814 /* We will try to get MSI-X interrupts first */ 1815 ret = wx_acquire_msix_vectors(wx); 1816 if (ret == 0 || (ret == -ENOMEM)) 1817 return ret; 1818 1819 /* Disable VMDq support */ 1820 dev_warn(&wx->pdev->dev, "Disabling VMQQ support\n"); 1821 clear_bit(WX_FLAG_VMDQ_ENABLED, wx->flags); 1822 1823 /* Disable RSS */ 1824 dev_warn(&wx->pdev->dev, "Disabling RSS support\n"); 1825 wx->ring_feature[RING_F_RSS].limit = 1; 1826 1827 wx_set_num_queues(wx); 1828 1829 /* minmum one for queue, one for misc*/ 1830 nvecs = 1; 1831 nvecs = pci_alloc_irq_vectors(pdev, nvecs, 1832 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX); 1833 if (nvecs == 1) { 1834 if (pdev->msi_enabled) 1835 wx_err(wx, "Fallback to MSI.\n"); 1836 else 1837 wx_err(wx, "Fallback to INTx.\n"); 1838 } else { 1839 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs); 1840 return nvecs; 1841 } 1842 1843 pdev->irq = pci_irq_vector(pdev, 0); 1844 wx->num_q_vectors = 1; 1845 1846 return 0; 1847 } 1848 1849 static bool wx_cache_ring_vmdq(struct wx *wx) 1850 { 1851 struct wx_ring_feature *vmdq = &wx->ring_feature[RING_F_VMDQ]; 1852 struct wx_ring_feature *rss = &wx->ring_feature[RING_F_RSS]; 1853 u16 reg_idx; 1854 int i; 1855 1856 /* only proceed if VMDq is enabled */ 1857 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 1858 return false; 1859 1860 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1861 /* start at VMDq register offset for SR-IOV enabled setups */ 1862 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 1863 for (i = 0; i < wx->num_rx_queues; i++, reg_idx++) { 1864 /* If we are greater than indices move to next pool */ 1865 if ((reg_idx & ~vmdq->mask) >= rss->indices) 1866 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 1867 wx->rx_ring[i]->reg_idx = reg_idx; 1868 } 1869 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 1870 for (i = 0; i < wx->num_tx_queues; i++, reg_idx++) { 1871 /* If we are greater than indices move to next pool */ 1872 if ((reg_idx & rss->mask) >= rss->indices) 1873 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 1874 wx->tx_ring[i]->reg_idx = reg_idx; 1875 } 1876 } else { 1877 /* start at VMDq register offset for SR-IOV enabled setups */ 1878 reg_idx = vmdq->offset; 1879 for (i = 0; i < wx->num_rx_queues; i++) 1880 /* If we are greater than indices move to next pool */ 1881 wx->rx_ring[i]->reg_idx = reg_idx + i; 1882 1883 reg_idx = vmdq->offset; 1884 for (i = 0; i < wx->num_tx_queues; i++) 1885 /* If we are greater than indices move to next pool */ 1886 wx->tx_ring[i]->reg_idx = reg_idx + i; 1887 } 1888 1889 return true; 1890 } 1891 1892 /** 1893 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS 1894 * @wx: board private structure to initialize 1895 * 1896 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV. 1897 * 1898 **/ 1899 static void wx_cache_ring_rss(struct wx *wx) 1900 { 1901 u16 i; 1902 1903 if (wx_cache_ring_vmdq(wx)) 1904 return; 1905 1906 for (i = 0; i < wx->num_rx_queues; i++) 1907 wx->rx_ring[i]->reg_idx = i; 1908 1909 for (i = 0; i < wx->num_tx_queues; i++) 1910 wx->tx_ring[i]->reg_idx = i; 1911 } 1912 1913 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head) 1914 { 1915 ring->next = head->ring; 1916 head->ring = ring; 1917 head->count++; 1918 } 1919 1920 /** 1921 * wx_alloc_q_vector - Allocate memory for a single interrupt vector 1922 * @wx: board private structure to initialize 1923 * @v_count: q_vectors allocated on wx, used for ring interleaving 1924 * @v_idx: index of vector in wx struct 1925 * @txr_count: total number of Tx rings to allocate 1926 * @txr_idx: index of first Tx ring to allocate 1927 * @rxr_count: total number of Rx rings to allocate 1928 * @rxr_idx: index of first Rx ring to allocate 1929 * 1930 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1931 **/ 1932 static int wx_alloc_q_vector(struct wx *wx, 1933 unsigned int v_count, unsigned int v_idx, 1934 unsigned int txr_count, unsigned int txr_idx, 1935 unsigned int rxr_count, unsigned int rxr_idx) 1936 { 1937 struct wx_q_vector *q_vector; 1938 int ring_count, default_itr; 1939 struct wx_ring *ring; 1940 1941 /* note this will allocate space for the ring structure as well! */ 1942 ring_count = txr_count + rxr_count; 1943 1944 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 1945 GFP_KERNEL); 1946 if (!q_vector) 1947 return -ENOMEM; 1948 1949 /* initialize NAPI */ 1950 netif_napi_add(wx->netdev, &q_vector->napi, 1951 wx_poll); 1952 1953 /* tie q_vector and wx together */ 1954 wx->q_vector[v_idx] = q_vector; 1955 q_vector->wx = wx; 1956 q_vector->v_idx = v_idx; 1957 if (cpu_online(v_idx)) 1958 q_vector->numa_node = cpu_to_node(v_idx); 1959 1960 /* initialize pointer to rings */ 1961 ring = q_vector->ring; 1962 1963 switch (wx->mac.type) { 1964 case wx_mac_sp: 1965 case wx_mac_aml: 1966 case wx_mac_aml40: 1967 default_itr = WX_12K_ITR; 1968 break; 1969 default: 1970 default_itr = WX_7K_ITR; 1971 break; 1972 } 1973 1974 /* initialize ITR */ 1975 if (txr_count && !rxr_count) 1976 /* tx only vector */ 1977 q_vector->itr = wx->tx_itr_setting ? 1978 default_itr : wx->tx_itr_setting; 1979 else 1980 /* rx or rx/tx vector */ 1981 q_vector->itr = wx->rx_itr_setting ? 1982 default_itr : wx->rx_itr_setting; 1983 1984 while (txr_count) { 1985 /* assign generic ring traits */ 1986 ring->dev = &wx->pdev->dev; 1987 ring->netdev = wx->netdev; 1988 1989 /* configure backlink on ring */ 1990 ring->q_vector = q_vector; 1991 1992 /* update q_vector Tx values */ 1993 wx_add_ring(ring, &q_vector->tx); 1994 1995 /* apply Tx specific ring traits */ 1996 ring->count = wx->tx_ring_count; 1997 1998 ring->queue_index = txr_idx; 1999 2000 /* assign ring to wx */ 2001 wx->tx_ring[txr_idx] = ring; 2002 2003 /* update count and index */ 2004 txr_count--; 2005 txr_idx += v_count; 2006 2007 /* push pointer to next ring */ 2008 ring++; 2009 } 2010 2011 while (rxr_count) { 2012 /* assign generic ring traits */ 2013 ring->dev = &wx->pdev->dev; 2014 ring->netdev = wx->netdev; 2015 2016 /* configure backlink on ring */ 2017 ring->q_vector = q_vector; 2018 2019 /* update q_vector Rx values */ 2020 wx_add_ring(ring, &q_vector->rx); 2021 2022 /* apply Rx specific ring traits */ 2023 ring->count = wx->rx_ring_count; 2024 ring->queue_index = rxr_idx; 2025 2026 /* assign ring to wx */ 2027 wx->rx_ring[rxr_idx] = ring; 2028 2029 /* update count and index */ 2030 rxr_count--; 2031 rxr_idx += v_count; 2032 2033 /* push pointer to next ring */ 2034 ring++; 2035 } 2036 2037 return 0; 2038 } 2039 2040 /** 2041 * wx_free_q_vector - Free memory allocated for specific interrupt vector 2042 * @wx: board private structure to initialize 2043 * @v_idx: Index of vector to be freed 2044 * 2045 * This function frees the memory allocated to the q_vector. In addition if 2046 * NAPI is enabled it will delete any references to the NAPI struct prior 2047 * to freeing the q_vector. 2048 **/ 2049 static void wx_free_q_vector(struct wx *wx, int v_idx) 2050 { 2051 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2052 struct wx_ring *ring; 2053 2054 wx_for_each_ring(ring, q_vector->tx) 2055 wx->tx_ring[ring->queue_index] = NULL; 2056 2057 wx_for_each_ring(ring, q_vector->rx) 2058 wx->rx_ring[ring->queue_index] = NULL; 2059 2060 wx->q_vector[v_idx] = NULL; 2061 netif_napi_del(&q_vector->napi); 2062 kfree_rcu(q_vector, rcu); 2063 } 2064 2065 /** 2066 * wx_alloc_q_vectors - Allocate memory for interrupt vectors 2067 * @wx: board private structure to initialize 2068 * 2069 * We allocate one q_vector per queue interrupt. If allocation fails we 2070 * return -ENOMEM. 2071 **/ 2072 static int wx_alloc_q_vectors(struct wx *wx) 2073 { 2074 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 2075 unsigned int rxr_remaining = wx->num_rx_queues; 2076 unsigned int txr_remaining = wx->num_tx_queues; 2077 unsigned int q_vectors = wx->num_q_vectors; 2078 int rqpv, tqpv; 2079 int err; 2080 2081 for (; v_idx < q_vectors; v_idx++) { 2082 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 2083 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 2084 err = wx_alloc_q_vector(wx, q_vectors, v_idx, 2085 tqpv, txr_idx, 2086 rqpv, rxr_idx); 2087 2088 if (err) 2089 goto err_out; 2090 2091 /* update counts and index */ 2092 rxr_remaining -= rqpv; 2093 txr_remaining -= tqpv; 2094 rxr_idx++; 2095 txr_idx++; 2096 } 2097 2098 return 0; 2099 2100 err_out: 2101 wx->num_tx_queues = 0; 2102 wx->num_rx_queues = 0; 2103 wx->num_q_vectors = 0; 2104 2105 while (v_idx--) 2106 wx_free_q_vector(wx, v_idx); 2107 2108 return -ENOMEM; 2109 } 2110 2111 /** 2112 * wx_free_q_vectors - Free memory allocated for interrupt vectors 2113 * @wx: board private structure to initialize 2114 * 2115 * This function frees the memory allocated to the q_vectors. In addition if 2116 * NAPI is enabled it will delete any references to the NAPI struct prior 2117 * to freeing the q_vector. 2118 **/ 2119 static void wx_free_q_vectors(struct wx *wx) 2120 { 2121 int v_idx = wx->num_q_vectors; 2122 2123 wx->num_tx_queues = 0; 2124 wx->num_rx_queues = 0; 2125 wx->num_q_vectors = 0; 2126 2127 while (v_idx--) 2128 wx_free_q_vector(wx, v_idx); 2129 } 2130 2131 void wx_reset_interrupt_capability(struct wx *wx) 2132 { 2133 struct pci_dev *pdev = wx->pdev; 2134 2135 if (!pdev->msi_enabled && !pdev->msix_enabled) 2136 return; 2137 2138 if (pdev->msix_enabled) { 2139 kfree(wx->msix_q_entries); 2140 wx->msix_q_entries = NULL; 2141 kfree(wx->msix_entry); 2142 wx->msix_entry = NULL; 2143 } 2144 pci_free_irq_vectors(wx->pdev); 2145 } 2146 EXPORT_SYMBOL(wx_reset_interrupt_capability); 2147 2148 /** 2149 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings 2150 * @wx: board private structure to clear interrupt scheme on 2151 * 2152 * We go through and clear interrupt specific resources and reset the structure 2153 * to pre-load conditions 2154 **/ 2155 void wx_clear_interrupt_scheme(struct wx *wx) 2156 { 2157 wx_free_q_vectors(wx); 2158 wx_reset_interrupt_capability(wx); 2159 } 2160 EXPORT_SYMBOL(wx_clear_interrupt_scheme); 2161 2162 int wx_init_interrupt_scheme(struct wx *wx) 2163 { 2164 int ret; 2165 2166 /* Number of supported queues */ 2167 wx_set_num_queues(wx); 2168 2169 /* Set interrupt mode */ 2170 ret = wx_set_interrupt_capability(wx); 2171 if (ret) { 2172 wx_err(wx, "Allocate irq vectors for failed.\n"); 2173 return ret; 2174 } 2175 2176 /* Allocate memory for queues */ 2177 ret = wx_alloc_q_vectors(wx); 2178 if (ret) { 2179 wx_err(wx, "Unable to allocate memory for queue vectors.\n"); 2180 wx_reset_interrupt_capability(wx); 2181 return ret; 2182 } 2183 2184 wx_cache_ring_rss(wx); 2185 2186 return 0; 2187 } 2188 EXPORT_SYMBOL(wx_init_interrupt_scheme); 2189 2190 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data) 2191 { 2192 struct wx_q_vector *q_vector = data; 2193 2194 /* EIAM disabled interrupts (on this vector) for us */ 2195 if (q_vector->rx.ring || q_vector->tx.ring) 2196 napi_schedule_irqoff(&q_vector->napi); 2197 2198 return IRQ_HANDLED; 2199 } 2200 EXPORT_SYMBOL(wx_msix_clean_rings); 2201 2202 void wx_free_irq(struct wx *wx) 2203 { 2204 struct pci_dev *pdev = wx->pdev; 2205 int vector; 2206 2207 if (!(pdev->msix_enabled)) { 2208 if (!wx->misc_irq_domain) 2209 free_irq(pdev->irq, wx); 2210 return; 2211 } 2212 2213 for (vector = 0; vector < wx->num_q_vectors; vector++) { 2214 struct wx_q_vector *q_vector = wx->q_vector[vector]; 2215 struct msix_entry *entry = &wx->msix_q_entries[vector]; 2216 2217 /* free only the irqs that were actually requested */ 2218 if (!q_vector->rx.ring && !q_vector->tx.ring) 2219 continue; 2220 2221 free_irq(entry->vector, q_vector); 2222 } 2223 2224 if (!wx->misc_irq_domain) 2225 free_irq(wx->msix_entry->vector, wx); 2226 } 2227 EXPORT_SYMBOL(wx_free_irq); 2228 2229 /** 2230 * wx_setup_isb_resources - allocate interrupt status resources 2231 * @wx: board private structure 2232 * 2233 * Return 0 on success, negative on failure 2234 **/ 2235 int wx_setup_isb_resources(struct wx *wx) 2236 { 2237 struct pci_dev *pdev = wx->pdev; 2238 2239 if (wx->isb_mem) 2240 return 0; 2241 2242 wx->isb_mem = dma_alloc_coherent(&pdev->dev, 2243 sizeof(u32) * 4, 2244 &wx->isb_dma, 2245 GFP_KERNEL); 2246 if (!wx->isb_mem) { 2247 wx_err(wx, "Alloc isb_mem failed\n"); 2248 return -ENOMEM; 2249 } 2250 2251 return 0; 2252 } 2253 EXPORT_SYMBOL(wx_setup_isb_resources); 2254 2255 /** 2256 * wx_free_isb_resources - allocate all queues Rx resources 2257 * @wx: board private structure 2258 * 2259 * Return 0 on success, negative on failure 2260 **/ 2261 void wx_free_isb_resources(struct wx *wx) 2262 { 2263 struct pci_dev *pdev = wx->pdev; 2264 2265 dma_free_coherent(&pdev->dev, sizeof(u32) * 4, 2266 wx->isb_mem, wx->isb_dma); 2267 wx->isb_mem = NULL; 2268 } 2269 EXPORT_SYMBOL(wx_free_isb_resources); 2270 2271 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx) 2272 { 2273 u32 cur_tag = 0; 2274 2275 cur_tag = wx->isb_mem[WX_ISB_HEADER]; 2276 wx->isb_tag[idx] = cur_tag; 2277 2278 return (__force u32)cpu_to_le32(wx->isb_mem[idx]); 2279 } 2280 EXPORT_SYMBOL(wx_misc_isb); 2281 2282 /** 2283 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 2284 * @wx: pointer to wx struct 2285 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 2286 * @queue: queue to map the corresponding interrupt to 2287 * @msix_vector: the vector to map to the corresponding queue 2288 * 2289 **/ 2290 static void wx_set_ivar(struct wx *wx, s8 direction, 2291 u16 queue, u16 msix_vector) 2292 { 2293 u32 ivar, index; 2294 2295 if (direction == -1) { 2296 /* other causes */ 2297 if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) 2298 msix_vector = 0; 2299 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2300 index = 0; 2301 ivar = rd32(wx, WX_PX_MISC_IVAR); 2302 ivar &= ~(0xFF << index); 2303 ivar |= (msix_vector << index); 2304 wr32(wx, WX_PX_MISC_IVAR, ivar); 2305 } else { 2306 /* tx or rx causes */ 2307 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2308 index = ((16 * (queue & 1)) + (8 * direction)); 2309 ivar = rd32(wx, WX_PX_IVAR(queue >> 1)); 2310 ivar &= ~(0xFF << index); 2311 ivar |= (msix_vector << index); 2312 wr32(wx, WX_PX_IVAR(queue >> 1), ivar); 2313 } 2314 } 2315 2316 /** 2317 * wx_write_eitr - write EITR register in hardware specific way 2318 * @q_vector: structure containing interrupt and ring information 2319 * 2320 * This function is made to be called by ethtool and by the driver 2321 * when it needs to update EITR registers at runtime. Hardware 2322 * specific quirks/differences are taken care of here. 2323 */ 2324 void wx_write_eitr(struct wx_q_vector *q_vector) 2325 { 2326 struct wx *wx = q_vector->wx; 2327 int v_idx = q_vector->v_idx; 2328 u32 itr_reg; 2329 2330 switch (wx->mac.type) { 2331 case wx_mac_sp: 2332 itr_reg = q_vector->itr & WX_SP_MAX_EITR; 2333 break; 2334 case wx_mac_aml: 2335 case wx_mac_aml40: 2336 itr_reg = (q_vector->itr >> 3) & WX_AML_MAX_EITR; 2337 break; 2338 default: 2339 itr_reg = q_vector->itr & WX_EM_MAX_EITR; 2340 break; 2341 } 2342 2343 itr_reg |= WX_PX_ITR_CNT_WDIS; 2344 2345 wr32(wx, WX_PX_ITR(v_idx), itr_reg); 2346 } 2347 2348 /** 2349 * wx_configure_vectors - Configure vectors for hardware 2350 * @wx: board private structure 2351 * 2352 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx 2353 * interrupts. 2354 **/ 2355 void wx_configure_vectors(struct wx *wx) 2356 { 2357 struct pci_dev *pdev = wx->pdev; 2358 u32 eitrsel = 0; 2359 u16 v_idx, i; 2360 2361 if (pdev->msix_enabled) { 2362 /* Populate MSIX to EITR Select */ 2363 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2364 if (wx->num_vfs >= 32) 2365 eitrsel = BIT(wx->num_vfs % 32) - 1; 2366 } else { 2367 for (i = 0; i < wx->num_vfs; i++) 2368 eitrsel |= BIT(i); 2369 } 2370 wr32(wx, WX_PX_ITRSEL, eitrsel); 2371 /* use EIAM to auto-mask when MSI-X interrupt is asserted 2372 * this saves a register write for every interrupt 2373 */ 2374 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL); 2375 } else { 2376 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 2377 * specifically only auto mask tx and rx interrupts. 2378 */ 2379 wr32(wx, WX_PX_GPIE, 0); 2380 } 2381 2382 /* Populate the IVAR table and set the ITR values to the 2383 * corresponding register. 2384 */ 2385 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) { 2386 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2387 struct wx_ring *ring; 2388 2389 wx_for_each_ring(ring, q_vector->rx) 2390 wx_set_ivar(wx, 0, ring->reg_idx, v_idx); 2391 2392 wx_for_each_ring(ring, q_vector->tx) 2393 wx_set_ivar(wx, 1, ring->reg_idx, v_idx); 2394 2395 wx_write_eitr(q_vector); 2396 } 2397 2398 wx_set_ivar(wx, -1, 0, v_idx); 2399 if (pdev->msix_enabled) 2400 wr32(wx, WX_PX_ITR(v_idx), 1950); 2401 } 2402 EXPORT_SYMBOL(wx_configure_vectors); 2403 2404 /** 2405 * wx_clean_rx_ring - Free Rx Buffers per Queue 2406 * @rx_ring: ring to free buffers from 2407 **/ 2408 static void wx_clean_rx_ring(struct wx_ring *rx_ring) 2409 { 2410 struct wx_rx_buffer *rx_buffer; 2411 u16 i = rx_ring->next_to_clean; 2412 2413 rx_buffer = &rx_ring->rx_buffer_info[i]; 2414 2415 /* Free all the Rx ring sk_buffs */ 2416 while (i != rx_ring->next_to_alloc) { 2417 if (rx_buffer->skb) { 2418 struct sk_buff *skb = rx_buffer->skb; 2419 2420 dev_kfree_skb(skb); 2421 } 2422 2423 /* Invalidate cache lines that may have been written to by 2424 * device so that we avoid corrupting memory. 2425 */ 2426 dma_sync_single_range_for_cpu(rx_ring->dev, 2427 rx_buffer->dma, 2428 rx_buffer->page_offset, 2429 WX_RX_BUFSZ, 2430 DMA_FROM_DEVICE); 2431 2432 /* free resources associated with mapping */ 2433 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2434 2435 i++; 2436 rx_buffer++; 2437 if (i == rx_ring->count) { 2438 i = 0; 2439 rx_buffer = rx_ring->rx_buffer_info; 2440 } 2441 } 2442 2443 /* Zero out the descriptor ring */ 2444 memset(rx_ring->desc, 0, rx_ring->size); 2445 2446 rx_ring->next_to_alloc = 0; 2447 rx_ring->next_to_clean = 0; 2448 rx_ring->next_to_use = 0; 2449 } 2450 2451 /** 2452 * wx_clean_all_rx_rings - Free Rx Buffers for all queues 2453 * @wx: board private structure 2454 **/ 2455 void wx_clean_all_rx_rings(struct wx *wx) 2456 { 2457 int i; 2458 2459 for (i = 0; i < wx->num_rx_queues; i++) 2460 wx_clean_rx_ring(wx->rx_ring[i]); 2461 } 2462 EXPORT_SYMBOL(wx_clean_all_rx_rings); 2463 2464 /** 2465 * wx_free_rx_resources - Free Rx Resources 2466 * @rx_ring: ring to clean the resources from 2467 * 2468 * Free all receive software resources 2469 **/ 2470 static void wx_free_rx_resources(struct wx_ring *rx_ring) 2471 { 2472 wx_clean_rx_ring(rx_ring); 2473 kvfree(rx_ring->rx_buffer_info); 2474 rx_ring->rx_buffer_info = NULL; 2475 2476 /* if not set, then don't free */ 2477 if (!rx_ring->desc) 2478 return; 2479 2480 dma_free_coherent(rx_ring->dev, rx_ring->size, 2481 rx_ring->desc, rx_ring->dma); 2482 2483 rx_ring->desc = NULL; 2484 2485 if (rx_ring->page_pool) { 2486 page_pool_destroy(rx_ring->page_pool); 2487 rx_ring->page_pool = NULL; 2488 } 2489 } 2490 2491 /** 2492 * wx_free_all_rx_resources - Free Rx Resources for All Queues 2493 * @wx: pointer to hardware structure 2494 * 2495 * Free all receive software resources 2496 **/ 2497 static void wx_free_all_rx_resources(struct wx *wx) 2498 { 2499 int i; 2500 2501 for (i = 0; i < wx->num_rx_queues; i++) 2502 wx_free_rx_resources(wx->rx_ring[i]); 2503 } 2504 2505 /** 2506 * wx_clean_tx_ring - Free Tx Buffers 2507 * @tx_ring: ring to be cleaned 2508 **/ 2509 static void wx_clean_tx_ring(struct wx_ring *tx_ring) 2510 { 2511 struct wx_tx_buffer *tx_buffer; 2512 u16 i = tx_ring->next_to_clean; 2513 2514 tx_buffer = &tx_ring->tx_buffer_info[i]; 2515 2516 while (i != tx_ring->next_to_use) { 2517 union wx_tx_desc *eop_desc, *tx_desc; 2518 2519 /* Free all the Tx ring sk_buffs */ 2520 dev_kfree_skb_any(tx_buffer->skb); 2521 2522 /* unmap skb header data */ 2523 dma_unmap_single(tx_ring->dev, 2524 dma_unmap_addr(tx_buffer, dma), 2525 dma_unmap_len(tx_buffer, len), 2526 DMA_TO_DEVICE); 2527 2528 /* check for eop_desc to determine the end of the packet */ 2529 eop_desc = tx_buffer->next_to_watch; 2530 tx_desc = WX_TX_DESC(tx_ring, i); 2531 2532 /* unmap remaining buffers */ 2533 while (tx_desc != eop_desc) { 2534 tx_buffer++; 2535 tx_desc++; 2536 i++; 2537 if (unlikely(i == tx_ring->count)) { 2538 i = 0; 2539 tx_buffer = tx_ring->tx_buffer_info; 2540 tx_desc = WX_TX_DESC(tx_ring, 0); 2541 } 2542 2543 /* unmap any remaining paged data */ 2544 if (dma_unmap_len(tx_buffer, len)) 2545 dma_unmap_page(tx_ring->dev, 2546 dma_unmap_addr(tx_buffer, dma), 2547 dma_unmap_len(tx_buffer, len), 2548 DMA_TO_DEVICE); 2549 } 2550 2551 /* move us one more past the eop_desc for start of next pkt */ 2552 tx_buffer++; 2553 i++; 2554 if (unlikely(i == tx_ring->count)) { 2555 i = 0; 2556 tx_buffer = tx_ring->tx_buffer_info; 2557 } 2558 } 2559 2560 netdev_tx_reset_queue(wx_txring_txq(tx_ring)); 2561 2562 /* reset next_to_use and next_to_clean */ 2563 tx_ring->next_to_use = 0; 2564 tx_ring->next_to_clean = 0; 2565 } 2566 2567 /** 2568 * wx_clean_all_tx_rings - Free Tx Buffers for all queues 2569 * @wx: board private structure 2570 **/ 2571 void wx_clean_all_tx_rings(struct wx *wx) 2572 { 2573 int i; 2574 2575 for (i = 0; i < wx->num_tx_queues; i++) 2576 wx_clean_tx_ring(wx->tx_ring[i]); 2577 } 2578 EXPORT_SYMBOL(wx_clean_all_tx_rings); 2579 2580 /** 2581 * wx_free_tx_resources - Free Tx Resources per Queue 2582 * @tx_ring: Tx descriptor ring for a specific queue 2583 * 2584 * Free all transmit software resources 2585 **/ 2586 static void wx_free_tx_resources(struct wx_ring *tx_ring) 2587 { 2588 wx_clean_tx_ring(tx_ring); 2589 kvfree(tx_ring->tx_buffer_info); 2590 tx_ring->tx_buffer_info = NULL; 2591 2592 /* if not set, then don't free */ 2593 if (!tx_ring->desc) 2594 return; 2595 2596 dma_free_coherent(tx_ring->dev, tx_ring->size, 2597 tx_ring->desc, tx_ring->dma); 2598 tx_ring->desc = NULL; 2599 } 2600 2601 /** 2602 * wx_free_all_tx_resources - Free Tx Resources for All Queues 2603 * @wx: pointer to hardware structure 2604 * 2605 * Free all transmit software resources 2606 **/ 2607 static void wx_free_all_tx_resources(struct wx *wx) 2608 { 2609 int i; 2610 2611 for (i = 0; i < wx->num_tx_queues; i++) 2612 wx_free_tx_resources(wx->tx_ring[i]); 2613 } 2614 2615 void wx_free_resources(struct wx *wx) 2616 { 2617 wx_free_all_rx_resources(wx); 2618 wx_free_all_tx_resources(wx); 2619 } 2620 EXPORT_SYMBOL(wx_free_resources); 2621 2622 static int wx_alloc_page_pool(struct wx_ring *rx_ring) 2623 { 2624 int ret = 0; 2625 2626 struct page_pool_params pp_params = { 2627 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2628 .order = 0, 2629 .pool_size = rx_ring->count, 2630 .nid = dev_to_node(rx_ring->dev), 2631 .dev = rx_ring->dev, 2632 .dma_dir = DMA_FROM_DEVICE, 2633 .offset = 0, 2634 .max_len = PAGE_SIZE, 2635 }; 2636 2637 rx_ring->page_pool = page_pool_create(&pp_params); 2638 if (IS_ERR(rx_ring->page_pool)) { 2639 ret = PTR_ERR(rx_ring->page_pool); 2640 rx_ring->page_pool = NULL; 2641 } 2642 2643 return ret; 2644 } 2645 2646 /** 2647 * wx_setup_rx_resources - allocate Rx resources (Descriptors) 2648 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2649 * 2650 * Returns 0 on success, negative on failure 2651 **/ 2652 static int wx_setup_rx_resources(struct wx_ring *rx_ring) 2653 { 2654 struct device *dev = rx_ring->dev; 2655 int orig_node = dev_to_node(dev); 2656 int numa_node = NUMA_NO_NODE; 2657 int size, ret; 2658 2659 size = sizeof(struct wx_rx_buffer) * rx_ring->count; 2660 2661 if (rx_ring->q_vector) 2662 numa_node = rx_ring->q_vector->numa_node; 2663 2664 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2665 if (!rx_ring->rx_buffer_info) 2666 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL); 2667 if (!rx_ring->rx_buffer_info) 2668 goto err; 2669 2670 /* Round up to nearest 4K */ 2671 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc); 2672 rx_ring->size = ALIGN(rx_ring->size, 4096); 2673 2674 set_dev_node(dev, numa_node); 2675 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2676 &rx_ring->dma, GFP_KERNEL); 2677 if (!rx_ring->desc) { 2678 set_dev_node(dev, orig_node); 2679 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2680 &rx_ring->dma, GFP_KERNEL); 2681 } 2682 2683 if (!rx_ring->desc) 2684 goto err; 2685 2686 rx_ring->next_to_clean = 0; 2687 rx_ring->next_to_use = 0; 2688 2689 ret = wx_alloc_page_pool(rx_ring); 2690 if (ret < 0) { 2691 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret); 2692 goto err_desc; 2693 } 2694 2695 return 0; 2696 2697 err_desc: 2698 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2699 err: 2700 kvfree(rx_ring->rx_buffer_info); 2701 rx_ring->rx_buffer_info = NULL; 2702 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2703 return -ENOMEM; 2704 } 2705 2706 /** 2707 * wx_setup_all_rx_resources - allocate all queues Rx resources 2708 * @wx: pointer to hardware structure 2709 * 2710 * If this function returns with an error, then it's possible one or 2711 * more of the rings is populated (while the rest are not). It is the 2712 * callers duty to clean those orphaned rings. 2713 * 2714 * Return 0 on success, negative on failure 2715 **/ 2716 static int wx_setup_all_rx_resources(struct wx *wx) 2717 { 2718 int i, err = 0; 2719 2720 for (i = 0; i < wx->num_rx_queues; i++) { 2721 err = wx_setup_rx_resources(wx->rx_ring[i]); 2722 if (!err) 2723 continue; 2724 2725 wx_err(wx, "Allocation for Rx Queue %u failed\n", i); 2726 goto err_setup_rx; 2727 } 2728 2729 return 0; 2730 err_setup_rx: 2731 /* rewind the index freeing the rings as we go */ 2732 while (i--) 2733 wx_free_rx_resources(wx->rx_ring[i]); 2734 return err; 2735 } 2736 2737 /** 2738 * wx_setup_tx_resources - allocate Tx resources (Descriptors) 2739 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2740 * 2741 * Return 0 on success, negative on failure 2742 **/ 2743 static int wx_setup_tx_resources(struct wx_ring *tx_ring) 2744 { 2745 struct device *dev = tx_ring->dev; 2746 int orig_node = dev_to_node(dev); 2747 int numa_node = NUMA_NO_NODE; 2748 int size; 2749 2750 size = sizeof(struct wx_tx_buffer) * tx_ring->count; 2751 2752 if (tx_ring->q_vector) 2753 numa_node = tx_ring->q_vector->numa_node; 2754 2755 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2756 if (!tx_ring->tx_buffer_info) 2757 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL); 2758 if (!tx_ring->tx_buffer_info) 2759 goto err; 2760 2761 /* round up to nearest 4K */ 2762 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc); 2763 tx_ring->size = ALIGN(tx_ring->size, 4096); 2764 2765 set_dev_node(dev, numa_node); 2766 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2767 &tx_ring->dma, GFP_KERNEL); 2768 if (!tx_ring->desc) { 2769 set_dev_node(dev, orig_node); 2770 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2771 &tx_ring->dma, GFP_KERNEL); 2772 } 2773 2774 if (!tx_ring->desc) 2775 goto err; 2776 2777 tx_ring->next_to_use = 0; 2778 tx_ring->next_to_clean = 0; 2779 2780 return 0; 2781 2782 err: 2783 kvfree(tx_ring->tx_buffer_info); 2784 tx_ring->tx_buffer_info = NULL; 2785 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2786 return -ENOMEM; 2787 } 2788 2789 /** 2790 * wx_setup_all_tx_resources - allocate all queues Tx resources 2791 * @wx: pointer to private structure 2792 * 2793 * If this function returns with an error, then it's possible one or 2794 * more of the rings is populated (while the rest are not). It is the 2795 * callers duty to clean those orphaned rings. 2796 * 2797 * Return 0 on success, negative on failure 2798 **/ 2799 static int wx_setup_all_tx_resources(struct wx *wx) 2800 { 2801 int i, err = 0; 2802 2803 for (i = 0; i < wx->num_tx_queues; i++) { 2804 err = wx_setup_tx_resources(wx->tx_ring[i]); 2805 if (!err) 2806 continue; 2807 2808 wx_err(wx, "Allocation for Tx Queue %u failed\n", i); 2809 goto err_setup_tx; 2810 } 2811 2812 return 0; 2813 err_setup_tx: 2814 /* rewind the index freeing the rings as we go */ 2815 while (i--) 2816 wx_free_tx_resources(wx->tx_ring[i]); 2817 return err; 2818 } 2819 2820 int wx_setup_resources(struct wx *wx) 2821 { 2822 int err; 2823 2824 /* allocate transmit descriptors */ 2825 err = wx_setup_all_tx_resources(wx); 2826 if (err) 2827 return err; 2828 2829 /* allocate receive descriptors */ 2830 err = wx_setup_all_rx_resources(wx); 2831 if (err) 2832 goto err_free_tx; 2833 2834 err = wx_setup_isb_resources(wx); 2835 if (err) 2836 goto err_free_rx; 2837 2838 return 0; 2839 2840 err_free_rx: 2841 wx_free_all_rx_resources(wx); 2842 err_free_tx: 2843 wx_free_all_tx_resources(wx); 2844 2845 return err; 2846 } 2847 EXPORT_SYMBOL(wx_setup_resources); 2848 2849 /** 2850 * wx_get_stats64 - Get System Network Statistics 2851 * @netdev: network interface device structure 2852 * @stats: storage space for 64bit statistics 2853 */ 2854 void wx_get_stats64(struct net_device *netdev, 2855 struct rtnl_link_stats64 *stats) 2856 { 2857 struct wx *wx = netdev_priv(netdev); 2858 struct wx_hw_stats *hwstats; 2859 int i; 2860 2861 wx_update_stats(wx); 2862 2863 rcu_read_lock(); 2864 for (i = 0; i < wx->num_rx_queues; i++) { 2865 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]); 2866 u64 bytes, packets; 2867 unsigned int start; 2868 2869 if (ring) { 2870 do { 2871 start = u64_stats_fetch_begin(&ring->syncp); 2872 packets = ring->stats.packets; 2873 bytes = ring->stats.bytes; 2874 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2875 stats->rx_packets += packets; 2876 stats->rx_bytes += bytes; 2877 } 2878 } 2879 2880 for (i = 0; i < wx->num_tx_queues; i++) { 2881 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]); 2882 u64 bytes, packets; 2883 unsigned int start; 2884 2885 if (ring) { 2886 do { 2887 start = u64_stats_fetch_begin(&ring->syncp); 2888 packets = ring->stats.packets; 2889 bytes = ring->stats.bytes; 2890 } while (u64_stats_fetch_retry(&ring->syncp, 2891 start)); 2892 stats->tx_packets += packets; 2893 stats->tx_bytes += bytes; 2894 } 2895 } 2896 2897 rcu_read_unlock(); 2898 2899 hwstats = &wx->stats; 2900 stats->rx_errors = hwstats->crcerrs + hwstats->rlec; 2901 stats->multicast = hwstats->qmprc; 2902 stats->rx_length_errors = hwstats->rlec; 2903 stats->rx_crc_errors = hwstats->crcerrs; 2904 } 2905 EXPORT_SYMBOL(wx_get_stats64); 2906 2907 int wx_set_features(struct net_device *netdev, netdev_features_t features) 2908 { 2909 netdev_features_t changed = netdev->features ^ features; 2910 struct wx *wx = netdev_priv(netdev); 2911 bool need_reset = false; 2912 2913 if (features & NETIF_F_RXHASH) { 2914 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 2915 WX_RDB_RA_CTL_RSS_EN); 2916 wx->rss_enabled = true; 2917 } else { 2918 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0); 2919 wx->rss_enabled = false; 2920 } 2921 2922 netdev->features = features; 2923 2924 if (changed & NETIF_F_HW_VLAN_CTAG_RX && wx->do_reset) 2925 wx->do_reset(netdev); 2926 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER)) 2927 wx_set_rx_mode(netdev); 2928 2929 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 2930 return 0; 2931 2932 /* Check if Flow Director n-tuple support was enabled or disabled. If 2933 * the state changed, we need to reset. 2934 */ 2935 switch (features & NETIF_F_NTUPLE) { 2936 case NETIF_F_NTUPLE: 2937 /* turn off ATR, enable perfect filters and reset */ 2938 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 2939 need_reset = true; 2940 2941 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 2942 break; 2943 default: 2944 /* turn off perfect filters, enable ATR and reset */ 2945 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 2946 need_reset = true; 2947 2948 /* We cannot enable ATR if RSS is disabled */ 2949 if (wx->ring_feature[RING_F_RSS].limit <= 1) 2950 break; 2951 2952 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 2953 break; 2954 } 2955 2956 if (need_reset && wx->do_reset) 2957 wx->do_reset(netdev); 2958 2959 return 0; 2960 } 2961 EXPORT_SYMBOL(wx_set_features); 2962 2963 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \ 2964 NETIF_F_HW_VLAN_STAG_RX) 2965 2966 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \ 2967 NETIF_F_HW_VLAN_STAG_TX) 2968 2969 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \ 2970 NETIF_F_HW_VLAN_STAG_FILTER) 2971 2972 netdev_features_t wx_fix_features(struct net_device *netdev, 2973 netdev_features_t features) 2974 { 2975 netdev_features_t changed = netdev->features ^ features; 2976 struct wx *wx = netdev_priv(netdev); 2977 2978 if (changed & NETIF_VLAN_STRIPPING_FEATURES) { 2979 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES && 2980 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) { 2981 features &= ~NETIF_VLAN_STRIPPING_FEATURES; 2982 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES; 2983 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off."); 2984 } 2985 } 2986 2987 if (changed & NETIF_VLAN_INSERTION_FEATURES) { 2988 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES && 2989 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) { 2990 features &= ~NETIF_VLAN_INSERTION_FEATURES; 2991 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES; 2992 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off."); 2993 } 2994 } 2995 2996 if (changed & NETIF_VLAN_FILTERING_FEATURES) { 2997 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES && 2998 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) { 2999 features &= ~NETIF_VLAN_FILTERING_FEATURES; 3000 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES; 3001 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off."); 3002 } 3003 } 3004 3005 return features; 3006 } 3007 EXPORT_SYMBOL(wx_fix_features); 3008 3009 #define WX_MAX_TUNNEL_HDR_LEN 80 3010 netdev_features_t wx_features_check(struct sk_buff *skb, 3011 struct net_device *netdev, 3012 netdev_features_t features) 3013 { 3014 struct wx *wx = netdev_priv(netdev); 3015 3016 if (!skb->encapsulation) 3017 return features; 3018 3019 if (wx->mac.type == wx_mac_em) 3020 return features & ~NETIF_F_CSUM_MASK; 3021 3022 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) > 3023 WX_MAX_TUNNEL_HDR_LEN)) 3024 return features & ~NETIF_F_CSUM_MASK; 3025 3026 if (skb->inner_protocol_type == ENCAP_TYPE_ETHER && 3027 skb->inner_protocol != htons(ETH_P_IP) && 3028 skb->inner_protocol != htons(ETH_P_IPV6) && 3029 skb->inner_protocol != htons(ETH_P_TEB)) 3030 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 3031 3032 return features; 3033 } 3034 EXPORT_SYMBOL(wx_features_check); 3035 3036 void wx_set_ring(struct wx *wx, u32 new_tx_count, 3037 u32 new_rx_count, struct wx_ring *temp_ring) 3038 { 3039 int i, err = 0; 3040 3041 /* Setup new Tx resources and free the old Tx resources in that order. 3042 * We can then assign the new resources to the rings via a memcpy. 3043 * The advantage to this approach is that we are guaranteed to still 3044 * have resources even in the case of an allocation failure. 3045 */ 3046 if (new_tx_count != wx->tx_ring_count) { 3047 for (i = 0; i < wx->num_tx_queues; i++) { 3048 memcpy(&temp_ring[i], wx->tx_ring[i], 3049 sizeof(struct wx_ring)); 3050 3051 temp_ring[i].count = new_tx_count; 3052 err = wx_setup_tx_resources(&temp_ring[i]); 3053 if (err) { 3054 wx_err(wx, "setup new tx resources failed, keep using the old config\n"); 3055 while (i) { 3056 i--; 3057 wx_free_tx_resources(&temp_ring[i]); 3058 } 3059 return; 3060 } 3061 } 3062 3063 for (i = 0; i < wx->num_tx_queues; i++) { 3064 wx_free_tx_resources(wx->tx_ring[i]); 3065 3066 memcpy(wx->tx_ring[i], &temp_ring[i], 3067 sizeof(struct wx_ring)); 3068 } 3069 3070 wx->tx_ring_count = new_tx_count; 3071 } 3072 3073 /* Repeat the process for the Rx rings if needed */ 3074 if (new_rx_count != wx->rx_ring_count) { 3075 for (i = 0; i < wx->num_rx_queues; i++) { 3076 memcpy(&temp_ring[i], wx->rx_ring[i], 3077 sizeof(struct wx_ring)); 3078 3079 temp_ring[i].count = new_rx_count; 3080 err = wx_setup_rx_resources(&temp_ring[i]); 3081 if (err) { 3082 wx_err(wx, "setup new rx resources failed, keep using the old config\n"); 3083 while (i) { 3084 i--; 3085 wx_free_rx_resources(&temp_ring[i]); 3086 } 3087 return; 3088 } 3089 } 3090 3091 for (i = 0; i < wx->num_rx_queues; i++) { 3092 wx_free_rx_resources(wx->rx_ring[i]); 3093 memcpy(wx->rx_ring[i], &temp_ring[i], 3094 sizeof(struct wx_ring)); 3095 } 3096 3097 wx->rx_ring_count = new_rx_count; 3098 } 3099 } 3100 EXPORT_SYMBOL(wx_set_ring); 3101 3102 void wx_service_event_schedule(struct wx *wx) 3103 { 3104 if (!test_and_set_bit(WX_STATE_SERVICE_SCHED, wx->state)) 3105 queue_work(system_power_efficient_wq, &wx->service_task); 3106 } 3107 EXPORT_SYMBOL(wx_service_event_schedule); 3108 3109 void wx_service_event_complete(struct wx *wx) 3110 { 3111 if (WARN_ON(!test_bit(WX_STATE_SERVICE_SCHED, wx->state))) 3112 return; 3113 3114 /* flush memory to make sure state is correct before next watchdog */ 3115 smp_mb__before_atomic(); 3116 clear_bit(WX_STATE_SERVICE_SCHED, wx->state); 3117 } 3118 EXPORT_SYMBOL(wx_service_event_complete); 3119 3120 void wx_service_timer(struct timer_list *t) 3121 { 3122 struct wx *wx = timer_container_of(wx, t, service_timer); 3123 unsigned long next_event_offset = HZ * 2; 3124 3125 /* Reset the timer */ 3126 mod_timer(&wx->service_timer, next_event_offset + jiffies); 3127 3128 wx_service_event_schedule(wx); 3129 } 3130 EXPORT_SYMBOL(wx_service_timer); 3131 3132 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers."); 3133 MODULE_LICENSE("GPL"); 3134