1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <net/ip6_checksum.h> 6 #include <net/page_pool/helpers.h> 7 #include <net/inet_ecn.h> 8 #include <linux/workqueue.h> 9 #include <linux/iopoll.h> 10 #include <linux/sctp.h> 11 #include <linux/pci.h> 12 #include <net/tcp.h> 13 #include <net/ip.h> 14 15 #include "wx_type.h" 16 #include "wx_lib.h" 17 #include "wx_ptp.h" 18 #include "wx_hw.h" 19 #include "wx_vf_lib.h" 20 21 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 22 static struct wx_dec_ptype wx_ptype_lookup[256] = { 23 /* L2: mac */ 24 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 25 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2), 26 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 27 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 28 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 29 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2), 30 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 31 32 /* L2: ethertype filter */ 33 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE), 34 35 /* L3: ip non-tunnel */ 36 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3), 37 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3), 38 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4), 39 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4), 40 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4), 41 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3), 42 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3), 43 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3), 44 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4), 45 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4), 46 47 /* L2: fcoe */ 48 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 49 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3), 50 51 /* IPv4 --> IPv4/IPv6 */ 52 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3), 53 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3), 54 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4), 55 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4), 56 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4), 57 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3), 58 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3), 59 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4), 60 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4), 61 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4), 62 63 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */ 64 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3), 65 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3), 66 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3), 67 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4), 68 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4), 69 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4), 70 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3), 71 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3), 72 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4), 73 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4), 74 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4), 75 76 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */ 77 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3), 78 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3), 79 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3), 80 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4), 81 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4), 82 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4), 83 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3), 84 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3), 85 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4), 86 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4), 87 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4), 88 89 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */ 90 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3), 91 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3), 92 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3), 93 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4), 94 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4), 95 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4), 96 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3), 97 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3), 98 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4), 99 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4), 100 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4), 101 102 /* IPv6 --> IPv4/IPv6 */ 103 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3), 104 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3), 105 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4), 106 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4), 107 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4), 108 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3), 109 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3), 110 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4), 111 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4), 112 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4), 113 114 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */ 115 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3), 116 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3), 117 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3), 118 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4), 119 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4), 120 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4), 121 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3), 122 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3), 123 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4), 124 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4), 125 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4), 126 127 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */ 128 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3), 129 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3), 130 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3), 131 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4), 132 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4), 133 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4), 134 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3), 135 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3), 136 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4), 137 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4), 138 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4), 139 140 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */ 141 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3), 142 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3), 143 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3), 144 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4), 145 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4), 146 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4), 147 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3), 148 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3), 149 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4), 150 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4), 151 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4), 152 }; 153 154 struct wx_dec_ptype wx_decode_ptype(const u8 ptype) 155 { 156 return wx_ptype_lookup[ptype]; 157 } 158 EXPORT_SYMBOL(wx_decode_ptype); 159 160 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */ 161 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc, 162 const u32 stat_err_bits) 163 { 164 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 165 } 166 167 static void wx_dma_sync_frag(struct wx_ring *rx_ring, 168 struct wx_rx_buffer *rx_buffer) 169 { 170 struct sk_buff *skb = rx_buffer->skb; 171 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 172 173 dma_sync_single_range_for_cpu(rx_ring->dev, 174 WX_CB(skb)->dma, 175 skb_frag_off(frag), 176 skb_frag_size(frag), 177 DMA_FROM_DEVICE); 178 } 179 180 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring, 181 union wx_rx_desc *rx_desc, 182 struct sk_buff **skb, 183 int *rx_buffer_pgcnt) 184 { 185 struct wx_rx_buffer *rx_buffer; 186 unsigned int size; 187 188 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 189 size = le16_to_cpu(rx_desc->wb.upper.length); 190 191 #if (PAGE_SIZE < 8192) 192 *rx_buffer_pgcnt = page_count(rx_buffer->page); 193 #else 194 *rx_buffer_pgcnt = 0; 195 #endif 196 197 prefetchw(rx_buffer->page); 198 *skb = rx_buffer->skb; 199 200 /* Delay unmapping of the first packet. It carries the header 201 * information, HW may still access the header after the writeback. 202 * Only unmap it when EOP is reached 203 */ 204 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) { 205 if (!*skb) 206 goto skip_sync; 207 } else { 208 if (*skb) 209 wx_dma_sync_frag(rx_ring, rx_buffer); 210 } 211 212 /* we are reusing so sync this buffer for CPU use */ 213 dma_sync_single_range_for_cpu(rx_ring->dev, 214 rx_buffer->dma, 215 rx_buffer->page_offset, 216 size, 217 DMA_FROM_DEVICE); 218 skip_sync: 219 return rx_buffer; 220 } 221 222 static void wx_put_rx_buffer(struct wx_ring *rx_ring, 223 struct wx_rx_buffer *rx_buffer, 224 struct sk_buff *skb, 225 int rx_buffer_pgcnt) 226 { 227 /* clear contents of rx_buffer */ 228 rx_buffer->page = NULL; 229 rx_buffer->skb = NULL; 230 } 231 232 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring, 233 struct wx_rx_buffer *rx_buffer, 234 union wx_rx_desc *rx_desc) 235 { 236 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 237 #if (PAGE_SIZE < 8192) 238 unsigned int truesize = WX_RX_BUFSZ; 239 #else 240 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 241 #endif 242 struct sk_buff *skb = rx_buffer->skb; 243 244 if (!skb) { 245 void *page_addr = page_address(rx_buffer->page) + 246 rx_buffer->page_offset; 247 248 /* prefetch first cache line of first page */ 249 net_prefetch(page_addr); 250 251 /* allocate a skb to store the frags */ 252 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256); 253 if (unlikely(!skb)) 254 return NULL; 255 256 /* we will be copying header into skb->data in 257 * pskb_may_pull so it is in our interest to prefetch 258 * it now to avoid a possible cache miss 259 */ 260 prefetchw(skb->data); 261 262 if (size <= WX_RXBUFFER_256) { 263 memcpy(__skb_put(skb, size), page_addr, 264 ALIGN(size, sizeof(long))); 265 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true); 266 return skb; 267 } 268 269 skb_mark_for_recycle(skb); 270 271 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) 272 WX_CB(skb)->dma = rx_buffer->dma; 273 274 skb_add_rx_frag(skb, 0, rx_buffer->page, 275 rx_buffer->page_offset, 276 size, truesize); 277 goto out; 278 279 } else { 280 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, 281 rx_buffer->page_offset, size, truesize); 282 } 283 284 out: 285 #if (PAGE_SIZE < 8192) 286 /* flip page offset to other buffer */ 287 rx_buffer->page_offset ^= truesize; 288 #else 289 /* move offset up to the next cache line */ 290 rx_buffer->page_offset += truesize; 291 #endif 292 293 return skb; 294 } 295 296 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring, 297 struct wx_rx_buffer *bi) 298 { 299 struct page *page = bi->page; 300 dma_addr_t dma; 301 302 /* since we are recycling buffers we should seldom need to alloc */ 303 if (likely(page)) 304 return true; 305 306 page = page_pool_dev_alloc_pages(rx_ring->page_pool); 307 if (unlikely(!page)) 308 return false; 309 dma = page_pool_get_dma_addr(page); 310 311 bi->dma = dma; 312 bi->page = page; 313 bi->page_offset = 0; 314 315 return true; 316 } 317 318 /** 319 * wx_alloc_rx_buffers - Replace used receive buffers 320 * @rx_ring: ring to place buffers on 321 * @cleaned_count: number of buffers to replace 322 **/ 323 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count) 324 { 325 u16 i = rx_ring->next_to_use; 326 union wx_rx_desc *rx_desc; 327 struct wx_rx_buffer *bi; 328 329 /* nothing to do */ 330 if (!cleaned_count) 331 return; 332 333 rx_desc = WX_RX_DESC(rx_ring, i); 334 bi = &rx_ring->rx_buffer_info[i]; 335 i -= rx_ring->count; 336 337 do { 338 if (!wx_alloc_mapped_page(rx_ring, bi)) 339 break; 340 341 /* sync the buffer for use by the device */ 342 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 343 bi->page_offset, 344 WX_RX_BUFSZ, 345 DMA_FROM_DEVICE); 346 347 rx_desc->read.pkt_addr = 348 cpu_to_le64(bi->dma + bi->page_offset); 349 350 rx_desc++; 351 bi++; 352 i++; 353 if (unlikely(!i)) { 354 rx_desc = WX_RX_DESC(rx_ring, 0); 355 bi = rx_ring->rx_buffer_info; 356 i -= rx_ring->count; 357 } 358 359 /* clear the status bits for the next_to_use descriptor */ 360 rx_desc->wb.upper.status_error = 0; 361 /* clear the length for the next_to_use descriptor */ 362 rx_desc->wb.upper.length = 0; 363 364 cleaned_count--; 365 } while (cleaned_count); 366 367 i += rx_ring->count; 368 369 if (rx_ring->next_to_use != i) { 370 rx_ring->next_to_use = i; 371 /* update next to alloc since we have filled the ring */ 372 rx_ring->next_to_alloc = i; 373 374 /* Force memory writes to complete before letting h/w 375 * know there are new descriptors to fetch. (Only 376 * applicable for weak-ordered memory model archs, 377 * such as IA-64). 378 */ 379 wmb(); 380 writel(i, rx_ring->tail); 381 } 382 } 383 384 u16 wx_desc_unused(struct wx_ring *ring) 385 { 386 u16 ntc = ring->next_to_clean; 387 u16 ntu = ring->next_to_use; 388 389 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 390 } 391 392 /** 393 * wx_is_non_eop - process handling of non-EOP buffers 394 * @rx_ring: Rx ring being processed 395 * @rx_desc: Rx descriptor for current buffer 396 * @skb: Current socket buffer containing buffer in progress 397 * 398 * This function updates next to clean. If the buffer is an EOP buffer 399 * this function exits returning false, otherwise it will place the 400 * sk_buff in the next buffer to be chained and return true indicating 401 * that this is in fact a non-EOP buffer. 402 **/ 403 static bool wx_is_non_eop(struct wx_ring *rx_ring, 404 union wx_rx_desc *rx_desc, 405 struct sk_buff *skb) 406 { 407 u32 ntc = rx_ring->next_to_clean + 1; 408 409 /* fetch, update, and store next to clean */ 410 ntc = (ntc < rx_ring->count) ? ntc : 0; 411 rx_ring->next_to_clean = ntc; 412 413 prefetch(WX_RX_DESC(rx_ring, ntc)); 414 415 /* if we are the last buffer then there is nothing else to do */ 416 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))) 417 return false; 418 419 rx_ring->rx_buffer_info[ntc].skb = skb; 420 rx_ring->rx_stats.non_eop_descs++; 421 422 return true; 423 } 424 425 static void wx_pull_tail(struct sk_buff *skb) 426 { 427 skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 428 unsigned int pull_len; 429 unsigned char *va; 430 431 /* it is valid to use page_address instead of kmap since we are 432 * working with pages allocated out of the lomem pool per 433 * alloc_page(GFP_ATOMIC) 434 */ 435 va = skb_frag_address(frag); 436 437 /* we need the header to contain the greater of either ETH_HLEN or 438 * 60 bytes if the skb->len is less than 60 for skb_pad. 439 */ 440 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256); 441 442 /* align pull length to size of long to optimize memcpy performance */ 443 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 444 445 /* update all of the pointers */ 446 skb_frag_size_sub(frag, pull_len); 447 skb_frag_off_add(frag, pull_len); 448 skb->data_len -= pull_len; 449 skb->tail += pull_len; 450 } 451 452 /** 453 * wx_cleanup_headers - Correct corrupted or empty headers 454 * @rx_ring: rx descriptor ring packet is being transacted on 455 * @rx_desc: pointer to the EOP Rx descriptor 456 * @skb: pointer to current skb being fixed 457 * 458 * Check for corrupted packet headers caused by senders on the local L2 459 * embedded NIC switch not setting up their Tx Descriptors right. These 460 * should be very rare. 461 * 462 * Also address the case where we are pulling data in on pages only 463 * and as such no data is present in the skb header. 464 * 465 * In addition if skb is not at least 60 bytes we need to pad it so that 466 * it is large enough to qualify as a valid Ethernet frame. 467 * 468 * Returns true if an error was encountered and skb was freed. 469 **/ 470 static bool wx_cleanup_headers(struct wx_ring *rx_ring, 471 union wx_rx_desc *rx_desc, 472 struct sk_buff *skb) 473 { 474 struct net_device *netdev = rx_ring->netdev; 475 476 /* verify that the packet does not have any known errors */ 477 if (!netdev || 478 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) && 479 !(netdev->features & NETIF_F_RXALL))) { 480 dev_kfree_skb_any(skb); 481 return true; 482 } 483 484 /* place header in linear portion of buffer */ 485 if (!skb_headlen(skb)) 486 wx_pull_tail(skb); 487 488 /* if eth_skb_pad returns an error the skb was freed */ 489 if (eth_skb_pad(skb)) 490 return true; 491 492 return false; 493 } 494 495 static void wx_rx_hash(struct wx_ring *ring, 496 union wx_rx_desc *rx_desc, 497 struct sk_buff *skb) 498 { 499 u16 rss_type; 500 501 if (!(ring->netdev->features & NETIF_F_RXHASH)) 502 return; 503 504 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 505 WX_RXD_RSSTYPE_MASK; 506 507 if (!rss_type) 508 return; 509 510 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 511 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? 512 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); 513 } 514 515 /** 516 * wx_rx_checksum - indicate in skb if hw indicated a good cksum 517 * @ring: structure containing ring specific data 518 * @rx_desc: current Rx descriptor being processed 519 * @skb: skb currently being received and modified 520 **/ 521 static void wx_rx_checksum(struct wx_ring *ring, 522 union wx_rx_desc *rx_desc, 523 struct sk_buff *skb) 524 { 525 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc)); 526 527 skb_checksum_none_assert(skb); 528 /* Rx csum disabled */ 529 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 530 return; 531 532 /* if IPv4 header checksum error */ 533 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) && 534 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) || 535 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) && 536 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) { 537 ring->rx_stats.csum_err++; 538 return; 539 } 540 541 /* L4 checksum offload flag must set for the below code to work */ 542 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS)) 543 return; 544 545 /* Hardware can't guarantee csum if IPv6 Dest Header found */ 546 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && 547 wx_test_staterr(rx_desc, WX_RXD_STAT_IPV6EX)) 548 return; 549 550 /* if L4 checksum error */ 551 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) { 552 ring->rx_stats.csum_err++; 553 return; 554 } 555 556 /* It must be a TCP or UDP or SCTP packet with a valid checksum */ 557 skb->ip_summed = CHECKSUM_UNNECESSARY; 558 559 /* If there is an outer header present that might contain a checksum 560 * we need to bump the checksum level by 1 to reflect the fact that 561 * we are indicating we validated the inner checksum. 562 */ 563 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG) 564 __skb_incr_checksum_unnecessary(skb); 565 ring->rx_stats.csum_good_cnt++; 566 } 567 568 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc, 569 struct sk_buff *skb) 570 { 571 u16 ethertype; 572 u8 idx = 0; 573 574 if ((ring->netdev->features & 575 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) && 576 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) { 577 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & 578 0x1c0) >> 6; 579 ethertype = ring->q_vector->wx->tpid[idx]; 580 __vlan_hwaccel_put_tag(skb, htons(ethertype), 581 le16_to_cpu(rx_desc->wb.upper.vlan)); 582 } 583 } 584 585 /** 586 * wx_process_skb_fields - Populate skb header fields from Rx descriptor 587 * @rx_ring: rx descriptor ring packet is being transacted on 588 * @rx_desc: pointer to the EOP Rx descriptor 589 * @skb: pointer to current skb being populated 590 * 591 * This function checks the ring, descriptor, and packet information in 592 * order to populate the hash, checksum, protocol, and 593 * other fields within the skb. 594 **/ 595 static void wx_process_skb_fields(struct wx_ring *rx_ring, 596 union wx_rx_desc *rx_desc, 597 struct sk_buff *skb) 598 { 599 struct wx *wx = netdev_priv(rx_ring->netdev); 600 601 wx_rx_hash(rx_ring, rx_desc, skb); 602 wx_rx_checksum(rx_ring, rx_desc, skb); 603 604 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, wx->flags)) && 605 unlikely(wx_test_staterr(rx_desc, WX_RXD_STAT_TS))) { 606 wx_ptp_rx_hwtstamp(rx_ring->q_vector->wx, skb); 607 rx_ring->last_rx_timestamp = jiffies; 608 } 609 610 wx_rx_vlan(rx_ring, rx_desc, skb); 611 skb_record_rx_queue(skb, rx_ring->queue_index); 612 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 613 } 614 615 /** 616 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 617 * @q_vector: structure containing interrupt and ring information 618 * @rx_ring: rx descriptor ring to transact packets on 619 * @budget: Total limit on number of packets to process 620 * 621 * This function provides a "bounce buffer" approach to Rx interrupt 622 * processing. The advantage to this is that on systems that have 623 * expensive overhead for IOMMU access this provides a means of avoiding 624 * it by maintaining the mapping of the page to the system. 625 * 626 * Returns amount of work completed. 627 **/ 628 static int wx_clean_rx_irq(struct wx_q_vector *q_vector, 629 struct wx_ring *rx_ring, 630 int budget) 631 { 632 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 633 u16 cleaned_count = wx_desc_unused(rx_ring); 634 635 do { 636 struct wx_rx_buffer *rx_buffer; 637 union wx_rx_desc *rx_desc; 638 struct sk_buff *skb; 639 int rx_buffer_pgcnt; 640 641 /* return some buffers to hardware, one at a time is too slow */ 642 if (cleaned_count >= WX_RX_BUFFER_WRITE) { 643 wx_alloc_rx_buffers(rx_ring, cleaned_count); 644 cleaned_count = 0; 645 } 646 647 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean); 648 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD)) 649 break; 650 651 /* This memory barrier is needed to keep us from reading 652 * any other fields out of the rx_desc until we know the 653 * descriptor has been written back 654 */ 655 dma_rmb(); 656 657 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt); 658 659 /* retrieve a buffer from the ring */ 660 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc); 661 662 /* exit if we failed to retrieve a buffer */ 663 if (!skb) { 664 rx_ring->rx_stats.alloc_rx_buff_failed++; 665 break; 666 } 667 668 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt); 669 cleaned_count++; 670 671 /* place incomplete frames back on ring for completion */ 672 if (wx_is_non_eop(rx_ring, rx_desc, skb)) 673 continue; 674 675 /* verify the packet layout is correct */ 676 if (wx_cleanup_headers(rx_ring, rx_desc, skb)) 677 continue; 678 679 /* probably a little skewed due to removing CRC */ 680 total_rx_bytes += skb->len; 681 682 /* populate checksum, timestamp, VLAN, and protocol */ 683 wx_process_skb_fields(rx_ring, rx_desc, skb); 684 napi_gro_receive(&q_vector->napi, skb); 685 686 /* update budget accounting */ 687 total_rx_packets++; 688 } while (likely(total_rx_packets < budget)); 689 690 u64_stats_update_begin(&rx_ring->syncp); 691 rx_ring->stats.packets += total_rx_packets; 692 rx_ring->stats.bytes += total_rx_bytes; 693 u64_stats_update_end(&rx_ring->syncp); 694 q_vector->rx.total_packets += total_rx_packets; 695 q_vector->rx.total_bytes += total_rx_bytes; 696 697 return total_rx_packets; 698 } 699 700 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring) 701 { 702 return netdev_get_tx_queue(ring->netdev, ring->queue_index); 703 } 704 705 /** 706 * wx_clean_tx_irq - Reclaim resources after transmit completes 707 * @q_vector: structure containing interrupt and ring information 708 * @tx_ring: tx ring to clean 709 * @napi_budget: Used to determine if we are in netpoll 710 **/ 711 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector, 712 struct wx_ring *tx_ring, int napi_budget) 713 { 714 unsigned int budget = q_vector->wx->tx_work_limit; 715 unsigned int total_bytes = 0, total_packets = 0; 716 struct wx *wx = netdev_priv(tx_ring->netdev); 717 unsigned int i = tx_ring->next_to_clean; 718 struct wx_tx_buffer *tx_buffer; 719 union wx_tx_desc *tx_desc; 720 721 if (!netif_carrier_ok(tx_ring->netdev)) 722 return true; 723 724 tx_buffer = &tx_ring->tx_buffer_info[i]; 725 tx_desc = WX_TX_DESC(tx_ring, i); 726 i -= tx_ring->count; 727 728 do { 729 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch; 730 731 /* if next_to_watch is not set then there is no work pending */ 732 if (!eop_desc) 733 break; 734 735 /* prevent any other reads prior to eop_desc */ 736 smp_rmb(); 737 738 /* if DD is not set pending work has not been completed */ 739 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD))) 740 break; 741 742 /* clear next_to_watch to prevent false hangs */ 743 tx_buffer->next_to_watch = NULL; 744 745 /* update the statistics for this packet */ 746 total_bytes += tx_buffer->bytecount; 747 total_packets += tx_buffer->gso_segs; 748 749 /* schedule check for Tx timestamp */ 750 if (unlikely(test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state)) && 751 skb_shinfo(tx_buffer->skb)->tx_flags & SKBTX_IN_PROGRESS) 752 ptp_schedule_worker(wx->ptp_clock, 0); 753 754 /* free the skb */ 755 napi_consume_skb(tx_buffer->skb, napi_budget); 756 757 /* unmap skb header data */ 758 dma_unmap_single(tx_ring->dev, 759 dma_unmap_addr(tx_buffer, dma), 760 dma_unmap_len(tx_buffer, len), 761 DMA_TO_DEVICE); 762 763 /* clear tx_buffer data */ 764 dma_unmap_len_set(tx_buffer, len, 0); 765 766 /* unmap remaining buffers */ 767 while (tx_desc != eop_desc) { 768 tx_buffer++; 769 tx_desc++; 770 i++; 771 if (unlikely(!i)) { 772 i -= tx_ring->count; 773 tx_buffer = tx_ring->tx_buffer_info; 774 tx_desc = WX_TX_DESC(tx_ring, 0); 775 } 776 777 /* unmap any remaining paged data */ 778 if (dma_unmap_len(tx_buffer, len)) { 779 dma_unmap_page(tx_ring->dev, 780 dma_unmap_addr(tx_buffer, dma), 781 dma_unmap_len(tx_buffer, len), 782 DMA_TO_DEVICE); 783 dma_unmap_len_set(tx_buffer, len, 0); 784 } 785 } 786 787 /* move us one more past the eop_desc for start of next pkt */ 788 tx_buffer++; 789 tx_desc++; 790 i++; 791 if (unlikely(!i)) { 792 i -= tx_ring->count; 793 tx_buffer = tx_ring->tx_buffer_info; 794 tx_desc = WX_TX_DESC(tx_ring, 0); 795 } 796 797 /* issue prefetch for next Tx descriptor */ 798 prefetch(tx_desc); 799 800 /* update budget accounting */ 801 budget--; 802 } while (likely(budget)); 803 804 i += tx_ring->count; 805 tx_ring->next_to_clean = i; 806 u64_stats_update_begin(&tx_ring->syncp); 807 tx_ring->stats.bytes += total_bytes; 808 tx_ring->stats.packets += total_packets; 809 u64_stats_update_end(&tx_ring->syncp); 810 q_vector->tx.total_bytes += total_bytes; 811 q_vector->tx.total_packets += total_packets; 812 813 netdev_tx_completed_queue(wx_txring_txq(tx_ring), 814 total_packets, total_bytes); 815 816 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 817 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && 818 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { 819 /* Make sure that anybody stopping the queue after this 820 * sees the new next_to_clean. 821 */ 822 smp_mb(); 823 824 if (__netif_subqueue_stopped(tx_ring->netdev, 825 tx_ring->queue_index) && 826 netif_running(tx_ring->netdev)) { 827 netif_wake_subqueue(tx_ring->netdev, 828 tx_ring->queue_index); 829 ++tx_ring->tx_stats.restart_queue; 830 } 831 } 832 833 return !!budget; 834 } 835 836 static void wx_update_rx_dim_sample(struct wx_q_vector *q_vector) 837 { 838 struct dim_sample sample = {}; 839 840 dim_update_sample(q_vector->total_events, 841 q_vector->rx.total_packets, 842 q_vector->rx.total_bytes, 843 &sample); 844 845 net_dim(&q_vector->rx.dim, &sample); 846 } 847 848 static void wx_update_tx_dim_sample(struct wx_q_vector *q_vector) 849 { 850 struct dim_sample sample = {}; 851 852 dim_update_sample(q_vector->total_events, 853 q_vector->tx.total_packets, 854 q_vector->tx.total_bytes, 855 &sample); 856 857 net_dim(&q_vector->tx.dim, &sample); 858 } 859 860 static void wx_update_dim_sample(struct wx_q_vector *q_vector) 861 { 862 wx_update_rx_dim_sample(q_vector); 863 wx_update_tx_dim_sample(q_vector); 864 } 865 866 /** 867 * wx_poll - NAPI polling RX/TX cleanup routine 868 * @napi: napi struct with our devices info in it 869 * @budget: amount of work driver is allowed to do this pass, in packets 870 * 871 * This function will clean all queues associated with a q_vector. 872 **/ 873 static int wx_poll(struct napi_struct *napi, int budget) 874 { 875 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi); 876 int per_ring_budget, work_done = 0; 877 struct wx *wx = q_vector->wx; 878 bool clean_complete = true; 879 struct wx_ring *ring; 880 881 wx_for_each_ring(ring, q_vector->tx) { 882 if (!wx_clean_tx_irq(q_vector, ring, budget)) 883 clean_complete = false; 884 } 885 886 /* Exit if we are called by netpoll */ 887 if (budget <= 0) 888 return budget; 889 890 /* attempt to distribute budget to each queue fairly, but don't allow 891 * the budget to go below 1 because we'll exit polling 892 */ 893 if (q_vector->rx.count > 1) 894 per_ring_budget = max(budget / q_vector->rx.count, 1); 895 else 896 per_ring_budget = budget; 897 898 wx_for_each_ring(ring, q_vector->rx) { 899 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget); 900 901 work_done += cleaned; 902 if (cleaned >= per_ring_budget) 903 clean_complete = false; 904 } 905 906 /* If all work not completed, return budget and keep polling */ 907 if (!clean_complete) 908 return budget; 909 910 /* all work done, exit the polling mode */ 911 if (likely(napi_complete_done(napi, work_done))) { 912 if (wx->adaptive_itr) 913 wx_update_dim_sample(q_vector); 914 if (netif_running(wx->netdev)) 915 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx)); 916 } 917 918 return min(work_done, budget - 1); 919 } 920 921 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size) 922 { 923 if (likely(wx_desc_unused(tx_ring) >= size)) 924 return 0; 925 926 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); 927 928 /* For the next check */ 929 smp_mb(); 930 931 /* We need to check again in a case another CPU has just 932 * made room available. 933 */ 934 if (likely(wx_desc_unused(tx_ring) < size)) 935 return -EBUSY; 936 937 /* A reprieve! - use start_queue because it doesn't call schedule */ 938 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); 939 ++tx_ring->tx_stats.restart_queue; 940 941 return 0; 942 } 943 944 static u32 wx_tx_cmd_type(u32 tx_flags) 945 { 946 /* set type for advanced descriptor with frame checksum insertion */ 947 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS; 948 949 /* set HW vlan bit if vlan is present */ 950 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE); 951 /* set segmentation enable bits for TSO/FSO */ 952 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE); 953 /* set timestamp bit if present */ 954 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP); 955 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC); 956 957 return cmd_type; 958 } 959 960 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc, 961 u32 tx_flags, unsigned int paylen) 962 { 963 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT; 964 965 /* enable L4 checksum for TSO and TX checksum offload */ 966 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS); 967 /* enable IPv4 checksum for TSO */ 968 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS); 969 /* enable outer IPv4 checksum for TSO */ 970 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4, 971 WX_TXD_EIPCS); 972 /* Check Context must be set if Tx switch is enabled, which it 973 * always is for case where virtual functions are running 974 */ 975 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC); 976 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC, 977 WX_TXD_IPSEC); 978 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 979 } 980 981 static int wx_tx_map(struct wx_ring *tx_ring, 982 struct wx_tx_buffer *first, 983 const u8 hdr_len) 984 { 985 struct sk_buff *skb = first->skb; 986 struct wx_tx_buffer *tx_buffer; 987 u32 tx_flags = first->tx_flags; 988 u16 i = tx_ring->next_to_use; 989 unsigned int data_len, size; 990 union wx_tx_desc *tx_desc; 991 skb_frag_t *frag; 992 dma_addr_t dma; 993 u32 cmd_type; 994 995 cmd_type = wx_tx_cmd_type(tx_flags); 996 tx_desc = WX_TX_DESC(tx_ring, i); 997 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); 998 999 size = skb_headlen(skb); 1000 data_len = skb->data_len; 1001 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 1002 1003 tx_buffer = first; 1004 1005 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 1006 if (dma_mapping_error(tx_ring->dev, dma)) 1007 goto dma_error; 1008 1009 /* record length, and DMA address */ 1010 dma_unmap_len_set(tx_buffer, len, size); 1011 dma_unmap_addr_set(tx_buffer, dma, dma); 1012 1013 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1014 1015 while (unlikely(size > WX_MAX_DATA_PER_TXD)) { 1016 tx_desc->read.cmd_type_len = 1017 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD); 1018 1019 i++; 1020 tx_desc++; 1021 if (i == tx_ring->count) { 1022 tx_desc = WX_TX_DESC(tx_ring, 0); 1023 i = 0; 1024 } 1025 tx_desc->read.olinfo_status = 0; 1026 1027 dma += WX_MAX_DATA_PER_TXD; 1028 size -= WX_MAX_DATA_PER_TXD; 1029 1030 tx_desc->read.buffer_addr = cpu_to_le64(dma); 1031 } 1032 1033 if (likely(!data_len)) 1034 break; 1035 1036 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 1037 1038 i++; 1039 tx_desc++; 1040 if (i == tx_ring->count) { 1041 tx_desc = WX_TX_DESC(tx_ring, 0); 1042 i = 0; 1043 } 1044 tx_desc->read.olinfo_status = 0; 1045 1046 size = skb_frag_size(frag); 1047 1048 data_len -= size; 1049 1050 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1051 DMA_TO_DEVICE); 1052 1053 tx_buffer = &tx_ring->tx_buffer_info[i]; 1054 } 1055 1056 /* write last descriptor with RS and EOP bits */ 1057 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS; 1058 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 1059 1060 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount); 1061 1062 /* set the timestamp */ 1063 first->time_stamp = jiffies; 1064 skb_tx_timestamp(skb); 1065 1066 /* Force memory writes to complete before letting h/w know there 1067 * are new descriptors to fetch. (Only applicable for weak-ordered 1068 * memory model archs, such as IA-64). 1069 * 1070 * We also need this memory barrier to make certain all of the 1071 * status bits have been updated before next_to_watch is written. 1072 */ 1073 wmb(); 1074 1075 /* set next_to_watch value indicating a packet is present */ 1076 first->next_to_watch = tx_desc; 1077 1078 i++; 1079 if (i == tx_ring->count) 1080 i = 0; 1081 1082 tx_ring->next_to_use = i; 1083 1084 wx_maybe_stop_tx(tx_ring, DESC_NEEDED); 1085 1086 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more()) 1087 writel(i, tx_ring->tail); 1088 1089 return 0; 1090 dma_error: 1091 dev_err(tx_ring->dev, "TX DMA map failed\n"); 1092 1093 /* clear dma mappings for failed tx_buffer_info map */ 1094 for (;;) { 1095 tx_buffer = &tx_ring->tx_buffer_info[i]; 1096 if (dma_unmap_len(tx_buffer, len)) 1097 dma_unmap_page(tx_ring->dev, 1098 dma_unmap_addr(tx_buffer, dma), 1099 dma_unmap_len(tx_buffer, len), 1100 DMA_TO_DEVICE); 1101 dma_unmap_len_set(tx_buffer, len, 0); 1102 if (tx_buffer == first) 1103 break; 1104 if (i == 0) 1105 i += tx_ring->count; 1106 i--; 1107 } 1108 1109 dev_kfree_skb_any(first->skb); 1110 first->skb = NULL; 1111 1112 tx_ring->next_to_use = i; 1113 1114 return -ENOMEM; 1115 } 1116 1117 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens, 1118 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) 1119 { 1120 struct wx_tx_context_desc *context_desc; 1121 u16 i = tx_ring->next_to_use; 1122 1123 context_desc = WX_TX_CTXTDESC(tx_ring, i); 1124 i++; 1125 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 1126 1127 /* set bits to identify this as an advanced context descriptor */ 1128 type_tucmd |= WX_TXD_DTYP_CTXT; 1129 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 1130 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); 1131 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 1132 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 1133 } 1134 1135 union network_header { 1136 struct iphdr *ipv4; 1137 struct ipv6hdr *ipv6; 1138 void *raw; 1139 }; 1140 1141 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first) 1142 { 1143 u8 tun_prot = 0, l4_prot = 0, ptype = 0; 1144 struct sk_buff *skb = first->skb; 1145 unsigned char *exthdr, *l4_hdr; 1146 __be16 frag_off; 1147 1148 if (skb->encapsulation) { 1149 union network_header hdr; 1150 1151 switch (first->protocol) { 1152 case htons(ETH_P_IP): 1153 tun_prot = ip_hdr(skb)->protocol; 1154 ptype = WX_PTYPE_TUN_IPV4; 1155 break; 1156 case htons(ETH_P_IPV6): 1157 l4_hdr = skb_transport_header(skb); 1158 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1159 tun_prot = ipv6_hdr(skb)->nexthdr; 1160 if (l4_hdr != exthdr) 1161 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off); 1162 ptype = WX_PTYPE_TUN_IPV6; 1163 break; 1164 default: 1165 return ptype; 1166 } 1167 1168 if (tun_prot == IPPROTO_IPIP || tun_prot == IPPROTO_IPV6) { 1169 hdr.raw = (void *)inner_ip_hdr(skb); 1170 ptype |= WX_PTYPE_PKT_IPIP; 1171 } else if (tun_prot == IPPROTO_UDP) { 1172 hdr.raw = (void *)inner_ip_hdr(skb); 1173 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER || 1174 skb->inner_protocol != htons(ETH_P_TEB)) { 1175 ptype |= WX_PTYPE_PKT_IG; 1176 } else { 1177 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1178 == htons(ETH_P_8021Q)) 1179 ptype |= WX_PTYPE_PKT_IGMV; 1180 else 1181 ptype |= WX_PTYPE_PKT_IGM; 1182 } 1183 1184 } else if (tun_prot == IPPROTO_GRE) { 1185 hdr.raw = (void *)inner_ip_hdr(skb); 1186 if (skb->inner_protocol == htons(ETH_P_IP) || 1187 skb->inner_protocol == htons(ETH_P_IPV6)) { 1188 ptype |= WX_PTYPE_PKT_IG; 1189 } else { 1190 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto 1191 == htons(ETH_P_8021Q)) 1192 ptype |= WX_PTYPE_PKT_IGMV; 1193 else 1194 ptype |= WX_PTYPE_PKT_IGM; 1195 } 1196 } else { 1197 return ptype; 1198 } 1199 1200 switch (hdr.ipv4->version) { 1201 case IPVERSION: 1202 l4_prot = hdr.ipv4->protocol; 1203 break; 1204 case 6: 1205 l4_hdr = skb_inner_transport_header(skb); 1206 exthdr = skb_inner_network_header(skb) + sizeof(struct ipv6hdr); 1207 l4_prot = inner_ipv6_hdr(skb)->nexthdr; 1208 if (l4_hdr != exthdr) 1209 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1210 ptype |= WX_PTYPE_PKT_IPV6; 1211 break; 1212 default: 1213 return ptype; 1214 } 1215 } else { 1216 switch (first->protocol) { 1217 case htons(ETH_P_IP): 1218 l4_prot = ip_hdr(skb)->protocol; 1219 ptype = WX_PTYPE_PKT_IP; 1220 break; 1221 case htons(ETH_P_IPV6): 1222 l4_hdr = skb_transport_header(skb); 1223 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1224 l4_prot = ipv6_hdr(skb)->nexthdr; 1225 if (l4_hdr != exthdr) 1226 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1227 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6; 1228 break; 1229 default: 1230 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC; 1231 } 1232 } 1233 switch (l4_prot) { 1234 case IPPROTO_TCP: 1235 ptype |= WX_PTYPE_TYP_TCP; 1236 break; 1237 case IPPROTO_UDP: 1238 ptype |= WX_PTYPE_TYP_UDP; 1239 break; 1240 case IPPROTO_SCTP: 1241 ptype |= WX_PTYPE_TYP_SCTP; 1242 break; 1243 default: 1244 ptype |= WX_PTYPE_TYP_IP; 1245 break; 1246 } 1247 1248 return ptype; 1249 } 1250 1251 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1252 u8 *hdr_len, u8 ptype) 1253 { 1254 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; 1255 struct net_device *netdev = tx_ring->netdev; 1256 u32 l4len, tunhdr_eiplen_tunlen = 0; 1257 struct sk_buff *skb = first->skb; 1258 bool enc = skb->encapsulation; 1259 struct ipv6hdr *ipv6h; 1260 struct tcphdr *tcph; 1261 struct iphdr *iph; 1262 u8 tun_prot = 0; 1263 int err; 1264 1265 if (skb->ip_summed != CHECKSUM_PARTIAL) 1266 return 0; 1267 1268 if (!skb_is_gso(skb)) 1269 return 0; 1270 1271 err = skb_cow_head(skb, 0); 1272 if (err < 0) 1273 return err; 1274 1275 /* indicates the inner headers in the skbuff are valid. */ 1276 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb); 1277 if (iph->version == 4) { 1278 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1279 iph->tot_len = 0; 1280 iph->check = 0; 1281 tcph->check = ~csum_tcpudp_magic(iph->saddr, 1282 iph->daddr, 0, 1283 IPPROTO_TCP, 0); 1284 first->tx_flags |= WX_TX_FLAGS_TSO | 1285 WX_TX_FLAGS_CSUM | 1286 WX_TX_FLAGS_IPV4 | 1287 WX_TX_FLAGS_CC; 1288 } else if (iph->version == 6 && skb_is_gso_v6(skb)) { 1289 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb); 1290 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb); 1291 ipv6h->payload_len = 0; 1292 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, 1293 &ipv6h->daddr, 0, 1294 IPPROTO_TCP, 0); 1295 first->tx_flags |= WX_TX_FLAGS_TSO | 1296 WX_TX_FLAGS_CSUM | 1297 WX_TX_FLAGS_CC; 1298 } 1299 1300 /* compute header lengths */ 1301 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb); 1302 *hdr_len = enc ? skb_inner_transport_offset(skb) : 1303 skb_transport_offset(skb); 1304 *hdr_len += l4len; 1305 1306 /* update gso size and bytecount with header size */ 1307 first->gso_segs = skb_shinfo(skb)->gso_segs; 1308 first->bytecount += (first->gso_segs - 1) * *hdr_len; 1309 1310 /* mss_l4len_id: use 0 as index for TSO */ 1311 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT; 1312 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT; 1313 1314 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ 1315 if (enc) { 1316 unsigned char *exthdr, *l4_hdr; 1317 __be16 frag_off; 1318 1319 switch (first->protocol) { 1320 case htons(ETH_P_IP): 1321 tun_prot = ip_hdr(skb)->protocol; 1322 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4; 1323 break; 1324 case htons(ETH_P_IPV6): 1325 l4_hdr = skb_transport_header(skb); 1326 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1327 tun_prot = ipv6_hdr(skb)->nexthdr; 1328 if (l4_hdr != exthdr) 1329 ipv6_skip_exthdr(skb, exthdr - skb->data, &tun_prot, &frag_off); 1330 break; 1331 default: 1332 break; 1333 } 1334 switch (tun_prot) { 1335 case IPPROTO_UDP: 1336 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1337 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1338 WX_TXD_OUTER_IPLEN_SHIFT) | 1339 (((skb_inner_mac_header(skb) - 1340 skb_transport_header(skb)) >> 1) << 1341 WX_TXD_TUNNEL_LEN_SHIFT); 1342 break; 1343 case IPPROTO_GRE: 1344 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1345 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1346 WX_TXD_OUTER_IPLEN_SHIFT) | 1347 (((skb_inner_mac_header(skb) - 1348 skb_transport_header(skb)) >> 1) << 1349 WX_TXD_TUNNEL_LEN_SHIFT); 1350 break; 1351 case IPPROTO_IPIP: 1352 case IPPROTO_IPV6: 1353 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1354 (char *)ip_hdr(skb)) >> 2) << 1355 WX_TXD_OUTER_IPLEN_SHIFT; 1356 break; 1357 default: 1358 break; 1359 } 1360 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1; 1361 } else { 1362 vlan_macip_lens = skb_network_header_len(skb) >> 1; 1363 } 1364 1365 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT; 1366 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1367 1368 type_tucmd = ptype << 24; 1369 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1370 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1371 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1372 WX_TX_FLAGS_HW_VLAN, 1373 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1374 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1375 type_tucmd, mss_l4len_idx); 1376 1377 return 1; 1378 } 1379 1380 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first, 1381 u8 ptype) 1382 { 1383 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0; 1384 struct net_device *netdev = tx_ring->netdev; 1385 u32 mss_l4len_idx = 0, type_tucmd; 1386 struct sk_buff *skb = first->skb; 1387 u8 tun_prot = 0; 1388 1389 if (skb->ip_summed != CHECKSUM_PARTIAL) { 1390 csum_failed: 1391 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) && 1392 !(first->tx_flags & WX_TX_FLAGS_CC)) 1393 return; 1394 vlan_macip_lens = skb_network_offset(skb) << 1395 WX_TXD_MACLEN_SHIFT; 1396 } else { 1397 unsigned char *exthdr, *l4_hdr; 1398 __be16 frag_off; 1399 u8 l4_prot = 0; 1400 union { 1401 struct iphdr *ipv4; 1402 struct ipv6hdr *ipv6; 1403 u8 *raw; 1404 } network_hdr; 1405 union { 1406 struct tcphdr *tcphdr; 1407 u8 *raw; 1408 } transport_hdr; 1409 1410 if (skb->encapsulation) { 1411 network_hdr.raw = skb_inner_network_header(skb); 1412 transport_hdr.raw = skb_inner_transport_header(skb); 1413 vlan_macip_lens = skb_network_offset(skb) << 1414 WX_TXD_MACLEN_SHIFT; 1415 switch (first->protocol) { 1416 case htons(ETH_P_IP): 1417 tun_prot = ip_hdr(skb)->protocol; 1418 break; 1419 case htons(ETH_P_IPV6): 1420 l4_hdr = skb_transport_header(skb); 1421 exthdr = skb_network_header(skb) + sizeof(struct ipv6hdr); 1422 tun_prot = ipv6_hdr(skb)->nexthdr; 1423 if (l4_hdr != exthdr) 1424 ipv6_skip_exthdr(skb, exthdr - skb->data, 1425 &tun_prot, &frag_off); 1426 break; 1427 default: 1428 return; 1429 } 1430 switch (tun_prot) { 1431 case IPPROTO_UDP: 1432 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP; 1433 tunhdr_eiplen_tunlen |= 1434 ((skb_network_header_len(skb) >> 2) << 1435 WX_TXD_OUTER_IPLEN_SHIFT) | 1436 (((skb_inner_mac_header(skb) - 1437 skb_transport_header(skb)) >> 1) << 1438 WX_TXD_TUNNEL_LEN_SHIFT); 1439 break; 1440 case IPPROTO_GRE: 1441 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE; 1442 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) << 1443 WX_TXD_OUTER_IPLEN_SHIFT) | 1444 (((skb_inner_mac_header(skb) - 1445 skb_transport_header(skb)) >> 1) << 1446 WX_TXD_TUNNEL_LEN_SHIFT); 1447 break; 1448 case IPPROTO_IPIP: 1449 case IPPROTO_IPV6: 1450 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) - 1451 (char *)ip_hdr(skb)) >> 2) << 1452 WX_TXD_OUTER_IPLEN_SHIFT; 1453 break; 1454 default: 1455 break; 1456 } 1457 1458 } else { 1459 network_hdr.raw = skb_network_header(skb); 1460 transport_hdr.raw = skb_transport_header(skb); 1461 vlan_macip_lens = skb_network_offset(skb) << 1462 WX_TXD_MACLEN_SHIFT; 1463 } 1464 1465 switch (network_hdr.ipv4->version) { 1466 case IPVERSION: 1467 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1468 l4_prot = network_hdr.ipv4->protocol; 1469 break; 1470 case 6: 1471 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1; 1472 exthdr = network_hdr.raw + sizeof(struct ipv6hdr); 1473 l4_prot = network_hdr.ipv6->nexthdr; 1474 if (transport_hdr.raw != exthdr) 1475 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_prot, &frag_off); 1476 break; 1477 default: 1478 break; 1479 } 1480 1481 switch (l4_prot) { 1482 case IPPROTO_TCP: 1483 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << 1484 WX_TXD_L4LEN_SHIFT; 1485 break; 1486 case IPPROTO_SCTP: 1487 mss_l4len_idx = sizeof(struct sctphdr) << 1488 WX_TXD_L4LEN_SHIFT; 1489 break; 1490 case IPPROTO_UDP: 1491 mss_l4len_idx = sizeof(struct udphdr) << 1492 WX_TXD_L4LEN_SHIFT; 1493 break; 1494 default: 1495 skb_checksum_help(skb); 1496 goto csum_failed; 1497 } 1498 1499 /* update TX checksum flag */ 1500 first->tx_flags |= WX_TX_FLAGS_CSUM; 1501 } 1502 first->tx_flags |= WX_TX_FLAGS_CC; 1503 /* vlan_macip_lens: MACLEN, VLAN tag */ 1504 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK; 1505 1506 type_tucmd = ptype << 24; 1507 if (skb->vlan_proto == htons(ETH_P_8021AD) && 1508 netdev->features & NETIF_F_HW_VLAN_STAG_TX) 1509 type_tucmd |= WX_SET_FLAG(first->tx_flags, 1510 WX_TX_FLAGS_HW_VLAN, 1511 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT); 1512 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen, 1513 type_tucmd, mss_l4len_idx); 1514 } 1515 1516 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb, 1517 struct wx_ring *tx_ring) 1518 { 1519 struct wx *wx = netdev_priv(tx_ring->netdev); 1520 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 1521 struct wx_tx_buffer *first; 1522 u8 hdr_len = 0, ptype; 1523 unsigned short f; 1524 u32 tx_flags = 0; 1525 int tso; 1526 1527 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD, 1528 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD, 1529 * + 2 desc gap to keep tail from touching head, 1530 * + 1 desc for context descriptor, 1531 * otherwise try next time 1532 */ 1533 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 1534 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)-> 1535 frags[f])); 1536 1537 if (wx_maybe_stop_tx(tx_ring, count + 3)) { 1538 tx_ring->tx_stats.tx_busy++; 1539 return NETDEV_TX_BUSY; 1540 } 1541 1542 /* record the location of the first descriptor for this packet */ 1543 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 1544 first->skb = skb; 1545 first->bytecount = skb->len; 1546 first->gso_segs = 1; 1547 1548 /* if we have a HW VLAN tag being added default to the HW one */ 1549 if (skb_vlan_tag_present(skb)) { 1550 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT; 1551 tx_flags |= WX_TX_FLAGS_HW_VLAN; 1552 } 1553 1554 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1555 wx->ptp_clock) { 1556 if (wx->tstamp_config.tx_type == HWTSTAMP_TX_ON && 1557 !test_and_set_bit_lock(WX_STATE_PTP_TX_IN_PROGRESS, 1558 wx->state)) { 1559 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1560 tx_flags |= WX_TX_FLAGS_TSTAMP; 1561 wx->ptp_tx_skb = skb_get(skb); 1562 wx->ptp_tx_start = jiffies; 1563 } else { 1564 wx->tx_hwtstamp_skipped++; 1565 } 1566 } 1567 1568 /* record initial flags and protocol */ 1569 first->tx_flags = tx_flags; 1570 first->protocol = vlan_get_protocol(skb); 1571 1572 ptype = wx_encode_tx_desc_ptype(first); 1573 1574 tso = wx_tso(tx_ring, first, &hdr_len, ptype); 1575 if (tso < 0) 1576 goto out_drop; 1577 else if (!tso) 1578 wx_tx_csum(tx_ring, first, ptype); 1579 1580 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && tx_ring->atr_sample_rate) 1581 wx->atr(tx_ring, first, ptype); 1582 1583 if (wx_tx_map(tx_ring, first, hdr_len)) 1584 goto cleanup_tx_tstamp; 1585 1586 return NETDEV_TX_OK; 1587 out_drop: 1588 dev_kfree_skb_any(first->skb); 1589 first->skb = NULL; 1590 cleanup_tx_tstamp: 1591 if (unlikely(tx_flags & WX_TX_FLAGS_TSTAMP)) { 1592 dev_kfree_skb_any(wx->ptp_tx_skb); 1593 wx->ptp_tx_skb = NULL; 1594 wx->tx_hwtstamp_errors++; 1595 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 1596 } 1597 1598 return NETDEV_TX_OK; 1599 } 1600 1601 netdev_tx_t wx_xmit_frame(struct sk_buff *skb, 1602 struct net_device *netdev) 1603 { 1604 unsigned int r_idx = skb->queue_mapping; 1605 struct wx *wx = netdev_priv(netdev); 1606 struct wx_ring *tx_ring; 1607 1608 if (!netif_carrier_ok(netdev)) { 1609 dev_kfree_skb_any(skb); 1610 return NETDEV_TX_OK; 1611 } 1612 1613 /* The minimum packet size for olinfo paylen is 17 so pad the skb 1614 * in order to meet this minimum size requirement. 1615 */ 1616 if (skb_put_padto(skb, 17)) 1617 return NETDEV_TX_OK; 1618 1619 if (r_idx >= wx->num_tx_queues) 1620 r_idx = r_idx % wx->num_tx_queues; 1621 tx_ring = wx->tx_ring[r_idx]; 1622 1623 return wx_xmit_frame_ring(skb, tx_ring); 1624 } 1625 EXPORT_SYMBOL(wx_xmit_frame); 1626 1627 static void wx_set_itr(struct wx_q_vector *q_vector) 1628 { 1629 struct wx *wx = q_vector->wx; 1630 u32 new_itr; 1631 1632 if (!wx->adaptive_itr) 1633 return; 1634 1635 /* use the smallest value of new ITR delay calculations */ 1636 new_itr = min(q_vector->rx.itr, q_vector->tx.itr); 1637 new_itr <<= 2; 1638 1639 if (new_itr != q_vector->itr) { 1640 /* save the algorithm value here */ 1641 q_vector->itr = new_itr; 1642 1643 if (wx->pdev->is_virtfn) 1644 wx_write_eitr_vf(q_vector); 1645 else 1646 wx_write_eitr(q_vector); 1647 } 1648 } 1649 1650 static void wx_rx_dim_work(struct work_struct *work) 1651 { 1652 struct dim *dim = container_of(work, struct dim, work); 1653 struct dim_cq_moder rx_moder; 1654 struct wx_ring_container *rx; 1655 struct wx_q_vector *q_vector; 1656 1657 rx = container_of(dim, struct wx_ring_container, dim); 1658 1659 rx_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1660 rx->itr = rx_moder.usec; 1661 1662 q_vector = container_of(rx, struct wx_q_vector, rx); 1663 wx_set_itr(q_vector); 1664 1665 dim->state = DIM_START_MEASURE; 1666 } 1667 1668 static void wx_tx_dim_work(struct work_struct *work) 1669 { 1670 struct dim *dim = container_of(work, struct dim, work); 1671 struct dim_cq_moder tx_moder; 1672 struct wx_ring_container *tx; 1673 struct wx_q_vector *q_vector; 1674 1675 tx = container_of(dim, struct wx_ring_container, dim); 1676 1677 tx_moder = net_dim_get_tx_moderation(dim->mode, dim->profile_ix); 1678 tx->itr = tx_moder.usec; 1679 1680 q_vector = container_of(tx, struct wx_q_vector, tx); 1681 wx_set_itr(q_vector); 1682 1683 dim->state = DIM_START_MEASURE; 1684 } 1685 1686 void wx_napi_enable_all(struct wx *wx) 1687 { 1688 struct wx_q_vector *q_vector; 1689 int q_idx; 1690 1691 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1692 q_vector = wx->q_vector[q_idx]; 1693 1694 INIT_WORK(&q_vector->rx.dim.work, wx_rx_dim_work); 1695 INIT_WORK(&q_vector->tx.dim.work, wx_tx_dim_work); 1696 q_vector->rx.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1697 q_vector->tx.dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1698 napi_enable(&q_vector->napi); 1699 } 1700 } 1701 EXPORT_SYMBOL(wx_napi_enable_all); 1702 1703 void wx_napi_disable_all(struct wx *wx) 1704 { 1705 struct wx_q_vector *q_vector; 1706 int q_idx; 1707 1708 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) { 1709 q_vector = wx->q_vector[q_idx]; 1710 napi_disable(&q_vector->napi); 1711 disable_work_sync(&q_vector->rx.dim.work); 1712 disable_work_sync(&q_vector->tx.dim.work); 1713 } 1714 } 1715 EXPORT_SYMBOL(wx_napi_disable_all); 1716 1717 static bool wx_set_vmdq_queues(struct wx *wx) 1718 { 1719 u16 vmdq_i = wx->ring_feature[RING_F_VMDQ].limit; 1720 u16 rss_i = wx->ring_feature[RING_F_RSS].limit; 1721 u16 rss_m = WX_RSS_DISABLED_MASK; 1722 u16 vmdq_m = 0; 1723 1724 /* only proceed if VMDq is enabled */ 1725 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 1726 return false; 1727 /* Add starting offset to total pool count */ 1728 vmdq_i += wx->ring_feature[RING_F_VMDQ].offset; 1729 1730 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1731 /* double check we are limited to maximum pools */ 1732 vmdq_i = min_t(u16, 64, vmdq_i); 1733 1734 /* 64 pool mode with 2 queues per pool, or 1735 * 16/32/64 pool mode with 1 queue per pool 1736 */ 1737 if (vmdq_i > 32 || rss_i < 4) { 1738 vmdq_m = WX_VMDQ_2Q_MASK; 1739 rss_m = WX_RSS_2Q_MASK; 1740 rss_i = min_t(u16, rss_i, 2); 1741 /* 32 pool mode with 4 queues per pool */ 1742 } else { 1743 vmdq_m = WX_VMDQ_4Q_MASK; 1744 rss_m = WX_RSS_4Q_MASK; 1745 rss_i = 4; 1746 } 1747 } else { 1748 /* double check we are limited to maximum pools */ 1749 vmdq_i = min_t(u16, 8, vmdq_i); 1750 1751 /* when VMDQ on, disable RSS */ 1752 rss_i = 1; 1753 } 1754 1755 /* remove the starting offset from the pool count */ 1756 vmdq_i -= wx->ring_feature[RING_F_VMDQ].offset; 1757 1758 /* save features for later use */ 1759 wx->ring_feature[RING_F_VMDQ].indices = vmdq_i; 1760 wx->ring_feature[RING_F_VMDQ].mask = vmdq_m; 1761 1762 /* limit RSS based on user input and save for later use */ 1763 wx->ring_feature[RING_F_RSS].indices = rss_i; 1764 wx->ring_feature[RING_F_RSS].mask = rss_m; 1765 1766 wx->queues_per_pool = rss_i;/*maybe same to num_rx_queues_per_pool*/ 1767 wx->num_rx_pools = vmdq_i; 1768 wx->num_rx_queues_per_pool = rss_i; 1769 1770 wx->num_rx_queues = vmdq_i * rss_i; 1771 wx->num_tx_queues = vmdq_i * rss_i; 1772 1773 return true; 1774 } 1775 1776 /** 1777 * wx_set_rss_queues: Allocate queues for RSS 1778 * @wx: board private structure to initialize 1779 * 1780 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try 1781 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. 1782 * 1783 **/ 1784 static void wx_set_rss_queues(struct wx *wx) 1785 { 1786 struct wx_ring_feature *f; 1787 1788 /* set mask for 16 queue limit of RSS */ 1789 f = &wx->ring_feature[RING_F_RSS]; 1790 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) 1791 f->mask = WX_RSS_64Q_MASK; 1792 else 1793 f->mask = WX_RSS_8Q_MASK; 1794 f->indices = f->limit; 1795 1796 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 1797 goto out; 1798 1799 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 1800 1801 wx->ring_feature[RING_F_FDIR].indices = 1; 1802 /* Use Flow Director in addition to RSS to ensure the best 1803 * distribution of flows across cores, even when an FDIR flow 1804 * isn't matched. 1805 */ 1806 if (f->indices > 1) { 1807 f = &wx->ring_feature[RING_F_FDIR]; 1808 1809 f->indices = f->limit; 1810 1811 if (!(test_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 1812 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 1813 } 1814 1815 out: 1816 wx->num_rx_queues = f->indices; 1817 wx->num_tx_queues = f->indices; 1818 } 1819 1820 static void wx_set_num_queues(struct wx *wx) 1821 { 1822 /* Start with base case */ 1823 wx->num_rx_queues = 1; 1824 wx->num_tx_queues = 1; 1825 wx->queues_per_pool = 1; 1826 1827 if (wx_set_vmdq_queues(wx)) 1828 return; 1829 1830 wx_set_rss_queues(wx); 1831 } 1832 1833 /** 1834 * wx_acquire_msix_vectors - acquire MSI-X vectors 1835 * @wx: board private structure 1836 * 1837 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will 1838 * return a negative error code if unable to acquire MSI-X vectors for any 1839 * reason. 1840 */ 1841 static int wx_acquire_msix_vectors(struct wx *wx) 1842 { 1843 struct irq_affinity affd = { .post_vectors = 1 }; 1844 int nvecs, i; 1845 1846 /* We start by asking for one vector per queue pair */ 1847 nvecs = max(wx->num_rx_queues, wx->num_tx_queues); 1848 nvecs = min_t(int, nvecs, num_online_cpus()); 1849 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors); 1850 1851 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry), 1852 GFP_KERNEL); 1853 if (!wx->msix_q_entries) 1854 return -ENOMEM; 1855 1856 /* One for non-queue interrupts */ 1857 nvecs += 1; 1858 1859 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry), 1860 GFP_KERNEL); 1861 if (!wx->msix_entry) { 1862 kfree(wx->msix_q_entries); 1863 wx->msix_q_entries = NULL; 1864 return -ENOMEM; 1865 } 1866 1867 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs, 1868 nvecs, 1869 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, 1870 &affd); 1871 if (nvecs < 0) { 1872 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs); 1873 kfree(wx->msix_q_entries); 1874 wx->msix_q_entries = NULL; 1875 kfree(wx->msix_entry); 1876 wx->msix_entry = NULL; 1877 return nvecs; 1878 } 1879 1880 nvecs -= 1; 1881 for (i = 0; i < nvecs; i++) { 1882 wx->msix_q_entries[i].entry = i; 1883 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i); 1884 } 1885 1886 wx->num_q_vectors = nvecs; 1887 1888 wx->msix_entry->entry = nvecs; 1889 wx->msix_entry->vector = pci_irq_vector(wx->pdev, nvecs); 1890 1891 if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) { 1892 wx->msix_entry->entry = 0; 1893 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0); 1894 wx->msix_q_entries[0].entry = 0; 1895 wx->msix_q_entries[0].vector = pci_irq_vector(wx->pdev, 1); 1896 } 1897 1898 return 0; 1899 } 1900 1901 /** 1902 * wx_set_interrupt_capability - set MSI-X or MSI if supported 1903 * @wx: board private structure to initialize 1904 * 1905 * Attempt to configure the interrupts using the best available 1906 * capabilities of the hardware and the kernel. 1907 **/ 1908 static int wx_set_interrupt_capability(struct wx *wx) 1909 { 1910 struct pci_dev *pdev = wx->pdev; 1911 int nvecs, ret; 1912 1913 /* We will try to get MSI-X interrupts first */ 1914 ret = wx_acquire_msix_vectors(wx); 1915 if (ret == 0 || (ret == -ENOMEM) || pdev->is_virtfn) 1916 return ret; 1917 1918 /* Disable VMDq support */ 1919 dev_warn(&wx->pdev->dev, "Disabling VMQQ support\n"); 1920 clear_bit(WX_FLAG_VMDQ_ENABLED, wx->flags); 1921 1922 /* Disable RSS */ 1923 dev_warn(&wx->pdev->dev, "Disabling RSS support\n"); 1924 wx->ring_feature[RING_F_RSS].limit = 1; 1925 1926 wx_set_num_queues(wx); 1927 1928 /* minmum one for queue, one for misc*/ 1929 nvecs = 1; 1930 nvecs = pci_alloc_irq_vectors(pdev, nvecs, 1931 nvecs, PCI_IRQ_MSI | PCI_IRQ_INTX); 1932 if (nvecs == 1) { 1933 if (pdev->msi_enabled) 1934 wx_err(wx, "Fallback to MSI.\n"); 1935 else 1936 wx_err(wx, "Fallback to INTx.\n"); 1937 } else { 1938 wx_err(wx, "Failed to allocate MSI/INTx interrupts. Error: %d\n", nvecs); 1939 return nvecs; 1940 } 1941 1942 pdev->irq = pci_irq_vector(pdev, 0); 1943 wx->num_q_vectors = 1; 1944 1945 return 0; 1946 } 1947 1948 static bool wx_cache_ring_vmdq(struct wx *wx) 1949 { 1950 struct wx_ring_feature *vmdq = &wx->ring_feature[RING_F_VMDQ]; 1951 struct wx_ring_feature *rss = &wx->ring_feature[RING_F_RSS]; 1952 u16 reg_idx; 1953 int i; 1954 1955 /* only proceed if VMDq is enabled */ 1956 if (!test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 1957 return false; 1958 1959 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1960 /* start at VMDq register offset for SR-IOV enabled setups */ 1961 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 1962 for (i = 0; i < wx->num_rx_queues; i++, reg_idx++) { 1963 /* If we are greater than indices move to next pool */ 1964 if ((reg_idx & ~vmdq->mask) >= rss->indices) 1965 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 1966 wx->rx_ring[i]->reg_idx = reg_idx; 1967 } 1968 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); 1969 for (i = 0; i < wx->num_tx_queues; i++, reg_idx++) { 1970 /* If we are greater than indices move to next pool */ 1971 if ((reg_idx & rss->mask) >= rss->indices) 1972 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); 1973 wx->tx_ring[i]->reg_idx = reg_idx; 1974 } 1975 } else { 1976 /* start at VMDq register offset for SR-IOV enabled setups */ 1977 reg_idx = vmdq->offset; 1978 for (i = 0; i < wx->num_rx_queues; i++) 1979 /* If we are greater than indices move to next pool */ 1980 wx->rx_ring[i]->reg_idx = reg_idx + i; 1981 1982 reg_idx = vmdq->offset; 1983 for (i = 0; i < wx->num_tx_queues; i++) 1984 /* If we are greater than indices move to next pool */ 1985 wx->tx_ring[i]->reg_idx = reg_idx + i; 1986 } 1987 1988 return true; 1989 } 1990 1991 /** 1992 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS 1993 * @wx: board private structure to initialize 1994 * 1995 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV. 1996 * 1997 **/ 1998 static void wx_cache_ring_rss(struct wx *wx) 1999 { 2000 u16 i; 2001 2002 if (wx_cache_ring_vmdq(wx)) 2003 return; 2004 2005 for (i = 0; i < wx->num_rx_queues; i++) 2006 wx->rx_ring[i]->reg_idx = i; 2007 2008 for (i = 0; i < wx->num_tx_queues; i++) 2009 wx->tx_ring[i]->reg_idx = i; 2010 } 2011 2012 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head) 2013 { 2014 ring->next = head->ring; 2015 head->ring = ring; 2016 head->count++; 2017 } 2018 2019 /** 2020 * wx_alloc_q_vector - Allocate memory for a single interrupt vector 2021 * @wx: board private structure to initialize 2022 * @v_count: q_vectors allocated on wx, used for ring interleaving 2023 * @v_idx: index of vector in wx struct 2024 * @txr_count: total number of Tx rings to allocate 2025 * @txr_idx: index of first Tx ring to allocate 2026 * @rxr_count: total number of Rx rings to allocate 2027 * @rxr_idx: index of first Rx ring to allocate 2028 * 2029 * We allocate one q_vector. If allocation fails we return -ENOMEM. 2030 **/ 2031 static int wx_alloc_q_vector(struct wx *wx, 2032 unsigned int v_count, unsigned int v_idx, 2033 unsigned int txr_count, unsigned int txr_idx, 2034 unsigned int rxr_count, unsigned int rxr_idx) 2035 { 2036 struct wx_q_vector *q_vector; 2037 int ring_count, default_itr; 2038 struct wx_ring *ring; 2039 2040 /* note this will allocate space for the ring structure as well! */ 2041 ring_count = txr_count + rxr_count; 2042 2043 q_vector = kzalloc(struct_size(q_vector, ring, ring_count), 2044 GFP_KERNEL); 2045 if (!q_vector) 2046 return -ENOMEM; 2047 2048 /* initialize NAPI */ 2049 netif_napi_add(wx->netdev, &q_vector->napi, 2050 wx_poll); 2051 2052 /* tie q_vector and wx together */ 2053 wx->q_vector[v_idx] = q_vector; 2054 q_vector->wx = wx; 2055 q_vector->v_idx = v_idx; 2056 if (cpu_online(v_idx)) 2057 q_vector->numa_node = cpu_to_node(v_idx); 2058 2059 /* initialize pointer to rings */ 2060 ring = q_vector->ring; 2061 2062 switch (wx->mac.type) { 2063 case wx_mac_sp: 2064 case wx_mac_aml: 2065 case wx_mac_aml40: 2066 default_itr = WX_12K_ITR; 2067 break; 2068 default: 2069 default_itr = WX_7K_ITR; 2070 break; 2071 } 2072 2073 /* initialize ITR */ 2074 if (txr_count && !rxr_count) 2075 /* tx only vector */ 2076 q_vector->itr = wx->tx_itr_setting ? 2077 default_itr : wx->tx_itr_setting; 2078 else 2079 /* rx or rx/tx vector */ 2080 q_vector->itr = wx->rx_itr_setting ? 2081 default_itr : wx->rx_itr_setting; 2082 2083 while (txr_count) { 2084 /* assign generic ring traits */ 2085 ring->dev = &wx->pdev->dev; 2086 ring->netdev = wx->netdev; 2087 2088 /* configure backlink on ring */ 2089 ring->q_vector = q_vector; 2090 2091 /* update q_vector Tx values */ 2092 wx_add_ring(ring, &q_vector->tx); 2093 2094 /* apply Tx specific ring traits */ 2095 ring->count = wx->tx_ring_count; 2096 2097 ring->queue_index = txr_idx; 2098 2099 /* assign ring to wx */ 2100 wx->tx_ring[txr_idx] = ring; 2101 2102 /* update count and index */ 2103 txr_count--; 2104 txr_idx += v_count; 2105 2106 /* push pointer to next ring */ 2107 ring++; 2108 } 2109 2110 while (rxr_count) { 2111 /* assign generic ring traits */ 2112 ring->dev = &wx->pdev->dev; 2113 ring->netdev = wx->netdev; 2114 2115 /* configure backlink on ring */ 2116 ring->q_vector = q_vector; 2117 2118 /* update q_vector Rx values */ 2119 wx_add_ring(ring, &q_vector->rx); 2120 2121 /* apply Rx specific ring traits */ 2122 ring->count = wx->rx_ring_count; 2123 ring->queue_index = rxr_idx; 2124 2125 /* assign ring to wx */ 2126 wx->rx_ring[rxr_idx] = ring; 2127 2128 /* update count and index */ 2129 rxr_count--; 2130 rxr_idx += v_count; 2131 2132 /* push pointer to next ring */ 2133 ring++; 2134 } 2135 2136 return 0; 2137 } 2138 2139 /** 2140 * wx_free_q_vector - Free memory allocated for specific interrupt vector 2141 * @wx: board private structure to initialize 2142 * @v_idx: Index of vector to be freed 2143 * 2144 * This function frees the memory allocated to the q_vector. In addition if 2145 * NAPI is enabled it will delete any references to the NAPI struct prior 2146 * to freeing the q_vector. 2147 **/ 2148 static void wx_free_q_vector(struct wx *wx, int v_idx) 2149 { 2150 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2151 struct wx_ring *ring; 2152 2153 wx_for_each_ring(ring, q_vector->tx) 2154 wx->tx_ring[ring->queue_index] = NULL; 2155 2156 wx_for_each_ring(ring, q_vector->rx) 2157 wx->rx_ring[ring->queue_index] = NULL; 2158 2159 wx->q_vector[v_idx] = NULL; 2160 netif_napi_del(&q_vector->napi); 2161 kfree_rcu(q_vector, rcu); 2162 } 2163 2164 /** 2165 * wx_alloc_q_vectors - Allocate memory for interrupt vectors 2166 * @wx: board private structure to initialize 2167 * 2168 * We allocate one q_vector per queue interrupt. If allocation fails we 2169 * return -ENOMEM. 2170 **/ 2171 static int wx_alloc_q_vectors(struct wx *wx) 2172 { 2173 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0; 2174 unsigned int rxr_remaining = wx->num_rx_queues; 2175 unsigned int txr_remaining = wx->num_tx_queues; 2176 unsigned int q_vectors = wx->num_q_vectors; 2177 int rqpv, tqpv; 2178 int err; 2179 2180 for (; v_idx < q_vectors; v_idx++) { 2181 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 2182 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 2183 err = wx_alloc_q_vector(wx, q_vectors, v_idx, 2184 tqpv, txr_idx, 2185 rqpv, rxr_idx); 2186 2187 if (err) 2188 goto err_out; 2189 2190 /* update counts and index */ 2191 rxr_remaining -= rqpv; 2192 txr_remaining -= tqpv; 2193 rxr_idx++; 2194 txr_idx++; 2195 } 2196 2197 return 0; 2198 2199 err_out: 2200 wx->num_tx_queues = 0; 2201 wx->num_rx_queues = 0; 2202 wx->num_q_vectors = 0; 2203 2204 while (v_idx--) 2205 wx_free_q_vector(wx, v_idx); 2206 2207 return -ENOMEM; 2208 } 2209 2210 /** 2211 * wx_free_q_vectors - Free memory allocated for interrupt vectors 2212 * @wx: board private structure to initialize 2213 * 2214 * This function frees the memory allocated to the q_vectors. In addition if 2215 * NAPI is enabled it will delete any references to the NAPI struct prior 2216 * to freeing the q_vector. 2217 **/ 2218 static void wx_free_q_vectors(struct wx *wx) 2219 { 2220 int v_idx = wx->num_q_vectors; 2221 2222 wx->num_tx_queues = 0; 2223 wx->num_rx_queues = 0; 2224 wx->num_q_vectors = 0; 2225 2226 while (v_idx--) 2227 wx_free_q_vector(wx, v_idx); 2228 } 2229 2230 void wx_reset_interrupt_capability(struct wx *wx) 2231 { 2232 struct pci_dev *pdev = wx->pdev; 2233 2234 if (!pdev->msi_enabled && !pdev->msix_enabled) 2235 return; 2236 2237 if (pdev->msix_enabled) { 2238 kfree(wx->msix_q_entries); 2239 wx->msix_q_entries = NULL; 2240 kfree(wx->msix_entry); 2241 wx->msix_entry = NULL; 2242 } 2243 pci_free_irq_vectors(wx->pdev); 2244 } 2245 EXPORT_SYMBOL(wx_reset_interrupt_capability); 2246 2247 /** 2248 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings 2249 * @wx: board private structure to clear interrupt scheme on 2250 * 2251 * We go through and clear interrupt specific resources and reset the structure 2252 * to pre-load conditions 2253 **/ 2254 void wx_clear_interrupt_scheme(struct wx *wx) 2255 { 2256 wx_free_q_vectors(wx); 2257 wx_reset_interrupt_capability(wx); 2258 } 2259 EXPORT_SYMBOL(wx_clear_interrupt_scheme); 2260 2261 int wx_init_interrupt_scheme(struct wx *wx) 2262 { 2263 int ret; 2264 2265 /* Number of supported queues */ 2266 if (wx->pdev->is_virtfn) { 2267 if (wx->set_num_queues) 2268 wx->set_num_queues(wx); 2269 } else { 2270 wx_set_num_queues(wx); 2271 } 2272 2273 /* Set interrupt mode */ 2274 ret = wx_set_interrupt_capability(wx); 2275 if (ret) { 2276 wx_err(wx, "Allocate irq vectors for failed.\n"); 2277 return ret; 2278 } 2279 2280 /* Allocate memory for queues */ 2281 ret = wx_alloc_q_vectors(wx); 2282 if (ret) { 2283 wx_err(wx, "Unable to allocate memory for queue vectors.\n"); 2284 wx_reset_interrupt_capability(wx); 2285 return ret; 2286 } 2287 2288 wx_cache_ring_rss(wx); 2289 2290 return 0; 2291 } 2292 EXPORT_SYMBOL(wx_init_interrupt_scheme); 2293 2294 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data) 2295 { 2296 struct wx_q_vector *q_vector = data; 2297 2298 /* EIAM disabled interrupts (on this vector) for us */ 2299 if (q_vector->rx.ring || q_vector->tx.ring) { 2300 napi_schedule_irqoff(&q_vector->napi); 2301 q_vector->total_events++; 2302 } 2303 2304 return IRQ_HANDLED; 2305 } 2306 EXPORT_SYMBOL(wx_msix_clean_rings); 2307 2308 void wx_free_irq(struct wx *wx) 2309 { 2310 struct pci_dev *pdev = wx->pdev; 2311 int vector; 2312 2313 if (!(pdev->msix_enabled)) { 2314 if (!wx->misc_irq_domain) 2315 free_irq(pdev->irq, wx); 2316 return; 2317 } 2318 2319 for (vector = 0; vector < wx->num_q_vectors; vector++) { 2320 struct wx_q_vector *q_vector = wx->q_vector[vector]; 2321 struct msix_entry *entry = &wx->msix_q_entries[vector]; 2322 2323 /* free only the irqs that were actually requested */ 2324 if (!q_vector->rx.ring && !q_vector->tx.ring) 2325 continue; 2326 2327 free_irq(entry->vector, q_vector); 2328 } 2329 2330 if (!wx->misc_irq_domain) 2331 free_irq(wx->msix_entry->vector, wx); 2332 } 2333 EXPORT_SYMBOL(wx_free_irq); 2334 2335 /** 2336 * wx_setup_isb_resources - allocate interrupt status resources 2337 * @wx: board private structure 2338 * 2339 * Return 0 on success, negative on failure 2340 **/ 2341 int wx_setup_isb_resources(struct wx *wx) 2342 { 2343 struct pci_dev *pdev = wx->pdev; 2344 2345 if (wx->isb_mem) 2346 return 0; 2347 2348 wx->isb_mem = dma_alloc_coherent(&pdev->dev, 2349 sizeof(u32) * 4, 2350 &wx->isb_dma, 2351 GFP_KERNEL); 2352 if (!wx->isb_mem) { 2353 wx_err(wx, "Alloc isb_mem failed\n"); 2354 return -ENOMEM; 2355 } 2356 2357 return 0; 2358 } 2359 EXPORT_SYMBOL(wx_setup_isb_resources); 2360 2361 /** 2362 * wx_free_isb_resources - allocate all queues Rx resources 2363 * @wx: board private structure 2364 * 2365 * Return 0 on success, negative on failure 2366 **/ 2367 void wx_free_isb_resources(struct wx *wx) 2368 { 2369 struct pci_dev *pdev = wx->pdev; 2370 2371 dma_free_coherent(&pdev->dev, sizeof(u32) * 4, 2372 wx->isb_mem, wx->isb_dma); 2373 wx->isb_mem = NULL; 2374 } 2375 EXPORT_SYMBOL(wx_free_isb_resources); 2376 2377 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx) 2378 { 2379 u32 cur_tag = 0; 2380 2381 cur_tag = wx->isb_mem[WX_ISB_HEADER]; 2382 wx->isb_tag[idx] = cur_tag; 2383 2384 return (__force u32)cpu_to_le32(wx->isb_mem[idx]); 2385 } 2386 EXPORT_SYMBOL(wx_misc_isb); 2387 2388 /** 2389 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors 2390 * @wx: pointer to wx struct 2391 * @direction: 0 for Rx, 1 for Tx, -1 for other causes 2392 * @queue: queue to map the corresponding interrupt to 2393 * @msix_vector: the vector to map to the corresponding queue 2394 * 2395 **/ 2396 static void wx_set_ivar(struct wx *wx, s8 direction, 2397 u16 queue, u16 msix_vector) 2398 { 2399 u32 ivar, index; 2400 2401 if (direction == -1) { 2402 /* other causes */ 2403 if (test_bit(WX_FLAG_IRQ_VECTOR_SHARED, wx->flags)) 2404 msix_vector = 0; 2405 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2406 index = 0; 2407 ivar = rd32(wx, WX_PX_MISC_IVAR); 2408 ivar &= ~(0xFF << index); 2409 ivar |= (msix_vector << index); 2410 wr32(wx, WX_PX_MISC_IVAR, ivar); 2411 } else { 2412 /* tx or rx causes */ 2413 msix_vector |= WX_PX_IVAR_ALLOC_VAL; 2414 index = ((16 * (queue & 1)) + (8 * direction)); 2415 ivar = rd32(wx, WX_PX_IVAR(queue >> 1)); 2416 ivar &= ~(0xFF << index); 2417 ivar |= (msix_vector << index); 2418 wr32(wx, WX_PX_IVAR(queue >> 1), ivar); 2419 } 2420 } 2421 2422 /** 2423 * wx_write_eitr - write EITR register in hardware specific way 2424 * @q_vector: structure containing interrupt and ring information 2425 * 2426 * This function is made to be called by ethtool and by the driver 2427 * when it needs to update EITR registers at runtime. Hardware 2428 * specific quirks/differences are taken care of here. 2429 */ 2430 void wx_write_eitr(struct wx_q_vector *q_vector) 2431 { 2432 struct wx *wx = q_vector->wx; 2433 int v_idx = q_vector->v_idx; 2434 u32 itr_reg; 2435 2436 switch (wx->mac.type) { 2437 case wx_mac_sp: 2438 itr_reg = q_vector->itr & WX_SP_MAX_EITR; 2439 break; 2440 case wx_mac_aml: 2441 case wx_mac_aml40: 2442 itr_reg = (q_vector->itr >> 3) & WX_AML_MAX_EITR; 2443 break; 2444 default: 2445 itr_reg = q_vector->itr & WX_EM_MAX_EITR; 2446 break; 2447 } 2448 2449 itr_reg |= WX_PX_ITR_CNT_WDIS; 2450 2451 wr32(wx, WX_PX_ITR(v_idx), itr_reg); 2452 } 2453 2454 /** 2455 * wx_configure_vectors - Configure vectors for hardware 2456 * @wx: board private structure 2457 * 2458 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/INTx 2459 * interrupts. 2460 **/ 2461 void wx_configure_vectors(struct wx *wx) 2462 { 2463 struct pci_dev *pdev = wx->pdev; 2464 u32 eitrsel = 0; 2465 u16 v_idx, i; 2466 2467 if (pdev->msix_enabled) { 2468 /* Populate MSIX to EITR Select */ 2469 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2470 if (wx->num_vfs >= 32) 2471 eitrsel = BIT(wx->num_vfs % 32) - 1; 2472 } else { 2473 for (i = 0; i < wx->num_vfs; i++) 2474 eitrsel |= BIT(i); 2475 } 2476 wr32(wx, WX_PX_ITRSEL, eitrsel); 2477 /* use EIAM to auto-mask when MSI-X interrupt is asserted 2478 * this saves a register write for every interrupt 2479 */ 2480 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL); 2481 } else { 2482 /* legacy interrupts, use EIAM to auto-mask when reading EICR, 2483 * specifically only auto mask tx and rx interrupts. 2484 */ 2485 wr32(wx, WX_PX_GPIE, 0); 2486 } 2487 2488 /* Populate the IVAR table and set the ITR values to the 2489 * corresponding register. 2490 */ 2491 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) { 2492 struct wx_q_vector *q_vector = wx->q_vector[v_idx]; 2493 struct wx_ring *ring; 2494 2495 wx_for_each_ring(ring, q_vector->rx) 2496 wx_set_ivar(wx, 0, ring->reg_idx, v_idx); 2497 2498 wx_for_each_ring(ring, q_vector->tx) 2499 wx_set_ivar(wx, 1, ring->reg_idx, v_idx); 2500 2501 wx_write_eitr(q_vector); 2502 } 2503 2504 wx_set_ivar(wx, -1, 0, v_idx); 2505 if (pdev->msix_enabled) 2506 wr32(wx, WX_PX_ITR(v_idx), 1950); 2507 } 2508 EXPORT_SYMBOL(wx_configure_vectors); 2509 2510 /** 2511 * wx_clean_rx_ring - Free Rx Buffers per Queue 2512 * @rx_ring: ring to free buffers from 2513 **/ 2514 static void wx_clean_rx_ring(struct wx_ring *rx_ring) 2515 { 2516 struct wx_rx_buffer *rx_buffer; 2517 u16 i = rx_ring->next_to_clean; 2518 2519 rx_buffer = &rx_ring->rx_buffer_info[i]; 2520 2521 /* Free all the Rx ring sk_buffs */ 2522 while (i != rx_ring->next_to_alloc) { 2523 if (rx_buffer->skb) { 2524 struct sk_buff *skb = rx_buffer->skb; 2525 2526 dev_kfree_skb(skb); 2527 } 2528 2529 /* Invalidate cache lines that may have been written to by 2530 * device so that we avoid corrupting memory. 2531 */ 2532 dma_sync_single_range_for_cpu(rx_ring->dev, 2533 rx_buffer->dma, 2534 rx_buffer->page_offset, 2535 WX_RX_BUFSZ, 2536 DMA_FROM_DEVICE); 2537 2538 /* free resources associated with mapping */ 2539 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false); 2540 2541 i++; 2542 rx_buffer++; 2543 if (i == rx_ring->count) { 2544 i = 0; 2545 rx_buffer = rx_ring->rx_buffer_info; 2546 } 2547 } 2548 2549 /* Zero out the descriptor ring */ 2550 memset(rx_ring->desc, 0, rx_ring->size); 2551 2552 rx_ring->next_to_alloc = 0; 2553 rx_ring->next_to_clean = 0; 2554 rx_ring->next_to_use = 0; 2555 } 2556 2557 /** 2558 * wx_clean_all_rx_rings - Free Rx Buffers for all queues 2559 * @wx: board private structure 2560 **/ 2561 void wx_clean_all_rx_rings(struct wx *wx) 2562 { 2563 int i; 2564 2565 for (i = 0; i < wx->num_rx_queues; i++) 2566 wx_clean_rx_ring(wx->rx_ring[i]); 2567 } 2568 EXPORT_SYMBOL(wx_clean_all_rx_rings); 2569 2570 /** 2571 * wx_free_rx_resources - Free Rx Resources 2572 * @rx_ring: ring to clean the resources from 2573 * 2574 * Free all receive software resources 2575 **/ 2576 static void wx_free_rx_resources(struct wx_ring *rx_ring) 2577 { 2578 wx_clean_rx_ring(rx_ring); 2579 kvfree(rx_ring->rx_buffer_info); 2580 rx_ring->rx_buffer_info = NULL; 2581 2582 /* if not set, then don't free */ 2583 if (!rx_ring->desc) 2584 return; 2585 2586 dma_free_coherent(rx_ring->dev, rx_ring->size, 2587 rx_ring->desc, rx_ring->dma); 2588 2589 rx_ring->desc = NULL; 2590 2591 if (rx_ring->page_pool) { 2592 page_pool_destroy(rx_ring->page_pool); 2593 rx_ring->page_pool = NULL; 2594 } 2595 } 2596 2597 /** 2598 * wx_free_all_rx_resources - Free Rx Resources for All Queues 2599 * @wx: pointer to hardware structure 2600 * 2601 * Free all receive software resources 2602 **/ 2603 static void wx_free_all_rx_resources(struct wx *wx) 2604 { 2605 int i; 2606 2607 for (i = 0; i < wx->num_rx_queues; i++) 2608 wx_free_rx_resources(wx->rx_ring[i]); 2609 } 2610 2611 /** 2612 * wx_clean_tx_ring - Free Tx Buffers 2613 * @tx_ring: ring to be cleaned 2614 **/ 2615 static void wx_clean_tx_ring(struct wx_ring *tx_ring) 2616 { 2617 struct wx_tx_buffer *tx_buffer; 2618 u16 i = tx_ring->next_to_clean; 2619 2620 tx_buffer = &tx_ring->tx_buffer_info[i]; 2621 2622 while (i != tx_ring->next_to_use) { 2623 union wx_tx_desc *eop_desc, *tx_desc; 2624 2625 /* Free all the Tx ring sk_buffs */ 2626 dev_kfree_skb_any(tx_buffer->skb); 2627 2628 /* unmap skb header data */ 2629 dma_unmap_single(tx_ring->dev, 2630 dma_unmap_addr(tx_buffer, dma), 2631 dma_unmap_len(tx_buffer, len), 2632 DMA_TO_DEVICE); 2633 2634 /* check for eop_desc to determine the end of the packet */ 2635 eop_desc = tx_buffer->next_to_watch; 2636 tx_desc = WX_TX_DESC(tx_ring, i); 2637 2638 /* unmap remaining buffers */ 2639 while (tx_desc != eop_desc) { 2640 tx_buffer++; 2641 tx_desc++; 2642 i++; 2643 if (unlikely(i == tx_ring->count)) { 2644 i = 0; 2645 tx_buffer = tx_ring->tx_buffer_info; 2646 tx_desc = WX_TX_DESC(tx_ring, 0); 2647 } 2648 2649 /* unmap any remaining paged data */ 2650 if (dma_unmap_len(tx_buffer, len)) 2651 dma_unmap_page(tx_ring->dev, 2652 dma_unmap_addr(tx_buffer, dma), 2653 dma_unmap_len(tx_buffer, len), 2654 DMA_TO_DEVICE); 2655 } 2656 2657 /* move us one more past the eop_desc for start of next pkt */ 2658 tx_buffer++; 2659 i++; 2660 if (unlikely(i == tx_ring->count)) { 2661 i = 0; 2662 tx_buffer = tx_ring->tx_buffer_info; 2663 } 2664 } 2665 2666 netdev_tx_reset_queue(wx_txring_txq(tx_ring)); 2667 2668 /* reset next_to_use and next_to_clean */ 2669 tx_ring->next_to_use = 0; 2670 tx_ring->next_to_clean = 0; 2671 } 2672 2673 /** 2674 * wx_clean_all_tx_rings - Free Tx Buffers for all queues 2675 * @wx: board private structure 2676 **/ 2677 void wx_clean_all_tx_rings(struct wx *wx) 2678 { 2679 int i; 2680 2681 for (i = 0; i < wx->num_tx_queues; i++) 2682 wx_clean_tx_ring(wx->tx_ring[i]); 2683 } 2684 EXPORT_SYMBOL(wx_clean_all_tx_rings); 2685 2686 /** 2687 * wx_free_tx_resources - Free Tx Resources per Queue 2688 * @tx_ring: Tx descriptor ring for a specific queue 2689 * 2690 * Free all transmit software resources 2691 **/ 2692 static void wx_free_tx_resources(struct wx_ring *tx_ring) 2693 { 2694 wx_clean_tx_ring(tx_ring); 2695 kvfree(tx_ring->tx_buffer_info); 2696 tx_ring->tx_buffer_info = NULL; 2697 2698 /* if not set, then don't free */ 2699 if (!tx_ring->desc) 2700 return; 2701 2702 dma_free_coherent(tx_ring->dev, tx_ring->size, 2703 tx_ring->desc, tx_ring->dma); 2704 tx_ring->desc = NULL; 2705 } 2706 2707 /** 2708 * wx_free_all_tx_resources - Free Tx Resources for All Queues 2709 * @wx: pointer to hardware structure 2710 * 2711 * Free all transmit software resources 2712 **/ 2713 static void wx_free_all_tx_resources(struct wx *wx) 2714 { 2715 int i; 2716 2717 for (i = 0; i < wx->num_tx_queues; i++) 2718 wx_free_tx_resources(wx->tx_ring[i]); 2719 } 2720 2721 void wx_free_resources(struct wx *wx) 2722 { 2723 wx_free_all_rx_resources(wx); 2724 wx_free_all_tx_resources(wx); 2725 } 2726 EXPORT_SYMBOL(wx_free_resources); 2727 2728 static int wx_alloc_page_pool(struct wx_ring *rx_ring) 2729 { 2730 int ret = 0; 2731 2732 struct page_pool_params pp_params = { 2733 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 2734 .order = 0, 2735 .pool_size = rx_ring->count, 2736 .nid = dev_to_node(rx_ring->dev), 2737 .dev = rx_ring->dev, 2738 .dma_dir = DMA_FROM_DEVICE, 2739 .offset = 0, 2740 .max_len = PAGE_SIZE, 2741 }; 2742 2743 rx_ring->page_pool = page_pool_create(&pp_params); 2744 if (IS_ERR(rx_ring->page_pool)) { 2745 ret = PTR_ERR(rx_ring->page_pool); 2746 rx_ring->page_pool = NULL; 2747 } 2748 2749 return ret; 2750 } 2751 2752 /** 2753 * wx_setup_rx_resources - allocate Rx resources (Descriptors) 2754 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2755 * 2756 * Returns 0 on success, negative on failure 2757 **/ 2758 static int wx_setup_rx_resources(struct wx_ring *rx_ring) 2759 { 2760 struct device *dev = rx_ring->dev; 2761 int orig_node = dev_to_node(dev); 2762 int numa_node = NUMA_NO_NODE; 2763 int size, ret; 2764 2765 size = sizeof(struct wx_rx_buffer) * rx_ring->count; 2766 2767 if (rx_ring->q_vector) 2768 numa_node = rx_ring->q_vector->numa_node; 2769 2770 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2771 if (!rx_ring->rx_buffer_info) 2772 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL); 2773 if (!rx_ring->rx_buffer_info) 2774 goto err; 2775 2776 /* Round up to nearest 4K */ 2777 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc); 2778 rx_ring->size = ALIGN(rx_ring->size, 4096); 2779 2780 set_dev_node(dev, numa_node); 2781 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2782 &rx_ring->dma, GFP_KERNEL); 2783 if (!rx_ring->desc) { 2784 set_dev_node(dev, orig_node); 2785 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2786 &rx_ring->dma, GFP_KERNEL); 2787 } 2788 2789 if (!rx_ring->desc) 2790 goto err; 2791 2792 rx_ring->next_to_clean = 0; 2793 rx_ring->next_to_use = 0; 2794 2795 ret = wx_alloc_page_pool(rx_ring); 2796 if (ret < 0) { 2797 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret); 2798 goto err_desc; 2799 } 2800 2801 return 0; 2802 2803 err_desc: 2804 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma); 2805 err: 2806 kvfree(rx_ring->rx_buffer_info); 2807 rx_ring->rx_buffer_info = NULL; 2808 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2809 return -ENOMEM; 2810 } 2811 2812 /** 2813 * wx_setup_all_rx_resources - allocate all queues Rx resources 2814 * @wx: pointer to hardware structure 2815 * 2816 * If this function returns with an error, then it's possible one or 2817 * more of the rings is populated (while the rest are not). It is the 2818 * callers duty to clean those orphaned rings. 2819 * 2820 * Return 0 on success, negative on failure 2821 **/ 2822 static int wx_setup_all_rx_resources(struct wx *wx) 2823 { 2824 int i, err = 0; 2825 2826 for (i = 0; i < wx->num_rx_queues; i++) { 2827 err = wx_setup_rx_resources(wx->rx_ring[i]); 2828 if (!err) 2829 continue; 2830 2831 wx_err(wx, "Allocation for Rx Queue %u failed\n", i); 2832 goto err_setup_rx; 2833 } 2834 2835 return 0; 2836 err_setup_rx: 2837 /* rewind the index freeing the rings as we go */ 2838 while (i--) 2839 wx_free_rx_resources(wx->rx_ring[i]); 2840 return err; 2841 } 2842 2843 /** 2844 * wx_setup_tx_resources - allocate Tx resources (Descriptors) 2845 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2846 * 2847 * Return 0 on success, negative on failure 2848 **/ 2849 static int wx_setup_tx_resources(struct wx_ring *tx_ring) 2850 { 2851 struct device *dev = tx_ring->dev; 2852 int orig_node = dev_to_node(dev); 2853 int numa_node = NUMA_NO_NODE; 2854 int size; 2855 2856 size = sizeof(struct wx_tx_buffer) * tx_ring->count; 2857 2858 if (tx_ring->q_vector) 2859 numa_node = tx_ring->q_vector->numa_node; 2860 2861 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node); 2862 if (!tx_ring->tx_buffer_info) 2863 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL); 2864 if (!tx_ring->tx_buffer_info) 2865 goto err; 2866 2867 /* round up to nearest 4K */ 2868 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc); 2869 tx_ring->size = ALIGN(tx_ring->size, 4096); 2870 2871 set_dev_node(dev, numa_node); 2872 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2873 &tx_ring->dma, GFP_KERNEL); 2874 if (!tx_ring->desc) { 2875 set_dev_node(dev, orig_node); 2876 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2877 &tx_ring->dma, GFP_KERNEL); 2878 } 2879 2880 if (!tx_ring->desc) 2881 goto err; 2882 2883 tx_ring->next_to_use = 0; 2884 tx_ring->next_to_clean = 0; 2885 2886 return 0; 2887 2888 err: 2889 kvfree(tx_ring->tx_buffer_info); 2890 tx_ring->tx_buffer_info = NULL; 2891 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2892 return -ENOMEM; 2893 } 2894 2895 /** 2896 * wx_setup_all_tx_resources - allocate all queues Tx resources 2897 * @wx: pointer to private structure 2898 * 2899 * If this function returns with an error, then it's possible one or 2900 * more of the rings is populated (while the rest are not). It is the 2901 * callers duty to clean those orphaned rings. 2902 * 2903 * Return 0 on success, negative on failure 2904 **/ 2905 static int wx_setup_all_tx_resources(struct wx *wx) 2906 { 2907 int i, err = 0; 2908 2909 for (i = 0; i < wx->num_tx_queues; i++) { 2910 err = wx_setup_tx_resources(wx->tx_ring[i]); 2911 if (!err) 2912 continue; 2913 2914 wx_err(wx, "Allocation for Tx Queue %u failed\n", i); 2915 goto err_setup_tx; 2916 } 2917 2918 return 0; 2919 err_setup_tx: 2920 /* rewind the index freeing the rings as we go */ 2921 while (i--) 2922 wx_free_tx_resources(wx->tx_ring[i]); 2923 return err; 2924 } 2925 2926 int wx_setup_resources(struct wx *wx) 2927 { 2928 int err; 2929 2930 /* allocate transmit descriptors */ 2931 err = wx_setup_all_tx_resources(wx); 2932 if (err) 2933 return err; 2934 2935 /* allocate receive descriptors */ 2936 err = wx_setup_all_rx_resources(wx); 2937 if (err) 2938 goto err_free_tx; 2939 2940 err = wx_setup_isb_resources(wx); 2941 if (err) 2942 goto err_free_rx; 2943 2944 return 0; 2945 2946 err_free_rx: 2947 wx_free_all_rx_resources(wx); 2948 err_free_tx: 2949 wx_free_all_tx_resources(wx); 2950 2951 return err; 2952 } 2953 EXPORT_SYMBOL(wx_setup_resources); 2954 2955 /** 2956 * wx_get_stats64 - Get System Network Statistics 2957 * @netdev: network interface device structure 2958 * @stats: storage space for 64bit statistics 2959 */ 2960 void wx_get_stats64(struct net_device *netdev, 2961 struct rtnl_link_stats64 *stats) 2962 { 2963 struct wx *wx = netdev_priv(netdev); 2964 struct wx_hw_stats *hwstats; 2965 int i; 2966 2967 wx_update_stats(wx); 2968 2969 rcu_read_lock(); 2970 for (i = 0; i < wx->num_rx_queues; i++) { 2971 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]); 2972 u64 bytes, packets; 2973 unsigned int start; 2974 2975 if (ring) { 2976 do { 2977 start = u64_stats_fetch_begin(&ring->syncp); 2978 packets = ring->stats.packets; 2979 bytes = ring->stats.bytes; 2980 } while (u64_stats_fetch_retry(&ring->syncp, start)); 2981 stats->rx_packets += packets; 2982 stats->rx_bytes += bytes; 2983 } 2984 } 2985 2986 for (i = 0; i < wx->num_tx_queues; i++) { 2987 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]); 2988 u64 bytes, packets; 2989 unsigned int start; 2990 2991 if (ring) { 2992 do { 2993 start = u64_stats_fetch_begin(&ring->syncp); 2994 packets = ring->stats.packets; 2995 bytes = ring->stats.bytes; 2996 } while (u64_stats_fetch_retry(&ring->syncp, 2997 start)); 2998 stats->tx_packets += packets; 2999 stats->tx_bytes += bytes; 3000 } 3001 } 3002 3003 rcu_read_unlock(); 3004 3005 hwstats = &wx->stats; 3006 stats->rx_errors = hwstats->crcerrs + hwstats->rlec; 3007 stats->multicast = hwstats->qmprc; 3008 stats->rx_length_errors = hwstats->rlec; 3009 stats->rx_crc_errors = hwstats->crcerrs; 3010 } 3011 EXPORT_SYMBOL(wx_get_stats64); 3012 3013 int wx_set_features(struct net_device *netdev, netdev_features_t features) 3014 { 3015 netdev_features_t changed = netdev->features ^ features; 3016 struct wx *wx = netdev_priv(netdev); 3017 bool need_reset = false; 3018 3019 wx->rss_enabled = !!(features & NETIF_F_RXHASH); 3020 wx_enable_rss(wx, wx->rss_enabled); 3021 3022 netdev->features = features; 3023 3024 if (changed & NETIF_F_HW_VLAN_CTAG_RX && wx->do_reset) 3025 wx->do_reset(netdev); 3026 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER)) 3027 wx_set_rx_mode(netdev); 3028 3029 if (!(test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags))) 3030 return 0; 3031 3032 /* Check if Flow Director n-tuple support was enabled or disabled. If 3033 * the state changed, we need to reset. 3034 */ 3035 switch (features & NETIF_F_NTUPLE) { 3036 case NETIF_F_NTUPLE: 3037 /* turn off ATR, enable perfect filters and reset */ 3038 if (!(test_and_set_bit(WX_FLAG_FDIR_PERFECT, wx->flags))) 3039 need_reset = true; 3040 3041 clear_bit(WX_FLAG_FDIR_HASH, wx->flags); 3042 break; 3043 default: 3044 /* turn off perfect filters, enable ATR and reset */ 3045 if (test_and_clear_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 3046 need_reset = true; 3047 3048 /* We cannot enable ATR if RSS is disabled */ 3049 if (wx->ring_feature[RING_F_RSS].limit <= 1) 3050 break; 3051 3052 set_bit(WX_FLAG_FDIR_HASH, wx->flags); 3053 break; 3054 } 3055 3056 if (need_reset && wx->do_reset) 3057 wx->do_reset(netdev); 3058 3059 return 0; 3060 } 3061 EXPORT_SYMBOL(wx_set_features); 3062 3063 #define NETIF_VLAN_STRIPPING_FEATURES (NETIF_F_HW_VLAN_CTAG_RX | \ 3064 NETIF_F_HW_VLAN_STAG_RX) 3065 3066 #define NETIF_VLAN_INSERTION_FEATURES (NETIF_F_HW_VLAN_CTAG_TX | \ 3067 NETIF_F_HW_VLAN_STAG_TX) 3068 3069 #define NETIF_VLAN_FILTERING_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \ 3070 NETIF_F_HW_VLAN_STAG_FILTER) 3071 3072 netdev_features_t wx_fix_features(struct net_device *netdev, 3073 netdev_features_t features) 3074 { 3075 netdev_features_t changed = netdev->features ^ features; 3076 struct wx *wx = netdev_priv(netdev); 3077 3078 if (changed & NETIF_VLAN_STRIPPING_FEATURES) { 3079 if ((features & NETIF_VLAN_STRIPPING_FEATURES) != NETIF_VLAN_STRIPPING_FEATURES && 3080 (features & NETIF_VLAN_STRIPPING_FEATURES) != 0) { 3081 features &= ~NETIF_VLAN_STRIPPING_FEATURES; 3082 features |= netdev->features & NETIF_VLAN_STRIPPING_FEATURES; 3083 wx_err(wx, "802.1Q and 802.1ad VLAN stripping must be either both on or both off."); 3084 } 3085 } 3086 3087 if (changed & NETIF_VLAN_INSERTION_FEATURES) { 3088 if ((features & NETIF_VLAN_INSERTION_FEATURES) != NETIF_VLAN_INSERTION_FEATURES && 3089 (features & NETIF_VLAN_INSERTION_FEATURES) != 0) { 3090 features &= ~NETIF_VLAN_INSERTION_FEATURES; 3091 features |= netdev->features & NETIF_VLAN_INSERTION_FEATURES; 3092 wx_err(wx, "802.1Q and 802.1ad VLAN insertion must be either both on or both off."); 3093 } 3094 } 3095 3096 if (changed & NETIF_VLAN_FILTERING_FEATURES) { 3097 if ((features & NETIF_VLAN_FILTERING_FEATURES) != NETIF_VLAN_FILTERING_FEATURES && 3098 (features & NETIF_VLAN_FILTERING_FEATURES) != 0) { 3099 features &= ~NETIF_VLAN_FILTERING_FEATURES; 3100 features |= netdev->features & NETIF_VLAN_FILTERING_FEATURES; 3101 wx_err(wx, "802.1Q and 802.1ad VLAN filtering must be either both on or both off."); 3102 } 3103 } 3104 3105 return features; 3106 } 3107 EXPORT_SYMBOL(wx_fix_features); 3108 3109 #define WX_MAX_TUNNEL_HDR_LEN 80 3110 netdev_features_t wx_features_check(struct sk_buff *skb, 3111 struct net_device *netdev, 3112 netdev_features_t features) 3113 { 3114 struct wx *wx = netdev_priv(netdev); 3115 3116 if (!skb->encapsulation) 3117 return features; 3118 3119 if (wx->mac.type == wx_mac_em) 3120 return features & ~NETIF_F_CSUM_MASK; 3121 3122 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) > 3123 WX_MAX_TUNNEL_HDR_LEN)) 3124 return features & ~NETIF_F_CSUM_MASK; 3125 3126 if (skb->inner_protocol_type == ENCAP_TYPE_ETHER && 3127 skb->inner_protocol != htons(ETH_P_IP) && 3128 skb->inner_protocol != htons(ETH_P_IPV6) && 3129 skb->inner_protocol != htons(ETH_P_TEB)) 3130 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 3131 3132 return features; 3133 } 3134 EXPORT_SYMBOL(wx_features_check); 3135 3136 void wx_set_ring(struct wx *wx, u32 new_tx_count, 3137 u32 new_rx_count, struct wx_ring *temp_ring) 3138 { 3139 int i, err = 0; 3140 3141 /* Setup new Tx resources and free the old Tx resources in that order. 3142 * We can then assign the new resources to the rings via a memcpy. 3143 * The advantage to this approach is that we are guaranteed to still 3144 * have resources even in the case of an allocation failure. 3145 */ 3146 if (new_tx_count != wx->tx_ring_count) { 3147 for (i = 0; i < wx->num_tx_queues; i++) { 3148 memcpy(&temp_ring[i], wx->tx_ring[i], 3149 sizeof(struct wx_ring)); 3150 3151 temp_ring[i].count = new_tx_count; 3152 err = wx_setup_tx_resources(&temp_ring[i]); 3153 if (err) { 3154 wx_err(wx, "setup new tx resources failed, keep using the old config\n"); 3155 while (i) { 3156 i--; 3157 wx_free_tx_resources(&temp_ring[i]); 3158 } 3159 return; 3160 } 3161 } 3162 3163 for (i = 0; i < wx->num_tx_queues; i++) { 3164 wx_free_tx_resources(wx->tx_ring[i]); 3165 3166 memcpy(wx->tx_ring[i], &temp_ring[i], 3167 sizeof(struct wx_ring)); 3168 } 3169 3170 wx->tx_ring_count = new_tx_count; 3171 } 3172 3173 /* Repeat the process for the Rx rings if needed */ 3174 if (new_rx_count != wx->rx_ring_count) { 3175 for (i = 0; i < wx->num_rx_queues; i++) { 3176 memcpy(&temp_ring[i], wx->rx_ring[i], 3177 sizeof(struct wx_ring)); 3178 3179 temp_ring[i].count = new_rx_count; 3180 err = wx_setup_rx_resources(&temp_ring[i]); 3181 if (err) { 3182 wx_err(wx, "setup new rx resources failed, keep using the old config\n"); 3183 while (i) { 3184 i--; 3185 wx_free_rx_resources(&temp_ring[i]); 3186 } 3187 return; 3188 } 3189 } 3190 3191 for (i = 0; i < wx->num_rx_queues; i++) { 3192 wx_free_rx_resources(wx->rx_ring[i]); 3193 memcpy(wx->rx_ring[i], &temp_ring[i], 3194 sizeof(struct wx_ring)); 3195 } 3196 3197 wx->rx_ring_count = new_rx_count; 3198 } 3199 } 3200 EXPORT_SYMBOL(wx_set_ring); 3201 3202 void wx_service_event_schedule(struct wx *wx) 3203 { 3204 if (!test_and_set_bit(WX_STATE_SERVICE_SCHED, wx->state)) 3205 queue_work(system_power_efficient_wq, &wx->service_task); 3206 } 3207 EXPORT_SYMBOL(wx_service_event_schedule); 3208 3209 void wx_service_event_complete(struct wx *wx) 3210 { 3211 if (WARN_ON(!test_bit(WX_STATE_SERVICE_SCHED, wx->state))) 3212 return; 3213 3214 /* flush memory to make sure state is correct before next watchdog */ 3215 smp_mb__before_atomic(); 3216 clear_bit(WX_STATE_SERVICE_SCHED, wx->state); 3217 } 3218 EXPORT_SYMBOL(wx_service_event_complete); 3219 3220 void wx_service_timer(struct timer_list *t) 3221 { 3222 struct wx *wx = timer_container_of(wx, t, service_timer); 3223 unsigned long next_event_offset = HZ * 2; 3224 3225 /* Reset the timer */ 3226 mod_timer(&wx->service_timer, next_event_offset + jiffies); 3227 3228 wx_service_event_schedule(wx); 3229 } 3230 EXPORT_SYMBOL(wx_service_timer); 3231 3232 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers."); 3233 MODULE_LICENSE("GPL"); 3234