1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/netdevice.h> 6 #include <linux/if_ether.h> 7 #include <linux/if_vlan.h> 8 #include <linux/iopoll.h> 9 #include <linux/pci.h> 10 11 #include "wx_type.h" 12 #include "wx_lib.h" 13 #include "wx_sriov.h" 14 #include "wx_hw.h" 15 16 static int wx_phy_read_reg_mdi(struct mii_bus *bus, int phy_addr, int devnum, int regnum) 17 { 18 struct wx *wx = bus->priv; 19 u32 command, val; 20 int ret; 21 22 /* setup and write the address cycle command */ 23 command = WX_MSCA_RA(regnum) | 24 WX_MSCA_PA(phy_addr) | 25 WX_MSCA_DA(devnum); 26 wr32(wx, WX_MSCA, command); 27 28 command = WX_MSCC_CMD(WX_MSCA_CMD_READ) | WX_MSCC_BUSY; 29 if (wx->mac.type == wx_mac_em) 30 command |= WX_MDIO_CLK(6); 31 wr32(wx, WX_MSCC, command); 32 33 /* wait to complete */ 34 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 35 100000, false, wx, WX_MSCC); 36 if (ret) { 37 wx_err(wx, "Mdio read c22 command did not complete.\n"); 38 return ret; 39 } 40 41 return (u16)rd32(wx, WX_MSCC); 42 } 43 44 static int wx_phy_write_reg_mdi(struct mii_bus *bus, int phy_addr, 45 int devnum, int regnum, u16 value) 46 { 47 struct wx *wx = bus->priv; 48 u32 command, val; 49 int ret; 50 51 /* setup and write the address cycle command */ 52 command = WX_MSCA_RA(regnum) | 53 WX_MSCA_PA(phy_addr) | 54 WX_MSCA_DA(devnum); 55 wr32(wx, WX_MSCA, command); 56 57 command = value | WX_MSCC_CMD(WX_MSCA_CMD_WRITE) | WX_MSCC_BUSY; 58 if (wx->mac.type == wx_mac_em) 59 command |= WX_MDIO_CLK(6); 60 wr32(wx, WX_MSCC, command); 61 62 /* wait to complete */ 63 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 64 100000, false, wx, WX_MSCC); 65 if (ret) 66 wx_err(wx, "Mdio write c22 command did not complete.\n"); 67 68 return ret; 69 } 70 71 int wx_phy_read_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum) 72 { 73 struct wx *wx = bus->priv; 74 75 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF); 76 return wx_phy_read_reg_mdi(bus, phy_addr, 0, regnum); 77 } 78 EXPORT_SYMBOL(wx_phy_read_reg_mdi_c22); 79 80 int wx_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum, u16 value) 81 { 82 struct wx *wx = bus->priv; 83 84 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF); 85 return wx_phy_write_reg_mdi(bus, phy_addr, 0, regnum, value); 86 } 87 EXPORT_SYMBOL(wx_phy_write_reg_mdi_c22); 88 89 int wx_phy_read_reg_mdi_c45(struct mii_bus *bus, int phy_addr, int devnum, int regnum) 90 { 91 struct wx *wx = bus->priv; 92 93 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0); 94 return wx_phy_read_reg_mdi(bus, phy_addr, devnum, regnum); 95 } 96 EXPORT_SYMBOL(wx_phy_read_reg_mdi_c45); 97 98 int wx_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr, 99 int devnum, int regnum, u16 value) 100 { 101 struct wx *wx = bus->priv; 102 103 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0); 104 return wx_phy_write_reg_mdi(bus, phy_addr, devnum, regnum, value); 105 } 106 EXPORT_SYMBOL(wx_phy_write_reg_mdi_c45); 107 108 static void wx_intr_disable(struct wx *wx, u64 qmask) 109 { 110 u32 mask; 111 112 mask = (qmask & U32_MAX); 113 if (mask) 114 wr32(wx, WX_PX_IMS(0), mask); 115 116 switch (wx->mac.type) { 117 case wx_mac_sp: 118 case wx_mac_aml: 119 mask = (qmask >> 32); 120 if (mask) 121 wr32(wx, WX_PX_IMS(1), mask); 122 break; 123 default: 124 break; 125 } 126 } 127 128 void wx_intr_enable(struct wx *wx, u64 qmask) 129 { 130 u32 mask; 131 132 mask = (qmask & U32_MAX); 133 if (mask) 134 wr32(wx, WX_PX_IMC(0), mask); 135 136 switch (wx->mac.type) { 137 case wx_mac_sp: 138 case wx_mac_aml: 139 mask = (qmask >> 32); 140 if (mask) 141 wr32(wx, WX_PX_IMC(1), mask); 142 break; 143 default: 144 break; 145 } 146 } 147 EXPORT_SYMBOL(wx_intr_enable); 148 149 /** 150 * wx_irq_disable - Mask off interrupt generation on the NIC 151 * @wx: board private structure 152 **/ 153 void wx_irq_disable(struct wx *wx) 154 { 155 struct pci_dev *pdev = wx->pdev; 156 157 wr32(wx, WX_PX_MISC_IEN, 0); 158 wx_intr_disable(wx, WX_INTR_ALL); 159 160 if (pdev->msix_enabled) { 161 int vector; 162 163 for (vector = 0; vector < wx->num_q_vectors; vector++) 164 synchronize_irq(wx->msix_q_entries[vector].vector); 165 166 synchronize_irq(wx->msix_entry->vector); 167 } else { 168 synchronize_irq(pdev->irq); 169 } 170 } 171 EXPORT_SYMBOL(wx_irq_disable); 172 173 /* cmd_addr is used for some special command: 174 * 1. to be sector address, when implemented erase sector command 175 * 2. to be flash address when implemented read, write flash address 176 */ 177 static int wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr) 178 { 179 u32 cmd_val = 0, val = 0; 180 181 cmd_val = WX_SPI_CMD_CMD(cmd) | 182 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) | 183 cmd_addr; 184 wr32(wx, WX_SPI_CMD, cmd_val); 185 186 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, 187 false, wx, WX_SPI_STATUS); 188 } 189 190 static int wx_flash_read_dword(struct wx *wx, u32 addr, u32 *data) 191 { 192 int ret = 0; 193 194 ret = wx_fmgr_cmd_op(wx, WX_SPI_CMD_READ_DWORD, addr); 195 if (ret < 0) 196 return ret; 197 198 *data = rd32(wx, WX_SPI_DATA); 199 200 return ret; 201 } 202 203 int wx_check_flash_load(struct wx *hw, u32 check_bit) 204 { 205 u32 reg = 0; 206 int err = 0; 207 208 /* if there's flash existing */ 209 if (!(rd32(hw, WX_SPI_STATUS) & 210 WX_SPI_STATUS_FLASH_BYPASS)) { 211 /* wait hw load flash done */ 212 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, 213 false, hw, WX_SPI_ILDR_STATUS); 214 if (err < 0) 215 wx_err(hw, "Check flash load timeout.\n"); 216 } 217 218 return err; 219 } 220 EXPORT_SYMBOL(wx_check_flash_load); 221 222 void wx_control_hw(struct wx *wx, bool drv) 223 { 224 /* True : Let firmware know the driver has taken over 225 * False : Let firmware take over control of hw 226 */ 227 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD, 228 drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0); 229 } 230 EXPORT_SYMBOL(wx_control_hw); 231 232 /** 233 * wx_mng_present - returns 0 when management capability is present 234 * @wx: pointer to hardware structure 235 */ 236 int wx_mng_present(struct wx *wx) 237 { 238 u32 fwsm; 239 240 fwsm = rd32(wx, WX_MIS_ST); 241 if (fwsm & WX_MIS_ST_MNG_INIT_DN) 242 return 0; 243 else 244 return -EACCES; 245 } 246 EXPORT_SYMBOL(wx_mng_present); 247 248 /* Software lock to be held while software semaphore is being accessed. */ 249 static DEFINE_MUTEX(wx_sw_sync_lock); 250 251 /** 252 * wx_release_sw_sync - Release SW semaphore 253 * @wx: pointer to hardware structure 254 * @mask: Mask to specify which semaphore to release 255 * 256 * Releases the SW semaphore for the specified 257 * function (CSR, PHY0, PHY1, EEPROM, Flash) 258 **/ 259 static void wx_release_sw_sync(struct wx *wx, u32 mask) 260 { 261 mutex_lock(&wx_sw_sync_lock); 262 wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0); 263 mutex_unlock(&wx_sw_sync_lock); 264 } 265 266 /** 267 * wx_acquire_sw_sync - Acquire SW semaphore 268 * @wx: pointer to hardware structure 269 * @mask: Mask to specify which semaphore to acquire 270 * 271 * Acquires the SW semaphore for the specified 272 * function (CSR, PHY0, PHY1, EEPROM, Flash) 273 **/ 274 static int wx_acquire_sw_sync(struct wx *wx, u32 mask) 275 { 276 u32 sem = 0; 277 int ret = 0; 278 279 mutex_lock(&wx_sw_sync_lock); 280 ret = read_poll_timeout(rd32, sem, !(sem & mask), 281 5000, 2000000, false, wx, WX_MNG_SWFW_SYNC); 282 if (!ret) { 283 sem |= mask; 284 wr32(wx, WX_MNG_SWFW_SYNC, sem); 285 } else { 286 wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem); 287 } 288 mutex_unlock(&wx_sw_sync_lock); 289 290 return ret; 291 } 292 293 static int wx_host_interface_command_s(struct wx *wx, u32 *buffer, 294 u32 length, u32 timeout, bool return_data) 295 { 296 u32 hdr_size = sizeof(struct wx_hic_hdr); 297 u32 hicr, i, bi, buf[64] = {}; 298 int status = 0; 299 u32 dword_len; 300 u16 buf_len; 301 302 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 303 if (status != 0) 304 return status; 305 306 dword_len = length >> 2; 307 308 /* The device driver writes the relevant command block 309 * into the ram area. 310 */ 311 for (i = 0; i < dword_len; i++) { 312 wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 313 /* write flush */ 314 buf[i] = rd32a(wx, WX_MNG_MBOX, i); 315 } 316 /* Setting this bit tells the ARC that a new command is pending. */ 317 wr32m(wx, WX_MNG_MBOX_CTL, 318 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY); 319 320 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, 321 timeout * 1000, false, wx, WX_MNG_MBOX_CTL); 322 323 buf[0] = rd32(wx, WX_MNG_MBOX); 324 if ((buf[0] & 0xff0000) >> 16 == 0x80) { 325 wx_err(wx, "Unknown FW command: 0x%x\n", buffer[0] & 0xff); 326 status = -EINVAL; 327 goto rel_out; 328 } 329 330 /* Check command completion */ 331 if (status) { 332 wx_err(wx, "Command has failed with no status valid.\n"); 333 wx_dbg(wx, "write value:\n"); 334 for (i = 0; i < dword_len; i++) 335 wx_dbg(wx, "%x ", buffer[i]); 336 wx_dbg(wx, "read value:\n"); 337 for (i = 0; i < dword_len; i++) 338 wx_dbg(wx, "%x ", buf[i]); 339 wx_dbg(wx, "\ncheck: %x %x\n", buffer[0] & 0xff, ~buf[0] >> 24); 340 341 goto rel_out; 342 } 343 344 if (!return_data) 345 goto rel_out; 346 347 /* Calculate length in DWORDs */ 348 dword_len = hdr_size >> 2; 349 350 /* first pull in the header so we know the buffer length */ 351 for (bi = 0; bi < dword_len; bi++) { 352 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 353 le32_to_cpus(&buffer[bi]); 354 } 355 356 /* If there is any thing in data position pull it in */ 357 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len; 358 if (buf_len == 0) 359 goto rel_out; 360 361 if (length < buf_len + hdr_size) { 362 wx_err(wx, "Buffer not large enough for reply message.\n"); 363 status = -EFAULT; 364 goto rel_out; 365 } 366 367 /* Calculate length in DWORDs, add 3 for odd lengths */ 368 dword_len = (buf_len + 3) >> 2; 369 370 /* Pull in the rest of the buffer (bi is where we left off) */ 371 for (; bi <= dword_len; bi++) { 372 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 373 le32_to_cpus(&buffer[bi]); 374 } 375 376 rel_out: 377 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 378 return status; 379 } 380 381 static bool wx_poll_fw_reply(struct wx *wx, u32 *buffer, u8 send_cmd) 382 { 383 u32 dword_len = sizeof(struct wx_hic_hdr) >> 2; 384 struct wx_hic_hdr *recv_hdr; 385 u32 i; 386 387 /* read hdr */ 388 for (i = 0; i < dword_len; i++) { 389 buffer[i] = rd32a(wx, WX_FW2SW_MBOX, i); 390 le32_to_cpus(&buffer[i]); 391 } 392 393 /* check hdr */ 394 recv_hdr = (struct wx_hic_hdr *)buffer; 395 if (recv_hdr->cmd == send_cmd && 396 recv_hdr->index == wx->swfw_index) 397 return true; 398 399 return false; 400 } 401 402 static int wx_host_interface_command_r(struct wx *wx, u32 *buffer, 403 u32 length, u32 timeout, bool return_data) 404 { 405 struct wx_hic_hdr *hdr = (struct wx_hic_hdr *)buffer; 406 u32 hdr_size = sizeof(struct wx_hic_hdr); 407 bool busy, reply; 408 u32 dword_len; 409 u16 buf_len; 410 int err = 0; 411 u8 send_cmd; 412 u32 i; 413 414 /* wait to get lock */ 415 might_sleep(); 416 err = read_poll_timeout(test_and_set_bit, busy, !busy, 1000, timeout * 1000, 417 false, WX_STATE_SWFW_BUSY, wx->state); 418 if (err) 419 return err; 420 421 /* index to unique seq id for each mbox message */ 422 hdr->index = wx->swfw_index; 423 send_cmd = hdr->cmd; 424 425 dword_len = length >> 2; 426 /* write data to SW-FW mbox array */ 427 for (i = 0; i < dword_len; i++) { 428 wr32a(wx, WX_SW2FW_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 429 /* write flush */ 430 rd32a(wx, WX_SW2FW_MBOX, i); 431 } 432 433 /* generate interrupt to notify FW */ 434 wr32m(wx, WX_SW2FW_MBOX_CMD, WX_SW2FW_MBOX_CMD_VLD, 0); 435 wr32m(wx, WX_SW2FW_MBOX_CMD, WX_SW2FW_MBOX_CMD_VLD, WX_SW2FW_MBOX_CMD_VLD); 436 437 /* polling reply from FW */ 438 err = read_poll_timeout(wx_poll_fw_reply, reply, reply, 1000, 50000, 439 true, wx, buffer, send_cmd); 440 if (err) { 441 wx_err(wx, "Polling from FW messages timeout, cmd: 0x%x, index: %d\n", 442 send_cmd, wx->swfw_index); 443 goto rel_out; 444 } 445 446 /* expect no reply from FW then return */ 447 if (!return_data) 448 goto rel_out; 449 450 /* If there is any thing in data position pull it in */ 451 buf_len = hdr->buf_len; 452 if (buf_len == 0) 453 goto rel_out; 454 455 if (length < buf_len + hdr_size) { 456 wx_err(wx, "Buffer not large enough for reply message.\n"); 457 err = -EFAULT; 458 goto rel_out; 459 } 460 461 /* Calculate length in DWORDs, add 3 for odd lengths */ 462 dword_len = (buf_len + 3) >> 2; 463 for (i = hdr_size >> 2; i <= dword_len; i++) { 464 buffer[i] = rd32a(wx, WX_FW2SW_MBOX, i); 465 le32_to_cpus(&buffer[i]); 466 } 467 468 rel_out: 469 /* index++, index replace wx_hic_hdr.checksum */ 470 if (wx->swfw_index == WX_HIC_HDR_INDEX_MAX) 471 wx->swfw_index = 0; 472 else 473 wx->swfw_index++; 474 475 clear_bit(WX_STATE_SWFW_BUSY, wx->state); 476 return err; 477 } 478 479 /** 480 * wx_host_interface_command - Issue command to manageability block 481 * @wx: pointer to the HW structure 482 * @buffer: contains the command to write and where the return status will 483 * be placed 484 * @length: length of buffer, must be multiple of 4 bytes 485 * @timeout: time in ms to wait for command completion 486 * @return_data: read and return data from the buffer (true) or not (false) 487 * Needed because FW structures are big endian and decoding of 488 * these fields can be 8 bit or 16 bit based on command. Decoding 489 * is not easily understood without making a table of commands. 490 * So we will leave this up to the caller to read back the data 491 * in these cases. 492 **/ 493 int wx_host_interface_command(struct wx *wx, u32 *buffer, 494 u32 length, u32 timeout, bool return_data) 495 { 496 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) { 497 wx_err(wx, "Buffer length failure buffersize=%d.\n", length); 498 return -EINVAL; 499 } 500 501 /* Calculate length in DWORDs. We must be DWORD aligned */ 502 if ((length % (sizeof(u32))) != 0) { 503 wx_err(wx, "Buffer length failure, not aligned to dword"); 504 return -EINVAL; 505 } 506 507 if (test_bit(WX_FLAG_SWFW_RING, wx->flags)) 508 return wx_host_interface_command_r(wx, buffer, length, 509 timeout, return_data); 510 511 return wx_host_interface_command_s(wx, buffer, length, timeout, return_data); 512 } 513 EXPORT_SYMBOL(wx_host_interface_command); 514 515 int wx_set_pps(struct wx *wx, bool enable, u64 nsec, u64 cycles) 516 { 517 struct wx_hic_set_pps pps_cmd; 518 519 pps_cmd.hdr.cmd = FW_PPS_SET_CMD; 520 pps_cmd.hdr.buf_len = FW_PPS_SET_LEN; 521 pps_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 522 pps_cmd.lan_id = wx->bus.func; 523 pps_cmd.enable = (u8)enable; 524 pps_cmd.nsec = nsec; 525 pps_cmd.cycles = cycles; 526 pps_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 527 528 return wx_host_interface_command(wx, (u32 *)&pps_cmd, 529 sizeof(pps_cmd), 530 WX_HI_COMMAND_TIMEOUT, 531 false); 532 } 533 534 /** 535 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd 536 * assuming that the semaphore is already obtained. 537 * @wx: pointer to hardware structure 538 * @offset: offset of word in the EEPROM to read 539 * @data: word read from the EEPROM 540 * 541 * Reads a 16 bit word from the EEPROM using the hostif. 542 **/ 543 static int wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data) 544 { 545 struct wx_hic_read_shadow_ram buffer; 546 int status; 547 548 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 549 buffer.hdr.req.buf_lenh = 0; 550 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 551 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 552 553 /* convert offset from words to bytes */ 554 buffer.address = (__force u32)cpu_to_be32(offset * 2); 555 /* one word */ 556 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 557 558 status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer), 559 WX_HI_COMMAND_TIMEOUT, false); 560 561 if (status != 0) 562 return status; 563 564 if (!test_bit(WX_FLAG_SWFW_RING, wx->flags)) 565 *data = (u16)rd32a(wx, WX_MNG_MBOX, FW_NVM_DATA_OFFSET); 566 else 567 *data = (u16)rd32a(wx, WX_FW2SW_MBOX, FW_NVM_DATA_OFFSET); 568 569 return status; 570 } 571 572 /** 573 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd 574 * @wx: pointer to hardware structure 575 * @offset: offset of word in the EEPROM to read 576 * @data: word read from the EEPROM 577 * 578 * Reads a 16 bit word from the EEPROM using the hostif. 579 **/ 580 int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data) 581 { 582 int status = 0; 583 584 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 585 if (status == 0) { 586 status = wx_read_ee_hostif_data(wx, offset, data); 587 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 588 } 589 590 return status; 591 } 592 EXPORT_SYMBOL(wx_read_ee_hostif); 593 594 /** 595 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif 596 * @wx: pointer to hardware structure 597 * @offset: offset of word in the EEPROM to read 598 * @words: number of words 599 * @data: word(s) read from the EEPROM 600 * 601 * Reads a 16 bit word(s) from the EEPROM using the hostif. 602 **/ 603 int wx_read_ee_hostif_buffer(struct wx *wx, 604 u16 offset, u16 words, u16 *data) 605 { 606 struct wx_hic_read_shadow_ram buffer; 607 u32 current_word = 0; 608 u16 words_to_read; 609 u32 value = 0; 610 int status; 611 u32 mbox; 612 u32 i; 613 614 /* Take semaphore for the entire operation. */ 615 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 616 if (status != 0) 617 return status; 618 619 while (words) { 620 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 621 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 622 else 623 words_to_read = words; 624 625 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 626 buffer.hdr.req.buf_lenh = 0; 627 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 628 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 629 630 /* convert offset from words to bytes */ 631 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2); 632 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 633 634 status = wx_host_interface_command(wx, (u32 *)&buffer, 635 sizeof(buffer), 636 WX_HI_COMMAND_TIMEOUT, 637 false); 638 639 if (status != 0) { 640 wx_err(wx, "Host interface command failed\n"); 641 goto out; 642 } 643 644 if (!test_bit(WX_FLAG_SWFW_RING, wx->flags)) 645 mbox = WX_MNG_MBOX; 646 else 647 mbox = WX_FW2SW_MBOX; 648 for (i = 0; i < words_to_read; i++) { 649 u32 reg = mbox + (FW_NVM_DATA_OFFSET << 2) + 2 * i; 650 651 value = rd32(wx, reg); 652 data[current_word] = (u16)(value & 0xffff); 653 current_word++; 654 i++; 655 if (i < words_to_read) { 656 value >>= 16; 657 data[current_word] = (u16)(value & 0xffff); 658 current_word++; 659 } 660 } 661 words -= words_to_read; 662 } 663 664 out: 665 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 666 return status; 667 } 668 EXPORT_SYMBOL(wx_read_ee_hostif_buffer); 669 670 /** 671 * wx_init_eeprom_params - Initialize EEPROM params 672 * @wx: pointer to hardware structure 673 * 674 * Initializes the EEPROM parameters wx_eeprom_info within the 675 * wx_hw struct in order to set up EEPROM access. 676 **/ 677 void wx_init_eeprom_params(struct wx *wx) 678 { 679 struct wx_eeprom_info *eeprom = &wx->eeprom; 680 u16 eeprom_size; 681 u16 data = 0x80; 682 683 if (eeprom->type == wx_eeprom_uninitialized) { 684 eeprom->semaphore_delay = 10; 685 eeprom->type = wx_eeprom_none; 686 687 if (!(rd32(wx, WX_SPI_STATUS) & 688 WX_SPI_STATUS_FLASH_BYPASS)) { 689 eeprom->type = wx_flash; 690 691 eeprom_size = 4096; 692 eeprom->word_size = eeprom_size >> 1; 693 694 wx_dbg(wx, "Eeprom params: type = %d, size = %d\n", 695 eeprom->type, eeprom->word_size); 696 } 697 } 698 699 switch (wx->mac.type) { 700 case wx_mac_sp: 701 case wx_mac_aml: 702 if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) { 703 wx_err(wx, "NVM Read Error\n"); 704 return; 705 } 706 data = data >> 1; 707 break; 708 default: 709 break; 710 } 711 712 eeprom->sw_region_offset = data; 713 } 714 EXPORT_SYMBOL(wx_init_eeprom_params); 715 716 /** 717 * wx_get_mac_addr - Generic get MAC address 718 * @wx: pointer to hardware structure 719 * @mac_addr: Adapter MAC address 720 * 721 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 722 * A reset of the adapter must be performed prior to calling this function 723 * in order for the MAC address to have been loaded from the EEPROM into RAR0 724 **/ 725 void wx_get_mac_addr(struct wx *wx, u8 *mac_addr) 726 { 727 u32 rar_high; 728 u32 rar_low; 729 u16 i; 730 731 wr32(wx, WX_PSR_MAC_SWC_IDX, 0); 732 rar_high = rd32(wx, WX_PSR_MAC_SWC_AD_H); 733 rar_low = rd32(wx, WX_PSR_MAC_SWC_AD_L); 734 735 for (i = 0; i < 2; i++) 736 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8); 737 738 for (i = 0; i < 4; i++) 739 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8); 740 } 741 EXPORT_SYMBOL(wx_get_mac_addr); 742 743 /** 744 * wx_set_rar - Set Rx address register 745 * @wx: pointer to hardware structure 746 * @index: Receive address register to write 747 * @addr: Address to put into receive address register 748 * @pools: VMDq "set" or "pool" index 749 * @enable_addr: set flag that address is active 750 * 751 * Puts an ethernet address into a receive address register. 752 **/ 753 static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools, 754 u32 enable_addr) 755 { 756 u32 rar_entries = wx->mac.num_rar_entries; 757 u32 rar_low, rar_high; 758 759 /* Make sure we are using a valid rar index range */ 760 if (index >= rar_entries) { 761 wx_err(wx, "RAR index %d is out of range.\n", index); 762 return -EINVAL; 763 } 764 765 /* select the MAC address */ 766 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 767 768 /* setup VMDq pool mapping */ 769 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF); 770 771 switch (wx->mac.type) { 772 case wx_mac_sp: 773 case wx_mac_aml: 774 wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32); 775 break; 776 default: 777 break; 778 } 779 780 /* HW expects these in little endian so we reverse the byte 781 * order from network order (big endian) to little endian 782 * 783 * Some parts put the VMDq setting in the extra RAH bits, 784 * so save everything except the lower 16 bits that hold part 785 * of the address and the address valid bit. 786 */ 787 rar_low = ((u32)addr[5] | 788 ((u32)addr[4] << 8) | 789 ((u32)addr[3] << 16) | 790 ((u32)addr[2] << 24)); 791 rar_high = ((u32)addr[1] | 792 ((u32)addr[0] << 8)); 793 if (enable_addr != 0) 794 rar_high |= WX_PSR_MAC_SWC_AD_H_AV; 795 796 wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low); 797 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 798 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 799 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 800 WX_PSR_MAC_SWC_AD_H_AV), 801 rar_high); 802 803 return 0; 804 } 805 806 /** 807 * wx_clear_rar - Remove Rx address register 808 * @wx: pointer to hardware structure 809 * @index: Receive address register to write 810 * 811 * Clears an ethernet address from a receive address register. 812 **/ 813 static int wx_clear_rar(struct wx *wx, u32 index) 814 { 815 u32 rar_entries = wx->mac.num_rar_entries; 816 817 /* Make sure we are using a valid rar index range */ 818 if (index >= rar_entries) { 819 wx_err(wx, "RAR index %d is out of range.\n", index); 820 return -EINVAL; 821 } 822 823 /* Some parts put the VMDq setting in the extra RAH bits, 824 * so save everything except the lower 16 bits that hold part 825 * of the address and the address valid bit. 826 */ 827 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 828 829 wr32(wx, WX_PSR_MAC_SWC_VM_L, 0); 830 wr32(wx, WX_PSR_MAC_SWC_VM_H, 0); 831 832 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 833 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 834 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 835 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 836 WX_PSR_MAC_SWC_AD_H_AV), 837 0); 838 839 return 0; 840 } 841 842 /** 843 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address 844 * @wx: pointer to hardware struct 845 * @rar: receive address register index to disassociate 846 * @vmdq: VMDq pool index to remove from the rar 847 **/ 848 static int wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq) 849 { 850 u32 rar_entries = wx->mac.num_rar_entries; 851 u32 mpsar_lo, mpsar_hi; 852 853 /* Make sure we are using a valid rar index range */ 854 if (rar >= rar_entries) { 855 wx_err(wx, "RAR index %d is out of range.\n", rar); 856 return -EINVAL; 857 } 858 859 wr32(wx, WX_PSR_MAC_SWC_IDX, rar); 860 mpsar_lo = rd32(wx, WX_PSR_MAC_SWC_VM_L); 861 mpsar_hi = rd32(wx, WX_PSR_MAC_SWC_VM_H); 862 863 if (!mpsar_lo && !mpsar_hi) 864 return 0; 865 866 /* was that the last pool using this rar? */ 867 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 868 wx_clear_rar(wx, rar); 869 870 return 0; 871 } 872 873 /** 874 * wx_init_uta_tables - Initialize the Unicast Table Array 875 * @wx: pointer to hardware structure 876 **/ 877 static void wx_init_uta_tables(struct wx *wx) 878 { 879 int i; 880 881 wx_dbg(wx, " Clearing UTA\n"); 882 883 for (i = 0; i < 128; i++) 884 wr32(wx, WX_PSR_UC_TBL(i), 0); 885 } 886 887 /** 888 * wx_init_rx_addrs - Initializes receive address filters. 889 * @wx: pointer to hardware structure 890 * 891 * Places the MAC address in receive address register 0 and clears the rest 892 * of the receive address registers. Clears the multicast table. Assumes 893 * the receiver is in reset when the routine is called. 894 **/ 895 void wx_init_rx_addrs(struct wx *wx) 896 { 897 u32 rar_entries = wx->mac.num_rar_entries; 898 u32 psrctl; 899 int i; 900 901 /* If the current mac address is valid, assume it is a software override 902 * to the permanent address. 903 * Otherwise, use the permanent address from the eeprom. 904 */ 905 if (!is_valid_ether_addr(wx->mac.addr)) { 906 /* Get the MAC address from the RAR0 for later reference */ 907 wx_get_mac_addr(wx, wx->mac.addr); 908 wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr); 909 } else { 910 /* Setup the receive address. */ 911 wx_dbg(wx, "Overriding MAC Address in RAR[0]\n"); 912 wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr); 913 914 wx_set_rar(wx, 0, wx->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV); 915 916 switch (wx->mac.type) { 917 case wx_mac_sp: 918 case wx_mac_aml: 919 /* clear VMDq pool/queue selection for RAR 0 */ 920 wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL); 921 break; 922 default: 923 break; 924 } 925 } 926 927 /* Zero out the other receive addresses. */ 928 wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1); 929 for (i = 1; i < rar_entries; i++) { 930 wr32(wx, WX_PSR_MAC_SWC_IDX, i); 931 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 932 wr32(wx, WX_PSR_MAC_SWC_AD_H, 0); 933 } 934 935 /* Clear the MTA */ 936 wx->addr_ctrl.mta_in_use = 0; 937 psrctl = rd32(wx, WX_PSR_CTL); 938 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 939 psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT; 940 wr32(wx, WX_PSR_CTL, psrctl); 941 wx_dbg(wx, " Clearing MTA\n"); 942 for (i = 0; i < wx->mac.mcft_size; i++) 943 wr32(wx, WX_PSR_MC_TBL(i), 0); 944 945 wx_init_uta_tables(wx); 946 } 947 EXPORT_SYMBOL(wx_init_rx_addrs); 948 949 static void wx_sync_mac_table(struct wx *wx) 950 { 951 int i; 952 953 for (i = 0; i < wx->mac.num_rar_entries; i++) { 954 if (wx->mac_table[i].state & WX_MAC_STATE_MODIFIED) { 955 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 956 wx_set_rar(wx, i, 957 wx->mac_table[i].addr, 958 wx->mac_table[i].pools, 959 WX_PSR_MAC_SWC_AD_H_AV); 960 } else { 961 wx_clear_rar(wx, i); 962 } 963 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 964 } 965 } 966 } 967 968 static void wx_full_sync_mac_table(struct wx *wx) 969 { 970 int i; 971 972 for (i = 0; i < wx->mac.num_rar_entries; i++) { 973 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 974 wx_set_rar(wx, i, 975 wx->mac_table[i].addr, 976 wx->mac_table[i].pools, 977 WX_PSR_MAC_SWC_AD_H_AV); 978 } else { 979 wx_clear_rar(wx, i); 980 } 981 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 982 } 983 } 984 985 /* this function destroys the first RAR entry */ 986 void wx_mac_set_default_filter(struct wx *wx, u8 *addr) 987 { 988 memcpy(&wx->mac_table[0].addr, addr, ETH_ALEN); 989 wx->mac_table[0].pools = BIT(VMDQ_P(0)); 990 wx->mac_table[0].state = (WX_MAC_STATE_DEFAULT | WX_MAC_STATE_IN_USE); 991 wx_set_rar(wx, 0, wx->mac_table[0].addr, 992 wx->mac_table[0].pools, 993 WX_PSR_MAC_SWC_AD_H_AV); 994 } 995 EXPORT_SYMBOL(wx_mac_set_default_filter); 996 997 void wx_flush_sw_mac_table(struct wx *wx) 998 { 999 u32 i; 1000 1001 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1002 if (!(wx->mac_table[i].state & WX_MAC_STATE_IN_USE)) 1003 continue; 1004 1005 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 1006 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 1007 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 1008 wx->mac_table[i].pools = 0; 1009 } 1010 wx_sync_mac_table(wx); 1011 } 1012 EXPORT_SYMBOL(wx_flush_sw_mac_table); 1013 1014 int wx_add_mac_filter(struct wx *wx, u8 *addr, u16 pool) 1015 { 1016 u32 i; 1017 1018 if (is_zero_ether_addr(addr)) 1019 return -EINVAL; 1020 1021 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1022 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 1023 if (ether_addr_equal(addr, wx->mac_table[i].addr)) { 1024 if (wx->mac_table[i].pools != (1ULL << pool)) { 1025 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 1026 wx->mac_table[i].pools |= (1ULL << pool); 1027 wx_sync_mac_table(wx); 1028 return i; 1029 } 1030 } 1031 } 1032 1033 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) 1034 continue; 1035 wx->mac_table[i].state |= (WX_MAC_STATE_MODIFIED | 1036 WX_MAC_STATE_IN_USE); 1037 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 1038 wx->mac_table[i].pools |= (1ULL << pool); 1039 wx_sync_mac_table(wx); 1040 return i; 1041 } 1042 return -ENOMEM; 1043 } 1044 1045 int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool) 1046 { 1047 u32 i; 1048 1049 if (is_zero_ether_addr(addr)) 1050 return -EINVAL; 1051 1052 /* search table for addr, if found, set to 0 and sync */ 1053 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1054 if (!ether_addr_equal(addr, wx->mac_table[i].addr)) 1055 continue; 1056 1057 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 1058 wx->mac_table[i].pools &= ~(1ULL << pool); 1059 if (!wx->mac_table[i].pools) { 1060 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 1061 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 1062 } 1063 wx_sync_mac_table(wx); 1064 return 0; 1065 } 1066 return -ENOMEM; 1067 } 1068 1069 static int wx_available_rars(struct wx *wx) 1070 { 1071 u32 i, count = 0; 1072 1073 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1074 if (wx->mac_table[i].state == 0) 1075 count++; 1076 } 1077 1078 return count; 1079 } 1080 1081 /** 1082 * wx_write_uc_addr_list - write unicast addresses to RAR table 1083 * @netdev: network interface device structure 1084 * @pool: index for mac table 1085 * 1086 * Writes unicast address list to the RAR table. 1087 * Returns: -ENOMEM on failure/insufficient address space 1088 * 0 on no addresses written 1089 * X on writing X addresses to the RAR table 1090 **/ 1091 static int wx_write_uc_addr_list(struct net_device *netdev, int pool) 1092 { 1093 struct wx *wx = netdev_priv(netdev); 1094 int count = 0; 1095 1096 /* return ENOMEM indicating insufficient memory for addresses */ 1097 if (netdev_uc_count(netdev) > wx_available_rars(wx)) 1098 return -ENOMEM; 1099 1100 if (!netdev_uc_empty(netdev)) { 1101 struct netdev_hw_addr *ha; 1102 1103 netdev_for_each_uc_addr(ha, netdev) { 1104 wx_del_mac_filter(wx, ha->addr, pool); 1105 wx_add_mac_filter(wx, ha->addr, pool); 1106 count++; 1107 } 1108 } 1109 return count; 1110 } 1111 1112 /** 1113 * wx_mta_vector - Determines bit-vector in multicast table to set 1114 * @wx: pointer to private structure 1115 * @mc_addr: the multicast address 1116 * 1117 * Extracts the 12 bits, from a multicast address, to determine which 1118 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1119 * incoming rx multicast addresses, to determine the bit-vector to check in 1120 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1121 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1122 * to mc_filter_type. 1123 **/ 1124 static u32 wx_mta_vector(struct wx *wx, u8 *mc_addr) 1125 { 1126 u32 vector = 0; 1127 1128 switch (wx->mac.mc_filter_type) { 1129 case 0: /* use bits [47:36] of the address */ 1130 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1131 break; 1132 case 1: /* use bits [46:35] of the address */ 1133 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1134 break; 1135 case 2: /* use bits [45:34] of the address */ 1136 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1137 break; 1138 case 3: /* use bits [43:32] of the address */ 1139 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1140 break; 1141 default: /* Invalid mc_filter_type */ 1142 wx_err(wx, "MC filter type param set incorrectly\n"); 1143 break; 1144 } 1145 1146 /* vector can only be 12-bits or boundary will be exceeded */ 1147 vector &= 0xFFF; 1148 return vector; 1149 } 1150 1151 /** 1152 * wx_set_mta - Set bit-vector in multicast table 1153 * @wx: pointer to private structure 1154 * @mc_addr: Multicast address 1155 * 1156 * Sets the bit-vector in the multicast table. 1157 **/ 1158 static void wx_set_mta(struct wx *wx, u8 *mc_addr) 1159 { 1160 u32 vector, vector_bit, vector_reg; 1161 1162 wx->addr_ctrl.mta_in_use++; 1163 1164 vector = wx_mta_vector(wx, mc_addr); 1165 wx_dbg(wx, " bit-vector = 0x%03X\n", vector); 1166 1167 /* The MTA is a register array of 128 32-bit registers. It is treated 1168 * like an array of 4096 bits. We want to set bit 1169 * BitArray[vector_value]. So we figure out what register the bit is 1170 * in, read it, OR in the new bit, then write back the new value. The 1171 * register is determined by the upper 7 bits of the vector value and 1172 * the bit within that register are determined by the lower 5 bits of 1173 * the value. 1174 */ 1175 vector_reg = (vector >> 5) & 0x7F; 1176 vector_bit = vector & 0x1F; 1177 wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 1178 } 1179 1180 /** 1181 * wx_update_mc_addr_list - Updates MAC list of multicast addresses 1182 * @wx: pointer to private structure 1183 * @netdev: pointer to net device structure 1184 * 1185 * The given list replaces any existing list. Clears the MC addrs from receive 1186 * address registers and the multicast table. Uses unused receive address 1187 * registers for the first multicast addresses, and hashes the rest into the 1188 * multicast table. 1189 **/ 1190 static void wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev) 1191 { 1192 struct netdev_hw_addr *ha; 1193 u32 i, psrctl; 1194 1195 /* Set the new number of MC addresses that we are being requested to 1196 * use. 1197 */ 1198 wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 1199 wx->addr_ctrl.mta_in_use = 0; 1200 1201 /* Clear mta_shadow */ 1202 wx_dbg(wx, " Clearing MTA\n"); 1203 memset(&wx->mac.mta_shadow, 0, sizeof(wx->mac.mta_shadow)); 1204 1205 /* Update mta_shadow */ 1206 netdev_for_each_mc_addr(ha, netdev) { 1207 wx_dbg(wx, " Adding the multicast addresses:\n"); 1208 wx_set_mta(wx, ha->addr); 1209 } 1210 1211 /* Enable mta */ 1212 for (i = 0; i < wx->mac.mcft_size; i++) 1213 wr32a(wx, WX_PSR_MC_TBL(0), i, 1214 wx->mac.mta_shadow[i]); 1215 1216 if (wx->addr_ctrl.mta_in_use > 0) { 1217 psrctl = rd32(wx, WX_PSR_CTL); 1218 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 1219 psrctl |= WX_PSR_CTL_MFE | 1220 (wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT); 1221 wr32(wx, WX_PSR_CTL, psrctl); 1222 } 1223 1224 wx_dbg(wx, "Update mc addr list Complete\n"); 1225 } 1226 1227 static void wx_restore_vf_multicasts(struct wx *wx) 1228 { 1229 u32 i, j, vector_bit, vector_reg; 1230 struct vf_data_storage *vfinfo; 1231 1232 for (i = 0; i < wx->num_vfs; i++) { 1233 u32 vmolr = rd32(wx, WX_PSR_VM_L2CTL(i)); 1234 1235 vfinfo = &wx->vfinfo[i]; 1236 for (j = 0; j < vfinfo->num_vf_mc_hashes; j++) { 1237 wx->addr_ctrl.mta_in_use++; 1238 vector_reg = WX_PSR_MC_TBL_REG(vfinfo->vf_mc_hashes[j]); 1239 vector_bit = WX_PSR_MC_TBL_BIT(vfinfo->vf_mc_hashes[j]); 1240 wr32m(wx, WX_PSR_MC_TBL(vector_reg), 1241 BIT(vector_bit), BIT(vector_bit)); 1242 /* errata 5: maintain a copy of the reg table conf */ 1243 wx->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 1244 } 1245 if (vfinfo->num_vf_mc_hashes) 1246 vmolr |= WX_PSR_VM_L2CTL_ROMPE; 1247 else 1248 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE; 1249 wr32(wx, WX_PSR_VM_L2CTL(i), vmolr); 1250 } 1251 1252 /* Restore any VF macvlans */ 1253 wx_full_sync_mac_table(wx); 1254 } 1255 1256 /** 1257 * wx_write_mc_addr_list - write multicast addresses to MTA 1258 * @netdev: network interface device structure 1259 * 1260 * Writes multicast address list to the MTA hash table. 1261 * Returns: 0 on no addresses written 1262 * X on writing X addresses to MTA 1263 **/ 1264 static int wx_write_mc_addr_list(struct net_device *netdev) 1265 { 1266 struct wx *wx = netdev_priv(netdev); 1267 1268 if (!netif_running(netdev)) 1269 return 0; 1270 1271 wx_update_mc_addr_list(wx, netdev); 1272 1273 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1274 wx_restore_vf_multicasts(wx); 1275 1276 return netdev_mc_count(netdev); 1277 } 1278 1279 /** 1280 * wx_set_mac - Change the Ethernet Address of the NIC 1281 * @netdev: network interface device structure 1282 * @p: pointer to an address structure 1283 * 1284 * Returns 0 on success, negative on failure 1285 **/ 1286 int wx_set_mac(struct net_device *netdev, void *p) 1287 { 1288 struct wx *wx = netdev_priv(netdev); 1289 struct sockaddr *addr = p; 1290 int retval; 1291 1292 retval = eth_prepare_mac_addr_change(netdev, addr); 1293 if (retval) 1294 return retval; 1295 1296 wx_del_mac_filter(wx, wx->mac.addr, VMDQ_P(0)); 1297 eth_hw_addr_set(netdev, addr->sa_data); 1298 memcpy(wx->mac.addr, addr->sa_data, netdev->addr_len); 1299 1300 wx_mac_set_default_filter(wx, wx->mac.addr); 1301 1302 return 0; 1303 } 1304 EXPORT_SYMBOL(wx_set_mac); 1305 1306 void wx_disable_rx(struct wx *wx) 1307 { 1308 u32 pfdtxgswc; 1309 u32 rxctrl; 1310 1311 rxctrl = rd32(wx, WX_RDB_PB_CTL); 1312 if (rxctrl & WX_RDB_PB_CTL_RXEN) { 1313 pfdtxgswc = rd32(wx, WX_PSR_CTL); 1314 if (pfdtxgswc & WX_PSR_CTL_SW_EN) { 1315 pfdtxgswc &= ~WX_PSR_CTL_SW_EN; 1316 wr32(wx, WX_PSR_CTL, pfdtxgswc); 1317 wx->mac.set_lben = true; 1318 } else { 1319 wx->mac.set_lben = false; 1320 } 1321 rxctrl &= ~WX_RDB_PB_CTL_RXEN; 1322 wr32(wx, WX_RDB_PB_CTL, rxctrl); 1323 1324 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 1325 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 1326 /* disable mac receiver */ 1327 wr32m(wx, WX_MAC_RX_CFG, 1328 WX_MAC_RX_CFG_RE, 0); 1329 } 1330 } 1331 } 1332 EXPORT_SYMBOL(wx_disable_rx); 1333 1334 static void wx_enable_rx(struct wx *wx) 1335 { 1336 u32 psrctl; 1337 1338 /* enable mac receiver */ 1339 wr32m(wx, WX_MAC_RX_CFG, 1340 WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 1341 1342 wr32m(wx, WX_RDB_PB_CTL, 1343 WX_RDB_PB_CTL_RXEN, WX_RDB_PB_CTL_RXEN); 1344 1345 if (wx->mac.set_lben) { 1346 psrctl = rd32(wx, WX_PSR_CTL); 1347 psrctl |= WX_PSR_CTL_SW_EN; 1348 wr32(wx, WX_PSR_CTL, psrctl); 1349 wx->mac.set_lben = false; 1350 } 1351 } 1352 1353 /** 1354 * wx_set_rxpba - Initialize Rx packet buffer 1355 * @wx: pointer to private structure 1356 **/ 1357 static void wx_set_rxpba(struct wx *wx) 1358 { 1359 u32 rxpktsize, txpktsize, txpbthresh; 1360 u32 pbsize = wx->mac.rx_pb_size; 1361 1362 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 1363 if (test_bit(WX_FLAG_FDIR_HASH, wx->flags) || 1364 test_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 1365 pbsize -= 64; /* Default 64KB */ 1366 } 1367 1368 rxpktsize = pbsize << WX_RDB_PB_SZ_SHIFT; 1369 wr32(wx, WX_RDB_PB_SZ(0), rxpktsize); 1370 1371 /* Only support an equally distributed Tx packet buffer strategy. */ 1372 txpktsize = wx->mac.tx_pb_size; 1373 txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX; 1374 wr32(wx, WX_TDB_PB_SZ(0), txpktsize); 1375 wr32(wx, WX_TDM_PB_THRE(0), txpbthresh); 1376 } 1377 1378 #define WX_ETH_FRAMING 20 1379 1380 /** 1381 * wx_hpbthresh - calculate high water mark for flow control 1382 * 1383 * @wx: board private structure to calculate for 1384 **/ 1385 static int wx_hpbthresh(struct wx *wx) 1386 { 1387 struct net_device *dev = wx->netdev; 1388 int link, tc, kb, marker; 1389 u32 dv_id, rx_pba; 1390 1391 /* Calculate max LAN frame size */ 1392 link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + WX_ETH_FRAMING; 1393 tc = link; 1394 1395 /* Calculate delay value for device */ 1396 dv_id = WX_DV(link, tc); 1397 1398 /* Loopback switch introduces additional latency */ 1399 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1400 dv_id += WX_B2BT(tc); 1401 1402 /* Delay value is calculated in bit times convert to KB */ 1403 kb = WX_BT2KB(dv_id); 1404 rx_pba = rd32(wx, WX_RDB_PB_SZ(0)) >> WX_RDB_PB_SZ_SHIFT; 1405 1406 marker = rx_pba - kb; 1407 1408 /* It is possible that the packet buffer is not large enough 1409 * to provide required headroom. In this case throw an error 1410 * to user and a do the best we can. 1411 */ 1412 if (marker < 0) { 1413 dev_warn(&wx->pdev->dev, 1414 "Packet Buffer can not provide enough headroom to support flow control. Decrease MTU or number of traffic classes\n"); 1415 marker = tc + 1; 1416 } 1417 1418 return marker; 1419 } 1420 1421 /** 1422 * wx_lpbthresh - calculate low water mark for flow control 1423 * 1424 * @wx: board private structure to calculate for 1425 **/ 1426 static int wx_lpbthresh(struct wx *wx) 1427 { 1428 struct net_device *dev = wx->netdev; 1429 u32 dv_id; 1430 int tc; 1431 1432 /* Calculate max LAN frame size */ 1433 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 1434 1435 /* Calculate delay value for device */ 1436 dv_id = WX_LOW_DV(tc); 1437 1438 /* Delay value is calculated in bit times convert to KB */ 1439 return WX_BT2KB(dv_id); 1440 } 1441 1442 /** 1443 * wx_pbthresh_setup - calculate and setup high low water marks 1444 * 1445 * @wx: board private structure to calculate for 1446 **/ 1447 static void wx_pbthresh_setup(struct wx *wx) 1448 { 1449 wx->fc.high_water = wx_hpbthresh(wx); 1450 wx->fc.low_water = wx_lpbthresh(wx); 1451 1452 /* Low water marks must not be larger than high water marks */ 1453 if (wx->fc.low_water > wx->fc.high_water) 1454 wx->fc.low_water = 0; 1455 } 1456 1457 static void wx_set_ethertype_anti_spoofing(struct wx *wx, bool enable, int vf) 1458 { 1459 u32 pfvfspoof, reg_offset, vf_shift; 1460 1461 vf_shift = WX_VF_IND_SHIFT(vf); 1462 reg_offset = WX_VF_REG_OFFSET(vf); 1463 1464 pfvfspoof = rd32(wx, WX_TDM_ETYPE_AS(reg_offset)); 1465 if (enable) 1466 pfvfspoof |= BIT(vf_shift); 1467 else 1468 pfvfspoof &= ~BIT(vf_shift); 1469 wr32(wx, WX_TDM_ETYPE_AS(reg_offset), pfvfspoof); 1470 } 1471 1472 int wx_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting) 1473 { 1474 u32 index = WX_VF_REG_OFFSET(vf), vf_bit = WX_VF_IND_SHIFT(vf); 1475 struct wx *wx = netdev_priv(netdev); 1476 u32 regval; 1477 1478 if (vf >= wx->num_vfs) 1479 return -EINVAL; 1480 1481 wx->vfinfo[vf].spoofchk_enabled = setting; 1482 1483 regval = (setting << vf_bit); 1484 wr32m(wx, WX_TDM_MAC_AS(index), regval | BIT(vf_bit), regval); 1485 1486 if (wx->vfinfo[vf].vlan_count) 1487 wr32m(wx, WX_TDM_VLAN_AS(index), regval | BIT(vf_bit), regval); 1488 1489 return 0; 1490 } 1491 1492 static void wx_configure_virtualization(struct wx *wx) 1493 { 1494 u16 pool = wx->num_rx_pools; 1495 u32 reg_offset, vf_shift; 1496 u32 i; 1497 1498 if (!test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1499 return; 1500 1501 wr32m(wx, WX_PSR_VM_CTL, 1502 WX_PSR_VM_CTL_POOL_MASK | WX_PSR_VM_CTL_REPLEN, 1503 FIELD_PREP(WX_PSR_VM_CTL_POOL_MASK, VMDQ_P(0)) | 1504 WX_PSR_VM_CTL_REPLEN); 1505 while (pool--) 1506 wr32m(wx, WX_PSR_VM_L2CTL(pool), 1507 WX_PSR_VM_L2CTL_AUPE, WX_PSR_VM_L2CTL_AUPE); 1508 1509 if (wx->mac.type == wx_mac_em) { 1510 vf_shift = BIT(VMDQ_P(0)); 1511 /* Enable only the PF pools for Tx/Rx */ 1512 wr32(wx, WX_RDM_VF_RE(0), vf_shift); 1513 wr32(wx, WX_TDM_VF_TE(0), vf_shift); 1514 } else { 1515 vf_shift = WX_VF_IND_SHIFT(VMDQ_P(0)); 1516 reg_offset = WX_VF_REG_OFFSET(VMDQ_P(0)); 1517 1518 /* Enable only the PF pools for Tx/Rx */ 1519 wr32(wx, WX_RDM_VF_RE(reg_offset), GENMASK(31, vf_shift)); 1520 wr32(wx, WX_RDM_VF_RE(reg_offset ^ 1), reg_offset - 1); 1521 wr32(wx, WX_TDM_VF_TE(reg_offset), GENMASK(31, vf_shift)); 1522 wr32(wx, WX_TDM_VF_TE(reg_offset ^ 1), reg_offset - 1); 1523 } 1524 1525 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1526 clear_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1527 1528 for (i = 0; i < wx->num_vfs; i++) { 1529 if (!wx->vfinfo[i].spoofchk_enabled) 1530 wx_set_vf_spoofchk(wx->netdev, i, false); 1531 /* enable ethertype anti spoofing if hw supports it */ 1532 wx_set_ethertype_anti_spoofing(wx, true, i); 1533 } 1534 } 1535 1536 static void wx_configure_port(struct wx *wx) 1537 { 1538 u32 value, i; 1539 1540 if (wx->mac.type == wx_mac_em) { 1541 value = (wx->num_vfs == 0) ? 1542 WX_CFG_PORT_CTL_NUM_VT_NONE : 1543 WX_CFG_PORT_CTL_NUM_VT_8; 1544 } else { 1545 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) { 1546 if (wx->ring_feature[RING_F_RSS].indices == 4) 1547 value = WX_CFG_PORT_CTL_NUM_VT_32; 1548 else 1549 value = WX_CFG_PORT_CTL_NUM_VT_64; 1550 } else { 1551 value = 0; 1552 } 1553 } 1554 1555 value |= WX_CFG_PORT_CTL_D_VLAN | WX_CFG_PORT_CTL_QINQ; 1556 wr32m(wx, WX_CFG_PORT_CTL, 1557 WX_CFG_PORT_CTL_NUM_VT_MASK | 1558 WX_CFG_PORT_CTL_D_VLAN | 1559 WX_CFG_PORT_CTL_QINQ, 1560 value); 1561 1562 wr32(wx, WX_CFG_TAG_TPID(0), 1563 ETH_P_8021Q | ETH_P_8021AD << 16); 1564 wx->tpid[0] = ETH_P_8021Q; 1565 wx->tpid[1] = ETH_P_8021AD; 1566 for (i = 1; i < 4; i++) 1567 wr32(wx, WX_CFG_TAG_TPID(i), 1568 ETH_P_8021Q | ETH_P_8021Q << 16); 1569 for (i = 2; i < 8; i++) 1570 wx->tpid[i] = ETH_P_8021Q; 1571 } 1572 1573 /** 1574 * wx_disable_sec_rx_path - Stops the receive data path 1575 * @wx: pointer to private structure 1576 * 1577 * Stops the receive data path and waits for the HW to internally empty 1578 * the Rx security block 1579 **/ 1580 int wx_disable_sec_rx_path(struct wx *wx) 1581 { 1582 u32 secrx; 1583 1584 wr32m(wx, WX_RSC_CTL, 1585 WX_RSC_CTL_RX_DIS, WX_RSC_CTL_RX_DIS); 1586 1587 return read_poll_timeout(rd32, secrx, secrx & WX_RSC_ST_RSEC_RDY, 1588 1000, 40000, false, wx, WX_RSC_ST); 1589 } 1590 EXPORT_SYMBOL(wx_disable_sec_rx_path); 1591 1592 /** 1593 * wx_enable_sec_rx_path - Enables the receive data path 1594 * @wx: pointer to private structure 1595 * 1596 * Enables the receive data path. 1597 **/ 1598 void wx_enable_sec_rx_path(struct wx *wx) 1599 { 1600 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_RX_DIS, 0); 1601 WX_WRITE_FLUSH(wx); 1602 } 1603 EXPORT_SYMBOL(wx_enable_sec_rx_path); 1604 1605 static void wx_vlan_strip_control(struct wx *wx, bool enable) 1606 { 1607 int i, j; 1608 1609 for (i = 0; i < wx->num_rx_queues; i++) { 1610 struct wx_ring *ring = wx->rx_ring[i]; 1611 1612 j = ring->reg_idx; 1613 wr32m(wx, WX_PX_RR_CFG(j), WX_PX_RR_CFG_VLAN, 1614 enable ? WX_PX_RR_CFG_VLAN : 0); 1615 } 1616 } 1617 1618 static void wx_vlan_promisc_enable(struct wx *wx) 1619 { 1620 u32 vlnctrl, i, vind, bits, reg_idx; 1621 1622 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1623 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) { 1624 /* we need to keep the VLAN filter on in SRIOV */ 1625 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1626 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1627 } else { 1628 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1629 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1630 return; 1631 } 1632 /* We are already in VLAN promisc, nothing to do */ 1633 if (test_bit(WX_FLAG_VLAN_PROMISC, wx->flags)) 1634 return; 1635 /* Set flag so we don't redo unnecessary work */ 1636 set_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1637 /* Add PF to all active pools */ 1638 for (i = WX_PSR_VLAN_SWC_ENTRIES; --i;) { 1639 wr32(wx, WX_PSR_VLAN_SWC_IDX, i); 1640 vind = WX_VF_IND_SHIFT(VMDQ_P(0)); 1641 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0)); 1642 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx)); 1643 bits |= BIT(vind); 1644 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits); 1645 } 1646 /* Set all bits in the VLAN filter table array */ 1647 for (i = 0; i < wx->mac.vft_size; i++) 1648 wr32(wx, WX_PSR_VLAN_TBL(i), U32_MAX); 1649 } 1650 1651 static void wx_scrub_vfta(struct wx *wx) 1652 { 1653 u32 i, vid, bits, vfta, vind, vlvf, reg_idx; 1654 1655 for (i = WX_PSR_VLAN_SWC_ENTRIES; --i;) { 1656 wr32(wx, WX_PSR_VLAN_SWC_IDX, i); 1657 vlvf = rd32(wx, WX_PSR_VLAN_SWC_IDX); 1658 /* pull VLAN ID from VLVF */ 1659 vid = vlvf & ~WX_PSR_VLAN_SWC_VIEN; 1660 if (vlvf & WX_PSR_VLAN_SWC_VIEN) { 1661 /* if PF is part of this then continue */ 1662 if (test_bit(vid, wx->active_vlans)) 1663 continue; 1664 } 1665 /* remove PF from the pool */ 1666 vind = WX_VF_IND_SHIFT(VMDQ_P(0)); 1667 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0)); 1668 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx)); 1669 bits &= ~BIT(vind); 1670 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits); 1671 } 1672 /* extract values from vft_shadow and write back to VFTA */ 1673 for (i = 0; i < wx->mac.vft_size; i++) { 1674 vfta = wx->mac.vft_shadow[i]; 1675 wr32(wx, WX_PSR_VLAN_TBL(i), vfta); 1676 } 1677 } 1678 1679 static void wx_vlan_promisc_disable(struct wx *wx) 1680 { 1681 u32 vlnctrl; 1682 1683 /* configure vlan filtering */ 1684 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1685 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1686 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1687 /* We are not in VLAN promisc, nothing to do */ 1688 if (!test_bit(WX_FLAG_VLAN_PROMISC, wx->flags)) 1689 return; 1690 /* Set flag so we don't redo unnecessary work */ 1691 clear_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1692 wx_scrub_vfta(wx); 1693 } 1694 1695 void wx_set_rx_mode(struct net_device *netdev) 1696 { 1697 struct wx *wx = netdev_priv(netdev); 1698 netdev_features_t features; 1699 u32 fctrl, vmolr, vlnctrl; 1700 int count; 1701 1702 features = netdev->features; 1703 1704 /* Check for Promiscuous and All Multicast modes */ 1705 fctrl = rd32(wx, WX_PSR_CTL); 1706 fctrl &= ~(WX_PSR_CTL_UPE | WX_PSR_CTL_MPE); 1707 vmolr = rd32(wx, WX_PSR_VM_L2CTL(VMDQ_P(0))); 1708 vmolr &= ~(WX_PSR_VM_L2CTL_UPE | 1709 WX_PSR_VM_L2CTL_MPE | 1710 WX_PSR_VM_L2CTL_ROPE | 1711 WX_PSR_VM_L2CTL_ROMPE); 1712 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1713 vlnctrl &= ~(WX_PSR_VLAN_CTL_VFE | WX_PSR_VLAN_CTL_CFIEN); 1714 1715 /* set all bits that we expect to always be set */ 1716 fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE; 1717 vmolr |= WX_PSR_VM_L2CTL_BAM | 1718 WX_PSR_VM_L2CTL_AUPE | 1719 WX_PSR_VM_L2CTL_VACC; 1720 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1721 1722 wx->addr_ctrl.user_set_promisc = false; 1723 if (netdev->flags & IFF_PROMISC) { 1724 wx->addr_ctrl.user_set_promisc = true; 1725 fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE; 1726 /* pf don't want packets routing to vf, so clear UPE */ 1727 vmolr |= WX_PSR_VM_L2CTL_MPE; 1728 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags) && 1729 test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1730 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1731 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 1732 } 1733 1734 if (netdev->flags & IFF_ALLMULTI) { 1735 fctrl |= WX_PSR_CTL_MPE; 1736 vmolr |= WX_PSR_VM_L2CTL_MPE; 1737 } 1738 1739 if (netdev->features & NETIF_F_RXALL) { 1740 vmolr |= (WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_MPE); 1741 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1742 /* receive bad packets */ 1743 wr32m(wx, WX_RSC_CTL, 1744 WX_RSC_CTL_SAVE_MAC_ERR, 1745 WX_RSC_CTL_SAVE_MAC_ERR); 1746 } else { 1747 vmolr |= WX_PSR_VM_L2CTL_ROPE | WX_PSR_VM_L2CTL_ROMPE; 1748 } 1749 1750 /* Write addresses to available RAR registers, if there is not 1751 * sufficient space to store all the addresses then enable 1752 * unicast promiscuous mode 1753 */ 1754 count = wx_write_uc_addr_list(netdev, VMDQ_P(0)); 1755 if (count < 0) { 1756 vmolr &= ~WX_PSR_VM_L2CTL_ROPE; 1757 vmolr |= WX_PSR_VM_L2CTL_UPE; 1758 } 1759 1760 /* Write addresses to the MTA, if the attempt fails 1761 * then we should just turn on promiscuous mode so 1762 * that we can at least receive multicast traffic 1763 */ 1764 count = wx_write_mc_addr_list(netdev); 1765 if (count < 0) { 1766 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE; 1767 vmolr |= WX_PSR_VM_L2CTL_MPE; 1768 } 1769 1770 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1771 wr32(wx, WX_PSR_CTL, fctrl); 1772 wr32(wx, WX_PSR_VM_L2CTL(VMDQ_P(0)), vmolr); 1773 1774 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && 1775 (features & NETIF_F_HW_VLAN_STAG_RX)) 1776 wx_vlan_strip_control(wx, true); 1777 else 1778 wx_vlan_strip_control(wx, false); 1779 1780 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1781 wx_vlan_promisc_disable(wx); 1782 else 1783 wx_vlan_promisc_enable(wx); 1784 } 1785 EXPORT_SYMBOL(wx_set_rx_mode); 1786 1787 static void wx_set_rx_buffer_len(struct wx *wx) 1788 { 1789 struct net_device *netdev = wx->netdev; 1790 u32 mhadd, max_frame; 1791 1792 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 1793 /* adjust max frame to be at least the size of a standard frame */ 1794 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 1795 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 1796 1797 mhadd = rd32(wx, WX_PSR_MAX_SZ); 1798 if (max_frame != mhadd) 1799 wr32(wx, WX_PSR_MAX_SZ, max_frame); 1800 } 1801 1802 /** 1803 * wx_change_mtu - Change the Maximum Transfer Unit 1804 * @netdev: network interface device structure 1805 * @new_mtu: new value for maximum frame size 1806 * 1807 * Returns 0 on success, negative on failure 1808 **/ 1809 int wx_change_mtu(struct net_device *netdev, int new_mtu) 1810 { 1811 struct wx *wx = netdev_priv(netdev); 1812 1813 WRITE_ONCE(netdev->mtu, new_mtu); 1814 wx_set_rx_buffer_len(wx); 1815 1816 return 0; 1817 } 1818 EXPORT_SYMBOL(wx_change_mtu); 1819 1820 /* Disable the specified rx queue */ 1821 void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring) 1822 { 1823 u8 reg_idx = ring->reg_idx; 1824 u32 rxdctl; 1825 int ret; 1826 1827 /* write value back with RRCFG.EN bit cleared */ 1828 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1829 WX_PX_RR_CFG_RR_EN, 0); 1830 1831 /* the hardware may take up to 100us to really disable the rx queue */ 1832 ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN), 1833 10, 100, true, wx, WX_PX_RR_CFG(reg_idx)); 1834 1835 if (ret == -ETIMEDOUT) { 1836 /* Just for information */ 1837 wx_err(wx, 1838 "RRCFG.EN on Rx queue %d not cleared within the polling period\n", 1839 reg_idx); 1840 } 1841 } 1842 EXPORT_SYMBOL(wx_disable_rx_queue); 1843 1844 static void wx_enable_rx_queue(struct wx *wx, struct wx_ring *ring) 1845 { 1846 u8 reg_idx = ring->reg_idx; 1847 u32 rxdctl; 1848 int ret; 1849 1850 ret = read_poll_timeout(rd32, rxdctl, rxdctl & WX_PX_RR_CFG_RR_EN, 1851 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx)); 1852 1853 if (ret == -ETIMEDOUT) { 1854 /* Just for information */ 1855 wx_err(wx, 1856 "RRCFG.EN on Rx queue %d not set within the polling period\n", 1857 reg_idx); 1858 } 1859 } 1860 1861 static void wx_configure_srrctl(struct wx *wx, 1862 struct wx_ring *rx_ring) 1863 { 1864 u16 reg_idx = rx_ring->reg_idx; 1865 u32 srrctl; 1866 1867 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1868 srrctl &= ~(WX_PX_RR_CFG_RR_HDR_SZ | 1869 WX_PX_RR_CFG_RR_BUF_SZ | 1870 WX_PX_RR_CFG_SPLIT_MODE); 1871 /* configure header buffer length, needed for RSC */ 1872 srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT; 1873 1874 /* configure the packet buffer length */ 1875 srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT; 1876 1877 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 1878 } 1879 1880 static void wx_configure_tx_ring(struct wx *wx, 1881 struct wx_ring *ring) 1882 { 1883 u32 txdctl = WX_PX_TR_CFG_ENABLE; 1884 u8 reg_idx = ring->reg_idx; 1885 u64 tdba = ring->dma; 1886 int ret; 1887 1888 /* disable queue to avoid issues while updating state */ 1889 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH); 1890 WX_WRITE_FLUSH(wx); 1891 1892 wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32)); 1893 wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba)); 1894 1895 /* reset head and tail pointers */ 1896 wr32(wx, WX_PX_TR_RP(reg_idx), 0); 1897 wr32(wx, WX_PX_TR_WP(reg_idx), 0); 1898 ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx); 1899 1900 if (ring->count < WX_MAX_TXD) 1901 txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT; 1902 txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT; 1903 1904 ring->atr_count = 0; 1905 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && 1906 test_bit(WX_FLAG_FDIR_HASH, wx->flags)) 1907 ring->atr_sample_rate = wx->atr_sample_rate; 1908 else 1909 ring->atr_sample_rate = 0; 1910 1911 /* reinitialize tx_buffer_info */ 1912 memset(ring->tx_buffer_info, 0, 1913 sizeof(struct wx_tx_buffer) * ring->count); 1914 1915 /* enable queue */ 1916 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl); 1917 1918 /* poll to verify queue is enabled */ 1919 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE, 1920 1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx)); 1921 if (ret == -ETIMEDOUT) 1922 wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx); 1923 } 1924 1925 static void wx_configure_rx_ring(struct wx *wx, 1926 struct wx_ring *ring) 1927 { 1928 u16 reg_idx = ring->reg_idx; 1929 union wx_rx_desc *rx_desc; 1930 u64 rdba = ring->dma; 1931 u32 rxdctl; 1932 1933 /* disable queue to avoid issues while updating state */ 1934 rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1935 wx_disable_rx_queue(wx, ring); 1936 1937 wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32)); 1938 wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba)); 1939 1940 if (ring->count == WX_MAX_RXD) 1941 rxdctl |= 0 << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1942 else 1943 rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1944 1945 rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT; 1946 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl); 1947 1948 /* reset head and tail pointers */ 1949 wr32(wx, WX_PX_RR_RP(reg_idx), 0); 1950 wr32(wx, WX_PX_RR_WP(reg_idx), 0); 1951 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx); 1952 1953 wx_configure_srrctl(wx, ring); 1954 1955 /* initialize rx_buffer_info */ 1956 memset(ring->rx_buffer_info, 0, 1957 sizeof(struct wx_rx_buffer) * ring->count); 1958 1959 /* initialize Rx descriptor 0 */ 1960 rx_desc = WX_RX_DESC(ring, 0); 1961 rx_desc->wb.upper.length = 0; 1962 1963 /* enable receive descriptor ring */ 1964 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1965 WX_PX_RR_CFG_RR_EN, WX_PX_RR_CFG_RR_EN); 1966 1967 wx_enable_rx_queue(wx, ring); 1968 wx_alloc_rx_buffers(ring, wx_desc_unused(ring)); 1969 } 1970 1971 /** 1972 * wx_configure_tx - Configure Transmit Unit after Reset 1973 * @wx: pointer to private structure 1974 * 1975 * Configure the Tx unit of the MAC after a reset. 1976 **/ 1977 static void wx_configure_tx(struct wx *wx) 1978 { 1979 u32 i; 1980 1981 /* TDM_CTL.TE must be before Tx queues are enabled */ 1982 wr32m(wx, WX_TDM_CTL, 1983 WX_TDM_CTL_TE, WX_TDM_CTL_TE); 1984 1985 /* Setup the HW Tx Head and Tail descriptor pointers */ 1986 for (i = 0; i < wx->num_tx_queues; i++) 1987 wx_configure_tx_ring(wx, wx->tx_ring[i]); 1988 1989 wr32m(wx, WX_TSC_BUF_AE, WX_TSC_BUF_AE_THR, 0x10); 1990 1991 if (wx->mac.type == wx_mac_em) 1992 wr32m(wx, WX_TSC_CTL, WX_TSC_CTL_TX_DIS | WX_TSC_CTL_TSEC_DIS, 0x1); 1993 1994 /* enable mac transmitter */ 1995 wr32m(wx, WX_MAC_TX_CFG, 1996 WX_MAC_TX_CFG_TE, WX_MAC_TX_CFG_TE); 1997 } 1998 1999 static void wx_restore_vlan(struct wx *wx) 2000 { 2001 u16 vid = 1; 2002 2003 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), 0); 2004 2005 for_each_set_bit_from(vid, wx->active_vlans, VLAN_N_VID) 2006 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), vid); 2007 } 2008 2009 static void wx_store_reta(struct wx *wx) 2010 { 2011 u8 *indir_tbl = wx->rss_indir_tbl; 2012 u32 reta = 0; 2013 u32 i; 2014 2015 /* Fill out the redirection table as follows: 2016 * - 8 bit wide entries containing 4 bit RSS index 2017 */ 2018 for (i = 0; i < WX_MAX_RETA_ENTRIES; i++) { 2019 reta |= indir_tbl[i] << (i & 0x3) * 8; 2020 if ((i & 3) == 3) { 2021 wr32(wx, WX_RDB_RSSTBL(i >> 2), reta); 2022 reta = 0; 2023 } 2024 } 2025 } 2026 2027 static void wx_setup_reta(struct wx *wx) 2028 { 2029 u16 rss_i = wx->ring_feature[RING_F_RSS].indices; 2030 u32 random_key_size = WX_RSS_KEY_SIZE / 4; 2031 u32 i, j; 2032 2033 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) { 2034 if (wx->mac.type == wx_mac_em) 2035 rss_i = 1; 2036 else 2037 rss_i = rss_i < 4 ? 4 : rss_i; 2038 } 2039 2040 /* Fill out hash function seeds */ 2041 for (i = 0; i < random_key_size; i++) 2042 wr32(wx, WX_RDB_RSSRK(i), wx->rss_key[i]); 2043 2044 /* Fill out redirection table */ 2045 memset(wx->rss_indir_tbl, 0, sizeof(wx->rss_indir_tbl)); 2046 2047 for (i = 0, j = 0; i < WX_MAX_RETA_ENTRIES; i++, j++) { 2048 if (j == rss_i) 2049 j = 0; 2050 2051 wx->rss_indir_tbl[i] = j; 2052 } 2053 2054 wx_store_reta(wx); 2055 } 2056 2057 #define WX_RDB_RSS_PL_2 FIELD_PREP(GENMASK(31, 29), 1) 2058 #define WX_RDB_RSS_PL_4 FIELD_PREP(GENMASK(31, 29), 2) 2059 static void wx_setup_psrtype(struct wx *wx) 2060 { 2061 int rss_i = wx->ring_feature[RING_F_RSS].indices; 2062 u32 psrtype; 2063 int pool; 2064 2065 psrtype = WX_RDB_PL_CFG_L4HDR | 2066 WX_RDB_PL_CFG_L3HDR | 2067 WX_RDB_PL_CFG_L2HDR | 2068 WX_RDB_PL_CFG_TUN_OUTL2HDR | 2069 WX_RDB_PL_CFG_TUN_TUNHDR; 2070 2071 if (wx->mac.type == wx_mac_em) { 2072 for_each_set_bit(pool, &wx->fwd_bitmask, 8) 2073 wr32(wx, WX_RDB_PL_CFG(VMDQ_P(pool)), psrtype); 2074 } else { 2075 if (rss_i > 3) 2076 psrtype |= WX_RDB_RSS_PL_4; 2077 else if (rss_i > 1) 2078 psrtype |= WX_RDB_RSS_PL_2; 2079 2080 for_each_set_bit(pool, &wx->fwd_bitmask, 32) 2081 wr32(wx, WX_RDB_PL_CFG(VMDQ_P(pool)), psrtype); 2082 } 2083 } 2084 2085 static void wx_setup_mrqc(struct wx *wx) 2086 { 2087 u32 rss_field = 0; 2088 2089 /* VT, and RSS do not coexist at the same time */ 2090 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 2091 return; 2092 2093 /* Disable indicating checksum in descriptor, enables RSS hash */ 2094 wr32m(wx, WX_PSR_CTL, WX_PSR_CTL_PCSD, WX_PSR_CTL_PCSD); 2095 2096 /* Perform hash on these packet types */ 2097 rss_field = WX_RDB_RA_CTL_RSS_IPV4 | 2098 WX_RDB_RA_CTL_RSS_IPV4_TCP | 2099 WX_RDB_RA_CTL_RSS_IPV4_UDP | 2100 WX_RDB_RA_CTL_RSS_IPV6 | 2101 WX_RDB_RA_CTL_RSS_IPV6_TCP | 2102 WX_RDB_RA_CTL_RSS_IPV6_UDP; 2103 2104 netdev_rss_key_fill(wx->rss_key, sizeof(wx->rss_key)); 2105 2106 wx_setup_reta(wx); 2107 2108 if (wx->rss_enabled) 2109 rss_field |= WX_RDB_RA_CTL_RSS_EN; 2110 2111 wr32(wx, WX_RDB_RA_CTL, rss_field); 2112 } 2113 2114 /** 2115 * wx_configure_rx - Configure Receive Unit after Reset 2116 * @wx: pointer to private structure 2117 * 2118 * Configure the Rx unit of the MAC after a reset. 2119 **/ 2120 void wx_configure_rx(struct wx *wx) 2121 { 2122 int ret; 2123 u32 i; 2124 2125 wx_disable_rx(wx); 2126 wx_setup_psrtype(wx); 2127 2128 /* enable hw crc stripping */ 2129 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_CRC_STRIP, WX_RSC_CTL_CRC_STRIP); 2130 2131 if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) { 2132 u32 psrctl; 2133 2134 /* RSC Setup */ 2135 psrctl = rd32(wx, WX_PSR_CTL); 2136 psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */ 2137 psrctl |= WX_PSR_CTL_RSC_DIS; 2138 wr32(wx, WX_PSR_CTL, psrctl); 2139 } 2140 2141 wx_setup_mrqc(wx); 2142 2143 /* set_rx_buffer_len must be called before ring initialization */ 2144 wx_set_rx_buffer_len(wx); 2145 2146 /* Setup the HW Rx Head and Tail Descriptor Pointers and 2147 * the Base and Length of the Rx Descriptor Ring 2148 */ 2149 for (i = 0; i < wx->num_rx_queues; i++) 2150 wx_configure_rx_ring(wx, wx->rx_ring[i]); 2151 2152 /* Enable all receives, disable security engine prior to block traffic */ 2153 ret = wx_disable_sec_rx_path(wx); 2154 if (ret < 0) 2155 wx_err(wx, "The register status is abnormal, please check device."); 2156 2157 wx_enable_rx(wx); 2158 wx_enable_sec_rx_path(wx); 2159 } 2160 EXPORT_SYMBOL(wx_configure_rx); 2161 2162 static void wx_configure_isb(struct wx *wx) 2163 { 2164 /* set ISB Address */ 2165 wr32(wx, WX_PX_ISB_ADDR_L, wx->isb_dma & DMA_BIT_MASK(32)); 2166 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 2167 wr32(wx, WX_PX_ISB_ADDR_H, upper_32_bits(wx->isb_dma)); 2168 } 2169 2170 void wx_configure(struct wx *wx) 2171 { 2172 wx_set_rxpba(wx); 2173 wx_pbthresh_setup(wx); 2174 wx_configure_virtualization(wx); 2175 wx_configure_port(wx); 2176 2177 wx_set_rx_mode(wx->netdev); 2178 wx_restore_vlan(wx); 2179 2180 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) 2181 wx->configure_fdir(wx); 2182 2183 wx_configure_tx(wx); 2184 wx_configure_rx(wx); 2185 wx_configure_isb(wx); 2186 } 2187 EXPORT_SYMBOL(wx_configure); 2188 2189 /** 2190 * wx_disable_pcie_master - Disable PCI-express master access 2191 * @wx: pointer to hardware structure 2192 * 2193 * Disables PCI-Express master access and verifies there are no pending 2194 * requests. 2195 **/ 2196 int wx_disable_pcie_master(struct wx *wx) 2197 { 2198 int status = 0; 2199 u32 val; 2200 2201 /* Always set this bit to ensure any future transactions are blocked */ 2202 pci_clear_master(wx->pdev); 2203 2204 /* Exit if master requests are blocked */ 2205 if (!(rd32(wx, WX_PX_TRANSACTION_PENDING))) 2206 return 0; 2207 2208 /* Poll for master request bit to clear */ 2209 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT, 2210 false, wx, WX_PX_TRANSACTION_PENDING); 2211 if (status < 0) 2212 wx_err(wx, "PCIe transaction pending bit did not clear.\n"); 2213 2214 return status; 2215 } 2216 EXPORT_SYMBOL(wx_disable_pcie_master); 2217 2218 /** 2219 * wx_stop_adapter - Generic stop Tx/Rx units 2220 * @wx: pointer to hardware structure 2221 * 2222 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts, 2223 * disables transmit and receive units. The adapter_stopped flag is used by 2224 * the shared code and drivers to determine if the adapter is in a stopped 2225 * state and should not touch the hardware. 2226 **/ 2227 int wx_stop_adapter(struct wx *wx) 2228 { 2229 u16 i; 2230 2231 /* Set the adapter_stopped flag so other driver functions stop touching 2232 * the hardware 2233 */ 2234 wx->adapter_stopped = true; 2235 2236 /* Disable the receive unit */ 2237 wx_disable_rx(wx); 2238 2239 /* Set interrupt mask to stop interrupts from being generated */ 2240 wx_intr_disable(wx, WX_INTR_ALL); 2241 2242 /* Clear any pending interrupts, flush previous writes */ 2243 wr32(wx, WX_PX_MISC_IC, 0xffffffff); 2244 wr32(wx, WX_BME_CTL, 0x3); 2245 2246 /* Disable the transmit unit. Each queue must be disabled. */ 2247 for (i = 0; i < wx->mac.max_tx_queues; i++) { 2248 wr32m(wx, WX_PX_TR_CFG(i), 2249 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE, 2250 WX_PX_TR_CFG_SWFLSH); 2251 } 2252 2253 /* Disable the receive unit by stopping each queue */ 2254 for (i = 0; i < wx->mac.max_rx_queues; i++) { 2255 wr32m(wx, WX_PX_RR_CFG(i), 2256 WX_PX_RR_CFG_RR_EN, 0); 2257 } 2258 2259 /* flush all queues disables */ 2260 WX_WRITE_FLUSH(wx); 2261 2262 /* Prevent the PCI-E bus from hanging by disabling PCI-E master 2263 * access and verify no pending requests 2264 */ 2265 return wx_disable_pcie_master(wx); 2266 } 2267 EXPORT_SYMBOL(wx_stop_adapter); 2268 2269 void wx_reset_misc(struct wx *wx) 2270 { 2271 int i; 2272 2273 /* receive packets that size > 2048 */ 2274 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE); 2275 2276 /* clear counters on read */ 2277 wr32m(wx, WX_MMC_CONTROL, 2278 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD); 2279 2280 wr32m(wx, WX_MAC_RX_FLOW_CTRL, 2281 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE); 2282 2283 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 2284 2285 wr32m(wx, WX_MIS_RST_ST, 2286 WX_MIS_RST_ST_RST_INIT, 0x1E00); 2287 2288 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/ 2289 wr32(wx, WX_PSR_MNG_FLEX_SEL, 0); 2290 for (i = 0; i < 16; i++) { 2291 wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0); 2292 wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0); 2293 wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0); 2294 } 2295 wr32(wx, WX_PSR_LAN_FLEX_SEL, 0); 2296 for (i = 0; i < 16; i++) { 2297 wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0); 2298 wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0); 2299 wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0); 2300 } 2301 2302 /* set pause frame dst mac addr */ 2303 wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001); 2304 wr32(wx, WX_RDB_PFCMACDAH, 0x0180); 2305 } 2306 EXPORT_SYMBOL(wx_reset_misc); 2307 2308 /** 2309 * wx_get_pcie_msix_counts - Gets MSI-X vector count 2310 * @wx: pointer to hardware structure 2311 * @msix_count: number of MSI interrupts that can be obtained 2312 * @max_msix_count: number of MSI interrupts that mac need 2313 * 2314 * Read PCIe configuration space, and get the MSI-X vector count from 2315 * the capabilities table. 2316 **/ 2317 int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count) 2318 { 2319 struct pci_dev *pdev = wx->pdev; 2320 struct device *dev = &pdev->dev; 2321 int pos; 2322 2323 *msix_count = 1; 2324 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 2325 if (!pos) { 2326 dev_err(dev, "Unable to find MSI-X Capabilities\n"); 2327 return -EINVAL; 2328 } 2329 pci_read_config_word(pdev, 2330 pos + PCI_MSIX_FLAGS, 2331 msix_count); 2332 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK; 2333 /* MSI-X count is zero-based in HW */ 2334 *msix_count += 1; 2335 2336 if (*msix_count > max_msix_count) 2337 *msix_count = max_msix_count; 2338 2339 return 0; 2340 } 2341 EXPORT_SYMBOL(wx_get_pcie_msix_counts); 2342 2343 /** 2344 * wx_init_rss_key - Initialize wx RSS key 2345 * @wx: device handle 2346 * 2347 * Allocates and initializes the RSS key if it is not allocated. 2348 **/ 2349 static int wx_init_rss_key(struct wx *wx) 2350 { 2351 u32 *rss_key; 2352 2353 if (!wx->rss_key) { 2354 rss_key = kzalloc(WX_RSS_KEY_SIZE, GFP_KERNEL); 2355 if (unlikely(!rss_key)) 2356 return -ENOMEM; 2357 2358 netdev_rss_key_fill(rss_key, WX_RSS_KEY_SIZE); 2359 wx->rss_key = rss_key; 2360 } 2361 2362 return 0; 2363 } 2364 2365 int wx_sw_init(struct wx *wx) 2366 { 2367 struct pci_dev *pdev = wx->pdev; 2368 u32 ssid = 0; 2369 int err = 0; 2370 2371 wx->vendor_id = pdev->vendor; 2372 wx->device_id = pdev->device; 2373 wx->revision_id = pdev->revision; 2374 wx->oem_svid = pdev->subsystem_vendor; 2375 wx->oem_ssid = pdev->subsystem_device; 2376 wx->bus.device = PCI_SLOT(pdev->devfn); 2377 wx->bus.func = PCI_FUNC(pdev->devfn); 2378 2379 if (wx->oem_svid == PCI_VENDOR_ID_WANGXUN) { 2380 wx->subsystem_vendor_id = pdev->subsystem_vendor; 2381 wx->subsystem_device_id = pdev->subsystem_device; 2382 } else { 2383 err = wx_flash_read_dword(wx, 0xfffdc, &ssid); 2384 if (err < 0) { 2385 wx_err(wx, "read of internal subsystem device id failed\n"); 2386 return err; 2387 } 2388 2389 wx->subsystem_device_id = swab16((u16)ssid); 2390 } 2391 2392 err = wx_init_rss_key(wx); 2393 if (err < 0) { 2394 wx_err(wx, "rss key allocation failed\n"); 2395 return err; 2396 } 2397 2398 wx->mac_table = kcalloc(wx->mac.num_rar_entries, 2399 sizeof(struct wx_mac_addr), 2400 GFP_KERNEL); 2401 if (!wx->mac_table) { 2402 wx_err(wx, "mac_table allocation failed\n"); 2403 kfree(wx->rss_key); 2404 return -ENOMEM; 2405 } 2406 2407 bitmap_zero(wx->state, WX_STATE_NBITS); 2408 bitmap_zero(wx->flags, WX_PF_FLAGS_NBITS); 2409 wx->misc_irq_domain = false; 2410 2411 return 0; 2412 } 2413 EXPORT_SYMBOL(wx_sw_init); 2414 2415 /** 2416 * wx_find_vlvf_slot - find the vlanid or the first empty slot 2417 * @wx: pointer to hardware structure 2418 * @vlan: VLAN id to write to VLAN filter 2419 * 2420 * return the VLVF index where this VLAN id should be placed 2421 * 2422 **/ 2423 static int wx_find_vlvf_slot(struct wx *wx, u32 vlan) 2424 { 2425 u32 bits = 0, first_empty_slot = 0; 2426 int regindex; 2427 2428 /* short cut the special case */ 2429 if (vlan == 0) 2430 return 0; 2431 2432 /* Search for the vlan id in the VLVF entries. Save off the first empty 2433 * slot found along the way 2434 */ 2435 for (regindex = 1; regindex < WX_PSR_VLAN_SWC_ENTRIES; regindex++) { 2436 wr32(wx, WX_PSR_VLAN_SWC_IDX, regindex); 2437 bits = rd32(wx, WX_PSR_VLAN_SWC); 2438 if (!bits && !(first_empty_slot)) 2439 first_empty_slot = regindex; 2440 else if ((bits & 0x0FFF) == vlan) 2441 break; 2442 } 2443 2444 if (regindex >= WX_PSR_VLAN_SWC_ENTRIES) { 2445 if (first_empty_slot) 2446 regindex = first_empty_slot; 2447 else 2448 regindex = -ENOMEM; 2449 } 2450 2451 return regindex; 2452 } 2453 2454 /** 2455 * wx_set_vlvf - Set VLAN Pool Filter 2456 * @wx: pointer to hardware structure 2457 * @vlan: VLAN id to write to VLAN filter 2458 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2459 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2460 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 2461 * should be changed 2462 * 2463 * Turn on/off specified bit in VLVF table. 2464 **/ 2465 static int wx_set_vlvf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on, 2466 bool *vfta_changed) 2467 { 2468 int vlvf_index; 2469 u32 vt, bits; 2470 2471 /* If VT Mode is set 2472 * Either vlan_on 2473 * make sure the vlan is in VLVF 2474 * set the vind bit in the matching VLVFB 2475 * Or !vlan_on 2476 * clear the pool bit and possibly the vind 2477 */ 2478 vt = rd32(wx, WX_CFG_PORT_CTL); 2479 if (!(vt & WX_CFG_PORT_CTL_NUM_VT_MASK)) 2480 return 0; 2481 2482 vlvf_index = wx_find_vlvf_slot(wx, vlan); 2483 if (vlvf_index < 0) 2484 return vlvf_index; 2485 2486 wr32(wx, WX_PSR_VLAN_SWC_IDX, vlvf_index); 2487 if (vlan_on) { 2488 /* set the pool bit */ 2489 if (vind < 32) { 2490 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2491 bits |= (1 << vind); 2492 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits); 2493 } else { 2494 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2495 bits |= (1 << (vind - 32)); 2496 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits); 2497 } 2498 } else { 2499 /* clear the pool bit */ 2500 if (vind < 32) { 2501 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2502 bits &= ~(1 << vind); 2503 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits); 2504 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2505 } else { 2506 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2507 bits &= ~(1 << (vind - 32)); 2508 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits); 2509 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2510 } 2511 } 2512 2513 if (bits) { 2514 wr32(wx, WX_PSR_VLAN_SWC, (WX_PSR_VLAN_SWC_VIEN | vlan)); 2515 if (!vlan_on && vfta_changed) 2516 *vfta_changed = false; 2517 } else { 2518 wr32(wx, WX_PSR_VLAN_SWC, 0); 2519 } 2520 2521 return 0; 2522 } 2523 2524 /** 2525 * wx_set_vfta - Set VLAN filter table 2526 * @wx: pointer to hardware structure 2527 * @vlan: VLAN id to write to VLAN filter 2528 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2529 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2530 * 2531 * Turn on/off specified VLAN in the VLAN filter table. 2532 **/ 2533 int wx_set_vfta(struct wx *wx, u32 vlan, u32 vind, bool vlan_on) 2534 { 2535 u32 bitindex, vfta, targetbit; 2536 bool vfta_changed = false; 2537 int regindex, ret; 2538 2539 /* this is a 2 part operation - first the VFTA, then the 2540 * VLVF and VLVFB if VT Mode is set 2541 * We don't write the VFTA until we know the VLVF part succeeded. 2542 */ 2543 2544 /* Part 1 2545 * The VFTA is a bitstring made up of 128 32-bit registers 2546 * that enable the particular VLAN id, much like the MTA: 2547 * bits[11-5]: which register 2548 * bits[4-0]: which bit in the register 2549 */ 2550 regindex = (vlan >> 5) & 0x7F; 2551 bitindex = vlan & 0x1F; 2552 targetbit = (1 << bitindex); 2553 /* errata 5 */ 2554 vfta = wx->mac.vft_shadow[regindex]; 2555 if (vlan_on) { 2556 if (!(vfta & targetbit)) { 2557 vfta |= targetbit; 2558 vfta_changed = true; 2559 } 2560 } else { 2561 if ((vfta & targetbit)) { 2562 vfta &= ~targetbit; 2563 vfta_changed = true; 2564 } 2565 } 2566 /* Part 2 2567 * Call wx_set_vlvf to set VLVFB and VLVF 2568 */ 2569 ret = wx_set_vlvf(wx, vlan, vind, vlan_on, &vfta_changed); 2570 if (ret != 0) 2571 return ret; 2572 2573 if (vfta_changed) 2574 wr32(wx, WX_PSR_VLAN_TBL(regindex), vfta); 2575 wx->mac.vft_shadow[regindex] = vfta; 2576 2577 return 0; 2578 } 2579 2580 /** 2581 * wx_clear_vfta - Clear VLAN filter table 2582 * @wx: pointer to hardware structure 2583 * 2584 * Clears the VLAN filer table, and the VMDq index associated with the filter 2585 **/ 2586 static void wx_clear_vfta(struct wx *wx) 2587 { 2588 u32 offset; 2589 2590 for (offset = 0; offset < wx->mac.vft_size; offset++) { 2591 wr32(wx, WX_PSR_VLAN_TBL(offset), 0); 2592 wx->mac.vft_shadow[offset] = 0; 2593 } 2594 2595 for (offset = 0; offset < WX_PSR_VLAN_SWC_ENTRIES; offset++) { 2596 wr32(wx, WX_PSR_VLAN_SWC_IDX, offset); 2597 wr32(wx, WX_PSR_VLAN_SWC, 0); 2598 wr32(wx, WX_PSR_VLAN_SWC_VM_L, 0); 2599 wr32(wx, WX_PSR_VLAN_SWC_VM_H, 0); 2600 } 2601 } 2602 2603 int wx_vlan_rx_add_vid(struct net_device *netdev, 2604 __be16 proto, u16 vid) 2605 { 2606 struct wx *wx = netdev_priv(netdev); 2607 2608 /* add VID to filter table */ 2609 wx_set_vfta(wx, vid, VMDQ_P(0), true); 2610 set_bit(vid, wx->active_vlans); 2611 2612 return 0; 2613 } 2614 EXPORT_SYMBOL(wx_vlan_rx_add_vid); 2615 2616 int wx_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2617 { 2618 struct wx *wx = netdev_priv(netdev); 2619 2620 /* remove VID from filter table */ 2621 if (vid) 2622 wx_set_vfta(wx, vid, VMDQ_P(0), false); 2623 clear_bit(vid, wx->active_vlans); 2624 2625 return 0; 2626 } 2627 EXPORT_SYMBOL(wx_vlan_rx_kill_vid); 2628 2629 static void wx_enable_rx_drop(struct wx *wx, struct wx_ring *ring) 2630 { 2631 u16 reg_idx = ring->reg_idx; 2632 u32 srrctl; 2633 2634 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 2635 srrctl |= WX_PX_RR_CFG_DROP_EN; 2636 2637 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 2638 } 2639 2640 static void wx_disable_rx_drop(struct wx *wx, struct wx_ring *ring) 2641 { 2642 u16 reg_idx = ring->reg_idx; 2643 u32 srrctl; 2644 2645 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 2646 srrctl &= ~WX_PX_RR_CFG_DROP_EN; 2647 2648 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 2649 } 2650 2651 int wx_fc_enable(struct wx *wx, bool tx_pause, bool rx_pause) 2652 { 2653 u16 pause_time = WX_DEFAULT_FCPAUSE; 2654 u32 mflcn_reg, fccfg_reg, reg; 2655 u32 fcrtl, fcrth; 2656 int i; 2657 2658 /* Low water mark of zero causes XOFF floods */ 2659 if (tx_pause && wx->fc.high_water) { 2660 if (!wx->fc.low_water || wx->fc.low_water >= wx->fc.high_water) { 2661 wx_err(wx, "Invalid water mark configuration\n"); 2662 return -EINVAL; 2663 } 2664 } 2665 2666 /* Disable any previous flow control settings */ 2667 mflcn_reg = rd32(wx, WX_MAC_RX_FLOW_CTRL); 2668 mflcn_reg &= ~WX_MAC_RX_FLOW_CTRL_RFE; 2669 2670 fccfg_reg = rd32(wx, WX_RDB_RFCC); 2671 fccfg_reg &= ~WX_RDB_RFCC_RFCE_802_3X; 2672 2673 if (rx_pause) 2674 mflcn_reg |= WX_MAC_RX_FLOW_CTRL_RFE; 2675 if (tx_pause) 2676 fccfg_reg |= WX_RDB_RFCC_RFCE_802_3X; 2677 2678 /* Set 802.3x based flow control settings. */ 2679 wr32(wx, WX_MAC_RX_FLOW_CTRL, mflcn_reg); 2680 wr32(wx, WX_RDB_RFCC, fccfg_reg); 2681 2682 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2683 if (tx_pause && wx->fc.high_water) { 2684 fcrtl = (wx->fc.low_water << 10) | WX_RDB_RFCL_XONE; 2685 wr32(wx, WX_RDB_RFCL, fcrtl); 2686 fcrth = (wx->fc.high_water << 10) | WX_RDB_RFCH_XOFFE; 2687 } else { 2688 wr32(wx, WX_RDB_RFCL, 0); 2689 /* In order to prevent Tx hangs when the internal Tx 2690 * switch is enabled we must set the high water mark 2691 * to the Rx packet buffer size - 24KB. This allows 2692 * the Tx switch to function even under heavy Rx 2693 * workloads. 2694 */ 2695 fcrth = rd32(wx, WX_RDB_PB_SZ(0)) - 24576; 2696 } 2697 2698 wr32(wx, WX_RDB_RFCH, fcrth); 2699 2700 /* Configure pause time */ 2701 reg = pause_time * 0x00010001; 2702 wr32(wx, WX_RDB_RFCV, reg); 2703 2704 /* Configure flow control refresh threshold value */ 2705 wr32(wx, WX_RDB_RFCRT, pause_time / 2); 2706 2707 /* We should set the drop enable bit if: 2708 * Number of Rx queues > 1 and flow control is disabled 2709 * 2710 * This allows us to avoid head of line blocking for security 2711 * and performance reasons. 2712 */ 2713 if (wx->num_rx_queues > 1 && !tx_pause) { 2714 for (i = 0; i < wx->num_rx_queues; i++) 2715 wx_enable_rx_drop(wx, wx->rx_ring[i]); 2716 } else { 2717 for (i = 0; i < wx->num_rx_queues; i++) 2718 wx_disable_rx_drop(wx, wx->rx_ring[i]); 2719 } 2720 2721 return 0; 2722 } 2723 EXPORT_SYMBOL(wx_fc_enable); 2724 2725 /** 2726 * wx_update_stats - Update the board statistics counters. 2727 * @wx: board private structure 2728 **/ 2729 void wx_update_stats(struct wx *wx) 2730 { 2731 struct wx_hw_stats *hwstats = &wx->stats; 2732 2733 u64 non_eop_descs = 0, alloc_rx_buff_failed = 0; 2734 u64 hw_csum_rx_good = 0, hw_csum_rx_error = 0; 2735 u64 restart_queue = 0, tx_busy = 0; 2736 u32 i; 2737 2738 /* gather some stats to the wx struct that are per queue */ 2739 for (i = 0; i < wx->num_rx_queues; i++) { 2740 struct wx_ring *rx_ring = wx->rx_ring[i]; 2741 2742 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 2743 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 2744 hw_csum_rx_good += rx_ring->rx_stats.csum_good_cnt; 2745 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 2746 } 2747 wx->non_eop_descs = non_eop_descs; 2748 wx->alloc_rx_buff_failed = alloc_rx_buff_failed; 2749 wx->hw_csum_rx_error = hw_csum_rx_error; 2750 wx->hw_csum_rx_good = hw_csum_rx_good; 2751 2752 for (i = 0; i < wx->num_tx_queues; i++) { 2753 struct wx_ring *tx_ring = wx->tx_ring[i]; 2754 2755 restart_queue += tx_ring->tx_stats.restart_queue; 2756 tx_busy += tx_ring->tx_stats.tx_busy; 2757 } 2758 wx->restart_queue = restart_queue; 2759 wx->tx_busy = tx_busy; 2760 2761 hwstats->gprc += rd32(wx, WX_RDM_PKT_CNT); 2762 hwstats->gptc += rd32(wx, WX_TDM_PKT_CNT); 2763 hwstats->gorc += rd64(wx, WX_RDM_BYTE_CNT_LSB); 2764 hwstats->gotc += rd64(wx, WX_TDM_BYTE_CNT_LSB); 2765 hwstats->tpr += rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L); 2766 hwstats->tpt += rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L); 2767 hwstats->crcerrs += rd64(wx, WX_RX_CRC_ERROR_FRAMES_L); 2768 hwstats->rlec += rd64(wx, WX_RX_LEN_ERROR_FRAMES_L); 2769 hwstats->bprc += rd64(wx, WX_RX_BC_FRAMES_GOOD_L); 2770 hwstats->bptc += rd64(wx, WX_TX_BC_FRAMES_GOOD_L); 2771 hwstats->mprc += rd64(wx, WX_RX_MC_FRAMES_GOOD_L); 2772 hwstats->mptc += rd64(wx, WX_TX_MC_FRAMES_GOOD_L); 2773 hwstats->roc += rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD); 2774 hwstats->ruc += rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD); 2775 hwstats->lxonoffrxc += rd32(wx, WX_MAC_LXONOFFRXC); 2776 hwstats->lxontxc += rd32(wx, WX_RDB_LXONTXC); 2777 hwstats->lxofftxc += rd32(wx, WX_RDB_LXOFFTXC); 2778 hwstats->o2bgptc += rd32(wx, WX_TDM_OS2BMC_CNT); 2779 hwstats->b2ospc += rd32(wx, WX_MNG_BMC2OS_CNT); 2780 hwstats->o2bspc += rd32(wx, WX_MNG_OS2BMC_CNT); 2781 hwstats->b2ogprc += rd32(wx, WX_RDM_BMC2OS_CNT); 2782 hwstats->rdmdrop += rd32(wx, WX_RDM_DRP_PKT); 2783 2784 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 2785 hwstats->fdirmatch += rd32(wx, WX_RDB_FDIR_MATCH); 2786 hwstats->fdirmiss += rd32(wx, WX_RDB_FDIR_MISS); 2787 } 2788 2789 for (i = 0; i < wx->mac.max_rx_queues; i++) 2790 hwstats->qmprc += rd32(wx, WX_PX_MPRC(i)); 2791 } 2792 EXPORT_SYMBOL(wx_update_stats); 2793 2794 /** 2795 * wx_clear_hw_cntrs - Generic clear hardware counters 2796 * @wx: board private structure 2797 * 2798 * Clears all hardware statistics counters by reading them from the hardware 2799 * Statistics counters are clear on read. 2800 **/ 2801 void wx_clear_hw_cntrs(struct wx *wx) 2802 { 2803 u16 i = 0; 2804 2805 for (i = 0; i < wx->mac.max_rx_queues; i++) 2806 wr32(wx, WX_PX_MPRC(i), 0); 2807 2808 rd32(wx, WX_RDM_PKT_CNT); 2809 rd32(wx, WX_TDM_PKT_CNT); 2810 rd64(wx, WX_RDM_BYTE_CNT_LSB); 2811 rd32(wx, WX_TDM_BYTE_CNT_LSB); 2812 rd32(wx, WX_RDM_DRP_PKT); 2813 rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD); 2814 rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD); 2815 rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L); 2816 rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L); 2817 rd64(wx, WX_RX_MC_FRAMES_GOOD_L); 2818 rd64(wx, WX_TX_MC_FRAMES_GOOD_L); 2819 rd64(wx, WX_RX_BC_FRAMES_GOOD_L); 2820 rd64(wx, WX_TX_BC_FRAMES_GOOD_L); 2821 rd64(wx, WX_RX_CRC_ERROR_FRAMES_L); 2822 rd64(wx, WX_RX_LEN_ERROR_FRAMES_L); 2823 rd32(wx, WX_RDB_LXONTXC); 2824 rd32(wx, WX_RDB_LXOFFTXC); 2825 rd32(wx, WX_MAC_LXONOFFRXC); 2826 } 2827 EXPORT_SYMBOL(wx_clear_hw_cntrs); 2828 2829 /** 2830 * wx_start_hw - Prepare hardware for Tx/Rx 2831 * @wx: pointer to hardware structure 2832 * 2833 * Starts the hardware using the generic start_hw function 2834 * and the generation start_hw function. 2835 * Then performs revision-specific operations, if any. 2836 **/ 2837 void wx_start_hw(struct wx *wx) 2838 { 2839 int i; 2840 2841 /* Clear the VLAN filter table */ 2842 wx_clear_vfta(wx); 2843 WX_WRITE_FLUSH(wx); 2844 /* Clear the rate limiters */ 2845 for (i = 0; i < wx->mac.max_tx_queues; i++) { 2846 wr32(wx, WX_TDM_RP_IDX, i); 2847 wr32(wx, WX_TDM_RP_RATE, 0); 2848 } 2849 } 2850 EXPORT_SYMBOL(wx_start_hw); 2851 2852 MODULE_LICENSE("GPL"); 2853