1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/netdevice.h> 6 #include <linux/if_ether.h> 7 #include <linux/if_vlan.h> 8 #include <linux/iopoll.h> 9 #include <linux/pci.h> 10 11 #include "wx_type.h" 12 #include "wx_lib.h" 13 #include "wx_hw.h" 14 15 static int wx_phy_read_reg_mdi(struct mii_bus *bus, int phy_addr, int devnum, int regnum) 16 { 17 struct wx *wx = bus->priv; 18 u32 command, val; 19 int ret; 20 21 /* setup and write the address cycle command */ 22 command = WX_MSCA_RA(regnum) | 23 WX_MSCA_PA(phy_addr) | 24 WX_MSCA_DA(devnum); 25 wr32(wx, WX_MSCA, command); 26 27 command = WX_MSCC_CMD(WX_MSCA_CMD_READ) | WX_MSCC_BUSY; 28 if (wx->mac.type == wx_mac_em) 29 command |= WX_MDIO_CLK(6); 30 wr32(wx, WX_MSCC, command); 31 32 /* wait to complete */ 33 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 34 100000, false, wx, WX_MSCC); 35 if (ret) { 36 wx_err(wx, "Mdio read c22 command did not complete.\n"); 37 return ret; 38 } 39 40 return (u16)rd32(wx, WX_MSCC); 41 } 42 43 static int wx_phy_write_reg_mdi(struct mii_bus *bus, int phy_addr, 44 int devnum, int regnum, u16 value) 45 { 46 struct wx *wx = bus->priv; 47 u32 command, val; 48 int ret; 49 50 /* setup and write the address cycle command */ 51 command = WX_MSCA_RA(regnum) | 52 WX_MSCA_PA(phy_addr) | 53 WX_MSCA_DA(devnum); 54 wr32(wx, WX_MSCA, command); 55 56 command = value | WX_MSCC_CMD(WX_MSCA_CMD_WRITE) | WX_MSCC_BUSY; 57 if (wx->mac.type == wx_mac_em) 58 command |= WX_MDIO_CLK(6); 59 wr32(wx, WX_MSCC, command); 60 61 /* wait to complete */ 62 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 63 100000, false, wx, WX_MSCC); 64 if (ret) 65 wx_err(wx, "Mdio write c22 command did not complete.\n"); 66 67 return ret; 68 } 69 70 int wx_phy_read_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum) 71 { 72 struct wx *wx = bus->priv; 73 74 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF); 75 return wx_phy_read_reg_mdi(bus, phy_addr, 0, regnum); 76 } 77 EXPORT_SYMBOL(wx_phy_read_reg_mdi_c22); 78 79 int wx_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum, u16 value) 80 { 81 struct wx *wx = bus->priv; 82 83 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF); 84 return wx_phy_write_reg_mdi(bus, phy_addr, 0, regnum, value); 85 } 86 EXPORT_SYMBOL(wx_phy_write_reg_mdi_c22); 87 88 int wx_phy_read_reg_mdi_c45(struct mii_bus *bus, int phy_addr, int devnum, int regnum) 89 { 90 struct wx *wx = bus->priv; 91 92 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0); 93 return wx_phy_read_reg_mdi(bus, phy_addr, devnum, regnum); 94 } 95 EXPORT_SYMBOL(wx_phy_read_reg_mdi_c45); 96 97 int wx_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr, 98 int devnum, int regnum, u16 value) 99 { 100 struct wx *wx = bus->priv; 101 102 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0); 103 return wx_phy_write_reg_mdi(bus, phy_addr, devnum, regnum, value); 104 } 105 EXPORT_SYMBOL(wx_phy_write_reg_mdi_c45); 106 107 static void wx_intr_disable(struct wx *wx, u64 qmask) 108 { 109 u32 mask; 110 111 mask = (qmask & U32_MAX); 112 if (mask) 113 wr32(wx, WX_PX_IMS(0), mask); 114 115 switch (wx->mac.type) { 116 case wx_mac_sp: 117 case wx_mac_aml: 118 mask = (qmask >> 32); 119 if (mask) 120 wr32(wx, WX_PX_IMS(1), mask); 121 break; 122 default: 123 break; 124 } 125 } 126 127 void wx_intr_enable(struct wx *wx, u64 qmask) 128 { 129 u32 mask; 130 131 mask = (qmask & U32_MAX); 132 if (mask) 133 wr32(wx, WX_PX_IMC(0), mask); 134 135 switch (wx->mac.type) { 136 case wx_mac_sp: 137 case wx_mac_aml: 138 mask = (qmask >> 32); 139 if (mask) 140 wr32(wx, WX_PX_IMC(1), mask); 141 break; 142 default: 143 break; 144 } 145 } 146 EXPORT_SYMBOL(wx_intr_enable); 147 148 /** 149 * wx_irq_disable - Mask off interrupt generation on the NIC 150 * @wx: board private structure 151 **/ 152 void wx_irq_disable(struct wx *wx) 153 { 154 struct pci_dev *pdev = wx->pdev; 155 156 wr32(wx, WX_PX_MISC_IEN, 0); 157 wx_intr_disable(wx, WX_INTR_ALL); 158 159 if (pdev->msix_enabled) { 160 int vector; 161 162 for (vector = 0; vector < wx->num_q_vectors; vector++) 163 synchronize_irq(wx->msix_q_entries[vector].vector); 164 165 synchronize_irq(wx->msix_entry->vector); 166 } else { 167 synchronize_irq(pdev->irq); 168 } 169 } 170 EXPORT_SYMBOL(wx_irq_disable); 171 172 /* cmd_addr is used for some special command: 173 * 1. to be sector address, when implemented erase sector command 174 * 2. to be flash address when implemented read, write flash address 175 */ 176 static int wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr) 177 { 178 u32 cmd_val = 0, val = 0; 179 180 cmd_val = WX_SPI_CMD_CMD(cmd) | 181 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) | 182 cmd_addr; 183 wr32(wx, WX_SPI_CMD, cmd_val); 184 185 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, 186 false, wx, WX_SPI_STATUS); 187 } 188 189 static int wx_flash_read_dword(struct wx *wx, u32 addr, u32 *data) 190 { 191 int ret = 0; 192 193 ret = wx_fmgr_cmd_op(wx, WX_SPI_CMD_READ_DWORD, addr); 194 if (ret < 0) 195 return ret; 196 197 *data = rd32(wx, WX_SPI_DATA); 198 199 return ret; 200 } 201 202 int wx_check_flash_load(struct wx *hw, u32 check_bit) 203 { 204 u32 reg = 0; 205 int err = 0; 206 207 /* if there's flash existing */ 208 if (!(rd32(hw, WX_SPI_STATUS) & 209 WX_SPI_STATUS_FLASH_BYPASS)) { 210 /* wait hw load flash done */ 211 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, 212 false, hw, WX_SPI_ILDR_STATUS); 213 if (err < 0) 214 wx_err(hw, "Check flash load timeout.\n"); 215 } 216 217 return err; 218 } 219 EXPORT_SYMBOL(wx_check_flash_load); 220 221 void wx_control_hw(struct wx *wx, bool drv) 222 { 223 /* True : Let firmware know the driver has taken over 224 * False : Let firmware take over control of hw 225 */ 226 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD, 227 drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0); 228 } 229 EXPORT_SYMBOL(wx_control_hw); 230 231 /** 232 * wx_mng_present - returns 0 when management capability is present 233 * @wx: pointer to hardware structure 234 */ 235 int wx_mng_present(struct wx *wx) 236 { 237 u32 fwsm; 238 239 fwsm = rd32(wx, WX_MIS_ST); 240 if (fwsm & WX_MIS_ST_MNG_INIT_DN) 241 return 0; 242 else 243 return -EACCES; 244 } 245 EXPORT_SYMBOL(wx_mng_present); 246 247 /* Software lock to be held while software semaphore is being accessed. */ 248 static DEFINE_MUTEX(wx_sw_sync_lock); 249 250 /** 251 * wx_release_sw_sync - Release SW semaphore 252 * @wx: pointer to hardware structure 253 * @mask: Mask to specify which semaphore to release 254 * 255 * Releases the SW semaphore for the specified 256 * function (CSR, PHY0, PHY1, EEPROM, Flash) 257 **/ 258 static void wx_release_sw_sync(struct wx *wx, u32 mask) 259 { 260 mutex_lock(&wx_sw_sync_lock); 261 wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0); 262 mutex_unlock(&wx_sw_sync_lock); 263 } 264 265 /** 266 * wx_acquire_sw_sync - Acquire SW semaphore 267 * @wx: pointer to hardware structure 268 * @mask: Mask to specify which semaphore to acquire 269 * 270 * Acquires the SW semaphore for the specified 271 * function (CSR, PHY0, PHY1, EEPROM, Flash) 272 **/ 273 static int wx_acquire_sw_sync(struct wx *wx, u32 mask) 274 { 275 u32 sem = 0; 276 int ret = 0; 277 278 mutex_lock(&wx_sw_sync_lock); 279 ret = read_poll_timeout(rd32, sem, !(sem & mask), 280 5000, 2000000, false, wx, WX_MNG_SWFW_SYNC); 281 if (!ret) { 282 sem |= mask; 283 wr32(wx, WX_MNG_SWFW_SYNC, sem); 284 } else { 285 wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem); 286 } 287 mutex_unlock(&wx_sw_sync_lock); 288 289 return ret; 290 } 291 292 static int wx_host_interface_command_s(struct wx *wx, u32 *buffer, 293 u32 length, u32 timeout, bool return_data) 294 { 295 u32 hdr_size = sizeof(struct wx_hic_hdr); 296 u32 hicr, i, bi, buf[64] = {}; 297 int status = 0; 298 u32 dword_len; 299 u16 buf_len; 300 301 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 302 if (status != 0) 303 return status; 304 305 dword_len = length >> 2; 306 307 /* The device driver writes the relevant command block 308 * into the ram area. 309 */ 310 for (i = 0; i < dword_len; i++) { 311 wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 312 /* write flush */ 313 buf[i] = rd32a(wx, WX_MNG_MBOX, i); 314 } 315 /* Setting this bit tells the ARC that a new command is pending. */ 316 wr32m(wx, WX_MNG_MBOX_CTL, 317 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY); 318 319 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, 320 timeout * 1000, false, wx, WX_MNG_MBOX_CTL); 321 322 buf[0] = rd32(wx, WX_MNG_MBOX); 323 if ((buf[0] & 0xff0000) >> 16 == 0x80) { 324 wx_err(wx, "Unknown FW command: 0x%x\n", buffer[0] & 0xff); 325 status = -EINVAL; 326 goto rel_out; 327 } 328 329 /* Check command completion */ 330 if (status) { 331 wx_err(wx, "Command has failed with no status valid.\n"); 332 wx_dbg(wx, "write value:\n"); 333 for (i = 0; i < dword_len; i++) 334 wx_dbg(wx, "%x ", buffer[i]); 335 wx_dbg(wx, "read value:\n"); 336 for (i = 0; i < dword_len; i++) 337 wx_dbg(wx, "%x ", buf[i]); 338 wx_dbg(wx, "\ncheck: %x %x\n", buffer[0] & 0xff, ~buf[0] >> 24); 339 340 goto rel_out; 341 } 342 343 if (!return_data) 344 goto rel_out; 345 346 /* Calculate length in DWORDs */ 347 dword_len = hdr_size >> 2; 348 349 /* first pull in the header so we know the buffer length */ 350 for (bi = 0; bi < dword_len; bi++) { 351 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 352 le32_to_cpus(&buffer[bi]); 353 } 354 355 /* If there is any thing in data position pull it in */ 356 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len; 357 if (buf_len == 0) 358 goto rel_out; 359 360 if (length < buf_len + hdr_size) { 361 wx_err(wx, "Buffer not large enough for reply message.\n"); 362 status = -EFAULT; 363 goto rel_out; 364 } 365 366 /* Calculate length in DWORDs, add 3 for odd lengths */ 367 dword_len = (buf_len + 3) >> 2; 368 369 /* Pull in the rest of the buffer (bi is where we left off) */ 370 for (; bi <= dword_len; bi++) { 371 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 372 le32_to_cpus(&buffer[bi]); 373 } 374 375 rel_out: 376 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 377 return status; 378 } 379 380 static bool wx_poll_fw_reply(struct wx *wx, u32 *buffer, u8 send_cmd) 381 { 382 u32 dword_len = sizeof(struct wx_hic_hdr) >> 2; 383 struct wx_hic_hdr *recv_hdr; 384 u32 i; 385 386 /* read hdr */ 387 for (i = 0; i < dword_len; i++) { 388 buffer[i] = rd32a(wx, WX_FW2SW_MBOX, i); 389 le32_to_cpus(&buffer[i]); 390 } 391 392 /* check hdr */ 393 recv_hdr = (struct wx_hic_hdr *)buffer; 394 if (recv_hdr->cmd == send_cmd && 395 recv_hdr->index == wx->swfw_index) 396 return true; 397 398 return false; 399 } 400 401 static int wx_host_interface_command_r(struct wx *wx, u32 *buffer, 402 u32 length, u32 timeout, bool return_data) 403 { 404 struct wx_hic_hdr *hdr = (struct wx_hic_hdr *)buffer; 405 u32 hdr_size = sizeof(struct wx_hic_hdr); 406 bool busy, reply; 407 u32 dword_len; 408 u16 buf_len; 409 int err = 0; 410 u8 send_cmd; 411 u32 i; 412 413 /* wait to get lock */ 414 might_sleep(); 415 err = read_poll_timeout(test_and_set_bit, busy, !busy, 1000, timeout * 1000, 416 false, WX_STATE_SWFW_BUSY, wx->state); 417 if (err) 418 return err; 419 420 /* index to unique seq id for each mbox message */ 421 hdr->index = wx->swfw_index; 422 send_cmd = hdr->cmd; 423 424 dword_len = length >> 2; 425 /* write data to SW-FW mbox array */ 426 for (i = 0; i < dword_len; i++) { 427 wr32a(wx, WX_SW2FW_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 428 /* write flush */ 429 rd32a(wx, WX_SW2FW_MBOX, i); 430 } 431 432 /* generate interrupt to notify FW */ 433 wr32m(wx, WX_SW2FW_MBOX_CMD, WX_SW2FW_MBOX_CMD_VLD, 0); 434 wr32m(wx, WX_SW2FW_MBOX_CMD, WX_SW2FW_MBOX_CMD_VLD, WX_SW2FW_MBOX_CMD_VLD); 435 436 /* polling reply from FW */ 437 err = read_poll_timeout(wx_poll_fw_reply, reply, reply, 1000, 50000, 438 true, wx, buffer, send_cmd); 439 if (err) { 440 wx_err(wx, "Polling from FW messages timeout, cmd: 0x%x, index: %d\n", 441 send_cmd, wx->swfw_index); 442 goto rel_out; 443 } 444 445 /* expect no reply from FW then return */ 446 if (!return_data) 447 goto rel_out; 448 449 /* If there is any thing in data position pull it in */ 450 buf_len = hdr->buf_len; 451 if (buf_len == 0) 452 goto rel_out; 453 454 if (length < buf_len + hdr_size) { 455 wx_err(wx, "Buffer not large enough for reply message.\n"); 456 err = -EFAULT; 457 goto rel_out; 458 } 459 460 /* Calculate length in DWORDs, add 3 for odd lengths */ 461 dword_len = (buf_len + 3) >> 2; 462 for (i = hdr_size >> 2; i <= dword_len; i++) { 463 buffer[i] = rd32a(wx, WX_FW2SW_MBOX, i); 464 le32_to_cpus(&buffer[i]); 465 } 466 467 rel_out: 468 /* index++, index replace wx_hic_hdr.checksum */ 469 if (wx->swfw_index == WX_HIC_HDR_INDEX_MAX) 470 wx->swfw_index = 0; 471 else 472 wx->swfw_index++; 473 474 clear_bit(WX_STATE_SWFW_BUSY, wx->state); 475 return err; 476 } 477 478 /** 479 * wx_host_interface_command - Issue command to manageability block 480 * @wx: pointer to the HW structure 481 * @buffer: contains the command to write and where the return status will 482 * be placed 483 * @length: length of buffer, must be multiple of 4 bytes 484 * @timeout: time in ms to wait for command completion 485 * @return_data: read and return data from the buffer (true) or not (false) 486 * Needed because FW structures are big endian and decoding of 487 * these fields can be 8 bit or 16 bit based on command. Decoding 488 * is not easily understood without making a table of commands. 489 * So we will leave this up to the caller to read back the data 490 * in these cases. 491 **/ 492 int wx_host_interface_command(struct wx *wx, u32 *buffer, 493 u32 length, u32 timeout, bool return_data) 494 { 495 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) { 496 wx_err(wx, "Buffer length failure buffersize=%d.\n", length); 497 return -EINVAL; 498 } 499 500 /* Calculate length in DWORDs. We must be DWORD aligned */ 501 if ((length % (sizeof(u32))) != 0) { 502 wx_err(wx, "Buffer length failure, not aligned to dword"); 503 return -EINVAL; 504 } 505 506 if (test_bit(WX_FLAG_SWFW_RING, wx->flags)) 507 return wx_host_interface_command_r(wx, buffer, length, 508 timeout, return_data); 509 510 return wx_host_interface_command_s(wx, buffer, length, timeout, return_data); 511 } 512 EXPORT_SYMBOL(wx_host_interface_command); 513 514 int wx_set_pps(struct wx *wx, bool enable, u64 nsec, u64 cycles) 515 { 516 struct wx_hic_set_pps pps_cmd; 517 518 pps_cmd.hdr.cmd = FW_PPS_SET_CMD; 519 pps_cmd.hdr.buf_len = FW_PPS_SET_LEN; 520 pps_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 521 pps_cmd.lan_id = wx->bus.func; 522 pps_cmd.enable = (u8)enable; 523 pps_cmd.nsec = nsec; 524 pps_cmd.cycles = cycles; 525 pps_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 526 527 return wx_host_interface_command(wx, (u32 *)&pps_cmd, 528 sizeof(pps_cmd), 529 WX_HI_COMMAND_TIMEOUT, 530 false); 531 } 532 533 /** 534 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd 535 * assuming that the semaphore is already obtained. 536 * @wx: pointer to hardware structure 537 * @offset: offset of word in the EEPROM to read 538 * @data: word read from the EEPROM 539 * 540 * Reads a 16 bit word from the EEPROM using the hostif. 541 **/ 542 static int wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data) 543 { 544 struct wx_hic_read_shadow_ram buffer; 545 int status; 546 547 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 548 buffer.hdr.req.buf_lenh = 0; 549 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 550 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 551 552 /* convert offset from words to bytes */ 553 buffer.address = (__force u32)cpu_to_be32(offset * 2); 554 /* one word */ 555 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 556 557 status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer), 558 WX_HI_COMMAND_TIMEOUT, false); 559 560 if (status != 0) 561 return status; 562 563 if (!test_bit(WX_FLAG_SWFW_RING, wx->flags)) 564 *data = (u16)rd32a(wx, WX_MNG_MBOX, FW_NVM_DATA_OFFSET); 565 else 566 *data = (u16)rd32a(wx, WX_FW2SW_MBOX, FW_NVM_DATA_OFFSET); 567 568 return status; 569 } 570 571 /** 572 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd 573 * @wx: pointer to hardware structure 574 * @offset: offset of word in the EEPROM to read 575 * @data: word read from the EEPROM 576 * 577 * Reads a 16 bit word from the EEPROM using the hostif. 578 **/ 579 int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data) 580 { 581 int status = 0; 582 583 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 584 if (status == 0) { 585 status = wx_read_ee_hostif_data(wx, offset, data); 586 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 587 } 588 589 return status; 590 } 591 EXPORT_SYMBOL(wx_read_ee_hostif); 592 593 /** 594 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif 595 * @wx: pointer to hardware structure 596 * @offset: offset of word in the EEPROM to read 597 * @words: number of words 598 * @data: word(s) read from the EEPROM 599 * 600 * Reads a 16 bit word(s) from the EEPROM using the hostif. 601 **/ 602 int wx_read_ee_hostif_buffer(struct wx *wx, 603 u16 offset, u16 words, u16 *data) 604 { 605 struct wx_hic_read_shadow_ram buffer; 606 u32 current_word = 0; 607 u16 words_to_read; 608 u32 value = 0; 609 int status; 610 u32 mbox; 611 u32 i; 612 613 /* Take semaphore for the entire operation. */ 614 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 615 if (status != 0) 616 return status; 617 618 while (words) { 619 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 620 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 621 else 622 words_to_read = words; 623 624 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 625 buffer.hdr.req.buf_lenh = 0; 626 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 627 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 628 629 /* convert offset from words to bytes */ 630 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2); 631 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 632 633 status = wx_host_interface_command(wx, (u32 *)&buffer, 634 sizeof(buffer), 635 WX_HI_COMMAND_TIMEOUT, 636 false); 637 638 if (status != 0) { 639 wx_err(wx, "Host interface command failed\n"); 640 goto out; 641 } 642 643 if (!test_bit(WX_FLAG_SWFW_RING, wx->flags)) 644 mbox = WX_MNG_MBOX; 645 else 646 mbox = WX_FW2SW_MBOX; 647 for (i = 0; i < words_to_read; i++) { 648 u32 reg = mbox + (FW_NVM_DATA_OFFSET << 2) + 2 * i; 649 650 value = rd32(wx, reg); 651 data[current_word] = (u16)(value & 0xffff); 652 current_word++; 653 i++; 654 if (i < words_to_read) { 655 value >>= 16; 656 data[current_word] = (u16)(value & 0xffff); 657 current_word++; 658 } 659 } 660 words -= words_to_read; 661 } 662 663 out: 664 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 665 return status; 666 } 667 EXPORT_SYMBOL(wx_read_ee_hostif_buffer); 668 669 /** 670 * wx_init_eeprom_params - Initialize EEPROM params 671 * @wx: pointer to hardware structure 672 * 673 * Initializes the EEPROM parameters wx_eeprom_info within the 674 * wx_hw struct in order to set up EEPROM access. 675 **/ 676 void wx_init_eeprom_params(struct wx *wx) 677 { 678 struct wx_eeprom_info *eeprom = &wx->eeprom; 679 u16 eeprom_size; 680 u16 data = 0x80; 681 682 if (eeprom->type == wx_eeprom_uninitialized) { 683 eeprom->semaphore_delay = 10; 684 eeprom->type = wx_eeprom_none; 685 686 if (!(rd32(wx, WX_SPI_STATUS) & 687 WX_SPI_STATUS_FLASH_BYPASS)) { 688 eeprom->type = wx_flash; 689 690 eeprom_size = 4096; 691 eeprom->word_size = eeprom_size >> 1; 692 693 wx_dbg(wx, "Eeprom params: type = %d, size = %d\n", 694 eeprom->type, eeprom->word_size); 695 } 696 } 697 698 switch (wx->mac.type) { 699 case wx_mac_sp: 700 case wx_mac_aml: 701 if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) { 702 wx_err(wx, "NVM Read Error\n"); 703 return; 704 } 705 data = data >> 1; 706 break; 707 default: 708 break; 709 } 710 711 eeprom->sw_region_offset = data; 712 } 713 EXPORT_SYMBOL(wx_init_eeprom_params); 714 715 /** 716 * wx_get_mac_addr - Generic get MAC address 717 * @wx: pointer to hardware structure 718 * @mac_addr: Adapter MAC address 719 * 720 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 721 * A reset of the adapter must be performed prior to calling this function 722 * in order for the MAC address to have been loaded from the EEPROM into RAR0 723 **/ 724 void wx_get_mac_addr(struct wx *wx, u8 *mac_addr) 725 { 726 u32 rar_high; 727 u32 rar_low; 728 u16 i; 729 730 wr32(wx, WX_PSR_MAC_SWC_IDX, 0); 731 rar_high = rd32(wx, WX_PSR_MAC_SWC_AD_H); 732 rar_low = rd32(wx, WX_PSR_MAC_SWC_AD_L); 733 734 for (i = 0; i < 2; i++) 735 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8); 736 737 for (i = 0; i < 4; i++) 738 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8); 739 } 740 EXPORT_SYMBOL(wx_get_mac_addr); 741 742 /** 743 * wx_set_rar - Set Rx address register 744 * @wx: pointer to hardware structure 745 * @index: Receive address register to write 746 * @addr: Address to put into receive address register 747 * @pools: VMDq "set" or "pool" index 748 * @enable_addr: set flag that address is active 749 * 750 * Puts an ethernet address into a receive address register. 751 **/ 752 static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools, 753 u32 enable_addr) 754 { 755 u32 rar_entries = wx->mac.num_rar_entries; 756 u32 rar_low, rar_high; 757 758 /* Make sure we are using a valid rar index range */ 759 if (index >= rar_entries) { 760 wx_err(wx, "RAR index %d is out of range.\n", index); 761 return -EINVAL; 762 } 763 764 /* select the MAC address */ 765 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 766 767 /* setup VMDq pool mapping */ 768 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF); 769 770 switch (wx->mac.type) { 771 case wx_mac_sp: 772 case wx_mac_aml: 773 wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32); 774 break; 775 default: 776 break; 777 } 778 779 /* HW expects these in little endian so we reverse the byte 780 * order from network order (big endian) to little endian 781 * 782 * Some parts put the VMDq setting in the extra RAH bits, 783 * so save everything except the lower 16 bits that hold part 784 * of the address and the address valid bit. 785 */ 786 rar_low = ((u32)addr[5] | 787 ((u32)addr[4] << 8) | 788 ((u32)addr[3] << 16) | 789 ((u32)addr[2] << 24)); 790 rar_high = ((u32)addr[1] | 791 ((u32)addr[0] << 8)); 792 if (enable_addr != 0) 793 rar_high |= WX_PSR_MAC_SWC_AD_H_AV; 794 795 wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low); 796 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 797 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 798 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 799 WX_PSR_MAC_SWC_AD_H_AV), 800 rar_high); 801 802 return 0; 803 } 804 805 /** 806 * wx_clear_rar - Remove Rx address register 807 * @wx: pointer to hardware structure 808 * @index: Receive address register to write 809 * 810 * Clears an ethernet address from a receive address register. 811 **/ 812 static int wx_clear_rar(struct wx *wx, u32 index) 813 { 814 u32 rar_entries = wx->mac.num_rar_entries; 815 816 /* Make sure we are using a valid rar index range */ 817 if (index >= rar_entries) { 818 wx_err(wx, "RAR index %d is out of range.\n", index); 819 return -EINVAL; 820 } 821 822 /* Some parts put the VMDq setting in the extra RAH bits, 823 * so save everything except the lower 16 bits that hold part 824 * of the address and the address valid bit. 825 */ 826 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 827 828 wr32(wx, WX_PSR_MAC_SWC_VM_L, 0); 829 wr32(wx, WX_PSR_MAC_SWC_VM_H, 0); 830 831 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 832 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 833 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 834 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 835 WX_PSR_MAC_SWC_AD_H_AV), 836 0); 837 838 return 0; 839 } 840 841 /** 842 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address 843 * @wx: pointer to hardware struct 844 * @rar: receive address register index to disassociate 845 * @vmdq: VMDq pool index to remove from the rar 846 **/ 847 static int wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq) 848 { 849 u32 rar_entries = wx->mac.num_rar_entries; 850 u32 mpsar_lo, mpsar_hi; 851 852 /* Make sure we are using a valid rar index range */ 853 if (rar >= rar_entries) { 854 wx_err(wx, "RAR index %d is out of range.\n", rar); 855 return -EINVAL; 856 } 857 858 wr32(wx, WX_PSR_MAC_SWC_IDX, rar); 859 mpsar_lo = rd32(wx, WX_PSR_MAC_SWC_VM_L); 860 mpsar_hi = rd32(wx, WX_PSR_MAC_SWC_VM_H); 861 862 if (!mpsar_lo && !mpsar_hi) 863 return 0; 864 865 /* was that the last pool using this rar? */ 866 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 867 wx_clear_rar(wx, rar); 868 869 return 0; 870 } 871 872 /** 873 * wx_init_uta_tables - Initialize the Unicast Table Array 874 * @wx: pointer to hardware structure 875 **/ 876 static void wx_init_uta_tables(struct wx *wx) 877 { 878 int i; 879 880 wx_dbg(wx, " Clearing UTA\n"); 881 882 for (i = 0; i < 128; i++) 883 wr32(wx, WX_PSR_UC_TBL(i), 0); 884 } 885 886 /** 887 * wx_init_rx_addrs - Initializes receive address filters. 888 * @wx: pointer to hardware structure 889 * 890 * Places the MAC address in receive address register 0 and clears the rest 891 * of the receive address registers. Clears the multicast table. Assumes 892 * the receiver is in reset when the routine is called. 893 **/ 894 void wx_init_rx_addrs(struct wx *wx) 895 { 896 u32 rar_entries = wx->mac.num_rar_entries; 897 u32 psrctl; 898 int i; 899 900 /* If the current mac address is valid, assume it is a software override 901 * to the permanent address. 902 * Otherwise, use the permanent address from the eeprom. 903 */ 904 if (!is_valid_ether_addr(wx->mac.addr)) { 905 /* Get the MAC address from the RAR0 for later reference */ 906 wx_get_mac_addr(wx, wx->mac.addr); 907 wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr); 908 } else { 909 /* Setup the receive address. */ 910 wx_dbg(wx, "Overriding MAC Address in RAR[0]\n"); 911 wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr); 912 913 wx_set_rar(wx, 0, wx->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV); 914 915 switch (wx->mac.type) { 916 case wx_mac_sp: 917 case wx_mac_aml: 918 /* clear VMDq pool/queue selection for RAR 0 */ 919 wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL); 920 break; 921 default: 922 break; 923 } 924 } 925 926 /* Zero out the other receive addresses. */ 927 wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1); 928 for (i = 1; i < rar_entries; i++) { 929 wr32(wx, WX_PSR_MAC_SWC_IDX, i); 930 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 931 wr32(wx, WX_PSR_MAC_SWC_AD_H, 0); 932 } 933 934 /* Clear the MTA */ 935 wx->addr_ctrl.mta_in_use = 0; 936 psrctl = rd32(wx, WX_PSR_CTL); 937 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 938 psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT; 939 wr32(wx, WX_PSR_CTL, psrctl); 940 wx_dbg(wx, " Clearing MTA\n"); 941 for (i = 0; i < wx->mac.mcft_size; i++) 942 wr32(wx, WX_PSR_MC_TBL(i), 0); 943 944 wx_init_uta_tables(wx); 945 } 946 EXPORT_SYMBOL(wx_init_rx_addrs); 947 948 static void wx_sync_mac_table(struct wx *wx) 949 { 950 int i; 951 952 for (i = 0; i < wx->mac.num_rar_entries; i++) { 953 if (wx->mac_table[i].state & WX_MAC_STATE_MODIFIED) { 954 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 955 wx_set_rar(wx, i, 956 wx->mac_table[i].addr, 957 wx->mac_table[i].pools, 958 WX_PSR_MAC_SWC_AD_H_AV); 959 } else { 960 wx_clear_rar(wx, i); 961 } 962 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 963 } 964 } 965 } 966 967 /* this function destroys the first RAR entry */ 968 void wx_mac_set_default_filter(struct wx *wx, u8 *addr) 969 { 970 memcpy(&wx->mac_table[0].addr, addr, ETH_ALEN); 971 wx->mac_table[0].pools = 1ULL; 972 wx->mac_table[0].state = (WX_MAC_STATE_DEFAULT | WX_MAC_STATE_IN_USE); 973 wx_set_rar(wx, 0, wx->mac_table[0].addr, 974 wx->mac_table[0].pools, 975 WX_PSR_MAC_SWC_AD_H_AV); 976 } 977 EXPORT_SYMBOL(wx_mac_set_default_filter); 978 979 void wx_flush_sw_mac_table(struct wx *wx) 980 { 981 u32 i; 982 983 for (i = 0; i < wx->mac.num_rar_entries; i++) { 984 if (!(wx->mac_table[i].state & WX_MAC_STATE_IN_USE)) 985 continue; 986 987 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 988 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 989 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 990 wx->mac_table[i].pools = 0; 991 } 992 wx_sync_mac_table(wx); 993 } 994 EXPORT_SYMBOL(wx_flush_sw_mac_table); 995 996 static int wx_add_mac_filter(struct wx *wx, u8 *addr, u16 pool) 997 { 998 u32 i; 999 1000 if (is_zero_ether_addr(addr)) 1001 return -EINVAL; 1002 1003 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1004 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 1005 if (ether_addr_equal(addr, wx->mac_table[i].addr)) { 1006 if (wx->mac_table[i].pools != (1ULL << pool)) { 1007 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 1008 wx->mac_table[i].pools |= (1ULL << pool); 1009 wx_sync_mac_table(wx); 1010 return i; 1011 } 1012 } 1013 } 1014 1015 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) 1016 continue; 1017 wx->mac_table[i].state |= (WX_MAC_STATE_MODIFIED | 1018 WX_MAC_STATE_IN_USE); 1019 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 1020 wx->mac_table[i].pools |= (1ULL << pool); 1021 wx_sync_mac_table(wx); 1022 return i; 1023 } 1024 return -ENOMEM; 1025 } 1026 1027 static int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool) 1028 { 1029 u32 i; 1030 1031 if (is_zero_ether_addr(addr)) 1032 return -EINVAL; 1033 1034 /* search table for addr, if found, set to 0 and sync */ 1035 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1036 if (!ether_addr_equal(addr, wx->mac_table[i].addr)) 1037 continue; 1038 1039 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 1040 wx->mac_table[i].pools &= ~(1ULL << pool); 1041 if (!wx->mac_table[i].pools) { 1042 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 1043 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 1044 } 1045 wx_sync_mac_table(wx); 1046 return 0; 1047 } 1048 return -ENOMEM; 1049 } 1050 1051 static int wx_available_rars(struct wx *wx) 1052 { 1053 u32 i, count = 0; 1054 1055 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1056 if (wx->mac_table[i].state == 0) 1057 count++; 1058 } 1059 1060 return count; 1061 } 1062 1063 /** 1064 * wx_write_uc_addr_list - write unicast addresses to RAR table 1065 * @netdev: network interface device structure 1066 * @pool: index for mac table 1067 * 1068 * Writes unicast address list to the RAR table. 1069 * Returns: -ENOMEM on failure/insufficient address space 1070 * 0 on no addresses written 1071 * X on writing X addresses to the RAR table 1072 **/ 1073 static int wx_write_uc_addr_list(struct net_device *netdev, int pool) 1074 { 1075 struct wx *wx = netdev_priv(netdev); 1076 int count = 0; 1077 1078 /* return ENOMEM indicating insufficient memory for addresses */ 1079 if (netdev_uc_count(netdev) > wx_available_rars(wx)) 1080 return -ENOMEM; 1081 1082 if (!netdev_uc_empty(netdev)) { 1083 struct netdev_hw_addr *ha; 1084 1085 netdev_for_each_uc_addr(ha, netdev) { 1086 wx_del_mac_filter(wx, ha->addr, pool); 1087 wx_add_mac_filter(wx, ha->addr, pool); 1088 count++; 1089 } 1090 } 1091 return count; 1092 } 1093 1094 /** 1095 * wx_mta_vector - Determines bit-vector in multicast table to set 1096 * @wx: pointer to private structure 1097 * @mc_addr: the multicast address 1098 * 1099 * Extracts the 12 bits, from a multicast address, to determine which 1100 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1101 * incoming rx multicast addresses, to determine the bit-vector to check in 1102 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1103 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1104 * to mc_filter_type. 1105 **/ 1106 static u32 wx_mta_vector(struct wx *wx, u8 *mc_addr) 1107 { 1108 u32 vector = 0; 1109 1110 switch (wx->mac.mc_filter_type) { 1111 case 0: /* use bits [47:36] of the address */ 1112 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1113 break; 1114 case 1: /* use bits [46:35] of the address */ 1115 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1116 break; 1117 case 2: /* use bits [45:34] of the address */ 1118 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1119 break; 1120 case 3: /* use bits [43:32] of the address */ 1121 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1122 break; 1123 default: /* Invalid mc_filter_type */ 1124 wx_err(wx, "MC filter type param set incorrectly\n"); 1125 break; 1126 } 1127 1128 /* vector can only be 12-bits or boundary will be exceeded */ 1129 vector &= 0xFFF; 1130 return vector; 1131 } 1132 1133 /** 1134 * wx_set_mta - Set bit-vector in multicast table 1135 * @wx: pointer to private structure 1136 * @mc_addr: Multicast address 1137 * 1138 * Sets the bit-vector in the multicast table. 1139 **/ 1140 static void wx_set_mta(struct wx *wx, u8 *mc_addr) 1141 { 1142 u32 vector, vector_bit, vector_reg; 1143 1144 wx->addr_ctrl.mta_in_use++; 1145 1146 vector = wx_mta_vector(wx, mc_addr); 1147 wx_dbg(wx, " bit-vector = 0x%03X\n", vector); 1148 1149 /* The MTA is a register array of 128 32-bit registers. It is treated 1150 * like an array of 4096 bits. We want to set bit 1151 * BitArray[vector_value]. So we figure out what register the bit is 1152 * in, read it, OR in the new bit, then write back the new value. The 1153 * register is determined by the upper 7 bits of the vector value and 1154 * the bit within that register are determined by the lower 5 bits of 1155 * the value. 1156 */ 1157 vector_reg = (vector >> 5) & 0x7F; 1158 vector_bit = vector & 0x1F; 1159 wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 1160 } 1161 1162 /** 1163 * wx_update_mc_addr_list - Updates MAC list of multicast addresses 1164 * @wx: pointer to private structure 1165 * @netdev: pointer to net device structure 1166 * 1167 * The given list replaces any existing list. Clears the MC addrs from receive 1168 * address registers and the multicast table. Uses unused receive address 1169 * registers for the first multicast addresses, and hashes the rest into the 1170 * multicast table. 1171 **/ 1172 static void wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev) 1173 { 1174 struct netdev_hw_addr *ha; 1175 u32 i, psrctl; 1176 1177 /* Set the new number of MC addresses that we are being requested to 1178 * use. 1179 */ 1180 wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 1181 wx->addr_ctrl.mta_in_use = 0; 1182 1183 /* Clear mta_shadow */ 1184 wx_dbg(wx, " Clearing MTA\n"); 1185 memset(&wx->mac.mta_shadow, 0, sizeof(wx->mac.mta_shadow)); 1186 1187 /* Update mta_shadow */ 1188 netdev_for_each_mc_addr(ha, netdev) { 1189 wx_dbg(wx, " Adding the multicast addresses:\n"); 1190 wx_set_mta(wx, ha->addr); 1191 } 1192 1193 /* Enable mta */ 1194 for (i = 0; i < wx->mac.mcft_size; i++) 1195 wr32a(wx, WX_PSR_MC_TBL(0), i, 1196 wx->mac.mta_shadow[i]); 1197 1198 if (wx->addr_ctrl.mta_in_use > 0) { 1199 psrctl = rd32(wx, WX_PSR_CTL); 1200 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 1201 psrctl |= WX_PSR_CTL_MFE | 1202 (wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT); 1203 wr32(wx, WX_PSR_CTL, psrctl); 1204 } 1205 1206 wx_dbg(wx, "Update mc addr list Complete\n"); 1207 } 1208 1209 /** 1210 * wx_write_mc_addr_list - write multicast addresses to MTA 1211 * @netdev: network interface device structure 1212 * 1213 * Writes multicast address list to the MTA hash table. 1214 * Returns: 0 on no addresses written 1215 * X on writing X addresses to MTA 1216 **/ 1217 static int wx_write_mc_addr_list(struct net_device *netdev) 1218 { 1219 struct wx *wx = netdev_priv(netdev); 1220 1221 if (!netif_running(netdev)) 1222 return 0; 1223 1224 wx_update_mc_addr_list(wx, netdev); 1225 1226 return netdev_mc_count(netdev); 1227 } 1228 1229 /** 1230 * wx_set_mac - Change the Ethernet Address of the NIC 1231 * @netdev: network interface device structure 1232 * @p: pointer to an address structure 1233 * 1234 * Returns 0 on success, negative on failure 1235 **/ 1236 int wx_set_mac(struct net_device *netdev, void *p) 1237 { 1238 struct wx *wx = netdev_priv(netdev); 1239 struct sockaddr *addr = p; 1240 int retval; 1241 1242 retval = eth_prepare_mac_addr_change(netdev, addr); 1243 if (retval) 1244 return retval; 1245 1246 wx_del_mac_filter(wx, wx->mac.addr, 0); 1247 eth_hw_addr_set(netdev, addr->sa_data); 1248 memcpy(wx->mac.addr, addr->sa_data, netdev->addr_len); 1249 1250 wx_mac_set_default_filter(wx, wx->mac.addr); 1251 1252 return 0; 1253 } 1254 EXPORT_SYMBOL(wx_set_mac); 1255 1256 void wx_disable_rx(struct wx *wx) 1257 { 1258 u32 pfdtxgswc; 1259 u32 rxctrl; 1260 1261 rxctrl = rd32(wx, WX_RDB_PB_CTL); 1262 if (rxctrl & WX_RDB_PB_CTL_RXEN) { 1263 pfdtxgswc = rd32(wx, WX_PSR_CTL); 1264 if (pfdtxgswc & WX_PSR_CTL_SW_EN) { 1265 pfdtxgswc &= ~WX_PSR_CTL_SW_EN; 1266 wr32(wx, WX_PSR_CTL, pfdtxgswc); 1267 wx->mac.set_lben = true; 1268 } else { 1269 wx->mac.set_lben = false; 1270 } 1271 rxctrl &= ~WX_RDB_PB_CTL_RXEN; 1272 wr32(wx, WX_RDB_PB_CTL, rxctrl); 1273 1274 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 1275 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 1276 /* disable mac receiver */ 1277 wr32m(wx, WX_MAC_RX_CFG, 1278 WX_MAC_RX_CFG_RE, 0); 1279 } 1280 } 1281 } 1282 EXPORT_SYMBOL(wx_disable_rx); 1283 1284 static void wx_enable_rx(struct wx *wx) 1285 { 1286 u32 psrctl; 1287 1288 /* enable mac receiver */ 1289 wr32m(wx, WX_MAC_RX_CFG, 1290 WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 1291 1292 wr32m(wx, WX_RDB_PB_CTL, 1293 WX_RDB_PB_CTL_RXEN, WX_RDB_PB_CTL_RXEN); 1294 1295 if (wx->mac.set_lben) { 1296 psrctl = rd32(wx, WX_PSR_CTL); 1297 psrctl |= WX_PSR_CTL_SW_EN; 1298 wr32(wx, WX_PSR_CTL, psrctl); 1299 wx->mac.set_lben = false; 1300 } 1301 } 1302 1303 /** 1304 * wx_set_rxpba - Initialize Rx packet buffer 1305 * @wx: pointer to private structure 1306 **/ 1307 static void wx_set_rxpba(struct wx *wx) 1308 { 1309 u32 rxpktsize, txpktsize, txpbthresh; 1310 u32 pbsize = wx->mac.rx_pb_size; 1311 1312 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 1313 if (test_bit(WX_FLAG_FDIR_HASH, wx->flags) || 1314 test_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 1315 pbsize -= 64; /* Default 64KB */ 1316 } 1317 1318 rxpktsize = pbsize << WX_RDB_PB_SZ_SHIFT; 1319 wr32(wx, WX_RDB_PB_SZ(0), rxpktsize); 1320 1321 /* Only support an equally distributed Tx packet buffer strategy. */ 1322 txpktsize = wx->mac.tx_pb_size; 1323 txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX; 1324 wr32(wx, WX_TDB_PB_SZ(0), txpktsize); 1325 wr32(wx, WX_TDM_PB_THRE(0), txpbthresh); 1326 } 1327 1328 #define WX_ETH_FRAMING 20 1329 1330 /** 1331 * wx_hpbthresh - calculate high water mark for flow control 1332 * 1333 * @wx: board private structure to calculate for 1334 **/ 1335 static int wx_hpbthresh(struct wx *wx) 1336 { 1337 struct net_device *dev = wx->netdev; 1338 int link, tc, kb, marker; 1339 u32 dv_id, rx_pba; 1340 1341 /* Calculate max LAN frame size */ 1342 link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + WX_ETH_FRAMING; 1343 tc = link; 1344 1345 /* Calculate delay value for device */ 1346 dv_id = WX_DV(link, tc); 1347 1348 /* Delay value is calculated in bit times convert to KB */ 1349 kb = WX_BT2KB(dv_id); 1350 rx_pba = rd32(wx, WX_RDB_PB_SZ(0)) >> WX_RDB_PB_SZ_SHIFT; 1351 1352 marker = rx_pba - kb; 1353 1354 /* It is possible that the packet buffer is not large enough 1355 * to provide required headroom. In this case throw an error 1356 * to user and a do the best we can. 1357 */ 1358 if (marker < 0) { 1359 dev_warn(&wx->pdev->dev, 1360 "Packet Buffer can not provide enough headroom to support flow control. Decrease MTU or number of traffic classes\n"); 1361 marker = tc + 1; 1362 } 1363 1364 return marker; 1365 } 1366 1367 /** 1368 * wx_lpbthresh - calculate low water mark for flow control 1369 * 1370 * @wx: board private structure to calculate for 1371 **/ 1372 static int wx_lpbthresh(struct wx *wx) 1373 { 1374 struct net_device *dev = wx->netdev; 1375 u32 dv_id; 1376 int tc; 1377 1378 /* Calculate max LAN frame size */ 1379 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 1380 1381 /* Calculate delay value for device */ 1382 dv_id = WX_LOW_DV(tc); 1383 1384 /* Delay value is calculated in bit times convert to KB */ 1385 return WX_BT2KB(dv_id); 1386 } 1387 1388 /** 1389 * wx_pbthresh_setup - calculate and setup high low water marks 1390 * 1391 * @wx: board private structure to calculate for 1392 **/ 1393 static void wx_pbthresh_setup(struct wx *wx) 1394 { 1395 wx->fc.high_water = wx_hpbthresh(wx); 1396 wx->fc.low_water = wx_lpbthresh(wx); 1397 1398 /* Low water marks must not be larger than high water marks */ 1399 if (wx->fc.low_water > wx->fc.high_water) 1400 wx->fc.low_water = 0; 1401 } 1402 1403 static void wx_configure_port(struct wx *wx) 1404 { 1405 u32 value, i; 1406 1407 value = WX_CFG_PORT_CTL_D_VLAN | WX_CFG_PORT_CTL_QINQ; 1408 wr32m(wx, WX_CFG_PORT_CTL, 1409 WX_CFG_PORT_CTL_D_VLAN | 1410 WX_CFG_PORT_CTL_QINQ, 1411 value); 1412 1413 wr32(wx, WX_CFG_TAG_TPID(0), 1414 ETH_P_8021Q | ETH_P_8021AD << 16); 1415 wx->tpid[0] = ETH_P_8021Q; 1416 wx->tpid[1] = ETH_P_8021AD; 1417 for (i = 1; i < 4; i++) 1418 wr32(wx, WX_CFG_TAG_TPID(i), 1419 ETH_P_8021Q | ETH_P_8021Q << 16); 1420 for (i = 2; i < 8; i++) 1421 wx->tpid[i] = ETH_P_8021Q; 1422 } 1423 1424 /** 1425 * wx_disable_sec_rx_path - Stops the receive data path 1426 * @wx: pointer to private structure 1427 * 1428 * Stops the receive data path and waits for the HW to internally empty 1429 * the Rx security block 1430 **/ 1431 int wx_disable_sec_rx_path(struct wx *wx) 1432 { 1433 u32 secrx; 1434 1435 wr32m(wx, WX_RSC_CTL, 1436 WX_RSC_CTL_RX_DIS, WX_RSC_CTL_RX_DIS); 1437 1438 return read_poll_timeout(rd32, secrx, secrx & WX_RSC_ST_RSEC_RDY, 1439 1000, 40000, false, wx, WX_RSC_ST); 1440 } 1441 EXPORT_SYMBOL(wx_disable_sec_rx_path); 1442 1443 /** 1444 * wx_enable_sec_rx_path - Enables the receive data path 1445 * @wx: pointer to private structure 1446 * 1447 * Enables the receive data path. 1448 **/ 1449 void wx_enable_sec_rx_path(struct wx *wx) 1450 { 1451 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_RX_DIS, 0); 1452 WX_WRITE_FLUSH(wx); 1453 } 1454 EXPORT_SYMBOL(wx_enable_sec_rx_path); 1455 1456 static void wx_vlan_strip_control(struct wx *wx, bool enable) 1457 { 1458 int i, j; 1459 1460 for (i = 0; i < wx->num_rx_queues; i++) { 1461 struct wx_ring *ring = wx->rx_ring[i]; 1462 1463 j = ring->reg_idx; 1464 wr32m(wx, WX_PX_RR_CFG(j), WX_PX_RR_CFG_VLAN, 1465 enable ? WX_PX_RR_CFG_VLAN : 0); 1466 } 1467 } 1468 1469 void wx_set_rx_mode(struct net_device *netdev) 1470 { 1471 struct wx *wx = netdev_priv(netdev); 1472 netdev_features_t features; 1473 u32 fctrl, vmolr, vlnctrl; 1474 int count; 1475 1476 features = netdev->features; 1477 1478 /* Check for Promiscuous and All Multicast modes */ 1479 fctrl = rd32(wx, WX_PSR_CTL); 1480 fctrl &= ~(WX_PSR_CTL_UPE | WX_PSR_CTL_MPE); 1481 vmolr = rd32(wx, WX_PSR_VM_L2CTL(0)); 1482 vmolr &= ~(WX_PSR_VM_L2CTL_UPE | 1483 WX_PSR_VM_L2CTL_MPE | 1484 WX_PSR_VM_L2CTL_ROPE | 1485 WX_PSR_VM_L2CTL_ROMPE); 1486 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1487 vlnctrl &= ~(WX_PSR_VLAN_CTL_VFE | WX_PSR_VLAN_CTL_CFIEN); 1488 1489 /* set all bits that we expect to always be set */ 1490 fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE; 1491 vmolr |= WX_PSR_VM_L2CTL_BAM | 1492 WX_PSR_VM_L2CTL_AUPE | 1493 WX_PSR_VM_L2CTL_VACC; 1494 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1495 1496 wx->addr_ctrl.user_set_promisc = false; 1497 if (netdev->flags & IFF_PROMISC) { 1498 wx->addr_ctrl.user_set_promisc = true; 1499 fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE; 1500 /* pf don't want packets routing to vf, so clear UPE */ 1501 vmolr |= WX_PSR_VM_L2CTL_MPE; 1502 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1503 } 1504 1505 if (netdev->flags & IFF_ALLMULTI) { 1506 fctrl |= WX_PSR_CTL_MPE; 1507 vmolr |= WX_PSR_VM_L2CTL_MPE; 1508 } 1509 1510 if (netdev->features & NETIF_F_RXALL) { 1511 vmolr |= (WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_MPE); 1512 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1513 /* receive bad packets */ 1514 wr32m(wx, WX_RSC_CTL, 1515 WX_RSC_CTL_SAVE_MAC_ERR, 1516 WX_RSC_CTL_SAVE_MAC_ERR); 1517 } else { 1518 vmolr |= WX_PSR_VM_L2CTL_ROPE | WX_PSR_VM_L2CTL_ROMPE; 1519 } 1520 1521 /* Write addresses to available RAR registers, if there is not 1522 * sufficient space to store all the addresses then enable 1523 * unicast promiscuous mode 1524 */ 1525 count = wx_write_uc_addr_list(netdev, 0); 1526 if (count < 0) { 1527 vmolr &= ~WX_PSR_VM_L2CTL_ROPE; 1528 vmolr |= WX_PSR_VM_L2CTL_UPE; 1529 } 1530 1531 /* Write addresses to the MTA, if the attempt fails 1532 * then we should just turn on promiscuous mode so 1533 * that we can at least receive multicast traffic 1534 */ 1535 count = wx_write_mc_addr_list(netdev); 1536 if (count < 0) { 1537 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE; 1538 vmolr |= WX_PSR_VM_L2CTL_MPE; 1539 } 1540 1541 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1542 wr32(wx, WX_PSR_CTL, fctrl); 1543 wr32(wx, WX_PSR_VM_L2CTL(0), vmolr); 1544 1545 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && 1546 (features & NETIF_F_HW_VLAN_STAG_RX)) 1547 wx_vlan_strip_control(wx, true); 1548 else 1549 wx_vlan_strip_control(wx, false); 1550 1551 } 1552 EXPORT_SYMBOL(wx_set_rx_mode); 1553 1554 static void wx_set_rx_buffer_len(struct wx *wx) 1555 { 1556 struct net_device *netdev = wx->netdev; 1557 u32 mhadd, max_frame; 1558 1559 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 1560 /* adjust max frame to be at least the size of a standard frame */ 1561 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 1562 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 1563 1564 mhadd = rd32(wx, WX_PSR_MAX_SZ); 1565 if (max_frame != mhadd) 1566 wr32(wx, WX_PSR_MAX_SZ, max_frame); 1567 } 1568 1569 /** 1570 * wx_change_mtu - Change the Maximum Transfer Unit 1571 * @netdev: network interface device structure 1572 * @new_mtu: new value for maximum frame size 1573 * 1574 * Returns 0 on success, negative on failure 1575 **/ 1576 int wx_change_mtu(struct net_device *netdev, int new_mtu) 1577 { 1578 struct wx *wx = netdev_priv(netdev); 1579 1580 WRITE_ONCE(netdev->mtu, new_mtu); 1581 wx_set_rx_buffer_len(wx); 1582 1583 return 0; 1584 } 1585 EXPORT_SYMBOL(wx_change_mtu); 1586 1587 /* Disable the specified rx queue */ 1588 void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring) 1589 { 1590 u8 reg_idx = ring->reg_idx; 1591 u32 rxdctl; 1592 int ret; 1593 1594 /* write value back with RRCFG.EN bit cleared */ 1595 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1596 WX_PX_RR_CFG_RR_EN, 0); 1597 1598 /* the hardware may take up to 100us to really disable the rx queue */ 1599 ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN), 1600 10, 100, true, wx, WX_PX_RR_CFG(reg_idx)); 1601 1602 if (ret == -ETIMEDOUT) { 1603 /* Just for information */ 1604 wx_err(wx, 1605 "RRCFG.EN on Rx queue %d not cleared within the polling period\n", 1606 reg_idx); 1607 } 1608 } 1609 EXPORT_SYMBOL(wx_disable_rx_queue); 1610 1611 static void wx_enable_rx_queue(struct wx *wx, struct wx_ring *ring) 1612 { 1613 u8 reg_idx = ring->reg_idx; 1614 u32 rxdctl; 1615 int ret; 1616 1617 ret = read_poll_timeout(rd32, rxdctl, rxdctl & WX_PX_RR_CFG_RR_EN, 1618 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx)); 1619 1620 if (ret == -ETIMEDOUT) { 1621 /* Just for information */ 1622 wx_err(wx, 1623 "RRCFG.EN on Rx queue %d not set within the polling period\n", 1624 reg_idx); 1625 } 1626 } 1627 1628 static void wx_configure_srrctl(struct wx *wx, 1629 struct wx_ring *rx_ring) 1630 { 1631 u16 reg_idx = rx_ring->reg_idx; 1632 u32 srrctl; 1633 1634 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1635 srrctl &= ~(WX_PX_RR_CFG_RR_HDR_SZ | 1636 WX_PX_RR_CFG_RR_BUF_SZ | 1637 WX_PX_RR_CFG_SPLIT_MODE); 1638 /* configure header buffer length, needed for RSC */ 1639 srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT; 1640 1641 /* configure the packet buffer length */ 1642 srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT; 1643 1644 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 1645 } 1646 1647 static void wx_configure_tx_ring(struct wx *wx, 1648 struct wx_ring *ring) 1649 { 1650 u32 txdctl = WX_PX_TR_CFG_ENABLE; 1651 u8 reg_idx = ring->reg_idx; 1652 u64 tdba = ring->dma; 1653 int ret; 1654 1655 /* disable queue to avoid issues while updating state */ 1656 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH); 1657 WX_WRITE_FLUSH(wx); 1658 1659 wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32)); 1660 wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba)); 1661 1662 /* reset head and tail pointers */ 1663 wr32(wx, WX_PX_TR_RP(reg_idx), 0); 1664 wr32(wx, WX_PX_TR_WP(reg_idx), 0); 1665 ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx); 1666 1667 if (ring->count < WX_MAX_TXD) 1668 txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT; 1669 txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT; 1670 1671 ring->atr_count = 0; 1672 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && 1673 test_bit(WX_FLAG_FDIR_HASH, wx->flags)) 1674 ring->atr_sample_rate = wx->atr_sample_rate; 1675 else 1676 ring->atr_sample_rate = 0; 1677 1678 /* reinitialize tx_buffer_info */ 1679 memset(ring->tx_buffer_info, 0, 1680 sizeof(struct wx_tx_buffer) * ring->count); 1681 1682 /* enable queue */ 1683 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl); 1684 1685 /* poll to verify queue is enabled */ 1686 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE, 1687 1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx)); 1688 if (ret == -ETIMEDOUT) 1689 wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx); 1690 } 1691 1692 static void wx_configure_rx_ring(struct wx *wx, 1693 struct wx_ring *ring) 1694 { 1695 u16 reg_idx = ring->reg_idx; 1696 union wx_rx_desc *rx_desc; 1697 u64 rdba = ring->dma; 1698 u32 rxdctl; 1699 1700 /* disable queue to avoid issues while updating state */ 1701 rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1702 wx_disable_rx_queue(wx, ring); 1703 1704 wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32)); 1705 wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba)); 1706 1707 if (ring->count == WX_MAX_RXD) 1708 rxdctl |= 0 << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1709 else 1710 rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1711 1712 rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT; 1713 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl); 1714 1715 /* reset head and tail pointers */ 1716 wr32(wx, WX_PX_RR_RP(reg_idx), 0); 1717 wr32(wx, WX_PX_RR_WP(reg_idx), 0); 1718 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx); 1719 1720 wx_configure_srrctl(wx, ring); 1721 1722 /* initialize rx_buffer_info */ 1723 memset(ring->rx_buffer_info, 0, 1724 sizeof(struct wx_rx_buffer) * ring->count); 1725 1726 /* initialize Rx descriptor 0 */ 1727 rx_desc = WX_RX_DESC(ring, 0); 1728 rx_desc->wb.upper.length = 0; 1729 1730 /* enable receive descriptor ring */ 1731 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1732 WX_PX_RR_CFG_RR_EN, WX_PX_RR_CFG_RR_EN); 1733 1734 wx_enable_rx_queue(wx, ring); 1735 wx_alloc_rx_buffers(ring, wx_desc_unused(ring)); 1736 } 1737 1738 /** 1739 * wx_configure_tx - Configure Transmit Unit after Reset 1740 * @wx: pointer to private structure 1741 * 1742 * Configure the Tx unit of the MAC after a reset. 1743 **/ 1744 static void wx_configure_tx(struct wx *wx) 1745 { 1746 u32 i; 1747 1748 /* TDM_CTL.TE must be before Tx queues are enabled */ 1749 wr32m(wx, WX_TDM_CTL, 1750 WX_TDM_CTL_TE, WX_TDM_CTL_TE); 1751 1752 /* Setup the HW Tx Head and Tail descriptor pointers */ 1753 for (i = 0; i < wx->num_tx_queues; i++) 1754 wx_configure_tx_ring(wx, wx->tx_ring[i]); 1755 1756 wr32m(wx, WX_TSC_BUF_AE, WX_TSC_BUF_AE_THR, 0x10); 1757 1758 if (wx->mac.type == wx_mac_em) 1759 wr32m(wx, WX_TSC_CTL, WX_TSC_CTL_TX_DIS | WX_TSC_CTL_TSEC_DIS, 0x1); 1760 1761 /* enable mac transmitter */ 1762 wr32m(wx, WX_MAC_TX_CFG, 1763 WX_MAC_TX_CFG_TE, WX_MAC_TX_CFG_TE); 1764 } 1765 1766 static void wx_restore_vlan(struct wx *wx) 1767 { 1768 u16 vid = 1; 1769 1770 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), 0); 1771 1772 for_each_set_bit_from(vid, wx->active_vlans, VLAN_N_VID) 1773 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), vid); 1774 } 1775 1776 static void wx_store_reta(struct wx *wx) 1777 { 1778 u8 *indir_tbl = wx->rss_indir_tbl; 1779 u32 reta = 0; 1780 u32 i; 1781 1782 /* Fill out the redirection table as follows: 1783 * - 8 bit wide entries containing 4 bit RSS index 1784 */ 1785 for (i = 0; i < WX_MAX_RETA_ENTRIES; i++) { 1786 reta |= indir_tbl[i] << (i & 0x3) * 8; 1787 if ((i & 3) == 3) { 1788 wr32(wx, WX_RDB_RSSTBL(i >> 2), reta); 1789 reta = 0; 1790 } 1791 } 1792 } 1793 1794 static void wx_setup_reta(struct wx *wx) 1795 { 1796 u16 rss_i = wx->ring_feature[RING_F_RSS].indices; 1797 u32 random_key_size = WX_RSS_KEY_SIZE / 4; 1798 u32 i, j; 1799 1800 /* Fill out hash function seeds */ 1801 for (i = 0; i < random_key_size; i++) 1802 wr32(wx, WX_RDB_RSSRK(i), wx->rss_key[i]); 1803 1804 /* Fill out redirection table */ 1805 memset(wx->rss_indir_tbl, 0, sizeof(wx->rss_indir_tbl)); 1806 1807 for (i = 0, j = 0; i < WX_MAX_RETA_ENTRIES; i++, j++) { 1808 if (j == rss_i) 1809 j = 0; 1810 1811 wx->rss_indir_tbl[i] = j; 1812 } 1813 1814 wx_store_reta(wx); 1815 } 1816 1817 static void wx_setup_mrqc(struct wx *wx) 1818 { 1819 u32 rss_field = 0; 1820 1821 /* Disable indicating checksum in descriptor, enables RSS hash */ 1822 wr32m(wx, WX_PSR_CTL, WX_PSR_CTL_PCSD, WX_PSR_CTL_PCSD); 1823 1824 /* Perform hash on these packet types */ 1825 rss_field = WX_RDB_RA_CTL_RSS_IPV4 | 1826 WX_RDB_RA_CTL_RSS_IPV4_TCP | 1827 WX_RDB_RA_CTL_RSS_IPV4_UDP | 1828 WX_RDB_RA_CTL_RSS_IPV6 | 1829 WX_RDB_RA_CTL_RSS_IPV6_TCP | 1830 WX_RDB_RA_CTL_RSS_IPV6_UDP; 1831 1832 netdev_rss_key_fill(wx->rss_key, sizeof(wx->rss_key)); 1833 1834 wx_setup_reta(wx); 1835 1836 if (wx->rss_enabled) 1837 rss_field |= WX_RDB_RA_CTL_RSS_EN; 1838 1839 wr32(wx, WX_RDB_RA_CTL, rss_field); 1840 } 1841 1842 /** 1843 * wx_configure_rx - Configure Receive Unit after Reset 1844 * @wx: pointer to private structure 1845 * 1846 * Configure the Rx unit of the MAC after a reset. 1847 **/ 1848 void wx_configure_rx(struct wx *wx) 1849 { 1850 u32 psrtype, i; 1851 int ret; 1852 1853 wx_disable_rx(wx); 1854 1855 psrtype = WX_RDB_PL_CFG_L4HDR | 1856 WX_RDB_PL_CFG_L3HDR | 1857 WX_RDB_PL_CFG_L2HDR | 1858 WX_RDB_PL_CFG_TUN_TUNHDR; 1859 wr32(wx, WX_RDB_PL_CFG(0), psrtype); 1860 1861 /* enable hw crc stripping */ 1862 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_CRC_STRIP, WX_RSC_CTL_CRC_STRIP); 1863 1864 if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) { 1865 u32 psrctl; 1866 1867 /* RSC Setup */ 1868 psrctl = rd32(wx, WX_PSR_CTL); 1869 psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */ 1870 psrctl |= WX_PSR_CTL_RSC_DIS; 1871 wr32(wx, WX_PSR_CTL, psrctl); 1872 } 1873 1874 wx_setup_mrqc(wx); 1875 1876 /* set_rx_buffer_len must be called before ring initialization */ 1877 wx_set_rx_buffer_len(wx); 1878 1879 /* Setup the HW Rx Head and Tail Descriptor Pointers and 1880 * the Base and Length of the Rx Descriptor Ring 1881 */ 1882 for (i = 0; i < wx->num_rx_queues; i++) 1883 wx_configure_rx_ring(wx, wx->rx_ring[i]); 1884 1885 /* Enable all receives, disable security engine prior to block traffic */ 1886 ret = wx_disable_sec_rx_path(wx); 1887 if (ret < 0) 1888 wx_err(wx, "The register status is abnormal, please check device."); 1889 1890 wx_enable_rx(wx); 1891 wx_enable_sec_rx_path(wx); 1892 } 1893 EXPORT_SYMBOL(wx_configure_rx); 1894 1895 static void wx_configure_isb(struct wx *wx) 1896 { 1897 /* set ISB Address */ 1898 wr32(wx, WX_PX_ISB_ADDR_L, wx->isb_dma & DMA_BIT_MASK(32)); 1899 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 1900 wr32(wx, WX_PX_ISB_ADDR_H, upper_32_bits(wx->isb_dma)); 1901 } 1902 1903 void wx_configure(struct wx *wx) 1904 { 1905 wx_set_rxpba(wx); 1906 wx_pbthresh_setup(wx); 1907 wx_configure_port(wx); 1908 1909 wx_set_rx_mode(wx->netdev); 1910 wx_restore_vlan(wx); 1911 1912 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) 1913 wx->configure_fdir(wx); 1914 1915 wx_configure_tx(wx); 1916 wx_configure_rx(wx); 1917 wx_configure_isb(wx); 1918 } 1919 EXPORT_SYMBOL(wx_configure); 1920 1921 /** 1922 * wx_disable_pcie_master - Disable PCI-express master access 1923 * @wx: pointer to hardware structure 1924 * 1925 * Disables PCI-Express master access and verifies there are no pending 1926 * requests. 1927 **/ 1928 int wx_disable_pcie_master(struct wx *wx) 1929 { 1930 int status = 0; 1931 u32 val; 1932 1933 /* Always set this bit to ensure any future transactions are blocked */ 1934 pci_clear_master(wx->pdev); 1935 1936 /* Exit if master requests are blocked */ 1937 if (!(rd32(wx, WX_PX_TRANSACTION_PENDING))) 1938 return 0; 1939 1940 /* Poll for master request bit to clear */ 1941 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT, 1942 false, wx, WX_PX_TRANSACTION_PENDING); 1943 if (status < 0) 1944 wx_err(wx, "PCIe transaction pending bit did not clear.\n"); 1945 1946 return status; 1947 } 1948 EXPORT_SYMBOL(wx_disable_pcie_master); 1949 1950 /** 1951 * wx_stop_adapter - Generic stop Tx/Rx units 1952 * @wx: pointer to hardware structure 1953 * 1954 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts, 1955 * disables transmit and receive units. The adapter_stopped flag is used by 1956 * the shared code and drivers to determine if the adapter is in a stopped 1957 * state and should not touch the hardware. 1958 **/ 1959 int wx_stop_adapter(struct wx *wx) 1960 { 1961 u16 i; 1962 1963 /* Set the adapter_stopped flag so other driver functions stop touching 1964 * the hardware 1965 */ 1966 wx->adapter_stopped = true; 1967 1968 /* Disable the receive unit */ 1969 wx_disable_rx(wx); 1970 1971 /* Set interrupt mask to stop interrupts from being generated */ 1972 wx_intr_disable(wx, WX_INTR_ALL); 1973 1974 /* Clear any pending interrupts, flush previous writes */ 1975 wr32(wx, WX_PX_MISC_IC, 0xffffffff); 1976 wr32(wx, WX_BME_CTL, 0x3); 1977 1978 /* Disable the transmit unit. Each queue must be disabled. */ 1979 for (i = 0; i < wx->mac.max_tx_queues; i++) { 1980 wr32m(wx, WX_PX_TR_CFG(i), 1981 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE, 1982 WX_PX_TR_CFG_SWFLSH); 1983 } 1984 1985 /* Disable the receive unit by stopping each queue */ 1986 for (i = 0; i < wx->mac.max_rx_queues; i++) { 1987 wr32m(wx, WX_PX_RR_CFG(i), 1988 WX_PX_RR_CFG_RR_EN, 0); 1989 } 1990 1991 /* flush all queues disables */ 1992 WX_WRITE_FLUSH(wx); 1993 1994 /* Prevent the PCI-E bus from hanging by disabling PCI-E master 1995 * access and verify no pending requests 1996 */ 1997 return wx_disable_pcie_master(wx); 1998 } 1999 EXPORT_SYMBOL(wx_stop_adapter); 2000 2001 void wx_reset_misc(struct wx *wx) 2002 { 2003 int i; 2004 2005 /* receive packets that size > 2048 */ 2006 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE); 2007 2008 /* clear counters on read */ 2009 wr32m(wx, WX_MMC_CONTROL, 2010 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD); 2011 2012 wr32m(wx, WX_MAC_RX_FLOW_CTRL, 2013 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE); 2014 2015 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 2016 2017 wr32m(wx, WX_MIS_RST_ST, 2018 WX_MIS_RST_ST_RST_INIT, 0x1E00); 2019 2020 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/ 2021 wr32(wx, WX_PSR_MNG_FLEX_SEL, 0); 2022 for (i = 0; i < 16; i++) { 2023 wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0); 2024 wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0); 2025 wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0); 2026 } 2027 wr32(wx, WX_PSR_LAN_FLEX_SEL, 0); 2028 for (i = 0; i < 16; i++) { 2029 wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0); 2030 wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0); 2031 wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0); 2032 } 2033 2034 /* set pause frame dst mac addr */ 2035 wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001); 2036 wr32(wx, WX_RDB_PFCMACDAH, 0x0180); 2037 } 2038 EXPORT_SYMBOL(wx_reset_misc); 2039 2040 /** 2041 * wx_get_pcie_msix_counts - Gets MSI-X vector count 2042 * @wx: pointer to hardware structure 2043 * @msix_count: number of MSI interrupts that can be obtained 2044 * @max_msix_count: number of MSI interrupts that mac need 2045 * 2046 * Read PCIe configuration space, and get the MSI-X vector count from 2047 * the capabilities table. 2048 **/ 2049 int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count) 2050 { 2051 struct pci_dev *pdev = wx->pdev; 2052 struct device *dev = &pdev->dev; 2053 int pos; 2054 2055 *msix_count = 1; 2056 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 2057 if (!pos) { 2058 dev_err(dev, "Unable to find MSI-X Capabilities\n"); 2059 return -EINVAL; 2060 } 2061 pci_read_config_word(pdev, 2062 pos + PCI_MSIX_FLAGS, 2063 msix_count); 2064 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK; 2065 /* MSI-X count is zero-based in HW */ 2066 *msix_count += 1; 2067 2068 if (*msix_count > max_msix_count) 2069 *msix_count = max_msix_count; 2070 2071 return 0; 2072 } 2073 EXPORT_SYMBOL(wx_get_pcie_msix_counts); 2074 2075 /** 2076 * wx_init_rss_key - Initialize wx RSS key 2077 * @wx: device handle 2078 * 2079 * Allocates and initializes the RSS key if it is not allocated. 2080 **/ 2081 static int wx_init_rss_key(struct wx *wx) 2082 { 2083 u32 *rss_key; 2084 2085 if (!wx->rss_key) { 2086 rss_key = kzalloc(WX_RSS_KEY_SIZE, GFP_KERNEL); 2087 if (unlikely(!rss_key)) 2088 return -ENOMEM; 2089 2090 netdev_rss_key_fill(rss_key, WX_RSS_KEY_SIZE); 2091 wx->rss_key = rss_key; 2092 } 2093 2094 return 0; 2095 } 2096 2097 int wx_sw_init(struct wx *wx) 2098 { 2099 struct pci_dev *pdev = wx->pdev; 2100 u32 ssid = 0; 2101 int err = 0; 2102 2103 wx->vendor_id = pdev->vendor; 2104 wx->device_id = pdev->device; 2105 wx->revision_id = pdev->revision; 2106 wx->oem_svid = pdev->subsystem_vendor; 2107 wx->oem_ssid = pdev->subsystem_device; 2108 wx->bus.device = PCI_SLOT(pdev->devfn); 2109 wx->bus.func = PCI_FUNC(pdev->devfn); 2110 2111 if (wx->oem_svid == PCI_VENDOR_ID_WANGXUN) { 2112 wx->subsystem_vendor_id = pdev->subsystem_vendor; 2113 wx->subsystem_device_id = pdev->subsystem_device; 2114 } else { 2115 err = wx_flash_read_dword(wx, 0xfffdc, &ssid); 2116 if (err < 0) { 2117 wx_err(wx, "read of internal subsystem device id failed\n"); 2118 return err; 2119 } 2120 2121 wx->subsystem_device_id = swab16((u16)ssid); 2122 } 2123 2124 err = wx_init_rss_key(wx); 2125 if (err < 0) { 2126 wx_err(wx, "rss key allocation failed\n"); 2127 return err; 2128 } 2129 2130 wx->mac_table = kcalloc(wx->mac.num_rar_entries, 2131 sizeof(struct wx_mac_addr), 2132 GFP_KERNEL); 2133 if (!wx->mac_table) { 2134 wx_err(wx, "mac_table allocation failed\n"); 2135 kfree(wx->rss_key); 2136 return -ENOMEM; 2137 } 2138 2139 bitmap_zero(wx->state, WX_STATE_NBITS); 2140 bitmap_zero(wx->flags, WX_PF_FLAGS_NBITS); 2141 wx->misc_irq_domain = false; 2142 2143 return 0; 2144 } 2145 EXPORT_SYMBOL(wx_sw_init); 2146 2147 /** 2148 * wx_find_vlvf_slot - find the vlanid or the first empty slot 2149 * @wx: pointer to hardware structure 2150 * @vlan: VLAN id to write to VLAN filter 2151 * 2152 * return the VLVF index where this VLAN id should be placed 2153 * 2154 **/ 2155 static int wx_find_vlvf_slot(struct wx *wx, u32 vlan) 2156 { 2157 u32 bits = 0, first_empty_slot = 0; 2158 int regindex; 2159 2160 /* short cut the special case */ 2161 if (vlan == 0) 2162 return 0; 2163 2164 /* Search for the vlan id in the VLVF entries. Save off the first empty 2165 * slot found along the way 2166 */ 2167 for (regindex = 1; regindex < WX_PSR_VLAN_SWC_ENTRIES; regindex++) { 2168 wr32(wx, WX_PSR_VLAN_SWC_IDX, regindex); 2169 bits = rd32(wx, WX_PSR_VLAN_SWC); 2170 if (!bits && !(first_empty_slot)) 2171 first_empty_slot = regindex; 2172 else if ((bits & 0x0FFF) == vlan) 2173 break; 2174 } 2175 2176 if (regindex >= WX_PSR_VLAN_SWC_ENTRIES) { 2177 if (first_empty_slot) 2178 regindex = first_empty_slot; 2179 else 2180 regindex = -ENOMEM; 2181 } 2182 2183 return regindex; 2184 } 2185 2186 /** 2187 * wx_set_vlvf - Set VLAN Pool Filter 2188 * @wx: pointer to hardware structure 2189 * @vlan: VLAN id to write to VLAN filter 2190 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2191 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2192 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 2193 * should be changed 2194 * 2195 * Turn on/off specified bit in VLVF table. 2196 **/ 2197 static int wx_set_vlvf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on, 2198 bool *vfta_changed) 2199 { 2200 int vlvf_index; 2201 u32 vt, bits; 2202 2203 /* If VT Mode is set 2204 * Either vlan_on 2205 * make sure the vlan is in VLVF 2206 * set the vind bit in the matching VLVFB 2207 * Or !vlan_on 2208 * clear the pool bit and possibly the vind 2209 */ 2210 vt = rd32(wx, WX_CFG_PORT_CTL); 2211 if (!(vt & WX_CFG_PORT_CTL_NUM_VT_MASK)) 2212 return 0; 2213 2214 vlvf_index = wx_find_vlvf_slot(wx, vlan); 2215 if (vlvf_index < 0) 2216 return vlvf_index; 2217 2218 wr32(wx, WX_PSR_VLAN_SWC_IDX, vlvf_index); 2219 if (vlan_on) { 2220 /* set the pool bit */ 2221 if (vind < 32) { 2222 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2223 bits |= (1 << vind); 2224 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits); 2225 } else { 2226 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2227 bits |= (1 << (vind - 32)); 2228 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits); 2229 } 2230 } else { 2231 /* clear the pool bit */ 2232 if (vind < 32) { 2233 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2234 bits &= ~(1 << vind); 2235 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits); 2236 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2237 } else { 2238 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2239 bits &= ~(1 << (vind - 32)); 2240 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits); 2241 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2242 } 2243 } 2244 2245 if (bits) { 2246 wr32(wx, WX_PSR_VLAN_SWC, (WX_PSR_VLAN_SWC_VIEN | vlan)); 2247 if (!vlan_on && vfta_changed) 2248 *vfta_changed = false; 2249 } else { 2250 wr32(wx, WX_PSR_VLAN_SWC, 0); 2251 } 2252 2253 return 0; 2254 } 2255 2256 /** 2257 * wx_set_vfta - Set VLAN filter table 2258 * @wx: pointer to hardware structure 2259 * @vlan: VLAN id to write to VLAN filter 2260 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2261 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2262 * 2263 * Turn on/off specified VLAN in the VLAN filter table. 2264 **/ 2265 static int wx_set_vfta(struct wx *wx, u32 vlan, u32 vind, bool vlan_on) 2266 { 2267 u32 bitindex, vfta, targetbit; 2268 bool vfta_changed = false; 2269 int regindex, ret; 2270 2271 /* this is a 2 part operation - first the VFTA, then the 2272 * VLVF and VLVFB if VT Mode is set 2273 * We don't write the VFTA until we know the VLVF part succeeded. 2274 */ 2275 2276 /* Part 1 2277 * The VFTA is a bitstring made up of 128 32-bit registers 2278 * that enable the particular VLAN id, much like the MTA: 2279 * bits[11-5]: which register 2280 * bits[4-0]: which bit in the register 2281 */ 2282 regindex = (vlan >> 5) & 0x7F; 2283 bitindex = vlan & 0x1F; 2284 targetbit = (1 << bitindex); 2285 /* errata 5 */ 2286 vfta = wx->mac.vft_shadow[regindex]; 2287 if (vlan_on) { 2288 if (!(vfta & targetbit)) { 2289 vfta |= targetbit; 2290 vfta_changed = true; 2291 } 2292 } else { 2293 if ((vfta & targetbit)) { 2294 vfta &= ~targetbit; 2295 vfta_changed = true; 2296 } 2297 } 2298 /* Part 2 2299 * Call wx_set_vlvf to set VLVFB and VLVF 2300 */ 2301 ret = wx_set_vlvf(wx, vlan, vind, vlan_on, &vfta_changed); 2302 if (ret != 0) 2303 return ret; 2304 2305 if (vfta_changed) 2306 wr32(wx, WX_PSR_VLAN_TBL(regindex), vfta); 2307 wx->mac.vft_shadow[regindex] = vfta; 2308 2309 return 0; 2310 } 2311 2312 /** 2313 * wx_clear_vfta - Clear VLAN filter table 2314 * @wx: pointer to hardware structure 2315 * 2316 * Clears the VLAN filer table, and the VMDq index associated with the filter 2317 **/ 2318 static void wx_clear_vfta(struct wx *wx) 2319 { 2320 u32 offset; 2321 2322 for (offset = 0; offset < wx->mac.vft_size; offset++) { 2323 wr32(wx, WX_PSR_VLAN_TBL(offset), 0); 2324 wx->mac.vft_shadow[offset] = 0; 2325 } 2326 2327 for (offset = 0; offset < WX_PSR_VLAN_SWC_ENTRIES; offset++) { 2328 wr32(wx, WX_PSR_VLAN_SWC_IDX, offset); 2329 wr32(wx, WX_PSR_VLAN_SWC, 0); 2330 wr32(wx, WX_PSR_VLAN_SWC_VM_L, 0); 2331 wr32(wx, WX_PSR_VLAN_SWC_VM_H, 0); 2332 } 2333 } 2334 2335 int wx_vlan_rx_add_vid(struct net_device *netdev, 2336 __be16 proto, u16 vid) 2337 { 2338 struct wx *wx = netdev_priv(netdev); 2339 2340 /* add VID to filter table */ 2341 wx_set_vfta(wx, vid, VMDQ_P(0), true); 2342 set_bit(vid, wx->active_vlans); 2343 2344 return 0; 2345 } 2346 EXPORT_SYMBOL(wx_vlan_rx_add_vid); 2347 2348 int wx_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2349 { 2350 struct wx *wx = netdev_priv(netdev); 2351 2352 /* remove VID from filter table */ 2353 if (vid) 2354 wx_set_vfta(wx, vid, VMDQ_P(0), false); 2355 clear_bit(vid, wx->active_vlans); 2356 2357 return 0; 2358 } 2359 EXPORT_SYMBOL(wx_vlan_rx_kill_vid); 2360 2361 static void wx_enable_rx_drop(struct wx *wx, struct wx_ring *ring) 2362 { 2363 u16 reg_idx = ring->reg_idx; 2364 u32 srrctl; 2365 2366 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 2367 srrctl |= WX_PX_RR_CFG_DROP_EN; 2368 2369 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 2370 } 2371 2372 static void wx_disable_rx_drop(struct wx *wx, struct wx_ring *ring) 2373 { 2374 u16 reg_idx = ring->reg_idx; 2375 u32 srrctl; 2376 2377 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 2378 srrctl &= ~WX_PX_RR_CFG_DROP_EN; 2379 2380 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 2381 } 2382 2383 int wx_fc_enable(struct wx *wx, bool tx_pause, bool rx_pause) 2384 { 2385 u16 pause_time = WX_DEFAULT_FCPAUSE; 2386 u32 mflcn_reg, fccfg_reg, reg; 2387 u32 fcrtl, fcrth; 2388 int i; 2389 2390 /* Low water mark of zero causes XOFF floods */ 2391 if (tx_pause && wx->fc.high_water) { 2392 if (!wx->fc.low_water || wx->fc.low_water >= wx->fc.high_water) { 2393 wx_err(wx, "Invalid water mark configuration\n"); 2394 return -EINVAL; 2395 } 2396 } 2397 2398 /* Disable any previous flow control settings */ 2399 mflcn_reg = rd32(wx, WX_MAC_RX_FLOW_CTRL); 2400 mflcn_reg &= ~WX_MAC_RX_FLOW_CTRL_RFE; 2401 2402 fccfg_reg = rd32(wx, WX_RDB_RFCC); 2403 fccfg_reg &= ~WX_RDB_RFCC_RFCE_802_3X; 2404 2405 if (rx_pause) 2406 mflcn_reg |= WX_MAC_RX_FLOW_CTRL_RFE; 2407 if (tx_pause) 2408 fccfg_reg |= WX_RDB_RFCC_RFCE_802_3X; 2409 2410 /* Set 802.3x based flow control settings. */ 2411 wr32(wx, WX_MAC_RX_FLOW_CTRL, mflcn_reg); 2412 wr32(wx, WX_RDB_RFCC, fccfg_reg); 2413 2414 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2415 if (tx_pause && wx->fc.high_water) { 2416 fcrtl = (wx->fc.low_water << 10) | WX_RDB_RFCL_XONE; 2417 wr32(wx, WX_RDB_RFCL, fcrtl); 2418 fcrth = (wx->fc.high_water << 10) | WX_RDB_RFCH_XOFFE; 2419 } else { 2420 wr32(wx, WX_RDB_RFCL, 0); 2421 /* In order to prevent Tx hangs when the internal Tx 2422 * switch is enabled we must set the high water mark 2423 * to the Rx packet buffer size - 24KB. This allows 2424 * the Tx switch to function even under heavy Rx 2425 * workloads. 2426 */ 2427 fcrth = rd32(wx, WX_RDB_PB_SZ(0)) - 24576; 2428 } 2429 2430 wr32(wx, WX_RDB_RFCH, fcrth); 2431 2432 /* Configure pause time */ 2433 reg = pause_time * 0x00010001; 2434 wr32(wx, WX_RDB_RFCV, reg); 2435 2436 /* Configure flow control refresh threshold value */ 2437 wr32(wx, WX_RDB_RFCRT, pause_time / 2); 2438 2439 /* We should set the drop enable bit if: 2440 * Number of Rx queues > 1 and flow control is disabled 2441 * 2442 * This allows us to avoid head of line blocking for security 2443 * and performance reasons. 2444 */ 2445 if (wx->num_rx_queues > 1 && !tx_pause) { 2446 for (i = 0; i < wx->num_rx_queues; i++) 2447 wx_enable_rx_drop(wx, wx->rx_ring[i]); 2448 } else { 2449 for (i = 0; i < wx->num_rx_queues; i++) 2450 wx_disable_rx_drop(wx, wx->rx_ring[i]); 2451 } 2452 2453 return 0; 2454 } 2455 EXPORT_SYMBOL(wx_fc_enable); 2456 2457 /** 2458 * wx_update_stats - Update the board statistics counters. 2459 * @wx: board private structure 2460 **/ 2461 void wx_update_stats(struct wx *wx) 2462 { 2463 struct wx_hw_stats *hwstats = &wx->stats; 2464 2465 u64 non_eop_descs = 0, alloc_rx_buff_failed = 0; 2466 u64 hw_csum_rx_good = 0, hw_csum_rx_error = 0; 2467 u64 restart_queue = 0, tx_busy = 0; 2468 u32 i; 2469 2470 /* gather some stats to the wx struct that are per queue */ 2471 for (i = 0; i < wx->num_rx_queues; i++) { 2472 struct wx_ring *rx_ring = wx->rx_ring[i]; 2473 2474 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 2475 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 2476 hw_csum_rx_good += rx_ring->rx_stats.csum_good_cnt; 2477 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 2478 } 2479 wx->non_eop_descs = non_eop_descs; 2480 wx->alloc_rx_buff_failed = alloc_rx_buff_failed; 2481 wx->hw_csum_rx_error = hw_csum_rx_error; 2482 wx->hw_csum_rx_good = hw_csum_rx_good; 2483 2484 for (i = 0; i < wx->num_tx_queues; i++) { 2485 struct wx_ring *tx_ring = wx->tx_ring[i]; 2486 2487 restart_queue += tx_ring->tx_stats.restart_queue; 2488 tx_busy += tx_ring->tx_stats.tx_busy; 2489 } 2490 wx->restart_queue = restart_queue; 2491 wx->tx_busy = tx_busy; 2492 2493 hwstats->gprc += rd32(wx, WX_RDM_PKT_CNT); 2494 hwstats->gptc += rd32(wx, WX_TDM_PKT_CNT); 2495 hwstats->gorc += rd64(wx, WX_RDM_BYTE_CNT_LSB); 2496 hwstats->gotc += rd64(wx, WX_TDM_BYTE_CNT_LSB); 2497 hwstats->tpr += rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L); 2498 hwstats->tpt += rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L); 2499 hwstats->crcerrs += rd64(wx, WX_RX_CRC_ERROR_FRAMES_L); 2500 hwstats->rlec += rd64(wx, WX_RX_LEN_ERROR_FRAMES_L); 2501 hwstats->bprc += rd64(wx, WX_RX_BC_FRAMES_GOOD_L); 2502 hwstats->bptc += rd64(wx, WX_TX_BC_FRAMES_GOOD_L); 2503 hwstats->mprc += rd64(wx, WX_RX_MC_FRAMES_GOOD_L); 2504 hwstats->mptc += rd64(wx, WX_TX_MC_FRAMES_GOOD_L); 2505 hwstats->roc += rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD); 2506 hwstats->ruc += rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD); 2507 hwstats->lxonoffrxc += rd32(wx, WX_MAC_LXONOFFRXC); 2508 hwstats->lxontxc += rd32(wx, WX_RDB_LXONTXC); 2509 hwstats->lxofftxc += rd32(wx, WX_RDB_LXOFFTXC); 2510 hwstats->o2bgptc += rd32(wx, WX_TDM_OS2BMC_CNT); 2511 hwstats->b2ospc += rd32(wx, WX_MNG_BMC2OS_CNT); 2512 hwstats->o2bspc += rd32(wx, WX_MNG_OS2BMC_CNT); 2513 hwstats->b2ogprc += rd32(wx, WX_RDM_BMC2OS_CNT); 2514 hwstats->rdmdrop += rd32(wx, WX_RDM_DRP_PKT); 2515 2516 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 2517 hwstats->fdirmatch += rd32(wx, WX_RDB_FDIR_MATCH); 2518 hwstats->fdirmiss += rd32(wx, WX_RDB_FDIR_MISS); 2519 } 2520 2521 for (i = 0; i < wx->mac.max_rx_queues; i++) 2522 hwstats->qmprc += rd32(wx, WX_PX_MPRC(i)); 2523 } 2524 EXPORT_SYMBOL(wx_update_stats); 2525 2526 /** 2527 * wx_clear_hw_cntrs - Generic clear hardware counters 2528 * @wx: board private structure 2529 * 2530 * Clears all hardware statistics counters by reading them from the hardware 2531 * Statistics counters are clear on read. 2532 **/ 2533 void wx_clear_hw_cntrs(struct wx *wx) 2534 { 2535 u16 i = 0; 2536 2537 for (i = 0; i < wx->mac.max_rx_queues; i++) 2538 wr32(wx, WX_PX_MPRC(i), 0); 2539 2540 rd32(wx, WX_RDM_PKT_CNT); 2541 rd32(wx, WX_TDM_PKT_CNT); 2542 rd64(wx, WX_RDM_BYTE_CNT_LSB); 2543 rd32(wx, WX_TDM_BYTE_CNT_LSB); 2544 rd32(wx, WX_RDM_DRP_PKT); 2545 rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD); 2546 rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD); 2547 rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L); 2548 rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L); 2549 rd64(wx, WX_RX_MC_FRAMES_GOOD_L); 2550 rd64(wx, WX_TX_MC_FRAMES_GOOD_L); 2551 rd64(wx, WX_RX_BC_FRAMES_GOOD_L); 2552 rd64(wx, WX_TX_BC_FRAMES_GOOD_L); 2553 rd64(wx, WX_RX_CRC_ERROR_FRAMES_L); 2554 rd64(wx, WX_RX_LEN_ERROR_FRAMES_L); 2555 rd32(wx, WX_RDB_LXONTXC); 2556 rd32(wx, WX_RDB_LXOFFTXC); 2557 rd32(wx, WX_MAC_LXONOFFRXC); 2558 } 2559 EXPORT_SYMBOL(wx_clear_hw_cntrs); 2560 2561 /** 2562 * wx_start_hw - Prepare hardware for Tx/Rx 2563 * @wx: pointer to hardware structure 2564 * 2565 * Starts the hardware using the generic start_hw function 2566 * and the generation start_hw function. 2567 * Then performs revision-specific operations, if any. 2568 **/ 2569 void wx_start_hw(struct wx *wx) 2570 { 2571 int i; 2572 2573 /* Clear the VLAN filter table */ 2574 wx_clear_vfta(wx); 2575 WX_WRITE_FLUSH(wx); 2576 /* Clear the rate limiters */ 2577 for (i = 0; i < wx->mac.max_tx_queues; i++) { 2578 wr32(wx, WX_TDM_RP_IDX, i); 2579 wr32(wx, WX_TDM_RP_RATE, 0); 2580 } 2581 } 2582 EXPORT_SYMBOL(wx_start_hw); 2583 2584 MODULE_LICENSE("GPL"); 2585